if_wb.c revision 123289
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 123289 2003-12-08 07:54:15Z obrien $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * Winbond fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 4041502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4141502Swpaul * Winbond itself and some made by Linksys. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8648745Swpaul#include "opt_bdg.h" 8741502Swpaul 8841502Swpaul#include <sys/param.h> 8941502Swpaul#include <sys/systm.h> 9041502Swpaul#include <sys/sockio.h> 9141502Swpaul#include <sys/mbuf.h> 9241502Swpaul#include <sys/malloc.h> 9341502Swpaul#include <sys/kernel.h> 9441502Swpaul#include <sys/socket.h> 9550675Swpaul#include <sys/queue.h> 9641502Swpaul 9741502Swpaul#include <net/if.h> 9841502Swpaul#include <net/if_arp.h> 9941502Swpaul#include <net/ethernet.h> 10041502Swpaul#include <net/if_dl.h> 10141502Swpaul#include <net/if_media.h> 10241502Swpaul 10341502Swpaul#include <net/bpf.h> 10441502Swpaul 10541502Swpaul#include <vm/vm.h> /* for vtophys */ 10641502Swpaul#include <vm/pmap.h> /* for vtophys */ 10741502Swpaul#include <machine/bus_memio.h> 10841502Swpaul#include <machine/bus_pio.h> 10941502Swpaul#include <machine/bus.h> 11049611Swpaul#include <machine/resource.h> 11149611Swpaul#include <sys/bus.h> 11249611Swpaul#include <sys/rman.h> 11341502Swpaul 114119288Simp#include <dev/pci/pcireg.h> 115119288Simp#include <dev/pci/pcivar.h> 11641502Swpaul 11750675Swpaul#include <dev/mii/mii.h> 11850675Swpaul#include <dev/mii/miivar.h> 11950675Swpaul 12051089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12150675Swpaul#include "miibus_if.h" 12250675Swpaul 12341502Swpaul#define WB_USEIOSPACE 12441502Swpaul 12541502Swpaul#include <pci/if_wbreg.h> 12641502Swpaul 127113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 128113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 12959758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 13059758Speter 13141502Swpaul/* 13241502Swpaul * Various supported device vendors/types and their names. 13341502Swpaul */ 13441502Swpaulstatic struct wb_type wb_devs[] = { 13541502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13641502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13741502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13841502Swpaul "Compex RL100-ATX 10/100baseTX" }, 13941502Swpaul { 0, 0, NULL } 14041502Swpaul}; 14141502Swpaul 14292739Salfredstatic int wb_probe (device_t); 14392739Salfredstatic int wb_attach (device_t); 14492739Salfredstatic int wb_detach (device_t); 14541502Swpaul 14698995Salfredstatic void wb_bfree (void *addr, void *args); 14792739Salfredstatic int wb_newbuf (struct wb_softc *, 14848745Swpaul struct wb_chain_onefrag *, 14992739Salfred struct mbuf *); 15092739Salfredstatic int wb_encap (struct wb_softc *, struct wb_chain *, 15192739Salfred struct mbuf *); 15241502Swpaul 15392739Salfredstatic void wb_rxeof (struct wb_softc *); 15492739Salfredstatic void wb_rxeoc (struct wb_softc *); 15592739Salfredstatic void wb_txeof (struct wb_softc *); 15692739Salfredstatic void wb_txeoc (struct wb_softc *); 15792739Salfredstatic void wb_intr (void *); 15892739Salfredstatic void wb_tick (void *); 15992739Salfredstatic void wb_start (struct ifnet *); 16092739Salfredstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 16192739Salfredstatic void wb_init (void *); 16292739Salfredstatic void wb_stop (struct wb_softc *); 16392739Salfredstatic void wb_watchdog (struct ifnet *); 16492739Salfredstatic void wb_shutdown (device_t); 16592739Salfredstatic int wb_ifmedia_upd (struct ifnet *); 16692739Salfredstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 16741502Swpaul 16892739Salfredstatic void wb_eeprom_putbyte (struct wb_softc *, int); 16992739Salfredstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 17092739Salfredstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 17192739Salfredstatic void wb_mii_sync (struct wb_softc *); 17292739Salfredstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 17392739Salfredstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 17492739Salfredstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 17541502Swpaul 17692739Salfredstatic void wb_setcfg (struct wb_softc *, u_int32_t); 177123289Sobrienstatic uint32_t wb_mchash (const uint8_t *); 17892739Salfredstatic void wb_setmulti (struct wb_softc *); 17992739Salfredstatic void wb_reset (struct wb_softc *); 18092739Salfredstatic void wb_fixmedia (struct wb_softc *); 18192739Salfredstatic int wb_list_rx_init (struct wb_softc *); 18292739Salfredstatic int wb_list_tx_init (struct wb_softc *); 18341502Swpaul 18492739Salfredstatic int wb_miibus_readreg (device_t, int, int); 18592739Salfredstatic int wb_miibus_writereg (device_t, int, int, int); 18692739Salfredstatic void wb_miibus_statchg (device_t); 18750675Swpaul 18849611Swpaul#ifdef WB_USEIOSPACE 18949611Swpaul#define WB_RES SYS_RES_IOPORT 19049611Swpaul#define WB_RID WB_PCI_LOIO 19149611Swpaul#else 19249611Swpaul#define WB_RES SYS_RES_MEMORY 19349611Swpaul#define WB_RID WB_PCI_LOMEM 19449611Swpaul#endif 19549611Swpaul 19649611Swpaulstatic device_method_t wb_methods[] = { 19749611Swpaul /* Device interface */ 19849611Swpaul DEVMETHOD(device_probe, wb_probe), 19949611Swpaul DEVMETHOD(device_attach, wb_attach), 20049611Swpaul DEVMETHOD(device_detach, wb_detach), 20149611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20250675Swpaul 20350675Swpaul /* bus interface, for miibus */ 20450675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20550675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20650675Swpaul 20750675Swpaul /* MII interface */ 20850675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 20950675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21050675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21149611Swpaul { 0, 0 } 21249611Swpaul}; 21349611Swpaul 21449611Swpaulstatic driver_t wb_driver = { 21551455Swpaul "wb", 21649611Swpaul wb_methods, 21749611Swpaul sizeof(struct wb_softc) 21849611Swpaul}; 21949611Swpaul 22049611Swpaulstatic devclass_t wb_devclass; 22149611Swpaul 222113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22351473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22449611Swpaul 22541502Swpaul#define WB_SETBIT(sc, reg, x) \ 22641502Swpaul CSR_WRITE_4(sc, reg, \ 227105221Sphk CSR_READ_4(sc, reg) | (x)) 22841502Swpaul 22941502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23041502Swpaul CSR_WRITE_4(sc, reg, \ 231105221Sphk CSR_READ_4(sc, reg) & ~(x)) 23241502Swpaul 23341502Swpaul#define SIO_SET(x) \ 23441502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 235105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23641502Swpaul 23741502Swpaul#define SIO_CLR(x) \ 23841502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 239105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 24041502Swpaul 24141502Swpaul/* 24241502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24341502Swpaul */ 244102336Salfredstatic void 245102336Salfredwb_eeprom_putbyte(sc, addr) 24641502Swpaul struct wb_softc *sc; 24742718Swpaul int addr; 24841502Swpaul{ 24941502Swpaul register int d, i; 25041502Swpaul 25141502Swpaul d = addr | WB_EECMD_READ; 25241502Swpaul 25341502Swpaul /* 25441502Swpaul * Feed in each bit and stobe the clock. 25541502Swpaul */ 25641502Swpaul for (i = 0x400; i; i >>= 1) { 25741502Swpaul if (d & i) { 25841502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 25941502Swpaul } else { 26041502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26141502Swpaul } 26241502Swpaul DELAY(100); 26341502Swpaul SIO_SET(WB_SIO_EE_CLK); 26441502Swpaul DELAY(150); 26541502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26641502Swpaul DELAY(100); 26741502Swpaul } 26841502Swpaul 26941502Swpaul return; 27041502Swpaul} 27141502Swpaul 27241502Swpaul/* 27341502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27441502Swpaul */ 275102336Salfredstatic void 276102336Salfredwb_eeprom_getword(sc, addr, dest) 27741502Swpaul struct wb_softc *sc; 27842718Swpaul int addr; 27941502Swpaul u_int16_t *dest; 28041502Swpaul{ 28141502Swpaul register int i; 28241502Swpaul u_int16_t word = 0; 28341502Swpaul 28441502Swpaul /* Enter EEPROM access mode. */ 28541502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28641502Swpaul 28741502Swpaul /* 28841502Swpaul * Send address of word we want to read. 28941502Swpaul */ 29041502Swpaul wb_eeprom_putbyte(sc, addr); 29141502Swpaul 29241502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29341502Swpaul 29441502Swpaul /* 29541502Swpaul * Start reading bits from EEPROM. 29641502Swpaul */ 29741502Swpaul for (i = 0x8000; i; i >>= 1) { 29841502Swpaul SIO_SET(WB_SIO_EE_CLK); 29941502Swpaul DELAY(100); 30041502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30141502Swpaul word |= i; 30241502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30341502Swpaul DELAY(100); 30441502Swpaul } 30541502Swpaul 30641502Swpaul /* Turn off EEPROM access mode. */ 30741502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30841502Swpaul 30941502Swpaul *dest = word; 31041502Swpaul 31141502Swpaul return; 31241502Swpaul} 31341502Swpaul 31441502Swpaul/* 31541502Swpaul * Read a sequence of words from the EEPROM. 31641502Swpaul */ 317102336Salfredstatic void 318102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 31941502Swpaul struct wb_softc *sc; 32041502Swpaul caddr_t dest; 32141502Swpaul int off; 32241502Swpaul int cnt; 32341502Swpaul int swap; 32441502Swpaul{ 32541502Swpaul int i; 32641502Swpaul u_int16_t word = 0, *ptr; 32741502Swpaul 32841502Swpaul for (i = 0; i < cnt; i++) { 32941502Swpaul wb_eeprom_getword(sc, off + i, &word); 33041502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33141502Swpaul if (swap) 33241502Swpaul *ptr = ntohs(word); 33341502Swpaul else 33441502Swpaul *ptr = word; 33541502Swpaul } 33641502Swpaul 33741502Swpaul return; 33841502Swpaul} 33941502Swpaul 34041502Swpaul/* 34141502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34241502Swpaul */ 343102336Salfredstatic void 344102336Salfredwb_mii_sync(sc) 34541502Swpaul struct wb_softc *sc; 34641502Swpaul{ 34741502Swpaul register int i; 34841502Swpaul 34941502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35041502Swpaul 35141502Swpaul for (i = 0; i < 32; i++) { 35241502Swpaul SIO_SET(WB_SIO_MII_CLK); 35341502Swpaul DELAY(1); 35441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35541502Swpaul DELAY(1); 35641502Swpaul } 35741502Swpaul 35841502Swpaul return; 35941502Swpaul} 36041502Swpaul 36141502Swpaul/* 36241502Swpaul * Clock a series of bits through the MII. 36341502Swpaul */ 364102336Salfredstatic void 365102336Salfredwb_mii_send(sc, bits, cnt) 36641502Swpaul struct wb_softc *sc; 36741502Swpaul u_int32_t bits; 36841502Swpaul int cnt; 36941502Swpaul{ 37041502Swpaul int i; 37141502Swpaul 37241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37341502Swpaul 37441502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37541502Swpaul if (bits & i) { 37641502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37741502Swpaul } else { 37841502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37941502Swpaul } 38041502Swpaul DELAY(1); 38141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38241502Swpaul DELAY(1); 38341502Swpaul SIO_SET(WB_SIO_MII_CLK); 38441502Swpaul } 38541502Swpaul} 38641502Swpaul 38741502Swpaul/* 38841502Swpaul * Read an PHY register through the MII. 38941502Swpaul */ 390102336Salfredstatic int 391102336Salfredwb_mii_readreg(sc, frame) 39241502Swpaul struct wb_softc *sc; 39341502Swpaul struct wb_mii_frame *frame; 39441502Swpaul 39541502Swpaul{ 39667087Swpaul int i, ack; 39741502Swpaul 39867087Swpaul WB_LOCK(sc); 39941502Swpaul 40041502Swpaul /* 40141502Swpaul * Set up frame for RX. 40241502Swpaul */ 40341502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40441502Swpaul frame->mii_opcode = WB_MII_READOP; 40541502Swpaul frame->mii_turnaround = 0; 40641502Swpaul frame->mii_data = 0; 40741502Swpaul 40841502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40941502Swpaul 41041502Swpaul /* 41141502Swpaul * Turn on data xmit. 41241502Swpaul */ 41341502Swpaul SIO_SET(WB_SIO_MII_DIR); 41441502Swpaul 41541502Swpaul wb_mii_sync(sc); 41641502Swpaul 41741502Swpaul /* 41841502Swpaul * Send command/address info. 41941502Swpaul */ 42041502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42141502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42241502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42341502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42441502Swpaul 42541502Swpaul /* Idle bit */ 42641502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42741502Swpaul DELAY(1); 42841502Swpaul SIO_SET(WB_SIO_MII_CLK); 42941502Swpaul DELAY(1); 43041502Swpaul 43141502Swpaul /* Turn off xmit. */ 43241502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43341502Swpaul /* Check for ack */ 43441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43541502Swpaul DELAY(1); 436109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43741502Swpaul SIO_SET(WB_SIO_MII_CLK); 43841502Swpaul DELAY(1); 43941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44041502Swpaul DELAY(1); 44141502Swpaul SIO_SET(WB_SIO_MII_CLK); 44241502Swpaul DELAY(1); 44341502Swpaul 44441502Swpaul /* 44541502Swpaul * Now try reading data bits. If the ack failed, we still 44641502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44741502Swpaul */ 44841502Swpaul if (ack) { 44941502Swpaul for(i = 0; i < 16; i++) { 45041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45141502Swpaul DELAY(1); 45241502Swpaul SIO_SET(WB_SIO_MII_CLK); 45341502Swpaul DELAY(1); 45441502Swpaul } 45541502Swpaul goto fail; 45641502Swpaul } 45741502Swpaul 45841502Swpaul for (i = 0x8000; i; i >>= 1) { 45941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46041502Swpaul DELAY(1); 46141502Swpaul if (!ack) { 46241502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46341502Swpaul frame->mii_data |= i; 46441502Swpaul DELAY(1); 46541502Swpaul } 46641502Swpaul SIO_SET(WB_SIO_MII_CLK); 46741502Swpaul DELAY(1); 46841502Swpaul } 46941502Swpaul 47041502Swpaulfail: 47141502Swpaul 47241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47341502Swpaul DELAY(1); 47441502Swpaul SIO_SET(WB_SIO_MII_CLK); 47541502Swpaul DELAY(1); 47641502Swpaul 47767087Swpaul WB_UNLOCK(sc); 47841502Swpaul 47941502Swpaul if (ack) 48041502Swpaul return(1); 48141502Swpaul return(0); 48241502Swpaul} 48341502Swpaul 48441502Swpaul/* 48541502Swpaul * Write to a PHY register through the MII. 48641502Swpaul */ 487102336Salfredstatic int 488102336Salfredwb_mii_writereg(sc, frame) 48941502Swpaul struct wb_softc *sc; 49041502Swpaul struct wb_mii_frame *frame; 49141502Swpaul 49241502Swpaul{ 49367087Swpaul WB_LOCK(sc); 49441502Swpaul 49541502Swpaul /* 49641502Swpaul * Set up frame for TX. 49741502Swpaul */ 49841502Swpaul 49941502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 50041502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50141502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50241502Swpaul 50341502Swpaul /* 50441502Swpaul * Turn on data output. 50541502Swpaul */ 50641502Swpaul SIO_SET(WB_SIO_MII_DIR); 50741502Swpaul 50841502Swpaul wb_mii_sync(sc); 50941502Swpaul 51041502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51141502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51241502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51341502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51441502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51541502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51641502Swpaul 51741502Swpaul /* Idle bit. */ 51841502Swpaul SIO_SET(WB_SIO_MII_CLK); 51941502Swpaul DELAY(1); 52041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52141502Swpaul DELAY(1); 52241502Swpaul 52341502Swpaul /* 52441502Swpaul * Turn off xmit. 52541502Swpaul */ 52641502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52741502Swpaul 52867087Swpaul WB_UNLOCK(sc); 52941502Swpaul 53041502Swpaul return(0); 53141502Swpaul} 53241502Swpaul 533102336Salfredstatic int 534102336Salfredwb_miibus_readreg(dev, phy, reg) 53550675Swpaul device_t dev; 53650675Swpaul int phy, reg; 53750675Swpaul{ 53841502Swpaul struct wb_softc *sc; 53941502Swpaul struct wb_mii_frame frame; 54041502Swpaul 54150675Swpaul sc = device_get_softc(dev); 54250675Swpaul 54341502Swpaul bzero((char *)&frame, sizeof(frame)); 54441502Swpaul 54550675Swpaul frame.mii_phyaddr = phy; 54641502Swpaul frame.mii_regaddr = reg; 54741502Swpaul wb_mii_readreg(sc, &frame); 54841502Swpaul 54941502Swpaul return(frame.mii_data); 55041502Swpaul} 55141502Swpaul 552102336Salfredstatic int 553102336Salfredwb_miibus_writereg(dev, phy, reg, data) 55450675Swpaul device_t dev; 55550675Swpaul int phy, reg, data; 55650675Swpaul{ 55741502Swpaul struct wb_softc *sc; 55841502Swpaul struct wb_mii_frame frame; 55941502Swpaul 56050675Swpaul sc = device_get_softc(dev); 56150675Swpaul 56241502Swpaul bzero((char *)&frame, sizeof(frame)); 56341502Swpaul 56450675Swpaul frame.mii_phyaddr = phy; 56541502Swpaul frame.mii_regaddr = reg; 56641502Swpaul frame.mii_data = data; 56741502Swpaul 56841502Swpaul wb_mii_writereg(sc, &frame); 56941502Swpaul 57050675Swpaul return(0); 57150675Swpaul} 57250675Swpaul 573102336Salfredstatic void 574102336Salfredwb_miibus_statchg(dev) 57550675Swpaul device_t dev; 57650675Swpaul{ 57750675Swpaul struct wb_softc *sc; 57850675Swpaul struct mii_data *mii; 57950675Swpaul 58050675Swpaul sc = device_get_softc(dev); 58167087Swpaul WB_LOCK(sc); 58250675Swpaul mii = device_get_softc(sc->wb_miibus); 58350675Swpaul wb_setcfg(sc, mii->mii_media_active); 58467087Swpaul WB_UNLOCK(sc); 58550675Swpaul 58641502Swpaul return; 58741502Swpaul} 58841502Swpaul 589122625Sobrienstatic u_int32_t 590122625Sobrienwb_mchash(addr) 591123289Sobrien const uint8_t *addr; 59241502Swpaul{ 593123289Sobrien uint32_t crc, carry; 594123289Sobrien int idx, bit; 595123289Sobrien uint8_t data; 59641502Swpaul 59741502Swpaul /* Compute CRC for the address value. */ 59841502Swpaul crc = 0xFFFFFFFF; /* initial value */ 59941502Swpaul 600122625Sobrien for (idx = 0; idx < 6; idx++) { 601122625Sobrien for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 602122625Sobrien carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 60341502Swpaul crc <<= 1; 60441502Swpaul if (carry) 60541502Swpaul crc = (crc ^ 0x04c11db6) | carry; 60641502Swpaul } 60741502Swpaul } 60841502Swpaul 60941502Swpaul /* 61041502Swpaul * return the filter bit position 61141502Swpaul * Note: I arrived at the following nonsense 61241502Swpaul * through experimentation. It's not the usual way to 61341502Swpaul * generate the bit position but it's the only thing 61441502Swpaul * I could come up with that works. 61541502Swpaul */ 61641502Swpaul return(~(crc >> 26) & 0x0000003F); 61741502Swpaul} 61841502Swpaul 61941502Swpaul/* 62041502Swpaul * Program the 64-bit multicast hash filter. 62141502Swpaul */ 622102336Salfredstatic void 623102336Salfredwb_setmulti(sc) 62441502Swpaul struct wb_softc *sc; 62541502Swpaul{ 62641502Swpaul struct ifnet *ifp; 62741502Swpaul int h = 0; 62841502Swpaul u_int32_t hashes[2] = { 0, 0 }; 62941502Swpaul struct ifmultiaddr *ifma; 63041502Swpaul u_int32_t rxfilt; 63141502Swpaul int mcnt = 0; 63241502Swpaul 63341502Swpaul ifp = &sc->arpcom.ac_if; 63441502Swpaul 63541502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 63641502Swpaul 63741502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 63841502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 63941502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 64041502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 64141502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 64241502Swpaul return; 64341502Swpaul } 64441502Swpaul 64541502Swpaul /* first, zot all the existing hash bits */ 64641502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 64741502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 64841502Swpaul 64941502Swpaul /* now program new ones */ 65072084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 65141502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 65241502Swpaul continue; 653122625Sobrien h = wb_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 65441502Swpaul if (h < 32) 65541502Swpaul hashes[0] |= (1 << h); 65641502Swpaul else 65741502Swpaul hashes[1] |= (1 << (h - 32)); 65841502Swpaul mcnt++; 65941502Swpaul } 66041502Swpaul 66141502Swpaul if (mcnt) 66241502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 66341502Swpaul else 66441502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 66541502Swpaul 66641502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 66741502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 66841502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 66941502Swpaul 67041502Swpaul return; 67141502Swpaul} 67241502Swpaul 67341502Swpaul/* 67441502Swpaul * The Winbond manual states that in order to fiddle with the 67541502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 67641502Swpaul * first have to put the transmit and/or receive logic in the idle state. 67741502Swpaul */ 678102336Salfredstatic void 679102336Salfredwb_setcfg(sc, media) 68041502Swpaul struct wb_softc *sc; 68150675Swpaul u_int32_t media; 68241502Swpaul{ 68341502Swpaul int i, restart = 0; 68441502Swpaul 68541502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 68641502Swpaul restart = 1; 68741502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 68841502Swpaul 68941502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69041502Swpaul DELAY(10); 69141502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 69241502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 69341502Swpaul break; 69441502Swpaul } 69541502Swpaul 69641502Swpaul if (i == WB_TIMEOUT) 69741502Swpaul printf("wb%d: failed to force tx and " 69841502Swpaul "rx to idle state\n", sc->wb_unit); 69941502Swpaul } 70041502Swpaul 70150675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 70250675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70350675Swpaul else 70441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70541502Swpaul 70650675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 70741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 70841502Swpaul else 70941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71041502Swpaul 71141502Swpaul if (restart) 71241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 71341502Swpaul 71441502Swpaul return; 71541502Swpaul} 71641502Swpaul 717102336Salfredstatic void 718102336Salfredwb_reset(sc) 71941502Swpaul struct wb_softc *sc; 72041502Swpaul{ 72141502Swpaul register int i; 72250675Swpaul struct mii_data *mii; 72341502Swpaul 72450675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 72550675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 72650675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 72750675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 72850675Swpaul 72941502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73141502Swpaul 73241502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 73341502Swpaul DELAY(10); 73441502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 73541502Swpaul break; 73641502Swpaul } 73741502Swpaul if (i == WB_TIMEOUT) 73841502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 73941502Swpaul 74041502Swpaul /* Wait a little while for the chip to get its brains in order. */ 74141502Swpaul DELAY(1000); 74241502Swpaul 74350675Swpaul if (sc->wb_miibus == NULL) 74450675Swpaul return; 74541502Swpaul 74650675Swpaul mii = device_get_softc(sc->wb_miibus); 74750675Swpaul if (mii == NULL) 74850675Swpaul return; 74950675Swpaul 75050675Swpaul if (mii->mii_instance) { 75150675Swpaul struct mii_softc *miisc; 75272012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 75350675Swpaul mii_phy_reset(miisc); 75450675Swpaul } 75550675Swpaul 75641502Swpaul return; 75741502Swpaul} 75841502Swpaul 759102336Salfredstatic void 760102336Salfredwb_fixmedia(sc) 76150675Swpaul struct wb_softc *sc; 76250675Swpaul{ 76350675Swpaul struct mii_data *mii = NULL; 76450675Swpaul struct ifnet *ifp; 76550675Swpaul u_int32_t media; 76650675Swpaul 76750675Swpaul if (sc->wb_miibus == NULL) 76850675Swpaul return; 76950675Swpaul 77050675Swpaul mii = device_get_softc(sc->wb_miibus); 77150675Swpaul ifp = &sc->arpcom.ac_if; 77250675Swpaul 77350675Swpaul mii_pollstat(mii); 77450675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 77550675Swpaul media = mii->mii_media_active & ~IFM_10_T; 77650675Swpaul media |= IFM_100_TX; 77750675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 77850675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 77950675Swpaul media |= IFM_10_T; 78050675Swpaul } else 78150675Swpaul return; 78250675Swpaul 78350675Swpaul ifmedia_set(&mii->mii_media, media); 78450675Swpaul 78550675Swpaul return; 78650675Swpaul} 78750675Swpaul 78841502Swpaul/* 78941502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 79041502Swpaul * IDs against our list and return a device name if we find a match. 79141502Swpaul */ 792102336Salfredstatic int 793102336Salfredwb_probe(dev) 79449611Swpaul device_t dev; 79541502Swpaul{ 79641502Swpaul struct wb_type *t; 79741502Swpaul 79841502Swpaul t = wb_devs; 79941502Swpaul 80041502Swpaul while(t->wb_name != NULL) { 80149611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 80249611Swpaul (pci_get_device(dev) == t->wb_did)) { 80349611Swpaul device_set_desc(dev, t->wb_name); 80449611Swpaul return(0); 80541502Swpaul } 80641502Swpaul t++; 80741502Swpaul } 80841502Swpaul 80949611Swpaul return(ENXIO); 81041502Swpaul} 81141502Swpaul 81241502Swpaul/* 81341502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 81441502Swpaul * setup and ethernet/BPF attach. 81541502Swpaul */ 816102336Salfredstatic int 817102336Salfredwb_attach(dev) 81849611Swpaul device_t dev; 81941502Swpaul{ 82041502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 82141502Swpaul struct wb_softc *sc; 82241502Swpaul struct ifnet *ifp; 82349611Swpaul int unit, error = 0, rid; 82441502Swpaul 82549611Swpaul sc = device_get_softc(dev); 82649611Swpaul unit = device_get_unit(dev); 82741502Swpaul 82893818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 82993818Sjhb MTX_DEF | MTX_RECURSE); 830117208Simp#ifndef BURN_BRIDGES 83141502Swpaul /* 83241502Swpaul * Handle power management nonsense. 83341502Swpaul */ 83441502Swpaul 83572813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 83672813Swpaul u_int32_t iobase, membase, irq; 83741502Swpaul 83872813Swpaul /* Save important PCI config data. */ 83972813Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 84072813Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 84172813Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 84241502Swpaul 84372813Swpaul /* Reset the power state. */ 84472813Swpaul printf("wb%d: chip is in D%d power mode " 84572813Swpaul "-- setting to D0\n", unit, 84672813Swpaul pci_get_powerstate(dev)); 84772813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 84841502Swpaul 84972813Swpaul /* Restore PCI config data. */ 85072813Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 85172813Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 85272813Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 85341502Swpaul } 854117208Simp#endif 85541502Swpaul /* 85641502Swpaul * Map control/status registers. 85741502Swpaul */ 85872813Swpaul pci_enable_busmaster(dev); 85941502Swpaul 86049611Swpaul rid = WB_RID; 86149611Swpaul sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 86249611Swpaul 0, ~0, 1, RF_ACTIVE); 86349611Swpaul 86449611Swpaul if (sc->wb_res == NULL) { 86549611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 86649611Swpaul error = ENXIO; 86741502Swpaul goto fail; 86841502Swpaul } 86941502Swpaul 87049611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 87149611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 87249611Swpaul 87341502Swpaul /* Allocate interrupt */ 87449611Swpaul rid = 0; 87549611Swpaul sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 87649611Swpaul RF_SHAREABLE | RF_ACTIVE); 87749611Swpaul 87849611Swpaul if (sc->wb_irq == NULL) { 87941502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 88049611Swpaul error = ENXIO; 88141502Swpaul goto fail; 88241502Swpaul } 88341502Swpaul 88450675Swpaul /* Save the cache line size. */ 88550675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 88650675Swpaul 88741502Swpaul /* Reset the adapter. */ 88841502Swpaul wb_reset(sc); 88941502Swpaul 89041502Swpaul /* 89141502Swpaul * Get station address from the EEPROM. 89241502Swpaul */ 89341502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 89441502Swpaul 89541502Swpaul /* 89641502Swpaul * A Winbond chip was detected. Inform the world. 89741502Swpaul */ 89841502Swpaul printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 89941502Swpaul 90041502Swpaul sc->wb_unit = unit; 90141502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 90241502Swpaul 90350675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 90451657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 90550675Swpaul 90650675Swpaul if (sc->wb_ldata == NULL) { 90741502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 90849611Swpaul error = ENXIO; 90949611Swpaul goto fail; 91041502Swpaul } 91141502Swpaul 91241502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 91341502Swpaul 91441502Swpaul ifp = &sc->arpcom.ac_if; 91541502Swpaul ifp->if_softc = sc; 916121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 91741502Swpaul ifp->if_mtu = ETHERMTU; 91841502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 91941502Swpaul ifp->if_ioctl = wb_ioctl; 92041502Swpaul ifp->if_output = ether_output; 92141502Swpaul ifp->if_start = wb_start; 92241502Swpaul ifp->if_watchdog = wb_watchdog; 92341502Swpaul ifp->if_init = wb_init; 92441502Swpaul ifp->if_baudrate = 10000000; 92543515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 92641502Swpaul 92750675Swpaul /* 92850675Swpaul * Do MII setup. 92950675Swpaul */ 93050675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 93150675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 93249611Swpaul error = ENXIO; 93341502Swpaul goto fail; 93441502Swpaul } 93541502Swpaul 93641502Swpaul /* 93763090Sarchie * Call MI attach routine. 93841502Swpaul */ 939106936Ssam ether_ifattach(ifp, eaddr); 94041502Swpaul 941113609Snjl /* Hook interrupt last to avoid having to lock softc */ 942112872Snjl error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 943112872Snjl wb_intr, sc, &sc->wb_intrhand); 944112872Snjl 945112872Snjl if (error) { 946112872Snjl printf("wb%d: couldn't set up irq\n", unit); 947113609Snjl ether_ifdetach(ifp); 948112872Snjl goto fail; 949112872Snjl } 950112872Snjl 95141502Swpaulfail: 95250675Swpaul if (error) 953112872Snjl wb_detach(dev); 95450675Swpaul 95549611Swpaul return(error); 95641502Swpaul} 95741502Swpaul 958113609Snjl/* 959113609Snjl * Shutdown hardware and free up resources. This can be called any 960113609Snjl * time after the mutex has been initialized. It is called in both 961113609Snjl * the error case in attach and the normal detach case so it needs 962113609Snjl * to be careful about only freeing resources that have actually been 963113609Snjl * allocated. 964113609Snjl */ 965102336Salfredstatic int 966102336Salfredwb_detach(dev) 96749611Swpaul device_t dev; 96849611Swpaul{ 96949611Swpaul struct wb_softc *sc; 97049611Swpaul struct ifnet *ifp; 97149611Swpaul 97249611Swpaul sc = device_get_softc(dev); 973112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 97467087Swpaul WB_LOCK(sc); 97549611Swpaul ifp = &sc->arpcom.ac_if; 97649611Swpaul 977113609Snjl /* 978113609Snjl * Delete any miibus and phy devices attached to this interface. 979113609Snjl * This should only be done if attach succeeded. 980113609Snjl */ 981113812Simp if (device_is_attached(dev)) { 982113609Snjl wb_stop(sc); 983112872Snjl ether_ifdetach(ifp); 984113609Snjl } 985113609Snjl if (sc->wb_miibus) 986112872Snjl device_delete_child(dev, sc->wb_miibus); 987113609Snjl bus_generic_detach(dev); 98850675Swpaul 989112872Snjl if (sc->wb_intrhand) 990112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 991112872Snjl if (sc->wb_irq) 992112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 993112872Snjl if (sc->wb_res) 994112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 99549611Swpaul 996112872Snjl if (sc->wb_ldata) { 997112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 998112872Snjl M_DEVBUF); 999112872Snjl } 100049611Swpaul 100167087Swpaul WB_UNLOCK(sc); 100267087Swpaul mtx_destroy(&sc->wb_mtx); 100349611Swpaul 100449611Swpaul return(0); 100549611Swpaul} 100649611Swpaul 100741502Swpaul/* 100841502Swpaul * Initialize the transmit descriptors. 100941502Swpaul */ 1010102336Salfredstatic int 1011102336Salfredwb_list_tx_init(sc) 101241502Swpaul struct wb_softc *sc; 101341502Swpaul{ 101441502Swpaul struct wb_chain_data *cd; 101541502Swpaul struct wb_list_data *ld; 101641502Swpaul int i; 101741502Swpaul 101841502Swpaul cd = &sc->wb_cdata; 101941502Swpaul ld = sc->wb_ldata; 102041502Swpaul 102141502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 102241502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 102341502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 102441502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 102541502Swpaul &cd->wb_tx_chain[0]; 102641502Swpaul } else { 102741502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 102841502Swpaul &cd->wb_tx_chain[i + 1]; 102941502Swpaul } 103041502Swpaul } 103141502Swpaul 103241502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 103341502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 103441502Swpaul 103541502Swpaul return(0); 103641502Swpaul} 103741502Swpaul 103841502Swpaul 103941502Swpaul/* 104041502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 104141502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 104241502Swpaul * points back to the first. 104341502Swpaul */ 1044102336Salfredstatic int 1045102336Salfredwb_list_rx_init(sc) 104641502Swpaul struct wb_softc *sc; 104741502Swpaul{ 104841502Swpaul struct wb_chain_data *cd; 104941502Swpaul struct wb_list_data *ld; 105041502Swpaul int i; 105141502Swpaul 105241502Swpaul cd = &sc->wb_cdata; 105341502Swpaul ld = sc->wb_ldata; 105441502Swpaul 105541502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 105641502Swpaul cd->wb_rx_chain[i].wb_ptr = 105741502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 105850675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 105948745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 106041502Swpaul return(ENOBUFS); 106141502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 106241502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 106341502Swpaul ld->wb_rx_list[i].wb_next = 106441502Swpaul vtophys(&ld->wb_rx_list[0]); 106541502Swpaul } else { 106641502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 106741502Swpaul &cd->wb_rx_chain[i + 1]; 106841502Swpaul ld->wb_rx_list[i].wb_next = 106941502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 107041502Swpaul } 107141502Swpaul } 107241502Swpaul 107341502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 107441502Swpaul 107541502Swpaul return(0); 107641502Swpaul} 107741502Swpaul 1078102336Salfredstatic void 1079102336Salfredwb_bfree(buf, args) 108098995Salfred void *buf; 108164837Sdwmalone void *args; 108250675Swpaul{ 108350675Swpaul return; 108450675Swpaul} 108550675Swpaul 108641502Swpaul/* 108741502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 108841502Swpaul */ 1089102336Salfredstatic int 1090102336Salfredwb_newbuf(sc, c, m) 109141502Swpaul struct wb_softc *sc; 109241502Swpaul struct wb_chain_onefrag *c; 109348745Swpaul struct mbuf *m; 109441502Swpaul{ 109541502Swpaul struct mbuf *m_new = NULL; 109641502Swpaul 109748745Swpaul if (m == NULL) { 1098111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 109987846Sluigi if (m_new == NULL) 110048745Swpaul return(ENOBUFS); 110164837Sdwmalone m_new->m_data = c->wb_buf; 110264837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 110368621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 110468621Sbmilekic EXT_NET_DRV); 110548745Swpaul } else { 110648745Swpaul m_new = m; 110750675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 110848745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 110941502Swpaul } 111041502Swpaul 111148745Swpaul m_adj(m_new, sizeof(u_int64_t)); 111248745Swpaul 111341502Swpaul c->wb_mbuf = m_new; 111441502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 111550675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 111641502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 111741502Swpaul 111841502Swpaul return(0); 111941502Swpaul} 112041502Swpaul 112141502Swpaul/* 112241502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 112341502Swpaul * the higher level protocols. 112441502Swpaul */ 1125102336Salfredstatic void 1126102336Salfredwb_rxeof(sc) 112741502Swpaul struct wb_softc *sc; 112841502Swpaul{ 112950675Swpaul struct mbuf *m = NULL; 113041502Swpaul struct ifnet *ifp; 113141502Swpaul struct wb_chain_onefrag *cur_rx; 113241502Swpaul int total_len = 0; 113341502Swpaul u_int32_t rxstat; 113441502Swpaul 1135122689Ssam WB_LOCK_ASSERT(sc); 1136122689Ssam 113741502Swpaul ifp = &sc->arpcom.ac_if; 113841502Swpaul 113941502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 114041502Swpaul WB_RXSTAT_OWN)) { 114148745Swpaul struct mbuf *m0 = NULL; 114248745Swpaul 114341502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 114441502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 114550675Swpaul 114648745Swpaul m = cur_rx->wb_mbuf; 114741502Swpaul 114850675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 114950675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 115050675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 115150675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 115250675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 115341502Swpaul ifp->if_ierrors++; 115450675Swpaul wb_newbuf(sc, cur_rx, m); 115541502Swpaul printf("wb%x: receiver babbling: possible chip " 115641502Swpaul "bug, forcing reset\n", sc->wb_unit); 115750675Swpaul wb_fixmedia(sc); 115850675Swpaul wb_reset(sc); 115950675Swpaul wb_init(sc); 116041502Swpaul return; 116141502Swpaul } 116241502Swpaul 116342718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 116442718Swpaul ifp->if_ierrors++; 116548745Swpaul wb_newbuf(sc, cur_rx, m); 116650675Swpaul break; 116742718Swpaul } 116842718Swpaul 116941502Swpaul /* No errors; receive the packet. */ 117041502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 117141502Swpaul 117241502Swpaul /* 117341934Swpaul * XXX The Winbond chip includes the CRC with every 117441934Swpaul * received frame, and there's no way to turn this 117541934Swpaul * behavior off (at least, I can't find anything in 117641934Swpaul * the manual that explains how to do it) so we have 117741934Swpaul * to trim off the CRC manually. 117841934Swpaul */ 117941934Swpaul total_len -= ETHER_CRC_LEN; 118041934Swpaul 118178508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 118278508Sbmilekic NULL); 118348745Swpaul wb_newbuf(sc, cur_rx, m); 118448745Swpaul if (m0 == NULL) { 118548745Swpaul ifp->if_ierrors++; 118650675Swpaul break; 118741502Swpaul } 118848745Swpaul m = m0; 118941502Swpaul 119041502Swpaul ifp->if_ipackets++; 1191122689Ssam WB_UNLOCK(sc); 1192106936Ssam (*ifp->if_input)(ifp, m); 1193122689Ssam WB_LOCK(sc); 119441502Swpaul } 119541502Swpaul} 119641502Swpaul 1197105221Sphkstatic void 1198102336Salfredwb_rxeoc(sc) 119941502Swpaul struct wb_softc *sc; 120041502Swpaul{ 120141502Swpaul wb_rxeof(sc); 120241502Swpaul 120341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120441502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 120541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120641502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 120741502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 120841502Swpaul 120941502Swpaul return; 121041502Swpaul} 121141502Swpaul 121241502Swpaul/* 121341502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 121441502Swpaul * the list buffers. 121541502Swpaul */ 1216102336Salfredstatic void 1217102336Salfredwb_txeof(sc) 121841502Swpaul struct wb_softc *sc; 121941502Swpaul{ 122041502Swpaul struct wb_chain *cur_tx; 122141502Swpaul struct ifnet *ifp; 122241502Swpaul 122341502Swpaul ifp = &sc->arpcom.ac_if; 122441502Swpaul 122541502Swpaul /* Clear the timeout timer. */ 122641502Swpaul ifp->if_timer = 0; 122741502Swpaul 122841502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 122941502Swpaul return; 123041502Swpaul 123141502Swpaul /* 123241502Swpaul * Go through our tx list and free mbufs for those 123341502Swpaul * frames that have been transmitted. 123441502Swpaul */ 123541502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 123641502Swpaul u_int32_t txstat; 123741502Swpaul 123841502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 123941502Swpaul txstat = WB_TXSTATUS(cur_tx); 124041502Swpaul 124141502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 124241502Swpaul break; 124341502Swpaul 124441502Swpaul if (txstat & WB_TXSTAT_TXERR) { 124541502Swpaul ifp->if_oerrors++; 124641502Swpaul if (txstat & WB_TXSTAT_ABORT) 124741502Swpaul ifp->if_collisions++; 124841502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 124941502Swpaul ifp->if_collisions++; 125041502Swpaul } 125141502Swpaul 125241502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 125341502Swpaul 125441502Swpaul ifp->if_opackets++; 125541502Swpaul m_freem(cur_tx->wb_mbuf); 125641502Swpaul cur_tx->wb_mbuf = NULL; 125741502Swpaul 125841502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 125941502Swpaul sc->wb_cdata.wb_tx_head = NULL; 126041502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 126141502Swpaul break; 126241502Swpaul } 126341502Swpaul 126441502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 126541502Swpaul } 126641502Swpaul 126741502Swpaul return; 126841502Swpaul} 126941502Swpaul 127041502Swpaul/* 127141502Swpaul * TX 'end of channel' interrupt handler. 127241502Swpaul */ 1273102336Salfredstatic void 1274102336Salfredwb_txeoc(sc) 127541502Swpaul struct wb_softc *sc; 127641502Swpaul{ 127741502Swpaul struct ifnet *ifp; 127841502Swpaul 127941502Swpaul ifp = &sc->arpcom.ac_if; 128041502Swpaul 128141502Swpaul ifp->if_timer = 0; 128241502Swpaul 128341502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 128441502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 128541502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 128641502Swpaul } else { 128741502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 128841502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 128941502Swpaul ifp->if_timer = 5; 129041502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 129141502Swpaul } 129241502Swpaul } 129341502Swpaul 129441502Swpaul return; 129541502Swpaul} 129641502Swpaul 1297102336Salfredstatic void 1298102336Salfredwb_intr(arg) 129941502Swpaul void *arg; 130041502Swpaul{ 130141502Swpaul struct wb_softc *sc; 130241502Swpaul struct ifnet *ifp; 130341502Swpaul u_int32_t status; 130441502Swpaul 130541502Swpaul sc = arg; 130667087Swpaul WB_LOCK(sc); 130741502Swpaul ifp = &sc->arpcom.ac_if; 130841502Swpaul 130967087Swpaul if (!(ifp->if_flags & IFF_UP)) { 131067087Swpaul WB_UNLOCK(sc); 131141502Swpaul return; 131267087Swpaul } 131341502Swpaul 131441502Swpaul /* Disable interrupts. */ 131541502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 131641502Swpaul 131741502Swpaul for (;;) { 131841502Swpaul 131941502Swpaul status = CSR_READ_4(sc, WB_ISR); 132041502Swpaul if (status) 132141502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 132241502Swpaul 132341502Swpaul if ((status & WB_INTRS) == 0) 132441502Swpaul break; 132541502Swpaul 132641502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 132741502Swpaul ifp->if_ierrors++; 132841502Swpaul wb_reset(sc); 132950675Swpaul if (status & WB_ISR_RX_ERR) 133050675Swpaul wb_fixmedia(sc); 133141502Swpaul wb_init(sc); 133250675Swpaul continue; 133341502Swpaul } 133441502Swpaul 133550675Swpaul if (status & WB_ISR_RX_OK) 133650675Swpaul wb_rxeof(sc); 133750675Swpaul 133850675Swpaul if (status & WB_ISR_RX_IDLE) 133950675Swpaul wb_rxeoc(sc); 134050675Swpaul 134141502Swpaul if (status & WB_ISR_TX_OK) 134241502Swpaul wb_txeof(sc); 134341502Swpaul 134441502Swpaul if (status & WB_ISR_TX_NOBUF) 134541502Swpaul wb_txeoc(sc); 134641502Swpaul 134741502Swpaul if (status & WB_ISR_TX_IDLE) { 134841502Swpaul wb_txeof(sc); 134941502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 135041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135141502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 135241502Swpaul } 135341502Swpaul } 135441502Swpaul 135541502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 135641502Swpaul ifp->if_oerrors++; 135741502Swpaul wb_txeof(sc); 135841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135941502Swpaul /* Jack up TX threshold */ 136041502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 136141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 136241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 136341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136441502Swpaul } 136541502Swpaul 136641502Swpaul if (status & WB_ISR_BUS_ERR) { 136741502Swpaul wb_reset(sc); 136841502Swpaul wb_init(sc); 136941502Swpaul } 137041502Swpaul 137141502Swpaul } 137241502Swpaul 137341502Swpaul /* Re-enable interrupts. */ 137441502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 137541502Swpaul 137641502Swpaul if (ifp->if_snd.ifq_head != NULL) { 137741502Swpaul wb_start(ifp); 137841502Swpaul } 137941502Swpaul 138067087Swpaul WB_UNLOCK(sc); 138167087Swpaul 138241502Swpaul return; 138341502Swpaul} 138441502Swpaul 1385102336Salfredstatic void 1386102336Salfredwb_tick(xsc) 138750675Swpaul void *xsc; 138850675Swpaul{ 138950675Swpaul struct wb_softc *sc; 139050675Swpaul struct mii_data *mii; 139150675Swpaul 139250675Swpaul sc = xsc; 139367087Swpaul WB_LOCK(sc); 139450675Swpaul mii = device_get_softc(sc->wb_miibus); 139550675Swpaul 139650675Swpaul mii_tick(mii); 139750675Swpaul 139850675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 139950675Swpaul 140067087Swpaul WB_UNLOCK(sc); 140150685Swpaul 140250675Swpaul return; 140350675Swpaul} 140450675Swpaul 140541502Swpaul/* 140641502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 140741502Swpaul * pointers to the fragment pointers. 140841502Swpaul */ 1409102336Salfredstatic int 1410102336Salfredwb_encap(sc, c, m_head) 141141502Swpaul struct wb_softc *sc; 141241502Swpaul struct wb_chain *c; 141341502Swpaul struct mbuf *m_head; 141441502Swpaul{ 141541502Swpaul int frag = 0; 141641502Swpaul struct wb_desc *f = NULL; 141741502Swpaul int total_len; 141841502Swpaul struct mbuf *m; 141941502Swpaul 142041502Swpaul /* 142141502Swpaul * Start packing the mbufs in this chain into 142241502Swpaul * the fragment pointers. Stop when we run out 142341502Swpaul * of fragments or hit the end of the mbuf chain. 142441502Swpaul */ 142541502Swpaul m = m_head; 142641502Swpaul total_len = 0; 142741502Swpaul 142841502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 142941502Swpaul if (m->m_len != 0) { 143041502Swpaul if (frag == WB_MAXFRAGS) 143141502Swpaul break; 143241502Swpaul total_len += m->m_len; 143341502Swpaul f = &c->wb_ptr->wb_frag[frag]; 143441502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 143541502Swpaul if (frag == 0) { 143641502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 143741502Swpaul f->wb_status = 0; 143841502Swpaul } else 143941502Swpaul f->wb_status = WB_TXSTAT_OWN; 144041502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 144141502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 144241502Swpaul frag++; 144341502Swpaul } 144441502Swpaul } 144541502Swpaul 144641502Swpaul /* 144741502Swpaul * Handle special case: we used up all 16 fragments, 144841502Swpaul * but we have more mbufs left in the chain. Copy the 144941502Swpaul * data into an mbuf cluster. Note that we don't 145041502Swpaul * bother clearing the values in the other fragment 145141502Swpaul * pointers/counters; it wouldn't gain us anything, 145241502Swpaul * and would waste cycles. 145341502Swpaul */ 145441502Swpaul if (m != NULL) { 145541502Swpaul struct mbuf *m_new = NULL; 145641502Swpaul 1457111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145887846Sluigi if (m_new == NULL) 145941502Swpaul return(1); 146041502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1461111119Simp MCLGET(m_new, M_DONTWAIT); 146241502Swpaul if (!(m_new->m_flags & M_EXT)) { 146341502Swpaul m_freem(m_new); 146441502Swpaul return(1); 146541502Swpaul } 146641502Swpaul } 146741502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 146841502Swpaul mtod(m_new, caddr_t)); 146941502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 147041502Swpaul m_freem(m_head); 147141502Swpaul m_head = m_new; 147241502Swpaul f = &c->wb_ptr->wb_frag[0]; 147341502Swpaul f->wb_status = 0; 147441502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 147541502Swpaul f->wb_ctl = total_len = m_new->m_len; 147641502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 147741502Swpaul frag = 1; 147841502Swpaul } 147941502Swpaul 148041502Swpaul if (total_len < WB_MIN_FRAMELEN) { 148141502Swpaul f = &c->wb_ptr->wb_frag[frag]; 148241502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 148341502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 148441502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 148541502Swpaul f->wb_status = WB_TXSTAT_OWN; 148641502Swpaul frag++; 148741502Swpaul } 148841502Swpaul 148941502Swpaul c->wb_mbuf = m_head; 149041502Swpaul c->wb_lastdesc = frag - 1; 149141502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 149241502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 149341502Swpaul 149441502Swpaul return(0); 149541502Swpaul} 149641502Swpaul 149741502Swpaul/* 149841502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 149941502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 150041502Swpaul * copy of the pointers since the transmit list fragment pointers are 150141502Swpaul * physical addresses. 150241502Swpaul */ 150341502Swpaul 1504102336Salfredstatic void 1505102336Salfredwb_start(ifp) 150641502Swpaul struct ifnet *ifp; 150741502Swpaul{ 150841502Swpaul struct wb_softc *sc; 150941502Swpaul struct mbuf *m_head = NULL; 151041502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 151141502Swpaul 151241502Swpaul sc = ifp->if_softc; 151367087Swpaul WB_LOCK(sc); 151441502Swpaul 151541502Swpaul /* 151641502Swpaul * Check for an available queue slot. If there are none, 151741502Swpaul * punt. 151841502Swpaul */ 151941502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 152041502Swpaul ifp->if_flags |= IFF_OACTIVE; 152167087Swpaul WB_UNLOCK(sc); 152241502Swpaul return; 152341502Swpaul } 152441502Swpaul 152541502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 152641502Swpaul 152741502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 152841502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 152941502Swpaul if (m_head == NULL) 153041502Swpaul break; 153141502Swpaul 153241502Swpaul /* Pick a descriptor off the free list. */ 153341502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 153441502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 153541502Swpaul 153641502Swpaul /* Pack the data into the descriptor. */ 153741502Swpaul wb_encap(sc, cur_tx, m_head); 153841502Swpaul 153941502Swpaul if (cur_tx != start_tx) 154041502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 154141502Swpaul 154241502Swpaul /* 154341502Swpaul * If there's a BPF listener, bounce a copy of this frame 154441502Swpaul * to him. 154541502Swpaul */ 1546106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 154741502Swpaul } 154841502Swpaul 154941502Swpaul /* 155041526Swpaul * If there are no packets queued, bail. 155141526Swpaul */ 155267087Swpaul if (cur_tx == NULL) { 155367087Swpaul WB_UNLOCK(sc); 155441526Swpaul return; 155567087Swpaul } 155641526Swpaul 155741526Swpaul /* 155841502Swpaul * Place the request for the upload interrupt 155941502Swpaul * in the last descriptor in the chain. This way, if 156041502Swpaul * we're chaining several packets at once, we'll only 156141502Swpaul * get an interupt once for the whole chain rather than 156241502Swpaul * once for each packet. 156341502Swpaul */ 156441502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 156542718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 156641502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 156741502Swpaul 156841502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 156941502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 157041502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 157141502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 157241502Swpaul } else { 157341502Swpaul /* 157441502Swpaul * We need to distinguish between the case where 157541502Swpaul * the own bit is clear because the chip cleared it 157641502Swpaul * and where the own bit is clear because we haven't 157741502Swpaul * set it yet. The magic value WB_UNSET is just some 157841502Swpaul * ramdomly chosen number which doesn't have the own 157941502Swpaul * bit set. When we actually transmit the frame, the 158041502Swpaul * status word will have _only_ the own bit set, so 158141502Swpaul * the txeoc handler will be able to tell if it needs 158241502Swpaul * to initiate another transmission to flush out pending 158341502Swpaul * frames. 158441502Swpaul */ 158541502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 158641502Swpaul } 158741502Swpaul 158841502Swpaul /* 158941502Swpaul * Set a timeout in case the chip goes out to lunch. 159041502Swpaul */ 159141502Swpaul ifp->if_timer = 5; 159267087Swpaul WB_UNLOCK(sc); 159341502Swpaul 159441502Swpaul return; 159541502Swpaul} 159641502Swpaul 1597102336Salfredstatic void 1598102336Salfredwb_init(xsc) 159941502Swpaul void *xsc; 160041502Swpaul{ 160141502Swpaul struct wb_softc *sc = xsc; 160241502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160367087Swpaul int i; 160450675Swpaul struct mii_data *mii; 160541502Swpaul 160667087Swpaul WB_LOCK(sc); 160750675Swpaul mii = device_get_softc(sc->wb_miibus); 160841502Swpaul 160941502Swpaul /* 161041502Swpaul * Cancel pending I/O and free all RX/TX buffers. 161141502Swpaul */ 161241502Swpaul wb_stop(sc); 161341502Swpaul wb_reset(sc); 161441502Swpaul 161541502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 161641502Swpaul 161741502Swpaul /* 161841502Swpaul * Set cache alignment and burst length. 161941502Swpaul */ 162050675Swpaul#ifdef foo 162141502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 162241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 162341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 162450675Swpaul#endif 162541502Swpaul 162650675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 162750675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 162850675Swpaul switch(sc->wb_cachesize) { 162950675Swpaul case 32: 163050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 163150675Swpaul break; 163250675Swpaul case 16: 163350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 163450675Swpaul break; 163550675Swpaul case 8: 163650675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 163750675Swpaul break; 163850675Swpaul case 0: 163950675Swpaul default: 164050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 164150675Swpaul break; 164250675Swpaul } 164350675Swpaul 164441502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 164541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 164641502Swpaul 164741502Swpaul /* Init our MAC address */ 164841502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 164941502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 165041502Swpaul } 165141502Swpaul 165241502Swpaul /* Init circular RX list. */ 165341502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 165441502Swpaul printf("wb%d: initialization failed: no " 165541502Swpaul "memory for rx buffers\n", sc->wb_unit); 165641502Swpaul wb_stop(sc); 165767087Swpaul WB_UNLOCK(sc); 165841502Swpaul return; 165941502Swpaul } 166041502Swpaul 166141502Swpaul /* Init TX descriptors. */ 166241502Swpaul wb_list_tx_init(sc); 166341502Swpaul 166441502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 166541502Swpaul if (ifp->if_flags & IFF_PROMISC) { 166641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166741502Swpaul } else { 166841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166941502Swpaul } 167041502Swpaul 167141502Swpaul /* 167241502Swpaul * Set capture broadcast bit to capture broadcast frames. 167341502Swpaul */ 167441502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 167541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167641502Swpaul } else { 167741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167841502Swpaul } 167941502Swpaul 168041502Swpaul /* 168141502Swpaul * Program the multicast filter, if necessary. 168241502Swpaul */ 168341502Swpaul wb_setmulti(sc); 168441502Swpaul 168541502Swpaul /* 168641502Swpaul * Load the address of the RX list. 168741502Swpaul */ 168841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 168941502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 169041502Swpaul 169141502Swpaul /* 169241502Swpaul * Enable interrupts. 169341502Swpaul */ 169441502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 169541502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 169641502Swpaul 169741502Swpaul /* Enable receiver and transmitter. */ 169841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 169941502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 170041502Swpaul 170141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170241502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 170341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170441502Swpaul 170550675Swpaul mii_mediachg(mii); 170641502Swpaul 170741502Swpaul ifp->if_flags |= IFF_RUNNING; 170841502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 170941502Swpaul 171050675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 171167087Swpaul WB_UNLOCK(sc); 171250675Swpaul 171341502Swpaul return; 171441502Swpaul} 171541502Swpaul 171641502Swpaul/* 171741502Swpaul * Set media options. 171841502Swpaul */ 1719102336Salfredstatic int 1720102336Salfredwb_ifmedia_upd(ifp) 172141502Swpaul struct ifnet *ifp; 172241502Swpaul{ 172341502Swpaul struct wb_softc *sc; 172441502Swpaul 172541502Swpaul sc = ifp->if_softc; 172641502Swpaul 172750675Swpaul if (ifp->if_flags & IFF_UP) 172850675Swpaul wb_init(sc); 172941502Swpaul 173041502Swpaul return(0); 173141502Swpaul} 173241502Swpaul 173341502Swpaul/* 173441502Swpaul * Report current media status. 173541502Swpaul */ 1736102336Salfredstatic void 1737102336Salfredwb_ifmedia_sts(ifp, ifmr) 173841502Swpaul struct ifnet *ifp; 173941502Swpaul struct ifmediareq *ifmr; 174041502Swpaul{ 174141502Swpaul struct wb_softc *sc; 174250675Swpaul struct mii_data *mii; 174341502Swpaul 174441502Swpaul sc = ifp->if_softc; 174541502Swpaul 174650675Swpaul mii = device_get_softc(sc->wb_miibus); 174741502Swpaul 174850675Swpaul mii_pollstat(mii); 174950675Swpaul ifmr->ifm_active = mii->mii_media_active; 175050675Swpaul ifmr->ifm_status = mii->mii_media_status; 175141502Swpaul 175241502Swpaul return; 175341502Swpaul} 175441502Swpaul 1755102336Salfredstatic int 1756102336Salfredwb_ioctl(ifp, command, data) 175741502Swpaul struct ifnet *ifp; 175841502Swpaul u_long command; 175941502Swpaul caddr_t data; 176041502Swpaul{ 176141502Swpaul struct wb_softc *sc = ifp->if_softc; 176250675Swpaul struct mii_data *mii; 176341502Swpaul struct ifreq *ifr = (struct ifreq *) data; 176467087Swpaul int error = 0; 176541502Swpaul 176667087Swpaul WB_LOCK(sc); 176741502Swpaul 176841502Swpaul switch(command) { 176941502Swpaul case SIOCSIFFLAGS: 177041502Swpaul if (ifp->if_flags & IFF_UP) { 177141502Swpaul wb_init(sc); 177241502Swpaul } else { 177341502Swpaul if (ifp->if_flags & IFF_RUNNING) 177441502Swpaul wb_stop(sc); 177541502Swpaul } 177641502Swpaul error = 0; 177741502Swpaul break; 177841502Swpaul case SIOCADDMULTI: 177941502Swpaul case SIOCDELMULTI: 178041502Swpaul wb_setmulti(sc); 178141502Swpaul error = 0; 178241502Swpaul break; 178341502Swpaul case SIOCGIFMEDIA: 178441502Swpaul case SIOCSIFMEDIA: 178550675Swpaul mii = device_get_softc(sc->wb_miibus); 178650675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 178741502Swpaul break; 178841502Swpaul default: 1789106936Ssam error = ether_ioctl(ifp, command, data); 179041502Swpaul break; 179141502Swpaul } 179241502Swpaul 179367087Swpaul WB_UNLOCK(sc); 179441502Swpaul 179541502Swpaul return(error); 179641502Swpaul} 179741502Swpaul 1798102336Salfredstatic void 1799102336Salfredwb_watchdog(ifp) 180041502Swpaul struct ifnet *ifp; 180141502Swpaul{ 180241502Swpaul struct wb_softc *sc; 180341502Swpaul 180441502Swpaul sc = ifp->if_softc; 180541502Swpaul 180667087Swpaul WB_LOCK(sc); 180741502Swpaul ifp->if_oerrors++; 180841502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 180950675Swpaul#ifdef foo 181041502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 181141502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 181241502Swpaul sc->wb_unit); 181350675Swpaul#endif 181441502Swpaul wb_stop(sc); 181541502Swpaul wb_reset(sc); 181641502Swpaul wb_init(sc); 181741502Swpaul 181841502Swpaul if (ifp->if_snd.ifq_head != NULL) 181941502Swpaul wb_start(ifp); 182067087Swpaul WB_UNLOCK(sc); 182141502Swpaul 182241502Swpaul return; 182341502Swpaul} 182441502Swpaul 182541502Swpaul/* 182641502Swpaul * Stop the adapter and free any mbufs allocated to the 182741502Swpaul * RX and TX lists. 182841502Swpaul */ 1829102336Salfredstatic void 1830102336Salfredwb_stop(sc) 183141502Swpaul struct wb_softc *sc; 183241502Swpaul{ 183341502Swpaul register int i; 183441502Swpaul struct ifnet *ifp; 183541502Swpaul 183667087Swpaul WB_LOCK(sc); 183741502Swpaul ifp = &sc->arpcom.ac_if; 183841502Swpaul ifp->if_timer = 0; 183941502Swpaul 184050675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 184150675Swpaul 184241502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 184341502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 184441502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 184541502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 184641502Swpaul 184741502Swpaul /* 184841502Swpaul * Free data in the RX lists. 184941502Swpaul */ 185041502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 185141502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 185241502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 185341502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 185441502Swpaul } 185541502Swpaul } 185641502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 185741502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 185841502Swpaul 185941502Swpaul /* 186041502Swpaul * Free the TX list buffers. 186141502Swpaul */ 186241502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 186341502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 186441502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 186541502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 186641502Swpaul } 186741502Swpaul } 186841502Swpaul 186941502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 187041502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 187141502Swpaul 187241502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 187367087Swpaul WB_UNLOCK(sc); 187441502Swpaul 187541502Swpaul return; 187641502Swpaul} 187741502Swpaul 187841502Swpaul/* 187941502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 188041502Swpaul * get confused by errant DMAs when rebooting. 188141502Swpaul */ 1882102336Salfredstatic void 1883102336Salfredwb_shutdown(dev) 188449611Swpaul device_t dev; 188541502Swpaul{ 188649611Swpaul struct wb_softc *sc; 188741502Swpaul 188849611Swpaul sc = device_get_softc(dev); 188941502Swpaul wb_stop(sc); 189041502Swpaul 189141502Swpaul return; 189241502Swpaul} 1893