if_wb.c revision 122625
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 3341502Swpaul/* 3441502Swpaul * Winbond fast ethernet PCI NIC driver 3541502Swpaul * 3641502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 3741502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 3841502Swpaul * Winbond itself and some made by Linksys. 3941502Swpaul * 4041502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4141502Swpaul * Electrical Engineering Department 4241502Swpaul * Columbia University, New York City 4341502Swpaul */ 4441502Swpaul 4541502Swpaul/* 4641502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4741502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 4841502Swpaul * one major difference which is that while the registers do many of 4941502Swpaul * the same things as a tulip adapter, the offsets are different: where 5041502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5141502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5241502Swpaul * programmed differently. 5341502Swpaul * 5441502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5541502Swpaul * a status word, a control word and 32-bit areas that can either be used 5641502Swpaul * to point to two external data blocks, or to point to a single block 5741502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 5841502Swpaul * together in blocks to form fixed length rings or can be chained 5941502Swpaul * together in linked lists. A single packet may be spread out over 6041502Swpaul * several descriptors if necessary. 6141502Swpaul * 6241502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6341502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6441502Swpaul * to hold an entire packet. The link list is looped back to created a 6541502Swpaul * closed ring. 6641502Swpaul * 6741502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 6841502Swpaul * which each contain several individual descriptors linked toghether. 6941502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7041502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7141502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7241502Swpaul * drivers. 7341502Swpaul * 7441502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7541502Swpaul * The sample boards I have all use a Davicom PHY. 7641502Swpaul * 7741502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 7841502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 7941502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8041502Swpaul * I have no idea what he's on about: transmit performance with all 8141502Swpaul * three of my test boards seems fine. 8241502Swpaul */ 8341502Swpaul 84113038Sobrien#include <sys/cdefs.h> 85113038Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 122625 2003-11-13 20:55:53Z obrien $"); 86113038Sobrien 8748745Swpaul#include "opt_bdg.h" 8841502Swpaul 8941502Swpaul#include <sys/param.h> 9041502Swpaul#include <sys/systm.h> 9141502Swpaul#include <sys/sockio.h> 9241502Swpaul#include <sys/mbuf.h> 9341502Swpaul#include <sys/malloc.h> 9441502Swpaul#include <sys/kernel.h> 9541502Swpaul#include <sys/socket.h> 9650675Swpaul#include <sys/queue.h> 9741502Swpaul 9841502Swpaul#include <net/if.h> 9941502Swpaul#include <net/if_arp.h> 10041502Swpaul#include <net/ethernet.h> 10141502Swpaul#include <net/if_dl.h> 10241502Swpaul#include <net/if_media.h> 10341502Swpaul 10441502Swpaul#include <net/bpf.h> 10541502Swpaul 10641502Swpaul#include <vm/vm.h> /* for vtophys */ 10741502Swpaul#include <vm/pmap.h> /* for vtophys */ 10841502Swpaul#include <machine/bus_memio.h> 10941502Swpaul#include <machine/bus_pio.h> 11041502Swpaul#include <machine/bus.h> 11149611Swpaul#include <machine/resource.h> 11249611Swpaul#include <sys/bus.h> 11349611Swpaul#include <sys/rman.h> 11441502Swpaul 115119288Simp#include <dev/pci/pcireg.h> 116119288Simp#include <dev/pci/pcivar.h> 11741502Swpaul 11850675Swpaul#include <dev/mii/mii.h> 11950675Swpaul#include <dev/mii/miivar.h> 12050675Swpaul 12151089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12250675Swpaul#include "miibus_if.h" 12350675Swpaul 12441502Swpaul#define WB_USEIOSPACE 12541502Swpaul 12641502Swpaul#include <pci/if_wbreg.h> 12741502Swpaul 128113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 129113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 13059758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 13159758Speter 13241502Swpaul/* 13341502Swpaul * Various supported device vendors/types and their names. 13441502Swpaul */ 13541502Swpaulstatic struct wb_type wb_devs[] = { 13641502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13741502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13841502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13941502Swpaul "Compex RL100-ATX 10/100baseTX" }, 14041502Swpaul { 0, 0, NULL } 14141502Swpaul}; 14241502Swpaul 14392739Salfredstatic int wb_probe (device_t); 14492739Salfredstatic int wb_attach (device_t); 14592739Salfredstatic int wb_detach (device_t); 14641502Swpaul 14798995Salfredstatic void wb_bfree (void *addr, void *args); 14892739Salfredstatic int wb_newbuf (struct wb_softc *, 14948745Swpaul struct wb_chain_onefrag *, 15092739Salfred struct mbuf *); 15192739Salfredstatic int wb_encap (struct wb_softc *, struct wb_chain *, 15292739Salfred struct mbuf *); 15341502Swpaul 15492739Salfredstatic void wb_rxeof (struct wb_softc *); 15592739Salfredstatic void wb_rxeoc (struct wb_softc *); 15692739Salfredstatic void wb_txeof (struct wb_softc *); 15792739Salfredstatic void wb_txeoc (struct wb_softc *); 15892739Salfredstatic void wb_intr (void *); 15992739Salfredstatic void wb_tick (void *); 16092739Salfredstatic void wb_start (struct ifnet *); 16192739Salfredstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 16292739Salfredstatic void wb_init (void *); 16392739Salfredstatic void wb_stop (struct wb_softc *); 16492739Salfredstatic void wb_watchdog (struct ifnet *); 16592739Salfredstatic void wb_shutdown (device_t); 16692739Salfredstatic int wb_ifmedia_upd (struct ifnet *); 16792739Salfredstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 16841502Swpaul 16992739Salfredstatic void wb_eeprom_putbyte (struct wb_softc *, int); 17092739Salfredstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 17192739Salfredstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 17292739Salfredstatic void wb_mii_sync (struct wb_softc *); 17392739Salfredstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 17492739Salfredstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 17592739Salfredstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 17641502Swpaul 17792739Salfredstatic void wb_setcfg (struct wb_softc *, u_int32_t); 178122625Sobrienstatic u_int32_t wb_mchash (caddr_t); 17992739Salfredstatic void wb_setmulti (struct wb_softc *); 18092739Salfredstatic void wb_reset (struct wb_softc *); 18192739Salfredstatic void wb_fixmedia (struct wb_softc *); 18292739Salfredstatic int wb_list_rx_init (struct wb_softc *); 18392739Salfredstatic int wb_list_tx_init (struct wb_softc *); 18441502Swpaul 18592739Salfredstatic int wb_miibus_readreg (device_t, int, int); 18692739Salfredstatic int wb_miibus_writereg (device_t, int, int, int); 18792739Salfredstatic void wb_miibus_statchg (device_t); 18850675Swpaul 18949611Swpaul#ifdef WB_USEIOSPACE 19049611Swpaul#define WB_RES SYS_RES_IOPORT 19149611Swpaul#define WB_RID WB_PCI_LOIO 19249611Swpaul#else 19349611Swpaul#define WB_RES SYS_RES_MEMORY 19449611Swpaul#define WB_RID WB_PCI_LOMEM 19549611Swpaul#endif 19649611Swpaul 19749611Swpaulstatic device_method_t wb_methods[] = { 19849611Swpaul /* Device interface */ 19949611Swpaul DEVMETHOD(device_probe, wb_probe), 20049611Swpaul DEVMETHOD(device_attach, wb_attach), 20149611Swpaul DEVMETHOD(device_detach, wb_detach), 20249611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20350675Swpaul 20450675Swpaul /* bus interface, for miibus */ 20550675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20650675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20750675Swpaul 20850675Swpaul /* MII interface */ 20950675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 21050675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21150675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21249611Swpaul { 0, 0 } 21349611Swpaul}; 21449611Swpaul 21549611Swpaulstatic driver_t wb_driver = { 21651455Swpaul "wb", 21749611Swpaul wb_methods, 21849611Swpaul sizeof(struct wb_softc) 21949611Swpaul}; 22049611Swpaul 22149611Swpaulstatic devclass_t wb_devclass; 22249611Swpaul 223113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22451473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22549611Swpaul 22641502Swpaul#define WB_SETBIT(sc, reg, x) \ 22741502Swpaul CSR_WRITE_4(sc, reg, \ 228105221Sphk CSR_READ_4(sc, reg) | (x)) 22941502Swpaul 23041502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23141502Swpaul CSR_WRITE_4(sc, reg, \ 232105221Sphk CSR_READ_4(sc, reg) & ~(x)) 23341502Swpaul 23441502Swpaul#define SIO_SET(x) \ 23541502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 236105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23741502Swpaul 23841502Swpaul#define SIO_CLR(x) \ 23941502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 240105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 24141502Swpaul 24241502Swpaul/* 24341502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24441502Swpaul */ 245102336Salfredstatic void 246102336Salfredwb_eeprom_putbyte(sc, addr) 24741502Swpaul struct wb_softc *sc; 24842718Swpaul int addr; 24941502Swpaul{ 25041502Swpaul register int d, i; 25141502Swpaul 25241502Swpaul d = addr | WB_EECMD_READ; 25341502Swpaul 25441502Swpaul /* 25541502Swpaul * Feed in each bit and stobe the clock. 25641502Swpaul */ 25741502Swpaul for (i = 0x400; i; i >>= 1) { 25841502Swpaul if (d & i) { 25941502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 26041502Swpaul } else { 26141502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26241502Swpaul } 26341502Swpaul DELAY(100); 26441502Swpaul SIO_SET(WB_SIO_EE_CLK); 26541502Swpaul DELAY(150); 26641502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26741502Swpaul DELAY(100); 26841502Swpaul } 26941502Swpaul 27041502Swpaul return; 27141502Swpaul} 27241502Swpaul 27341502Swpaul/* 27441502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27541502Swpaul */ 276102336Salfredstatic void 277102336Salfredwb_eeprom_getword(sc, addr, dest) 27841502Swpaul struct wb_softc *sc; 27942718Swpaul int addr; 28041502Swpaul u_int16_t *dest; 28141502Swpaul{ 28241502Swpaul register int i; 28341502Swpaul u_int16_t word = 0; 28441502Swpaul 28541502Swpaul /* Enter EEPROM access mode. */ 28641502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28741502Swpaul 28841502Swpaul /* 28941502Swpaul * Send address of word we want to read. 29041502Swpaul */ 29141502Swpaul wb_eeprom_putbyte(sc, addr); 29241502Swpaul 29341502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29441502Swpaul 29541502Swpaul /* 29641502Swpaul * Start reading bits from EEPROM. 29741502Swpaul */ 29841502Swpaul for (i = 0x8000; i; i >>= 1) { 29941502Swpaul SIO_SET(WB_SIO_EE_CLK); 30041502Swpaul DELAY(100); 30141502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30241502Swpaul word |= i; 30341502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30441502Swpaul DELAY(100); 30541502Swpaul } 30641502Swpaul 30741502Swpaul /* Turn off EEPROM access mode. */ 30841502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30941502Swpaul 31041502Swpaul *dest = word; 31141502Swpaul 31241502Swpaul return; 31341502Swpaul} 31441502Swpaul 31541502Swpaul/* 31641502Swpaul * Read a sequence of words from the EEPROM. 31741502Swpaul */ 318102336Salfredstatic void 319102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 32041502Swpaul struct wb_softc *sc; 32141502Swpaul caddr_t dest; 32241502Swpaul int off; 32341502Swpaul int cnt; 32441502Swpaul int swap; 32541502Swpaul{ 32641502Swpaul int i; 32741502Swpaul u_int16_t word = 0, *ptr; 32841502Swpaul 32941502Swpaul for (i = 0; i < cnt; i++) { 33041502Swpaul wb_eeprom_getword(sc, off + i, &word); 33141502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33241502Swpaul if (swap) 33341502Swpaul *ptr = ntohs(word); 33441502Swpaul else 33541502Swpaul *ptr = word; 33641502Swpaul } 33741502Swpaul 33841502Swpaul return; 33941502Swpaul} 34041502Swpaul 34141502Swpaul/* 34241502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34341502Swpaul */ 344102336Salfredstatic void 345102336Salfredwb_mii_sync(sc) 34641502Swpaul struct wb_softc *sc; 34741502Swpaul{ 34841502Swpaul register int i; 34941502Swpaul 35041502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35141502Swpaul 35241502Swpaul for (i = 0; i < 32; i++) { 35341502Swpaul SIO_SET(WB_SIO_MII_CLK); 35441502Swpaul DELAY(1); 35541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35641502Swpaul DELAY(1); 35741502Swpaul } 35841502Swpaul 35941502Swpaul return; 36041502Swpaul} 36141502Swpaul 36241502Swpaul/* 36341502Swpaul * Clock a series of bits through the MII. 36441502Swpaul */ 365102336Salfredstatic void 366102336Salfredwb_mii_send(sc, bits, cnt) 36741502Swpaul struct wb_softc *sc; 36841502Swpaul u_int32_t bits; 36941502Swpaul int cnt; 37041502Swpaul{ 37141502Swpaul int i; 37241502Swpaul 37341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37441502Swpaul 37541502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37641502Swpaul if (bits & i) { 37741502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37841502Swpaul } else { 37941502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 38041502Swpaul } 38141502Swpaul DELAY(1); 38241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38341502Swpaul DELAY(1); 38441502Swpaul SIO_SET(WB_SIO_MII_CLK); 38541502Swpaul } 38641502Swpaul} 38741502Swpaul 38841502Swpaul/* 38941502Swpaul * Read an PHY register through the MII. 39041502Swpaul */ 391102336Salfredstatic int 392102336Salfredwb_mii_readreg(sc, frame) 39341502Swpaul struct wb_softc *sc; 39441502Swpaul struct wb_mii_frame *frame; 39541502Swpaul 39641502Swpaul{ 39767087Swpaul int i, ack; 39841502Swpaul 39967087Swpaul WB_LOCK(sc); 40041502Swpaul 40141502Swpaul /* 40241502Swpaul * Set up frame for RX. 40341502Swpaul */ 40441502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40541502Swpaul frame->mii_opcode = WB_MII_READOP; 40641502Swpaul frame->mii_turnaround = 0; 40741502Swpaul frame->mii_data = 0; 40841502Swpaul 40941502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 41041502Swpaul 41141502Swpaul /* 41241502Swpaul * Turn on data xmit. 41341502Swpaul */ 41441502Swpaul SIO_SET(WB_SIO_MII_DIR); 41541502Swpaul 41641502Swpaul wb_mii_sync(sc); 41741502Swpaul 41841502Swpaul /* 41941502Swpaul * Send command/address info. 42041502Swpaul */ 42141502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42241502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42341502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42441502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42541502Swpaul 42641502Swpaul /* Idle bit */ 42741502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42841502Swpaul DELAY(1); 42941502Swpaul SIO_SET(WB_SIO_MII_CLK); 43041502Swpaul DELAY(1); 43141502Swpaul 43241502Swpaul /* Turn off xmit. */ 43341502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43441502Swpaul /* Check for ack */ 43541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43641502Swpaul DELAY(1); 437109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43841502Swpaul SIO_SET(WB_SIO_MII_CLK); 43941502Swpaul DELAY(1); 44041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44141502Swpaul DELAY(1); 44241502Swpaul SIO_SET(WB_SIO_MII_CLK); 44341502Swpaul DELAY(1); 44441502Swpaul 44541502Swpaul /* 44641502Swpaul * Now try reading data bits. If the ack failed, we still 44741502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44841502Swpaul */ 44941502Swpaul if (ack) { 45041502Swpaul for(i = 0; i < 16; i++) { 45141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45241502Swpaul DELAY(1); 45341502Swpaul SIO_SET(WB_SIO_MII_CLK); 45441502Swpaul DELAY(1); 45541502Swpaul } 45641502Swpaul goto fail; 45741502Swpaul } 45841502Swpaul 45941502Swpaul for (i = 0x8000; i; i >>= 1) { 46041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46141502Swpaul DELAY(1); 46241502Swpaul if (!ack) { 46341502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46441502Swpaul frame->mii_data |= i; 46541502Swpaul DELAY(1); 46641502Swpaul } 46741502Swpaul SIO_SET(WB_SIO_MII_CLK); 46841502Swpaul DELAY(1); 46941502Swpaul } 47041502Swpaul 47141502Swpaulfail: 47241502Swpaul 47341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47441502Swpaul DELAY(1); 47541502Swpaul SIO_SET(WB_SIO_MII_CLK); 47641502Swpaul DELAY(1); 47741502Swpaul 47867087Swpaul WB_UNLOCK(sc); 47941502Swpaul 48041502Swpaul if (ack) 48141502Swpaul return(1); 48241502Swpaul return(0); 48341502Swpaul} 48441502Swpaul 48541502Swpaul/* 48641502Swpaul * Write to a PHY register through the MII. 48741502Swpaul */ 488102336Salfredstatic int 489102336Salfredwb_mii_writereg(sc, frame) 49041502Swpaul struct wb_softc *sc; 49141502Swpaul struct wb_mii_frame *frame; 49241502Swpaul 49341502Swpaul{ 49467087Swpaul WB_LOCK(sc); 49541502Swpaul 49641502Swpaul /* 49741502Swpaul * Set up frame for TX. 49841502Swpaul */ 49941502Swpaul 50041502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 50141502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50241502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50341502Swpaul 50441502Swpaul /* 50541502Swpaul * Turn on data output. 50641502Swpaul */ 50741502Swpaul SIO_SET(WB_SIO_MII_DIR); 50841502Swpaul 50941502Swpaul wb_mii_sync(sc); 51041502Swpaul 51141502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51241502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51341502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51441502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51541502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51641502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51741502Swpaul 51841502Swpaul /* Idle bit. */ 51941502Swpaul SIO_SET(WB_SIO_MII_CLK); 52041502Swpaul DELAY(1); 52141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52241502Swpaul DELAY(1); 52341502Swpaul 52441502Swpaul /* 52541502Swpaul * Turn off xmit. 52641502Swpaul */ 52741502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52841502Swpaul 52967087Swpaul WB_UNLOCK(sc); 53041502Swpaul 53141502Swpaul return(0); 53241502Swpaul} 53341502Swpaul 534102336Salfredstatic int 535102336Salfredwb_miibus_readreg(dev, phy, reg) 53650675Swpaul device_t dev; 53750675Swpaul int phy, reg; 53850675Swpaul{ 53941502Swpaul struct wb_softc *sc; 54041502Swpaul struct wb_mii_frame frame; 54141502Swpaul 54250675Swpaul sc = device_get_softc(dev); 54350675Swpaul 54441502Swpaul bzero((char *)&frame, sizeof(frame)); 54541502Swpaul 54650675Swpaul frame.mii_phyaddr = phy; 54741502Swpaul frame.mii_regaddr = reg; 54841502Swpaul wb_mii_readreg(sc, &frame); 54941502Swpaul 55041502Swpaul return(frame.mii_data); 55141502Swpaul} 55241502Swpaul 553102336Salfredstatic int 554102336Salfredwb_miibus_writereg(dev, phy, reg, data) 55550675Swpaul device_t dev; 55650675Swpaul int phy, reg, data; 55750675Swpaul{ 55841502Swpaul struct wb_softc *sc; 55941502Swpaul struct wb_mii_frame frame; 56041502Swpaul 56150675Swpaul sc = device_get_softc(dev); 56250675Swpaul 56341502Swpaul bzero((char *)&frame, sizeof(frame)); 56441502Swpaul 56550675Swpaul frame.mii_phyaddr = phy; 56641502Swpaul frame.mii_regaddr = reg; 56741502Swpaul frame.mii_data = data; 56841502Swpaul 56941502Swpaul wb_mii_writereg(sc, &frame); 57041502Swpaul 57150675Swpaul return(0); 57250675Swpaul} 57350675Swpaul 574102336Salfredstatic void 575102336Salfredwb_miibus_statchg(dev) 57650675Swpaul device_t dev; 57750675Swpaul{ 57850675Swpaul struct wb_softc *sc; 57950675Swpaul struct mii_data *mii; 58050675Swpaul 58150675Swpaul sc = device_get_softc(dev); 58267087Swpaul WB_LOCK(sc); 58350675Swpaul mii = device_get_softc(sc->wb_miibus); 58450675Swpaul wb_setcfg(sc, mii->mii_media_active); 58567087Swpaul WB_UNLOCK(sc); 58650675Swpaul 58741502Swpaul return; 58841502Swpaul} 58941502Swpaul 590122625Sobrienstatic u_int32_t 591122625Sobrienwb_mchash(addr) 592122625Sobrien caddr_t addr; 59341502Swpaul{ 594122625Sobrien u_int32_t crc, carry; 595122625Sobrien int idx, bit; 596122625Sobrien u_int8_t data; 59741502Swpaul 59841502Swpaul /* Compute CRC for the address value. */ 59941502Swpaul crc = 0xFFFFFFFF; /* initial value */ 60041502Swpaul 601122625Sobrien for (idx = 0; idx < 6; idx++) { 602122625Sobrien for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 603122625Sobrien carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 60441502Swpaul crc <<= 1; 60541502Swpaul if (carry) 60641502Swpaul crc = (crc ^ 0x04c11db6) | carry; 60741502Swpaul } 60841502Swpaul } 60941502Swpaul 61041502Swpaul /* 61141502Swpaul * return the filter bit position 61241502Swpaul * Note: I arrived at the following nonsense 61341502Swpaul * through experimentation. It's not the usual way to 61441502Swpaul * generate the bit position but it's the only thing 61541502Swpaul * I could come up with that works. 61641502Swpaul */ 61741502Swpaul return(~(crc >> 26) & 0x0000003F); 61841502Swpaul} 61941502Swpaul 62041502Swpaul/* 62141502Swpaul * Program the 64-bit multicast hash filter. 62241502Swpaul */ 623102336Salfredstatic void 624102336Salfredwb_setmulti(sc) 62541502Swpaul struct wb_softc *sc; 62641502Swpaul{ 62741502Swpaul struct ifnet *ifp; 62841502Swpaul int h = 0; 62941502Swpaul u_int32_t hashes[2] = { 0, 0 }; 63041502Swpaul struct ifmultiaddr *ifma; 63141502Swpaul u_int32_t rxfilt; 63241502Swpaul int mcnt = 0; 63341502Swpaul 63441502Swpaul ifp = &sc->arpcom.ac_if; 63541502Swpaul 63641502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 63741502Swpaul 63841502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 63941502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 64041502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 64141502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 64241502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 64341502Swpaul return; 64441502Swpaul } 64541502Swpaul 64641502Swpaul /* first, zot all the existing hash bits */ 64741502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 64841502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 64941502Swpaul 65041502Swpaul /* now program new ones */ 65172084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 65241502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 65341502Swpaul continue; 654122625Sobrien h = wb_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 65541502Swpaul if (h < 32) 65641502Swpaul hashes[0] |= (1 << h); 65741502Swpaul else 65841502Swpaul hashes[1] |= (1 << (h - 32)); 65941502Swpaul mcnt++; 66041502Swpaul } 66141502Swpaul 66241502Swpaul if (mcnt) 66341502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 66441502Swpaul else 66541502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 66641502Swpaul 66741502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 66841502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 66941502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 67041502Swpaul 67141502Swpaul return; 67241502Swpaul} 67341502Swpaul 67441502Swpaul/* 67541502Swpaul * The Winbond manual states that in order to fiddle with the 67641502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 67741502Swpaul * first have to put the transmit and/or receive logic in the idle state. 67841502Swpaul */ 679102336Salfredstatic void 680102336Salfredwb_setcfg(sc, media) 68141502Swpaul struct wb_softc *sc; 68250675Swpaul u_int32_t media; 68341502Swpaul{ 68441502Swpaul int i, restart = 0; 68541502Swpaul 68641502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 68741502Swpaul restart = 1; 68841502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 68941502Swpaul 69041502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69141502Swpaul DELAY(10); 69241502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 69341502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 69441502Swpaul break; 69541502Swpaul } 69641502Swpaul 69741502Swpaul if (i == WB_TIMEOUT) 69841502Swpaul printf("wb%d: failed to force tx and " 69941502Swpaul "rx to idle state\n", sc->wb_unit); 70041502Swpaul } 70141502Swpaul 70250675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 70350675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70450675Swpaul else 70541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70641502Swpaul 70750675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 70841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 70941502Swpaul else 71041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71141502Swpaul 71241502Swpaul if (restart) 71341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 71441502Swpaul 71541502Swpaul return; 71641502Swpaul} 71741502Swpaul 718102336Salfredstatic void 719102336Salfredwb_reset(sc) 72041502Swpaul struct wb_softc *sc; 72141502Swpaul{ 72241502Swpaul register int i; 72350675Swpaul struct mii_data *mii; 72441502Swpaul 72550675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 72650675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 72750675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 72850675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 72950675Swpaul 73041502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73150675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73241502Swpaul 73341502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 73441502Swpaul DELAY(10); 73541502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 73641502Swpaul break; 73741502Swpaul } 73841502Swpaul if (i == WB_TIMEOUT) 73941502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 74041502Swpaul 74141502Swpaul /* Wait a little while for the chip to get its brains in order. */ 74241502Swpaul DELAY(1000); 74341502Swpaul 74450675Swpaul if (sc->wb_miibus == NULL) 74550675Swpaul return; 74641502Swpaul 74750675Swpaul mii = device_get_softc(sc->wb_miibus); 74850675Swpaul if (mii == NULL) 74950675Swpaul return; 75050675Swpaul 75150675Swpaul if (mii->mii_instance) { 75250675Swpaul struct mii_softc *miisc; 75372012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 75450675Swpaul mii_phy_reset(miisc); 75550675Swpaul } 75650675Swpaul 75741502Swpaul return; 75841502Swpaul} 75941502Swpaul 760102336Salfredstatic void 761102336Salfredwb_fixmedia(sc) 76250675Swpaul struct wb_softc *sc; 76350675Swpaul{ 76450675Swpaul struct mii_data *mii = NULL; 76550675Swpaul struct ifnet *ifp; 76650675Swpaul u_int32_t media; 76750675Swpaul 76850675Swpaul if (sc->wb_miibus == NULL) 76950675Swpaul return; 77050675Swpaul 77150675Swpaul mii = device_get_softc(sc->wb_miibus); 77250675Swpaul ifp = &sc->arpcom.ac_if; 77350675Swpaul 77450675Swpaul mii_pollstat(mii); 77550675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 77650675Swpaul media = mii->mii_media_active & ~IFM_10_T; 77750675Swpaul media |= IFM_100_TX; 77850675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 77950675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 78050675Swpaul media |= IFM_10_T; 78150675Swpaul } else 78250675Swpaul return; 78350675Swpaul 78450675Swpaul ifmedia_set(&mii->mii_media, media); 78550675Swpaul 78650675Swpaul return; 78750675Swpaul} 78850675Swpaul 78941502Swpaul/* 79041502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 79141502Swpaul * IDs against our list and return a device name if we find a match. 79241502Swpaul */ 793102336Salfredstatic int 794102336Salfredwb_probe(dev) 79549611Swpaul device_t dev; 79641502Swpaul{ 79741502Swpaul struct wb_type *t; 79841502Swpaul 79941502Swpaul t = wb_devs; 80041502Swpaul 80141502Swpaul while(t->wb_name != NULL) { 80249611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 80349611Swpaul (pci_get_device(dev) == t->wb_did)) { 80449611Swpaul device_set_desc(dev, t->wb_name); 80549611Swpaul return(0); 80641502Swpaul } 80741502Swpaul t++; 80841502Swpaul } 80941502Swpaul 81049611Swpaul return(ENXIO); 81141502Swpaul} 81241502Swpaul 81341502Swpaul/* 81441502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 81541502Swpaul * setup and ethernet/BPF attach. 81641502Swpaul */ 817102336Salfredstatic int 818102336Salfredwb_attach(dev) 81949611Swpaul device_t dev; 82041502Swpaul{ 82141502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 82241502Swpaul struct wb_softc *sc; 82341502Swpaul struct ifnet *ifp; 82449611Swpaul int unit, error = 0, rid; 82541502Swpaul 82649611Swpaul sc = device_get_softc(dev); 82749611Swpaul unit = device_get_unit(dev); 82841502Swpaul 82993818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 83093818Sjhb MTX_DEF | MTX_RECURSE); 831117208Simp#ifndef BURN_BRIDGES 83241502Swpaul /* 83341502Swpaul * Handle power management nonsense. 83441502Swpaul */ 83541502Swpaul 83672813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 83772813Swpaul u_int32_t iobase, membase, irq; 83841502Swpaul 83972813Swpaul /* Save important PCI config data. */ 84072813Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 84172813Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 84272813Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 84341502Swpaul 84472813Swpaul /* Reset the power state. */ 84572813Swpaul printf("wb%d: chip is in D%d power mode " 84672813Swpaul "-- setting to D0\n", unit, 84772813Swpaul pci_get_powerstate(dev)); 84872813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 84941502Swpaul 85072813Swpaul /* Restore PCI config data. */ 85172813Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 85272813Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 85372813Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 85441502Swpaul } 855117208Simp#endif 85641502Swpaul /* 85741502Swpaul * Map control/status registers. 85841502Swpaul */ 85972813Swpaul pci_enable_busmaster(dev); 86041502Swpaul 86149611Swpaul rid = WB_RID; 86249611Swpaul sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 86349611Swpaul 0, ~0, 1, RF_ACTIVE); 86449611Swpaul 86549611Swpaul if (sc->wb_res == NULL) { 86649611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 86749611Swpaul error = ENXIO; 86841502Swpaul goto fail; 86941502Swpaul } 87041502Swpaul 87149611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 87249611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 87349611Swpaul 87441502Swpaul /* Allocate interrupt */ 87549611Swpaul rid = 0; 87649611Swpaul sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 87749611Swpaul RF_SHAREABLE | RF_ACTIVE); 87849611Swpaul 87949611Swpaul if (sc->wb_irq == NULL) { 88041502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 88149611Swpaul error = ENXIO; 88241502Swpaul goto fail; 88341502Swpaul } 88441502Swpaul 88550675Swpaul /* Save the cache line size. */ 88650675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 88750675Swpaul 88841502Swpaul /* Reset the adapter. */ 88941502Swpaul wb_reset(sc); 89041502Swpaul 89141502Swpaul /* 89241502Swpaul * Get station address from the EEPROM. 89341502Swpaul */ 89441502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 89541502Swpaul 89641502Swpaul /* 89741502Swpaul * A Winbond chip was detected. Inform the world. 89841502Swpaul */ 89941502Swpaul printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 90041502Swpaul 90141502Swpaul sc->wb_unit = unit; 90241502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 90341502Swpaul 90450675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 90551657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 90650675Swpaul 90750675Swpaul if (sc->wb_ldata == NULL) { 90841502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 90949611Swpaul error = ENXIO; 91049611Swpaul goto fail; 91141502Swpaul } 91241502Swpaul 91341502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 91441502Swpaul 91541502Swpaul ifp = &sc->arpcom.ac_if; 91641502Swpaul ifp->if_softc = sc; 917121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 91841502Swpaul ifp->if_mtu = ETHERMTU; 91941502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 92041502Swpaul ifp->if_ioctl = wb_ioctl; 92141502Swpaul ifp->if_output = ether_output; 92241502Swpaul ifp->if_start = wb_start; 92341502Swpaul ifp->if_watchdog = wb_watchdog; 92441502Swpaul ifp->if_init = wb_init; 92541502Swpaul ifp->if_baudrate = 10000000; 92643515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 92741502Swpaul 92850675Swpaul /* 92950675Swpaul * Do MII setup. 93050675Swpaul */ 93150675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 93250675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 93349611Swpaul error = ENXIO; 93441502Swpaul goto fail; 93541502Swpaul } 93641502Swpaul 93741502Swpaul /* 93863090Sarchie * Call MI attach routine. 93941502Swpaul */ 940106936Ssam ether_ifattach(ifp, eaddr); 94141502Swpaul 942113609Snjl /* Hook interrupt last to avoid having to lock softc */ 943112872Snjl error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 944112872Snjl wb_intr, sc, &sc->wb_intrhand); 945112872Snjl 946112872Snjl if (error) { 947112872Snjl printf("wb%d: couldn't set up irq\n", unit); 948113609Snjl ether_ifdetach(ifp); 949112872Snjl goto fail; 950112872Snjl } 951112872Snjl 95241502Swpaulfail: 95350675Swpaul if (error) 954112872Snjl wb_detach(dev); 95550675Swpaul 95649611Swpaul return(error); 95741502Swpaul} 95841502Swpaul 959113609Snjl/* 960113609Snjl * Shutdown hardware and free up resources. This can be called any 961113609Snjl * time after the mutex has been initialized. It is called in both 962113609Snjl * the error case in attach and the normal detach case so it needs 963113609Snjl * to be careful about only freeing resources that have actually been 964113609Snjl * allocated. 965113609Snjl */ 966102336Salfredstatic int 967102336Salfredwb_detach(dev) 96849611Swpaul device_t dev; 96949611Swpaul{ 97049611Swpaul struct wb_softc *sc; 97149611Swpaul struct ifnet *ifp; 97249611Swpaul 97349611Swpaul sc = device_get_softc(dev); 974112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 97567087Swpaul WB_LOCK(sc); 97649611Swpaul ifp = &sc->arpcom.ac_if; 97749611Swpaul 978113609Snjl /* 979113609Snjl * Delete any miibus and phy devices attached to this interface. 980113609Snjl * This should only be done if attach succeeded. 981113609Snjl */ 982113812Simp if (device_is_attached(dev)) { 983113609Snjl wb_stop(sc); 984112872Snjl ether_ifdetach(ifp); 985113609Snjl } 986113609Snjl if (sc->wb_miibus) 987112872Snjl device_delete_child(dev, sc->wb_miibus); 988113609Snjl bus_generic_detach(dev); 98950675Swpaul 990112872Snjl if (sc->wb_intrhand) 991112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 992112872Snjl if (sc->wb_irq) 993112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 994112872Snjl if (sc->wb_res) 995112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 99649611Swpaul 997112872Snjl if (sc->wb_ldata) { 998112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 999112872Snjl M_DEVBUF); 1000112872Snjl } 100149611Swpaul 100267087Swpaul WB_UNLOCK(sc); 100367087Swpaul mtx_destroy(&sc->wb_mtx); 100449611Swpaul 100549611Swpaul return(0); 100649611Swpaul} 100749611Swpaul 100841502Swpaul/* 100941502Swpaul * Initialize the transmit descriptors. 101041502Swpaul */ 1011102336Salfredstatic int 1012102336Salfredwb_list_tx_init(sc) 101341502Swpaul struct wb_softc *sc; 101441502Swpaul{ 101541502Swpaul struct wb_chain_data *cd; 101641502Swpaul struct wb_list_data *ld; 101741502Swpaul int i; 101841502Swpaul 101941502Swpaul cd = &sc->wb_cdata; 102041502Swpaul ld = sc->wb_ldata; 102141502Swpaul 102241502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 102341502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 102441502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 102541502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 102641502Swpaul &cd->wb_tx_chain[0]; 102741502Swpaul } else { 102841502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 102941502Swpaul &cd->wb_tx_chain[i + 1]; 103041502Swpaul } 103141502Swpaul } 103241502Swpaul 103341502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 103441502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 103541502Swpaul 103641502Swpaul return(0); 103741502Swpaul} 103841502Swpaul 103941502Swpaul 104041502Swpaul/* 104141502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 104241502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 104341502Swpaul * points back to the first. 104441502Swpaul */ 1045102336Salfredstatic int 1046102336Salfredwb_list_rx_init(sc) 104741502Swpaul struct wb_softc *sc; 104841502Swpaul{ 104941502Swpaul struct wb_chain_data *cd; 105041502Swpaul struct wb_list_data *ld; 105141502Swpaul int i; 105241502Swpaul 105341502Swpaul cd = &sc->wb_cdata; 105441502Swpaul ld = sc->wb_ldata; 105541502Swpaul 105641502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 105741502Swpaul cd->wb_rx_chain[i].wb_ptr = 105841502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 105950675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 106048745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 106141502Swpaul return(ENOBUFS); 106241502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 106341502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 106441502Swpaul ld->wb_rx_list[i].wb_next = 106541502Swpaul vtophys(&ld->wb_rx_list[0]); 106641502Swpaul } else { 106741502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 106841502Swpaul &cd->wb_rx_chain[i + 1]; 106941502Swpaul ld->wb_rx_list[i].wb_next = 107041502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 107141502Swpaul } 107241502Swpaul } 107341502Swpaul 107441502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 107541502Swpaul 107641502Swpaul return(0); 107741502Swpaul} 107841502Swpaul 1079102336Salfredstatic void 1080102336Salfredwb_bfree(buf, args) 108198995Salfred void *buf; 108264837Sdwmalone void *args; 108350675Swpaul{ 108450675Swpaul return; 108550675Swpaul} 108650675Swpaul 108741502Swpaul/* 108841502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 108941502Swpaul */ 1090102336Salfredstatic int 1091102336Salfredwb_newbuf(sc, c, m) 109241502Swpaul struct wb_softc *sc; 109341502Swpaul struct wb_chain_onefrag *c; 109448745Swpaul struct mbuf *m; 109541502Swpaul{ 109641502Swpaul struct mbuf *m_new = NULL; 109741502Swpaul 109848745Swpaul if (m == NULL) { 1099111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 110087846Sluigi if (m_new == NULL) 110148745Swpaul return(ENOBUFS); 110264837Sdwmalone m_new->m_data = c->wb_buf; 110364837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 110468621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 110568621Sbmilekic EXT_NET_DRV); 110648745Swpaul } else { 110748745Swpaul m_new = m; 110850675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 110948745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 111041502Swpaul } 111141502Swpaul 111248745Swpaul m_adj(m_new, sizeof(u_int64_t)); 111348745Swpaul 111441502Swpaul c->wb_mbuf = m_new; 111541502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 111650675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 111741502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 111841502Swpaul 111941502Swpaul return(0); 112041502Swpaul} 112141502Swpaul 112241502Swpaul/* 112341502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 112441502Swpaul * the higher level protocols. 112541502Swpaul */ 1126102336Salfredstatic void 1127102336Salfredwb_rxeof(sc) 112841502Swpaul struct wb_softc *sc; 112941502Swpaul{ 113050675Swpaul struct mbuf *m = NULL; 113141502Swpaul struct ifnet *ifp; 113241502Swpaul struct wb_chain_onefrag *cur_rx; 113341502Swpaul int total_len = 0; 113441502Swpaul u_int32_t rxstat; 113541502Swpaul 113641502Swpaul ifp = &sc->arpcom.ac_if; 113741502Swpaul 113841502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 113941502Swpaul WB_RXSTAT_OWN)) { 114048745Swpaul struct mbuf *m0 = NULL; 114148745Swpaul 114241502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 114341502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 114450675Swpaul 114548745Swpaul m = cur_rx->wb_mbuf; 114641502Swpaul 114750675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 114850675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 114950675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 115050675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 115150675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 115241502Swpaul ifp->if_ierrors++; 115350675Swpaul wb_newbuf(sc, cur_rx, m); 115441502Swpaul printf("wb%x: receiver babbling: possible chip " 115541502Swpaul "bug, forcing reset\n", sc->wb_unit); 115650675Swpaul wb_fixmedia(sc); 115750675Swpaul wb_reset(sc); 115850675Swpaul wb_init(sc); 115941502Swpaul return; 116041502Swpaul } 116141502Swpaul 116242718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 116342718Swpaul ifp->if_ierrors++; 116448745Swpaul wb_newbuf(sc, cur_rx, m); 116550675Swpaul break; 116642718Swpaul } 116742718Swpaul 116841502Swpaul /* No errors; receive the packet. */ 116941502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 117041502Swpaul 117141502Swpaul /* 117241934Swpaul * XXX The Winbond chip includes the CRC with every 117341934Swpaul * received frame, and there's no way to turn this 117441934Swpaul * behavior off (at least, I can't find anything in 117541934Swpaul * the manual that explains how to do it) so we have 117641934Swpaul * to trim off the CRC manually. 117741934Swpaul */ 117841934Swpaul total_len -= ETHER_CRC_LEN; 117941934Swpaul 118078508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 118178508Sbmilekic NULL); 118248745Swpaul wb_newbuf(sc, cur_rx, m); 118348745Swpaul if (m0 == NULL) { 118448745Swpaul ifp->if_ierrors++; 118550675Swpaul break; 118641502Swpaul } 118748745Swpaul m = m0; 118841502Swpaul 118941502Swpaul ifp->if_ipackets++; 1190106936Ssam (*ifp->if_input)(ifp, m); 119141502Swpaul } 119241502Swpaul} 119341502Swpaul 1194105221Sphkstatic void 1195102336Salfredwb_rxeoc(sc) 119641502Swpaul struct wb_softc *sc; 119741502Swpaul{ 119841502Swpaul wb_rxeof(sc); 119941502Swpaul 120041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120141502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 120241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120341502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 120441502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 120541502Swpaul 120641502Swpaul return; 120741502Swpaul} 120841502Swpaul 120941502Swpaul/* 121041502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 121141502Swpaul * the list buffers. 121241502Swpaul */ 1213102336Salfredstatic void 1214102336Salfredwb_txeof(sc) 121541502Swpaul struct wb_softc *sc; 121641502Swpaul{ 121741502Swpaul struct wb_chain *cur_tx; 121841502Swpaul struct ifnet *ifp; 121941502Swpaul 122041502Swpaul ifp = &sc->arpcom.ac_if; 122141502Swpaul 122241502Swpaul /* Clear the timeout timer. */ 122341502Swpaul ifp->if_timer = 0; 122441502Swpaul 122541502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 122641502Swpaul return; 122741502Swpaul 122841502Swpaul /* 122941502Swpaul * Go through our tx list and free mbufs for those 123041502Swpaul * frames that have been transmitted. 123141502Swpaul */ 123241502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 123341502Swpaul u_int32_t txstat; 123441502Swpaul 123541502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 123641502Swpaul txstat = WB_TXSTATUS(cur_tx); 123741502Swpaul 123841502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 123941502Swpaul break; 124041502Swpaul 124141502Swpaul if (txstat & WB_TXSTAT_TXERR) { 124241502Swpaul ifp->if_oerrors++; 124341502Swpaul if (txstat & WB_TXSTAT_ABORT) 124441502Swpaul ifp->if_collisions++; 124541502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 124641502Swpaul ifp->if_collisions++; 124741502Swpaul } 124841502Swpaul 124941502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 125041502Swpaul 125141502Swpaul ifp->if_opackets++; 125241502Swpaul m_freem(cur_tx->wb_mbuf); 125341502Swpaul cur_tx->wb_mbuf = NULL; 125441502Swpaul 125541502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 125641502Swpaul sc->wb_cdata.wb_tx_head = NULL; 125741502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 125841502Swpaul break; 125941502Swpaul } 126041502Swpaul 126141502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 126241502Swpaul } 126341502Swpaul 126441502Swpaul return; 126541502Swpaul} 126641502Swpaul 126741502Swpaul/* 126841502Swpaul * TX 'end of channel' interrupt handler. 126941502Swpaul */ 1270102336Salfredstatic void 1271102336Salfredwb_txeoc(sc) 127241502Swpaul struct wb_softc *sc; 127341502Swpaul{ 127441502Swpaul struct ifnet *ifp; 127541502Swpaul 127641502Swpaul ifp = &sc->arpcom.ac_if; 127741502Swpaul 127841502Swpaul ifp->if_timer = 0; 127941502Swpaul 128041502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 128141502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 128241502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 128341502Swpaul } else { 128441502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 128541502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 128641502Swpaul ifp->if_timer = 5; 128741502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 128841502Swpaul } 128941502Swpaul } 129041502Swpaul 129141502Swpaul return; 129241502Swpaul} 129341502Swpaul 1294102336Salfredstatic void 1295102336Salfredwb_intr(arg) 129641502Swpaul void *arg; 129741502Swpaul{ 129841502Swpaul struct wb_softc *sc; 129941502Swpaul struct ifnet *ifp; 130041502Swpaul u_int32_t status; 130141502Swpaul 130241502Swpaul sc = arg; 130367087Swpaul WB_LOCK(sc); 130441502Swpaul ifp = &sc->arpcom.ac_if; 130541502Swpaul 130667087Swpaul if (!(ifp->if_flags & IFF_UP)) { 130767087Swpaul WB_UNLOCK(sc); 130841502Swpaul return; 130967087Swpaul } 131041502Swpaul 131141502Swpaul /* Disable interrupts. */ 131241502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 131341502Swpaul 131441502Swpaul for (;;) { 131541502Swpaul 131641502Swpaul status = CSR_READ_4(sc, WB_ISR); 131741502Swpaul if (status) 131841502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 131941502Swpaul 132041502Swpaul if ((status & WB_INTRS) == 0) 132141502Swpaul break; 132241502Swpaul 132341502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 132441502Swpaul ifp->if_ierrors++; 132541502Swpaul wb_reset(sc); 132650675Swpaul if (status & WB_ISR_RX_ERR) 132750675Swpaul wb_fixmedia(sc); 132841502Swpaul wb_init(sc); 132950675Swpaul continue; 133041502Swpaul } 133141502Swpaul 133250675Swpaul if (status & WB_ISR_RX_OK) 133350675Swpaul wb_rxeof(sc); 133450675Swpaul 133550675Swpaul if (status & WB_ISR_RX_IDLE) 133650675Swpaul wb_rxeoc(sc); 133750675Swpaul 133841502Swpaul if (status & WB_ISR_TX_OK) 133941502Swpaul wb_txeof(sc); 134041502Swpaul 134141502Swpaul if (status & WB_ISR_TX_NOBUF) 134241502Swpaul wb_txeoc(sc); 134341502Swpaul 134441502Swpaul if (status & WB_ISR_TX_IDLE) { 134541502Swpaul wb_txeof(sc); 134641502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 134741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 134841502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 134941502Swpaul } 135041502Swpaul } 135141502Swpaul 135241502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 135341502Swpaul ifp->if_oerrors++; 135441502Swpaul wb_txeof(sc); 135541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135641502Swpaul /* Jack up TX threshold */ 135741502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 135841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 135941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 136041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136141502Swpaul } 136241502Swpaul 136341502Swpaul if (status & WB_ISR_BUS_ERR) { 136441502Swpaul wb_reset(sc); 136541502Swpaul wb_init(sc); 136641502Swpaul } 136741502Swpaul 136841502Swpaul } 136941502Swpaul 137041502Swpaul /* Re-enable interrupts. */ 137141502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 137241502Swpaul 137341502Swpaul if (ifp->if_snd.ifq_head != NULL) { 137441502Swpaul wb_start(ifp); 137541502Swpaul } 137641502Swpaul 137767087Swpaul WB_UNLOCK(sc); 137867087Swpaul 137941502Swpaul return; 138041502Swpaul} 138141502Swpaul 1382102336Salfredstatic void 1383102336Salfredwb_tick(xsc) 138450675Swpaul void *xsc; 138550675Swpaul{ 138650675Swpaul struct wb_softc *sc; 138750675Swpaul struct mii_data *mii; 138850675Swpaul 138950675Swpaul sc = xsc; 139067087Swpaul WB_LOCK(sc); 139150675Swpaul mii = device_get_softc(sc->wb_miibus); 139250675Swpaul 139350675Swpaul mii_tick(mii); 139450675Swpaul 139550675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 139650675Swpaul 139767087Swpaul WB_UNLOCK(sc); 139850685Swpaul 139950675Swpaul return; 140050675Swpaul} 140150675Swpaul 140241502Swpaul/* 140341502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 140441502Swpaul * pointers to the fragment pointers. 140541502Swpaul */ 1406102336Salfredstatic int 1407102336Salfredwb_encap(sc, c, m_head) 140841502Swpaul struct wb_softc *sc; 140941502Swpaul struct wb_chain *c; 141041502Swpaul struct mbuf *m_head; 141141502Swpaul{ 141241502Swpaul int frag = 0; 141341502Swpaul struct wb_desc *f = NULL; 141441502Swpaul int total_len; 141541502Swpaul struct mbuf *m; 141641502Swpaul 141741502Swpaul /* 141841502Swpaul * Start packing the mbufs in this chain into 141941502Swpaul * the fragment pointers. Stop when we run out 142041502Swpaul * of fragments or hit the end of the mbuf chain. 142141502Swpaul */ 142241502Swpaul m = m_head; 142341502Swpaul total_len = 0; 142441502Swpaul 142541502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 142641502Swpaul if (m->m_len != 0) { 142741502Swpaul if (frag == WB_MAXFRAGS) 142841502Swpaul break; 142941502Swpaul total_len += m->m_len; 143041502Swpaul f = &c->wb_ptr->wb_frag[frag]; 143141502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 143241502Swpaul if (frag == 0) { 143341502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 143441502Swpaul f->wb_status = 0; 143541502Swpaul } else 143641502Swpaul f->wb_status = WB_TXSTAT_OWN; 143741502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 143841502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 143941502Swpaul frag++; 144041502Swpaul } 144141502Swpaul } 144241502Swpaul 144341502Swpaul /* 144441502Swpaul * Handle special case: we used up all 16 fragments, 144541502Swpaul * but we have more mbufs left in the chain. Copy the 144641502Swpaul * data into an mbuf cluster. Note that we don't 144741502Swpaul * bother clearing the values in the other fragment 144841502Swpaul * pointers/counters; it wouldn't gain us anything, 144941502Swpaul * and would waste cycles. 145041502Swpaul */ 145141502Swpaul if (m != NULL) { 145241502Swpaul struct mbuf *m_new = NULL; 145341502Swpaul 1454111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145587846Sluigi if (m_new == NULL) 145641502Swpaul return(1); 145741502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1458111119Simp MCLGET(m_new, M_DONTWAIT); 145941502Swpaul if (!(m_new->m_flags & M_EXT)) { 146041502Swpaul m_freem(m_new); 146141502Swpaul return(1); 146241502Swpaul } 146341502Swpaul } 146441502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 146541502Swpaul mtod(m_new, caddr_t)); 146641502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 146741502Swpaul m_freem(m_head); 146841502Swpaul m_head = m_new; 146941502Swpaul f = &c->wb_ptr->wb_frag[0]; 147041502Swpaul f->wb_status = 0; 147141502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 147241502Swpaul f->wb_ctl = total_len = m_new->m_len; 147341502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 147441502Swpaul frag = 1; 147541502Swpaul } 147641502Swpaul 147741502Swpaul if (total_len < WB_MIN_FRAMELEN) { 147841502Swpaul f = &c->wb_ptr->wb_frag[frag]; 147941502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 148041502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 148141502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 148241502Swpaul f->wb_status = WB_TXSTAT_OWN; 148341502Swpaul frag++; 148441502Swpaul } 148541502Swpaul 148641502Swpaul c->wb_mbuf = m_head; 148741502Swpaul c->wb_lastdesc = frag - 1; 148841502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 148941502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 149041502Swpaul 149141502Swpaul return(0); 149241502Swpaul} 149341502Swpaul 149441502Swpaul/* 149541502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 149641502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 149741502Swpaul * copy of the pointers since the transmit list fragment pointers are 149841502Swpaul * physical addresses. 149941502Swpaul */ 150041502Swpaul 1501102336Salfredstatic void 1502102336Salfredwb_start(ifp) 150341502Swpaul struct ifnet *ifp; 150441502Swpaul{ 150541502Swpaul struct wb_softc *sc; 150641502Swpaul struct mbuf *m_head = NULL; 150741502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 150841502Swpaul 150941502Swpaul sc = ifp->if_softc; 151067087Swpaul WB_LOCK(sc); 151141502Swpaul 151241502Swpaul /* 151341502Swpaul * Check for an available queue slot. If there are none, 151441502Swpaul * punt. 151541502Swpaul */ 151641502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 151741502Swpaul ifp->if_flags |= IFF_OACTIVE; 151867087Swpaul WB_UNLOCK(sc); 151941502Swpaul return; 152041502Swpaul } 152141502Swpaul 152241502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 152341502Swpaul 152441502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 152541502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 152641502Swpaul if (m_head == NULL) 152741502Swpaul break; 152841502Swpaul 152941502Swpaul /* Pick a descriptor off the free list. */ 153041502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 153141502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 153241502Swpaul 153341502Swpaul /* Pack the data into the descriptor. */ 153441502Swpaul wb_encap(sc, cur_tx, m_head); 153541502Swpaul 153641502Swpaul if (cur_tx != start_tx) 153741502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 153841502Swpaul 153941502Swpaul /* 154041502Swpaul * If there's a BPF listener, bounce a copy of this frame 154141502Swpaul * to him. 154241502Swpaul */ 1543106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 154441502Swpaul } 154541502Swpaul 154641502Swpaul /* 154741526Swpaul * If there are no packets queued, bail. 154841526Swpaul */ 154967087Swpaul if (cur_tx == NULL) { 155067087Swpaul WB_UNLOCK(sc); 155141526Swpaul return; 155267087Swpaul } 155341526Swpaul 155441526Swpaul /* 155541502Swpaul * Place the request for the upload interrupt 155641502Swpaul * in the last descriptor in the chain. This way, if 155741502Swpaul * we're chaining several packets at once, we'll only 155841502Swpaul * get an interupt once for the whole chain rather than 155941502Swpaul * once for each packet. 156041502Swpaul */ 156141502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 156242718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 156341502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 156441502Swpaul 156541502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 156641502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 156741502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 156841502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 156941502Swpaul } else { 157041502Swpaul /* 157141502Swpaul * We need to distinguish between the case where 157241502Swpaul * the own bit is clear because the chip cleared it 157341502Swpaul * and where the own bit is clear because we haven't 157441502Swpaul * set it yet. The magic value WB_UNSET is just some 157541502Swpaul * ramdomly chosen number which doesn't have the own 157641502Swpaul * bit set. When we actually transmit the frame, the 157741502Swpaul * status word will have _only_ the own bit set, so 157841502Swpaul * the txeoc handler will be able to tell if it needs 157941502Swpaul * to initiate another transmission to flush out pending 158041502Swpaul * frames. 158141502Swpaul */ 158241502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 158341502Swpaul } 158441502Swpaul 158541502Swpaul /* 158641502Swpaul * Set a timeout in case the chip goes out to lunch. 158741502Swpaul */ 158841502Swpaul ifp->if_timer = 5; 158967087Swpaul WB_UNLOCK(sc); 159041502Swpaul 159141502Swpaul return; 159241502Swpaul} 159341502Swpaul 1594102336Salfredstatic void 1595102336Salfredwb_init(xsc) 159641502Swpaul void *xsc; 159741502Swpaul{ 159841502Swpaul struct wb_softc *sc = xsc; 159941502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160067087Swpaul int i; 160150675Swpaul struct mii_data *mii; 160241502Swpaul 160367087Swpaul WB_LOCK(sc); 160450675Swpaul mii = device_get_softc(sc->wb_miibus); 160541502Swpaul 160641502Swpaul /* 160741502Swpaul * Cancel pending I/O and free all RX/TX buffers. 160841502Swpaul */ 160941502Swpaul wb_stop(sc); 161041502Swpaul wb_reset(sc); 161141502Swpaul 161241502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 161341502Swpaul 161441502Swpaul /* 161541502Swpaul * Set cache alignment and burst length. 161641502Swpaul */ 161750675Swpaul#ifdef foo 161841502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 161941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 162041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 162150675Swpaul#endif 162241502Swpaul 162350675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 162450675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 162550675Swpaul switch(sc->wb_cachesize) { 162650675Swpaul case 32: 162750675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 162850675Swpaul break; 162950675Swpaul case 16: 163050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 163150675Swpaul break; 163250675Swpaul case 8: 163350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 163450675Swpaul break; 163550675Swpaul case 0: 163650675Swpaul default: 163750675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 163850675Swpaul break; 163950675Swpaul } 164050675Swpaul 164141502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 164241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 164341502Swpaul 164441502Swpaul /* Init our MAC address */ 164541502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 164641502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 164741502Swpaul } 164841502Swpaul 164941502Swpaul /* Init circular RX list. */ 165041502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 165141502Swpaul printf("wb%d: initialization failed: no " 165241502Swpaul "memory for rx buffers\n", sc->wb_unit); 165341502Swpaul wb_stop(sc); 165467087Swpaul WB_UNLOCK(sc); 165541502Swpaul return; 165641502Swpaul } 165741502Swpaul 165841502Swpaul /* Init TX descriptors. */ 165941502Swpaul wb_list_tx_init(sc); 166041502Swpaul 166141502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 166241502Swpaul if (ifp->if_flags & IFF_PROMISC) { 166341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166441502Swpaul } else { 166541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166641502Swpaul } 166741502Swpaul 166841502Swpaul /* 166941502Swpaul * Set capture broadcast bit to capture broadcast frames. 167041502Swpaul */ 167141502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 167241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167341502Swpaul } else { 167441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167541502Swpaul } 167641502Swpaul 167741502Swpaul /* 167841502Swpaul * Program the multicast filter, if necessary. 167941502Swpaul */ 168041502Swpaul wb_setmulti(sc); 168141502Swpaul 168241502Swpaul /* 168341502Swpaul * Load the address of the RX list. 168441502Swpaul */ 168541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 168641502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 168741502Swpaul 168841502Swpaul /* 168941502Swpaul * Enable interrupts. 169041502Swpaul */ 169141502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 169241502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 169341502Swpaul 169441502Swpaul /* Enable receiver and transmitter. */ 169541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 169641502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 169741502Swpaul 169841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 169941502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 170041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170141502Swpaul 170250675Swpaul mii_mediachg(mii); 170341502Swpaul 170441502Swpaul ifp->if_flags |= IFF_RUNNING; 170541502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 170641502Swpaul 170750675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 170867087Swpaul WB_UNLOCK(sc); 170950675Swpaul 171041502Swpaul return; 171141502Swpaul} 171241502Swpaul 171341502Swpaul/* 171441502Swpaul * Set media options. 171541502Swpaul */ 1716102336Salfredstatic int 1717102336Salfredwb_ifmedia_upd(ifp) 171841502Swpaul struct ifnet *ifp; 171941502Swpaul{ 172041502Swpaul struct wb_softc *sc; 172141502Swpaul 172241502Swpaul sc = ifp->if_softc; 172341502Swpaul 172450675Swpaul if (ifp->if_flags & IFF_UP) 172550675Swpaul wb_init(sc); 172641502Swpaul 172741502Swpaul return(0); 172841502Swpaul} 172941502Swpaul 173041502Swpaul/* 173141502Swpaul * Report current media status. 173241502Swpaul */ 1733102336Salfredstatic void 1734102336Salfredwb_ifmedia_sts(ifp, ifmr) 173541502Swpaul struct ifnet *ifp; 173641502Swpaul struct ifmediareq *ifmr; 173741502Swpaul{ 173841502Swpaul struct wb_softc *sc; 173950675Swpaul struct mii_data *mii; 174041502Swpaul 174141502Swpaul sc = ifp->if_softc; 174241502Swpaul 174350675Swpaul mii = device_get_softc(sc->wb_miibus); 174441502Swpaul 174550675Swpaul mii_pollstat(mii); 174650675Swpaul ifmr->ifm_active = mii->mii_media_active; 174750675Swpaul ifmr->ifm_status = mii->mii_media_status; 174841502Swpaul 174941502Swpaul return; 175041502Swpaul} 175141502Swpaul 1752102336Salfredstatic int 1753102336Salfredwb_ioctl(ifp, command, data) 175441502Swpaul struct ifnet *ifp; 175541502Swpaul u_long command; 175641502Swpaul caddr_t data; 175741502Swpaul{ 175841502Swpaul struct wb_softc *sc = ifp->if_softc; 175950675Swpaul struct mii_data *mii; 176041502Swpaul struct ifreq *ifr = (struct ifreq *) data; 176167087Swpaul int error = 0; 176241502Swpaul 176367087Swpaul WB_LOCK(sc); 176441502Swpaul 176541502Swpaul switch(command) { 176641502Swpaul case SIOCSIFFLAGS: 176741502Swpaul if (ifp->if_flags & IFF_UP) { 176841502Swpaul wb_init(sc); 176941502Swpaul } else { 177041502Swpaul if (ifp->if_flags & IFF_RUNNING) 177141502Swpaul wb_stop(sc); 177241502Swpaul } 177341502Swpaul error = 0; 177441502Swpaul break; 177541502Swpaul case SIOCADDMULTI: 177641502Swpaul case SIOCDELMULTI: 177741502Swpaul wb_setmulti(sc); 177841502Swpaul error = 0; 177941502Swpaul break; 178041502Swpaul case SIOCGIFMEDIA: 178141502Swpaul case SIOCSIFMEDIA: 178250675Swpaul mii = device_get_softc(sc->wb_miibus); 178350675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 178441502Swpaul break; 178541502Swpaul default: 1786106936Ssam error = ether_ioctl(ifp, command, data); 178741502Swpaul break; 178841502Swpaul } 178941502Swpaul 179067087Swpaul WB_UNLOCK(sc); 179141502Swpaul 179241502Swpaul return(error); 179341502Swpaul} 179441502Swpaul 1795102336Salfredstatic void 1796102336Salfredwb_watchdog(ifp) 179741502Swpaul struct ifnet *ifp; 179841502Swpaul{ 179941502Swpaul struct wb_softc *sc; 180041502Swpaul 180141502Swpaul sc = ifp->if_softc; 180241502Swpaul 180367087Swpaul WB_LOCK(sc); 180441502Swpaul ifp->if_oerrors++; 180541502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 180650675Swpaul#ifdef foo 180741502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 180841502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 180941502Swpaul sc->wb_unit); 181050675Swpaul#endif 181141502Swpaul wb_stop(sc); 181241502Swpaul wb_reset(sc); 181341502Swpaul wb_init(sc); 181441502Swpaul 181541502Swpaul if (ifp->if_snd.ifq_head != NULL) 181641502Swpaul wb_start(ifp); 181767087Swpaul WB_UNLOCK(sc); 181841502Swpaul 181941502Swpaul return; 182041502Swpaul} 182141502Swpaul 182241502Swpaul/* 182341502Swpaul * Stop the adapter and free any mbufs allocated to the 182441502Swpaul * RX and TX lists. 182541502Swpaul */ 1826102336Salfredstatic void 1827102336Salfredwb_stop(sc) 182841502Swpaul struct wb_softc *sc; 182941502Swpaul{ 183041502Swpaul register int i; 183141502Swpaul struct ifnet *ifp; 183241502Swpaul 183367087Swpaul WB_LOCK(sc); 183441502Swpaul ifp = &sc->arpcom.ac_if; 183541502Swpaul ifp->if_timer = 0; 183641502Swpaul 183750675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 183850675Swpaul 183941502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 184041502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 184141502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 184241502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 184341502Swpaul 184441502Swpaul /* 184541502Swpaul * Free data in the RX lists. 184641502Swpaul */ 184741502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 184841502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 184941502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 185041502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 185141502Swpaul } 185241502Swpaul } 185341502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 185441502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 185541502Swpaul 185641502Swpaul /* 185741502Swpaul * Free the TX list buffers. 185841502Swpaul */ 185941502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 186041502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 186141502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 186241502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 186341502Swpaul } 186441502Swpaul } 186541502Swpaul 186641502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 186741502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 186841502Swpaul 186941502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 187067087Swpaul WB_UNLOCK(sc); 187141502Swpaul 187241502Swpaul return; 187341502Swpaul} 187441502Swpaul 187541502Swpaul/* 187641502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 187741502Swpaul * get confused by errant DMAs when rebooting. 187841502Swpaul */ 1879102336Salfredstatic void 1880102336Salfredwb_shutdown(dev) 188149611Swpaul device_t dev; 188241502Swpaul{ 188349611Swpaul struct wb_softc *sc; 188441502Swpaul 188549611Swpaul sc = device_get_softc(dev); 188641502Swpaul wb_stop(sc); 188741502Swpaul 188841502Swpaul return; 188941502Swpaul} 1890