if_wb.c revision 117208
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 3341502Swpaul/* 3441502Swpaul * Winbond fast ethernet PCI NIC driver 3541502Swpaul * 3641502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 3741502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 3841502Swpaul * Winbond itself and some made by Linksys. 3941502Swpaul * 4041502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4141502Swpaul * Electrical Engineering Department 4241502Swpaul * Columbia University, New York City 4341502Swpaul */ 4441502Swpaul 4541502Swpaul/* 4641502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4741502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 4841502Swpaul * one major difference which is that while the registers do many of 4941502Swpaul * the same things as a tulip adapter, the offsets are different: where 5041502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5141502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5241502Swpaul * programmed differently. 5341502Swpaul * 5441502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5541502Swpaul * a status word, a control word and 32-bit areas that can either be used 5641502Swpaul * to point to two external data blocks, or to point to a single block 5741502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 5841502Swpaul * together in blocks to form fixed length rings or can be chained 5941502Swpaul * together in linked lists. A single packet may be spread out over 6041502Swpaul * several descriptors if necessary. 6141502Swpaul * 6241502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6341502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6441502Swpaul * to hold an entire packet. The link list is looped back to created a 6541502Swpaul * closed ring. 6641502Swpaul * 6741502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 6841502Swpaul * which each contain several individual descriptors linked toghether. 6941502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7041502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7141502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7241502Swpaul * drivers. 7341502Swpaul * 7441502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7541502Swpaul * The sample boards I have all use a Davicom PHY. 7641502Swpaul * 7741502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 7841502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 7941502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8041502Swpaul * I have no idea what he's on about: transmit performance with all 8141502Swpaul * three of my test boards seems fine. 8241502Swpaul */ 8341502Swpaul 84113038Sobrien#include <sys/cdefs.h> 85113038Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 117208 2003-07-03 21:39:53Z imp $"); 86113038Sobrien 8748745Swpaul#include "opt_bdg.h" 8841502Swpaul 8941502Swpaul#include <sys/param.h> 9041502Swpaul#include <sys/systm.h> 9141502Swpaul#include <sys/sockio.h> 9241502Swpaul#include <sys/mbuf.h> 9341502Swpaul#include <sys/malloc.h> 9441502Swpaul#include <sys/kernel.h> 9541502Swpaul#include <sys/socket.h> 9650675Swpaul#include <sys/queue.h> 9741502Swpaul 9841502Swpaul#include <net/if.h> 9941502Swpaul#include <net/if_arp.h> 10041502Swpaul#include <net/ethernet.h> 10141502Swpaul#include <net/if_dl.h> 10241502Swpaul#include <net/if_media.h> 10341502Swpaul 10441502Swpaul#include <net/bpf.h> 10541502Swpaul 10641502Swpaul#include <vm/vm.h> /* for vtophys */ 10741502Swpaul#include <vm/pmap.h> /* for vtophys */ 10841502Swpaul#include <machine/bus_memio.h> 10941502Swpaul#include <machine/bus_pio.h> 11041502Swpaul#include <machine/bus.h> 11149611Swpaul#include <machine/resource.h> 11249611Swpaul#include <sys/bus.h> 11349611Swpaul#include <sys/rman.h> 11441502Swpaul 11541502Swpaul#include <pci/pcireg.h> 11641502Swpaul#include <pci/pcivar.h> 11741502Swpaul 11850675Swpaul#include <dev/mii/mii.h> 11950675Swpaul#include <dev/mii/miivar.h> 12050675Swpaul 12151089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12250675Swpaul#include "miibus_if.h" 12350675Swpaul 12441502Swpaul#define WB_USEIOSPACE 12541502Swpaul 12641502Swpaul#include <pci/if_wbreg.h> 12741502Swpaul 128113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 129113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 13059758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 13159758Speter 13241502Swpaul/* 13341502Swpaul * Various supported device vendors/types and their names. 13441502Swpaul */ 13541502Swpaulstatic struct wb_type wb_devs[] = { 13641502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13741502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13841502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13941502Swpaul "Compex RL100-ATX 10/100baseTX" }, 14041502Swpaul { 0, 0, NULL } 14141502Swpaul}; 14241502Swpaul 14392739Salfredstatic int wb_probe (device_t); 14492739Salfredstatic int wb_attach (device_t); 14592739Salfredstatic int wb_detach (device_t); 14641502Swpaul 14798995Salfredstatic void wb_bfree (void *addr, void *args); 14892739Salfredstatic int wb_newbuf (struct wb_softc *, 14948745Swpaul struct wb_chain_onefrag *, 15092739Salfred struct mbuf *); 15192739Salfredstatic int wb_encap (struct wb_softc *, struct wb_chain *, 15292739Salfred struct mbuf *); 15341502Swpaul 15492739Salfredstatic void wb_rxeof (struct wb_softc *); 15592739Salfredstatic void wb_rxeoc (struct wb_softc *); 15692739Salfredstatic void wb_txeof (struct wb_softc *); 15792739Salfredstatic void wb_txeoc (struct wb_softc *); 15892739Salfredstatic void wb_intr (void *); 15992739Salfredstatic void wb_tick (void *); 16092739Salfredstatic void wb_start (struct ifnet *); 16192739Salfredstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 16292739Salfredstatic void wb_init (void *); 16392739Salfredstatic void wb_stop (struct wb_softc *); 16492739Salfredstatic void wb_watchdog (struct ifnet *); 16592739Salfredstatic void wb_shutdown (device_t); 16692739Salfredstatic int wb_ifmedia_upd (struct ifnet *); 16792739Salfredstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 16841502Swpaul 16992739Salfredstatic void wb_eeprom_putbyte (struct wb_softc *, int); 17092739Salfredstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 17192739Salfredstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 17292739Salfredstatic void wb_mii_sync (struct wb_softc *); 17392739Salfredstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 17492739Salfredstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 17592739Salfredstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 17641502Swpaul 17792739Salfredstatic void wb_setcfg (struct wb_softc *, u_int32_t); 17892739Salfredstatic u_int8_t wb_calchash (caddr_t); 17992739Salfredstatic void wb_setmulti (struct wb_softc *); 18092739Salfredstatic void wb_reset (struct wb_softc *); 18192739Salfredstatic void wb_fixmedia (struct wb_softc *); 18292739Salfredstatic int wb_list_rx_init (struct wb_softc *); 18392739Salfredstatic int wb_list_tx_init (struct wb_softc *); 18441502Swpaul 18592739Salfredstatic int wb_miibus_readreg (device_t, int, int); 18692739Salfredstatic int wb_miibus_writereg (device_t, int, int, int); 18792739Salfredstatic void wb_miibus_statchg (device_t); 18850675Swpaul 18949611Swpaul#ifdef WB_USEIOSPACE 19049611Swpaul#define WB_RES SYS_RES_IOPORT 19149611Swpaul#define WB_RID WB_PCI_LOIO 19249611Swpaul#else 19349611Swpaul#define WB_RES SYS_RES_MEMORY 19449611Swpaul#define WB_RID WB_PCI_LOMEM 19549611Swpaul#endif 19649611Swpaul 19749611Swpaulstatic device_method_t wb_methods[] = { 19849611Swpaul /* Device interface */ 19949611Swpaul DEVMETHOD(device_probe, wb_probe), 20049611Swpaul DEVMETHOD(device_attach, wb_attach), 20149611Swpaul DEVMETHOD(device_detach, wb_detach), 20249611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20350675Swpaul 20450675Swpaul /* bus interface, for miibus */ 20550675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20650675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20750675Swpaul 20850675Swpaul /* MII interface */ 20950675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 21050675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21150675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21249611Swpaul { 0, 0 } 21349611Swpaul}; 21449611Swpaul 21549611Swpaulstatic driver_t wb_driver = { 21651455Swpaul "wb", 21749611Swpaul wb_methods, 21849611Swpaul sizeof(struct wb_softc) 21949611Swpaul}; 22049611Swpaul 22149611Swpaulstatic devclass_t wb_devclass; 22249611Swpaul 223113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22451473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22549611Swpaul 22641502Swpaul#define WB_SETBIT(sc, reg, x) \ 22741502Swpaul CSR_WRITE_4(sc, reg, \ 228105221Sphk CSR_READ_4(sc, reg) | (x)) 22941502Swpaul 23041502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23141502Swpaul CSR_WRITE_4(sc, reg, \ 232105221Sphk CSR_READ_4(sc, reg) & ~(x)) 23341502Swpaul 23441502Swpaul#define SIO_SET(x) \ 23541502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 236105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23741502Swpaul 23841502Swpaul#define SIO_CLR(x) \ 23941502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 240105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 24141502Swpaul 24241502Swpaul/* 24341502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24441502Swpaul */ 245102336Salfredstatic void 246102336Salfredwb_eeprom_putbyte(sc, addr) 24741502Swpaul struct wb_softc *sc; 24842718Swpaul int addr; 24941502Swpaul{ 25041502Swpaul register int d, i; 25141502Swpaul 25241502Swpaul d = addr | WB_EECMD_READ; 25341502Swpaul 25441502Swpaul /* 25541502Swpaul * Feed in each bit and stobe the clock. 25641502Swpaul */ 25741502Swpaul for (i = 0x400; i; i >>= 1) { 25841502Swpaul if (d & i) { 25941502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 26041502Swpaul } else { 26141502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26241502Swpaul } 26341502Swpaul DELAY(100); 26441502Swpaul SIO_SET(WB_SIO_EE_CLK); 26541502Swpaul DELAY(150); 26641502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26741502Swpaul DELAY(100); 26841502Swpaul } 26941502Swpaul 27041502Swpaul return; 27141502Swpaul} 27241502Swpaul 27341502Swpaul/* 27441502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27541502Swpaul */ 276102336Salfredstatic void 277102336Salfredwb_eeprom_getword(sc, addr, dest) 27841502Swpaul struct wb_softc *sc; 27942718Swpaul int addr; 28041502Swpaul u_int16_t *dest; 28141502Swpaul{ 28241502Swpaul register int i; 28341502Swpaul u_int16_t word = 0; 28441502Swpaul 28541502Swpaul /* Enter EEPROM access mode. */ 28641502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28741502Swpaul 28841502Swpaul /* 28941502Swpaul * Send address of word we want to read. 29041502Swpaul */ 29141502Swpaul wb_eeprom_putbyte(sc, addr); 29241502Swpaul 29341502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29441502Swpaul 29541502Swpaul /* 29641502Swpaul * Start reading bits from EEPROM. 29741502Swpaul */ 29841502Swpaul for (i = 0x8000; i; i >>= 1) { 29941502Swpaul SIO_SET(WB_SIO_EE_CLK); 30041502Swpaul DELAY(100); 30141502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30241502Swpaul word |= i; 30341502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30441502Swpaul DELAY(100); 30541502Swpaul } 30641502Swpaul 30741502Swpaul /* Turn off EEPROM access mode. */ 30841502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30941502Swpaul 31041502Swpaul *dest = word; 31141502Swpaul 31241502Swpaul return; 31341502Swpaul} 31441502Swpaul 31541502Swpaul/* 31641502Swpaul * Read a sequence of words from the EEPROM. 31741502Swpaul */ 318102336Salfredstatic void 319102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 32041502Swpaul struct wb_softc *sc; 32141502Swpaul caddr_t dest; 32241502Swpaul int off; 32341502Swpaul int cnt; 32441502Swpaul int swap; 32541502Swpaul{ 32641502Swpaul int i; 32741502Swpaul u_int16_t word = 0, *ptr; 32841502Swpaul 32941502Swpaul for (i = 0; i < cnt; i++) { 33041502Swpaul wb_eeprom_getword(sc, off + i, &word); 33141502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33241502Swpaul if (swap) 33341502Swpaul *ptr = ntohs(word); 33441502Swpaul else 33541502Swpaul *ptr = word; 33641502Swpaul } 33741502Swpaul 33841502Swpaul return; 33941502Swpaul} 34041502Swpaul 34141502Swpaul/* 34241502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34341502Swpaul */ 344102336Salfredstatic void 345102336Salfredwb_mii_sync(sc) 34641502Swpaul struct wb_softc *sc; 34741502Swpaul{ 34841502Swpaul register int i; 34941502Swpaul 35041502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35141502Swpaul 35241502Swpaul for (i = 0; i < 32; i++) { 35341502Swpaul SIO_SET(WB_SIO_MII_CLK); 35441502Swpaul DELAY(1); 35541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35641502Swpaul DELAY(1); 35741502Swpaul } 35841502Swpaul 35941502Swpaul return; 36041502Swpaul} 36141502Swpaul 36241502Swpaul/* 36341502Swpaul * Clock a series of bits through the MII. 36441502Swpaul */ 365102336Salfredstatic void 366102336Salfredwb_mii_send(sc, bits, cnt) 36741502Swpaul struct wb_softc *sc; 36841502Swpaul u_int32_t bits; 36941502Swpaul int cnt; 37041502Swpaul{ 37141502Swpaul int i; 37241502Swpaul 37341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37441502Swpaul 37541502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37641502Swpaul if (bits & i) { 37741502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37841502Swpaul } else { 37941502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 38041502Swpaul } 38141502Swpaul DELAY(1); 38241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38341502Swpaul DELAY(1); 38441502Swpaul SIO_SET(WB_SIO_MII_CLK); 38541502Swpaul } 38641502Swpaul} 38741502Swpaul 38841502Swpaul/* 38941502Swpaul * Read an PHY register through the MII. 39041502Swpaul */ 391102336Salfredstatic int 392102336Salfredwb_mii_readreg(sc, frame) 39341502Swpaul struct wb_softc *sc; 39441502Swpaul struct wb_mii_frame *frame; 39541502Swpaul 39641502Swpaul{ 39767087Swpaul int i, ack; 39841502Swpaul 39967087Swpaul WB_LOCK(sc); 40041502Swpaul 40141502Swpaul /* 40241502Swpaul * Set up frame for RX. 40341502Swpaul */ 40441502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40541502Swpaul frame->mii_opcode = WB_MII_READOP; 40641502Swpaul frame->mii_turnaround = 0; 40741502Swpaul frame->mii_data = 0; 40841502Swpaul 40941502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 41041502Swpaul 41141502Swpaul /* 41241502Swpaul * Turn on data xmit. 41341502Swpaul */ 41441502Swpaul SIO_SET(WB_SIO_MII_DIR); 41541502Swpaul 41641502Swpaul wb_mii_sync(sc); 41741502Swpaul 41841502Swpaul /* 41941502Swpaul * Send command/address info. 42041502Swpaul */ 42141502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42241502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42341502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42441502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42541502Swpaul 42641502Swpaul /* Idle bit */ 42741502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42841502Swpaul DELAY(1); 42941502Swpaul SIO_SET(WB_SIO_MII_CLK); 43041502Swpaul DELAY(1); 43141502Swpaul 43241502Swpaul /* Turn off xmit. */ 43341502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43441502Swpaul /* Check for ack */ 43541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43641502Swpaul DELAY(1); 437109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43841502Swpaul SIO_SET(WB_SIO_MII_CLK); 43941502Swpaul DELAY(1); 44041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44141502Swpaul DELAY(1); 44241502Swpaul SIO_SET(WB_SIO_MII_CLK); 44341502Swpaul DELAY(1); 44441502Swpaul 44541502Swpaul /* 44641502Swpaul * Now try reading data bits. If the ack failed, we still 44741502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44841502Swpaul */ 44941502Swpaul if (ack) { 45041502Swpaul for(i = 0; i < 16; i++) { 45141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45241502Swpaul DELAY(1); 45341502Swpaul SIO_SET(WB_SIO_MII_CLK); 45441502Swpaul DELAY(1); 45541502Swpaul } 45641502Swpaul goto fail; 45741502Swpaul } 45841502Swpaul 45941502Swpaul for (i = 0x8000; i; i >>= 1) { 46041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46141502Swpaul DELAY(1); 46241502Swpaul if (!ack) { 46341502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46441502Swpaul frame->mii_data |= i; 46541502Swpaul DELAY(1); 46641502Swpaul } 46741502Swpaul SIO_SET(WB_SIO_MII_CLK); 46841502Swpaul DELAY(1); 46941502Swpaul } 47041502Swpaul 47141502Swpaulfail: 47241502Swpaul 47341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47441502Swpaul DELAY(1); 47541502Swpaul SIO_SET(WB_SIO_MII_CLK); 47641502Swpaul DELAY(1); 47741502Swpaul 47867087Swpaul WB_UNLOCK(sc); 47941502Swpaul 48041502Swpaul if (ack) 48141502Swpaul return(1); 48241502Swpaul return(0); 48341502Swpaul} 48441502Swpaul 48541502Swpaul/* 48641502Swpaul * Write to a PHY register through the MII. 48741502Swpaul */ 488102336Salfredstatic int 489102336Salfredwb_mii_writereg(sc, frame) 49041502Swpaul struct wb_softc *sc; 49141502Swpaul struct wb_mii_frame *frame; 49241502Swpaul 49341502Swpaul{ 49467087Swpaul WB_LOCK(sc); 49541502Swpaul 49641502Swpaul /* 49741502Swpaul * Set up frame for TX. 49841502Swpaul */ 49941502Swpaul 50041502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 50141502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50241502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50341502Swpaul 50441502Swpaul /* 50541502Swpaul * Turn on data output. 50641502Swpaul */ 50741502Swpaul SIO_SET(WB_SIO_MII_DIR); 50841502Swpaul 50941502Swpaul wb_mii_sync(sc); 51041502Swpaul 51141502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51241502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51341502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51441502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51541502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51641502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51741502Swpaul 51841502Swpaul /* Idle bit. */ 51941502Swpaul SIO_SET(WB_SIO_MII_CLK); 52041502Swpaul DELAY(1); 52141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52241502Swpaul DELAY(1); 52341502Swpaul 52441502Swpaul /* 52541502Swpaul * Turn off xmit. 52641502Swpaul */ 52741502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52841502Swpaul 52967087Swpaul WB_UNLOCK(sc); 53041502Swpaul 53141502Swpaul return(0); 53241502Swpaul} 53341502Swpaul 534102336Salfredstatic int 535102336Salfredwb_miibus_readreg(dev, phy, reg) 53650675Swpaul device_t dev; 53750675Swpaul int phy, reg; 53850675Swpaul{ 53941502Swpaul struct wb_softc *sc; 54041502Swpaul struct wb_mii_frame frame; 54141502Swpaul 54250675Swpaul sc = device_get_softc(dev); 54350675Swpaul 54441502Swpaul bzero((char *)&frame, sizeof(frame)); 54541502Swpaul 54650675Swpaul frame.mii_phyaddr = phy; 54741502Swpaul frame.mii_regaddr = reg; 54841502Swpaul wb_mii_readreg(sc, &frame); 54941502Swpaul 55041502Swpaul return(frame.mii_data); 55141502Swpaul} 55241502Swpaul 553102336Salfredstatic int 554102336Salfredwb_miibus_writereg(dev, phy, reg, data) 55550675Swpaul device_t dev; 55650675Swpaul int phy, reg, data; 55750675Swpaul{ 55841502Swpaul struct wb_softc *sc; 55941502Swpaul struct wb_mii_frame frame; 56041502Swpaul 56150675Swpaul sc = device_get_softc(dev); 56250675Swpaul 56341502Swpaul bzero((char *)&frame, sizeof(frame)); 56441502Swpaul 56550675Swpaul frame.mii_phyaddr = phy; 56641502Swpaul frame.mii_regaddr = reg; 56741502Swpaul frame.mii_data = data; 56841502Swpaul 56941502Swpaul wb_mii_writereg(sc, &frame); 57041502Swpaul 57150675Swpaul return(0); 57250675Swpaul} 57350675Swpaul 574102336Salfredstatic void 575102336Salfredwb_miibus_statchg(dev) 57650675Swpaul device_t dev; 57750675Swpaul{ 57850675Swpaul struct wb_softc *sc; 57950675Swpaul struct mii_data *mii; 58050675Swpaul 58150675Swpaul sc = device_get_softc(dev); 58267087Swpaul WB_LOCK(sc); 58350675Swpaul mii = device_get_softc(sc->wb_miibus); 58450675Swpaul wb_setcfg(sc, mii->mii_media_active); 58567087Swpaul WB_UNLOCK(sc); 58650675Swpaul 58741502Swpaul return; 58841502Swpaul} 58941502Swpaul 59041502Swpaulstatic u_int8_t wb_calchash(addr) 59142718Swpaul caddr_t addr; 59241502Swpaul{ 59341502Swpaul u_int32_t crc, carry; 59441502Swpaul int i, j; 59541502Swpaul u_int8_t c; 59641502Swpaul 59741502Swpaul /* Compute CRC for the address value. */ 59841502Swpaul crc = 0xFFFFFFFF; /* initial value */ 59941502Swpaul 60041502Swpaul for (i = 0; i < 6; i++) { 60141502Swpaul c = *(addr + i); 60241502Swpaul for (j = 0; j < 8; j++) { 60341502Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 60441502Swpaul crc <<= 1; 60541502Swpaul c >>= 1; 60641502Swpaul if (carry) 60741502Swpaul crc = (crc ^ 0x04c11db6) | carry; 60841502Swpaul } 60941502Swpaul } 61041502Swpaul 61141502Swpaul /* 61241502Swpaul * return the filter bit position 61341502Swpaul * Note: I arrived at the following nonsense 61441502Swpaul * through experimentation. It's not the usual way to 61541502Swpaul * generate the bit position but it's the only thing 61641502Swpaul * I could come up with that works. 61741502Swpaul */ 61841502Swpaul return(~(crc >> 26) & 0x0000003F); 61941502Swpaul} 62041502Swpaul 62141502Swpaul/* 62241502Swpaul * Program the 64-bit multicast hash filter. 62341502Swpaul */ 624102336Salfredstatic void 625102336Salfredwb_setmulti(sc) 62641502Swpaul struct wb_softc *sc; 62741502Swpaul{ 62841502Swpaul struct ifnet *ifp; 62941502Swpaul int h = 0; 63041502Swpaul u_int32_t hashes[2] = { 0, 0 }; 63141502Swpaul struct ifmultiaddr *ifma; 63241502Swpaul u_int32_t rxfilt; 63341502Swpaul int mcnt = 0; 63441502Swpaul 63541502Swpaul ifp = &sc->arpcom.ac_if; 63641502Swpaul 63741502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 63841502Swpaul 63941502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 64041502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 64141502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 64241502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 64341502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 64441502Swpaul return; 64541502Swpaul } 64641502Swpaul 64741502Swpaul /* first, zot all the existing hash bits */ 64841502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 64941502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 65041502Swpaul 65141502Swpaul /* now program new ones */ 65272084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 65341502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 65441502Swpaul continue; 65541502Swpaul h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 65641502Swpaul if (h < 32) 65741502Swpaul hashes[0] |= (1 << h); 65841502Swpaul else 65941502Swpaul hashes[1] |= (1 << (h - 32)); 66041502Swpaul mcnt++; 66141502Swpaul } 66241502Swpaul 66341502Swpaul if (mcnt) 66441502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 66541502Swpaul else 66641502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 66741502Swpaul 66841502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 66941502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 67041502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 67141502Swpaul 67241502Swpaul return; 67341502Swpaul} 67441502Swpaul 67541502Swpaul/* 67641502Swpaul * The Winbond manual states that in order to fiddle with the 67741502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 67841502Swpaul * first have to put the transmit and/or receive logic in the idle state. 67941502Swpaul */ 680102336Salfredstatic void 681102336Salfredwb_setcfg(sc, media) 68241502Swpaul struct wb_softc *sc; 68350675Swpaul u_int32_t media; 68441502Swpaul{ 68541502Swpaul int i, restart = 0; 68641502Swpaul 68741502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 68841502Swpaul restart = 1; 68941502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 69041502Swpaul 69141502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69241502Swpaul DELAY(10); 69341502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 69441502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 69541502Swpaul break; 69641502Swpaul } 69741502Swpaul 69841502Swpaul if (i == WB_TIMEOUT) 69941502Swpaul printf("wb%d: failed to force tx and " 70041502Swpaul "rx to idle state\n", sc->wb_unit); 70141502Swpaul } 70241502Swpaul 70350675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 70450675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70550675Swpaul else 70641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70741502Swpaul 70850675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 70941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71041502Swpaul else 71141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71241502Swpaul 71341502Swpaul if (restart) 71441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 71541502Swpaul 71641502Swpaul return; 71741502Swpaul} 71841502Swpaul 719102336Salfredstatic void 720102336Salfredwb_reset(sc) 72141502Swpaul struct wb_softc *sc; 72241502Swpaul{ 72341502Swpaul register int i; 72450675Swpaul struct mii_data *mii; 72541502Swpaul 72650675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 72750675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 72850675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 72950675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 73050675Swpaul 73141502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73341502Swpaul 73441502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 73541502Swpaul DELAY(10); 73641502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 73741502Swpaul break; 73841502Swpaul } 73941502Swpaul if (i == WB_TIMEOUT) 74041502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 74141502Swpaul 74241502Swpaul /* Wait a little while for the chip to get its brains in order. */ 74341502Swpaul DELAY(1000); 74441502Swpaul 74550675Swpaul if (sc->wb_miibus == NULL) 74650675Swpaul return; 74741502Swpaul 74850675Swpaul mii = device_get_softc(sc->wb_miibus); 74950675Swpaul if (mii == NULL) 75050675Swpaul return; 75150675Swpaul 75250675Swpaul if (mii->mii_instance) { 75350675Swpaul struct mii_softc *miisc; 75472012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 75550675Swpaul mii_phy_reset(miisc); 75650675Swpaul } 75750675Swpaul 75841502Swpaul return; 75941502Swpaul} 76041502Swpaul 761102336Salfredstatic void 762102336Salfredwb_fixmedia(sc) 76350675Swpaul struct wb_softc *sc; 76450675Swpaul{ 76550675Swpaul struct mii_data *mii = NULL; 76650675Swpaul struct ifnet *ifp; 76750675Swpaul u_int32_t media; 76850675Swpaul 76950675Swpaul if (sc->wb_miibus == NULL) 77050675Swpaul return; 77150675Swpaul 77250675Swpaul mii = device_get_softc(sc->wb_miibus); 77350675Swpaul ifp = &sc->arpcom.ac_if; 77450675Swpaul 77550675Swpaul mii_pollstat(mii); 77650675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 77750675Swpaul media = mii->mii_media_active & ~IFM_10_T; 77850675Swpaul media |= IFM_100_TX; 77950675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 78050675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 78150675Swpaul media |= IFM_10_T; 78250675Swpaul } else 78350675Swpaul return; 78450675Swpaul 78550675Swpaul ifmedia_set(&mii->mii_media, media); 78650675Swpaul 78750675Swpaul return; 78850675Swpaul} 78950675Swpaul 79041502Swpaul/* 79141502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 79241502Swpaul * IDs against our list and return a device name if we find a match. 79341502Swpaul */ 794102336Salfredstatic int 795102336Salfredwb_probe(dev) 79649611Swpaul device_t dev; 79741502Swpaul{ 79841502Swpaul struct wb_type *t; 79941502Swpaul 80041502Swpaul t = wb_devs; 80141502Swpaul 80241502Swpaul while(t->wb_name != NULL) { 80349611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 80449611Swpaul (pci_get_device(dev) == t->wb_did)) { 80549611Swpaul device_set_desc(dev, t->wb_name); 80649611Swpaul return(0); 80741502Swpaul } 80841502Swpaul t++; 80941502Swpaul } 81041502Swpaul 81149611Swpaul return(ENXIO); 81241502Swpaul} 81341502Swpaul 81441502Swpaul/* 81541502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 81641502Swpaul * setup and ethernet/BPF attach. 81741502Swpaul */ 818102336Salfredstatic int 819102336Salfredwb_attach(dev) 82049611Swpaul device_t dev; 82141502Swpaul{ 82241502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 82341502Swpaul struct wb_softc *sc; 82441502Swpaul struct ifnet *ifp; 82549611Swpaul int unit, error = 0, rid; 82641502Swpaul 82749611Swpaul sc = device_get_softc(dev); 82849611Swpaul unit = device_get_unit(dev); 82941502Swpaul 83093818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 83193818Sjhb MTX_DEF | MTX_RECURSE); 832117208Simp#ifndef BURN_BRIDGES 83341502Swpaul /* 83441502Swpaul * Handle power management nonsense. 83541502Swpaul */ 83641502Swpaul 83772813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 83872813Swpaul u_int32_t iobase, membase, irq; 83941502Swpaul 84072813Swpaul /* Save important PCI config data. */ 84172813Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 84272813Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 84372813Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 84441502Swpaul 84572813Swpaul /* Reset the power state. */ 84672813Swpaul printf("wb%d: chip is in D%d power mode " 84772813Swpaul "-- setting to D0\n", unit, 84872813Swpaul pci_get_powerstate(dev)); 84972813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 85041502Swpaul 85172813Swpaul /* Restore PCI config data. */ 85272813Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 85372813Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 85472813Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 85541502Swpaul } 856117208Simp#endif 85741502Swpaul /* 85841502Swpaul * Map control/status registers. 85941502Swpaul */ 86072813Swpaul pci_enable_busmaster(dev); 86141502Swpaul 86249611Swpaul rid = WB_RID; 86349611Swpaul sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 86449611Swpaul 0, ~0, 1, RF_ACTIVE); 86549611Swpaul 86649611Swpaul if (sc->wb_res == NULL) { 86749611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 86849611Swpaul error = ENXIO; 86941502Swpaul goto fail; 87041502Swpaul } 87141502Swpaul 87249611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 87349611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 87449611Swpaul 87541502Swpaul /* Allocate interrupt */ 87649611Swpaul rid = 0; 87749611Swpaul sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 87849611Swpaul RF_SHAREABLE | RF_ACTIVE); 87949611Swpaul 88049611Swpaul if (sc->wb_irq == NULL) { 88141502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 88249611Swpaul error = ENXIO; 88341502Swpaul goto fail; 88441502Swpaul } 88541502Swpaul 88650675Swpaul /* Save the cache line size. */ 88750675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 88850675Swpaul 88941502Swpaul /* Reset the adapter. */ 89041502Swpaul wb_reset(sc); 89141502Swpaul 89241502Swpaul /* 89341502Swpaul * Get station address from the EEPROM. 89441502Swpaul */ 89541502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 89641502Swpaul 89741502Swpaul /* 89841502Swpaul * A Winbond chip was detected. Inform the world. 89941502Swpaul */ 90041502Swpaul printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 90141502Swpaul 90241502Swpaul sc->wb_unit = unit; 90341502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 90441502Swpaul 90550675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 90651657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 90750675Swpaul 90850675Swpaul if (sc->wb_ldata == NULL) { 90941502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 91049611Swpaul error = ENXIO; 91149611Swpaul goto fail; 91241502Swpaul } 91341502Swpaul 91441502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 91541502Swpaul 91641502Swpaul ifp = &sc->arpcom.ac_if; 91741502Swpaul ifp->if_softc = sc; 91841502Swpaul ifp->if_unit = unit; 91941502Swpaul ifp->if_name = "wb"; 92041502Swpaul ifp->if_mtu = ETHERMTU; 92141502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 92241502Swpaul ifp->if_ioctl = wb_ioctl; 92341502Swpaul ifp->if_output = ether_output; 92441502Swpaul ifp->if_start = wb_start; 92541502Swpaul ifp->if_watchdog = wb_watchdog; 92641502Swpaul ifp->if_init = wb_init; 92741502Swpaul ifp->if_baudrate = 10000000; 92843515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 92941502Swpaul 93050675Swpaul /* 93150675Swpaul * Do MII setup. 93250675Swpaul */ 93350675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 93450675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 93549611Swpaul error = ENXIO; 93641502Swpaul goto fail; 93741502Swpaul } 93841502Swpaul 93941502Swpaul /* 94063090Sarchie * Call MI attach routine. 94141502Swpaul */ 942106936Ssam ether_ifattach(ifp, eaddr); 94341502Swpaul 944113609Snjl /* Hook interrupt last to avoid having to lock softc */ 945112872Snjl error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 946112872Snjl wb_intr, sc, &sc->wb_intrhand); 947112872Snjl 948112872Snjl if (error) { 949112872Snjl printf("wb%d: couldn't set up irq\n", unit); 950113609Snjl ether_ifdetach(ifp); 951112872Snjl goto fail; 952112872Snjl } 953112872Snjl 95441502Swpaulfail: 95550675Swpaul if (error) 956112872Snjl wb_detach(dev); 95750675Swpaul 95849611Swpaul return(error); 95941502Swpaul} 96041502Swpaul 961113609Snjl/* 962113609Snjl * Shutdown hardware and free up resources. This can be called any 963113609Snjl * time after the mutex has been initialized. It is called in both 964113609Snjl * the error case in attach and the normal detach case so it needs 965113609Snjl * to be careful about only freeing resources that have actually been 966113609Snjl * allocated. 967113609Snjl */ 968102336Salfredstatic int 969102336Salfredwb_detach(dev) 97049611Swpaul device_t dev; 97149611Swpaul{ 97249611Swpaul struct wb_softc *sc; 97349611Swpaul struct ifnet *ifp; 97449611Swpaul 97549611Swpaul sc = device_get_softc(dev); 976112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 97767087Swpaul WB_LOCK(sc); 97849611Swpaul ifp = &sc->arpcom.ac_if; 97949611Swpaul 980113609Snjl /* 981113609Snjl * Delete any miibus and phy devices attached to this interface. 982113609Snjl * This should only be done if attach succeeded. 983113609Snjl */ 984113812Simp if (device_is_attached(dev)) { 985113609Snjl wb_stop(sc); 986112872Snjl ether_ifdetach(ifp); 987113609Snjl } 988113609Snjl if (sc->wb_miibus) 989112872Snjl device_delete_child(dev, sc->wb_miibus); 990113609Snjl bus_generic_detach(dev); 99150675Swpaul 992112872Snjl if (sc->wb_intrhand) 993112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 994112872Snjl if (sc->wb_irq) 995112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 996112872Snjl if (sc->wb_res) 997112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 99849611Swpaul 999112872Snjl if (sc->wb_ldata) { 1000112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1001112872Snjl M_DEVBUF); 1002112872Snjl } 100349611Swpaul 100467087Swpaul WB_UNLOCK(sc); 100567087Swpaul mtx_destroy(&sc->wb_mtx); 100649611Swpaul 100749611Swpaul return(0); 100849611Swpaul} 100949611Swpaul 101041502Swpaul/* 101141502Swpaul * Initialize the transmit descriptors. 101241502Swpaul */ 1013102336Salfredstatic int 1014102336Salfredwb_list_tx_init(sc) 101541502Swpaul struct wb_softc *sc; 101641502Swpaul{ 101741502Swpaul struct wb_chain_data *cd; 101841502Swpaul struct wb_list_data *ld; 101941502Swpaul int i; 102041502Swpaul 102141502Swpaul cd = &sc->wb_cdata; 102241502Swpaul ld = sc->wb_ldata; 102341502Swpaul 102441502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 102541502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 102641502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 102741502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 102841502Swpaul &cd->wb_tx_chain[0]; 102941502Swpaul } else { 103041502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 103141502Swpaul &cd->wb_tx_chain[i + 1]; 103241502Swpaul } 103341502Swpaul } 103441502Swpaul 103541502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 103641502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 103741502Swpaul 103841502Swpaul return(0); 103941502Swpaul} 104041502Swpaul 104141502Swpaul 104241502Swpaul/* 104341502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 104441502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 104541502Swpaul * points back to the first. 104641502Swpaul */ 1047102336Salfredstatic int 1048102336Salfredwb_list_rx_init(sc) 104941502Swpaul struct wb_softc *sc; 105041502Swpaul{ 105141502Swpaul struct wb_chain_data *cd; 105241502Swpaul struct wb_list_data *ld; 105341502Swpaul int i; 105441502Swpaul 105541502Swpaul cd = &sc->wb_cdata; 105641502Swpaul ld = sc->wb_ldata; 105741502Swpaul 105841502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 105941502Swpaul cd->wb_rx_chain[i].wb_ptr = 106041502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 106150675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 106248745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 106341502Swpaul return(ENOBUFS); 106441502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 106541502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 106641502Swpaul ld->wb_rx_list[i].wb_next = 106741502Swpaul vtophys(&ld->wb_rx_list[0]); 106841502Swpaul } else { 106941502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 107041502Swpaul &cd->wb_rx_chain[i + 1]; 107141502Swpaul ld->wb_rx_list[i].wb_next = 107241502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 107341502Swpaul } 107441502Swpaul } 107541502Swpaul 107641502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 107741502Swpaul 107841502Swpaul return(0); 107941502Swpaul} 108041502Swpaul 1081102336Salfredstatic void 1082102336Salfredwb_bfree(buf, args) 108398995Salfred void *buf; 108464837Sdwmalone void *args; 108550675Swpaul{ 108650675Swpaul return; 108750675Swpaul} 108850675Swpaul 108941502Swpaul/* 109041502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 109141502Swpaul */ 1092102336Salfredstatic int 1093102336Salfredwb_newbuf(sc, c, m) 109441502Swpaul struct wb_softc *sc; 109541502Swpaul struct wb_chain_onefrag *c; 109648745Swpaul struct mbuf *m; 109741502Swpaul{ 109841502Swpaul struct mbuf *m_new = NULL; 109941502Swpaul 110048745Swpaul if (m == NULL) { 1101111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 110287846Sluigi if (m_new == NULL) 110348745Swpaul return(ENOBUFS); 110464837Sdwmalone m_new->m_data = c->wb_buf; 110564837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 110668621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 110768621Sbmilekic EXT_NET_DRV); 110848745Swpaul } else { 110948745Swpaul m_new = m; 111050675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 111148745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 111241502Swpaul } 111341502Swpaul 111448745Swpaul m_adj(m_new, sizeof(u_int64_t)); 111548745Swpaul 111641502Swpaul c->wb_mbuf = m_new; 111741502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 111850675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 111941502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 112041502Swpaul 112141502Swpaul return(0); 112241502Swpaul} 112341502Swpaul 112441502Swpaul/* 112541502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 112641502Swpaul * the higher level protocols. 112741502Swpaul */ 1128102336Salfredstatic void 1129102336Salfredwb_rxeof(sc) 113041502Swpaul struct wb_softc *sc; 113141502Swpaul{ 113250675Swpaul struct mbuf *m = NULL; 113341502Swpaul struct ifnet *ifp; 113441502Swpaul struct wb_chain_onefrag *cur_rx; 113541502Swpaul int total_len = 0; 113641502Swpaul u_int32_t rxstat; 113741502Swpaul 113841502Swpaul ifp = &sc->arpcom.ac_if; 113941502Swpaul 114041502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 114141502Swpaul WB_RXSTAT_OWN)) { 114248745Swpaul struct mbuf *m0 = NULL; 114348745Swpaul 114441502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 114541502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 114650675Swpaul 114748745Swpaul m = cur_rx->wb_mbuf; 114841502Swpaul 114950675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 115050675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 115150675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 115250675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 115350675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 115441502Swpaul ifp->if_ierrors++; 115550675Swpaul wb_newbuf(sc, cur_rx, m); 115641502Swpaul printf("wb%x: receiver babbling: possible chip " 115741502Swpaul "bug, forcing reset\n", sc->wb_unit); 115850675Swpaul wb_fixmedia(sc); 115950675Swpaul wb_reset(sc); 116050675Swpaul wb_init(sc); 116141502Swpaul return; 116241502Swpaul } 116341502Swpaul 116442718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 116542718Swpaul ifp->if_ierrors++; 116648745Swpaul wb_newbuf(sc, cur_rx, m); 116750675Swpaul break; 116842718Swpaul } 116942718Swpaul 117041502Swpaul /* No errors; receive the packet. */ 117141502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 117241502Swpaul 117341502Swpaul /* 117441934Swpaul * XXX The Winbond chip includes the CRC with every 117541934Swpaul * received frame, and there's no way to turn this 117641934Swpaul * behavior off (at least, I can't find anything in 117741934Swpaul * the manual that explains how to do it) so we have 117841934Swpaul * to trim off the CRC manually. 117941934Swpaul */ 118041934Swpaul total_len -= ETHER_CRC_LEN; 118141934Swpaul 118278508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 118378508Sbmilekic NULL); 118448745Swpaul wb_newbuf(sc, cur_rx, m); 118548745Swpaul if (m0 == NULL) { 118648745Swpaul ifp->if_ierrors++; 118750675Swpaul break; 118841502Swpaul } 118948745Swpaul m = m0; 119041502Swpaul 119141502Swpaul ifp->if_ipackets++; 1192106936Ssam (*ifp->if_input)(ifp, m); 119341502Swpaul } 119441502Swpaul} 119541502Swpaul 1196105221Sphkstatic void 1197102336Salfredwb_rxeoc(sc) 119841502Swpaul struct wb_softc *sc; 119941502Swpaul{ 120041502Swpaul wb_rxeof(sc); 120141502Swpaul 120241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120341502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 120441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120541502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 120641502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 120741502Swpaul 120841502Swpaul return; 120941502Swpaul} 121041502Swpaul 121141502Swpaul/* 121241502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 121341502Swpaul * the list buffers. 121441502Swpaul */ 1215102336Salfredstatic void 1216102336Salfredwb_txeof(sc) 121741502Swpaul struct wb_softc *sc; 121841502Swpaul{ 121941502Swpaul struct wb_chain *cur_tx; 122041502Swpaul struct ifnet *ifp; 122141502Swpaul 122241502Swpaul ifp = &sc->arpcom.ac_if; 122341502Swpaul 122441502Swpaul /* Clear the timeout timer. */ 122541502Swpaul ifp->if_timer = 0; 122641502Swpaul 122741502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 122841502Swpaul return; 122941502Swpaul 123041502Swpaul /* 123141502Swpaul * Go through our tx list and free mbufs for those 123241502Swpaul * frames that have been transmitted. 123341502Swpaul */ 123441502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 123541502Swpaul u_int32_t txstat; 123641502Swpaul 123741502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 123841502Swpaul txstat = WB_TXSTATUS(cur_tx); 123941502Swpaul 124041502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 124141502Swpaul break; 124241502Swpaul 124341502Swpaul if (txstat & WB_TXSTAT_TXERR) { 124441502Swpaul ifp->if_oerrors++; 124541502Swpaul if (txstat & WB_TXSTAT_ABORT) 124641502Swpaul ifp->if_collisions++; 124741502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 124841502Swpaul ifp->if_collisions++; 124941502Swpaul } 125041502Swpaul 125141502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 125241502Swpaul 125341502Swpaul ifp->if_opackets++; 125441502Swpaul m_freem(cur_tx->wb_mbuf); 125541502Swpaul cur_tx->wb_mbuf = NULL; 125641502Swpaul 125741502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 125841502Swpaul sc->wb_cdata.wb_tx_head = NULL; 125941502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 126041502Swpaul break; 126141502Swpaul } 126241502Swpaul 126341502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 126441502Swpaul } 126541502Swpaul 126641502Swpaul return; 126741502Swpaul} 126841502Swpaul 126941502Swpaul/* 127041502Swpaul * TX 'end of channel' interrupt handler. 127141502Swpaul */ 1272102336Salfredstatic void 1273102336Salfredwb_txeoc(sc) 127441502Swpaul struct wb_softc *sc; 127541502Swpaul{ 127641502Swpaul struct ifnet *ifp; 127741502Swpaul 127841502Swpaul ifp = &sc->arpcom.ac_if; 127941502Swpaul 128041502Swpaul ifp->if_timer = 0; 128141502Swpaul 128241502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 128341502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 128441502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 128541502Swpaul } else { 128641502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 128741502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 128841502Swpaul ifp->if_timer = 5; 128941502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 129041502Swpaul } 129141502Swpaul } 129241502Swpaul 129341502Swpaul return; 129441502Swpaul} 129541502Swpaul 1296102336Salfredstatic void 1297102336Salfredwb_intr(arg) 129841502Swpaul void *arg; 129941502Swpaul{ 130041502Swpaul struct wb_softc *sc; 130141502Swpaul struct ifnet *ifp; 130241502Swpaul u_int32_t status; 130341502Swpaul 130441502Swpaul sc = arg; 130567087Swpaul WB_LOCK(sc); 130641502Swpaul ifp = &sc->arpcom.ac_if; 130741502Swpaul 130867087Swpaul if (!(ifp->if_flags & IFF_UP)) { 130967087Swpaul WB_UNLOCK(sc); 131041502Swpaul return; 131167087Swpaul } 131241502Swpaul 131341502Swpaul /* Disable interrupts. */ 131441502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 131541502Swpaul 131641502Swpaul for (;;) { 131741502Swpaul 131841502Swpaul status = CSR_READ_4(sc, WB_ISR); 131941502Swpaul if (status) 132041502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 132141502Swpaul 132241502Swpaul if ((status & WB_INTRS) == 0) 132341502Swpaul break; 132441502Swpaul 132541502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 132641502Swpaul ifp->if_ierrors++; 132741502Swpaul wb_reset(sc); 132850675Swpaul if (status & WB_ISR_RX_ERR) 132950675Swpaul wb_fixmedia(sc); 133041502Swpaul wb_init(sc); 133150675Swpaul continue; 133241502Swpaul } 133341502Swpaul 133450675Swpaul if (status & WB_ISR_RX_OK) 133550675Swpaul wb_rxeof(sc); 133650675Swpaul 133750675Swpaul if (status & WB_ISR_RX_IDLE) 133850675Swpaul wb_rxeoc(sc); 133950675Swpaul 134041502Swpaul if (status & WB_ISR_TX_OK) 134141502Swpaul wb_txeof(sc); 134241502Swpaul 134341502Swpaul if (status & WB_ISR_TX_NOBUF) 134441502Swpaul wb_txeoc(sc); 134541502Swpaul 134641502Swpaul if (status & WB_ISR_TX_IDLE) { 134741502Swpaul wb_txeof(sc); 134841502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 134941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135041502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 135141502Swpaul } 135241502Swpaul } 135341502Swpaul 135441502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 135541502Swpaul ifp->if_oerrors++; 135641502Swpaul wb_txeof(sc); 135741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135841502Swpaul /* Jack up TX threshold */ 135941502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 136041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 136141502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 136241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136341502Swpaul } 136441502Swpaul 136541502Swpaul if (status & WB_ISR_BUS_ERR) { 136641502Swpaul wb_reset(sc); 136741502Swpaul wb_init(sc); 136841502Swpaul } 136941502Swpaul 137041502Swpaul } 137141502Swpaul 137241502Swpaul /* Re-enable interrupts. */ 137341502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 137441502Swpaul 137541502Swpaul if (ifp->if_snd.ifq_head != NULL) { 137641502Swpaul wb_start(ifp); 137741502Swpaul } 137841502Swpaul 137967087Swpaul WB_UNLOCK(sc); 138067087Swpaul 138141502Swpaul return; 138241502Swpaul} 138341502Swpaul 1384102336Salfredstatic void 1385102336Salfredwb_tick(xsc) 138650675Swpaul void *xsc; 138750675Swpaul{ 138850675Swpaul struct wb_softc *sc; 138950675Swpaul struct mii_data *mii; 139050675Swpaul 139150675Swpaul sc = xsc; 139267087Swpaul WB_LOCK(sc); 139350675Swpaul mii = device_get_softc(sc->wb_miibus); 139450675Swpaul 139550675Swpaul mii_tick(mii); 139650675Swpaul 139750675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 139850675Swpaul 139967087Swpaul WB_UNLOCK(sc); 140050685Swpaul 140150675Swpaul return; 140250675Swpaul} 140350675Swpaul 140441502Swpaul/* 140541502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 140641502Swpaul * pointers to the fragment pointers. 140741502Swpaul */ 1408102336Salfredstatic int 1409102336Salfredwb_encap(sc, c, m_head) 141041502Swpaul struct wb_softc *sc; 141141502Swpaul struct wb_chain *c; 141241502Swpaul struct mbuf *m_head; 141341502Swpaul{ 141441502Swpaul int frag = 0; 141541502Swpaul struct wb_desc *f = NULL; 141641502Swpaul int total_len; 141741502Swpaul struct mbuf *m; 141841502Swpaul 141941502Swpaul /* 142041502Swpaul * Start packing the mbufs in this chain into 142141502Swpaul * the fragment pointers. Stop when we run out 142241502Swpaul * of fragments or hit the end of the mbuf chain. 142341502Swpaul */ 142441502Swpaul m = m_head; 142541502Swpaul total_len = 0; 142641502Swpaul 142741502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 142841502Swpaul if (m->m_len != 0) { 142941502Swpaul if (frag == WB_MAXFRAGS) 143041502Swpaul break; 143141502Swpaul total_len += m->m_len; 143241502Swpaul f = &c->wb_ptr->wb_frag[frag]; 143341502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 143441502Swpaul if (frag == 0) { 143541502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 143641502Swpaul f->wb_status = 0; 143741502Swpaul } else 143841502Swpaul f->wb_status = WB_TXSTAT_OWN; 143941502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 144041502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 144141502Swpaul frag++; 144241502Swpaul } 144341502Swpaul } 144441502Swpaul 144541502Swpaul /* 144641502Swpaul * Handle special case: we used up all 16 fragments, 144741502Swpaul * but we have more mbufs left in the chain. Copy the 144841502Swpaul * data into an mbuf cluster. Note that we don't 144941502Swpaul * bother clearing the values in the other fragment 145041502Swpaul * pointers/counters; it wouldn't gain us anything, 145141502Swpaul * and would waste cycles. 145241502Swpaul */ 145341502Swpaul if (m != NULL) { 145441502Swpaul struct mbuf *m_new = NULL; 145541502Swpaul 1456111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145787846Sluigi if (m_new == NULL) 145841502Swpaul return(1); 145941502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1460111119Simp MCLGET(m_new, M_DONTWAIT); 146141502Swpaul if (!(m_new->m_flags & M_EXT)) { 146241502Swpaul m_freem(m_new); 146341502Swpaul return(1); 146441502Swpaul } 146541502Swpaul } 146641502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 146741502Swpaul mtod(m_new, caddr_t)); 146841502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 146941502Swpaul m_freem(m_head); 147041502Swpaul m_head = m_new; 147141502Swpaul f = &c->wb_ptr->wb_frag[0]; 147241502Swpaul f->wb_status = 0; 147341502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 147441502Swpaul f->wb_ctl = total_len = m_new->m_len; 147541502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 147641502Swpaul frag = 1; 147741502Swpaul } 147841502Swpaul 147941502Swpaul if (total_len < WB_MIN_FRAMELEN) { 148041502Swpaul f = &c->wb_ptr->wb_frag[frag]; 148141502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 148241502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 148341502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 148441502Swpaul f->wb_status = WB_TXSTAT_OWN; 148541502Swpaul frag++; 148641502Swpaul } 148741502Swpaul 148841502Swpaul c->wb_mbuf = m_head; 148941502Swpaul c->wb_lastdesc = frag - 1; 149041502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 149141502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 149241502Swpaul 149341502Swpaul return(0); 149441502Swpaul} 149541502Swpaul 149641502Swpaul/* 149741502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 149841502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 149941502Swpaul * copy of the pointers since the transmit list fragment pointers are 150041502Swpaul * physical addresses. 150141502Swpaul */ 150241502Swpaul 1503102336Salfredstatic void 1504102336Salfredwb_start(ifp) 150541502Swpaul struct ifnet *ifp; 150641502Swpaul{ 150741502Swpaul struct wb_softc *sc; 150841502Swpaul struct mbuf *m_head = NULL; 150941502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 151041502Swpaul 151141502Swpaul sc = ifp->if_softc; 151267087Swpaul WB_LOCK(sc); 151341502Swpaul 151441502Swpaul /* 151541502Swpaul * Check for an available queue slot. If there are none, 151641502Swpaul * punt. 151741502Swpaul */ 151841502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 151941502Swpaul ifp->if_flags |= IFF_OACTIVE; 152067087Swpaul WB_UNLOCK(sc); 152141502Swpaul return; 152241502Swpaul } 152341502Swpaul 152441502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 152541502Swpaul 152641502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 152741502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 152841502Swpaul if (m_head == NULL) 152941502Swpaul break; 153041502Swpaul 153141502Swpaul /* Pick a descriptor off the free list. */ 153241502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 153341502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 153441502Swpaul 153541502Swpaul /* Pack the data into the descriptor. */ 153641502Swpaul wb_encap(sc, cur_tx, m_head); 153741502Swpaul 153841502Swpaul if (cur_tx != start_tx) 153941502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 154041502Swpaul 154141502Swpaul /* 154241502Swpaul * If there's a BPF listener, bounce a copy of this frame 154341502Swpaul * to him. 154441502Swpaul */ 1545106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 154641502Swpaul } 154741502Swpaul 154841502Swpaul /* 154941526Swpaul * If there are no packets queued, bail. 155041526Swpaul */ 155167087Swpaul if (cur_tx == NULL) { 155267087Swpaul WB_UNLOCK(sc); 155341526Swpaul return; 155467087Swpaul } 155541526Swpaul 155641526Swpaul /* 155741502Swpaul * Place the request for the upload interrupt 155841502Swpaul * in the last descriptor in the chain. This way, if 155941502Swpaul * we're chaining several packets at once, we'll only 156041502Swpaul * get an interupt once for the whole chain rather than 156141502Swpaul * once for each packet. 156241502Swpaul */ 156341502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 156442718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 156541502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 156641502Swpaul 156741502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 156841502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 156941502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 157041502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 157141502Swpaul } else { 157241502Swpaul /* 157341502Swpaul * We need to distinguish between the case where 157441502Swpaul * the own bit is clear because the chip cleared it 157541502Swpaul * and where the own bit is clear because we haven't 157641502Swpaul * set it yet. The magic value WB_UNSET is just some 157741502Swpaul * ramdomly chosen number which doesn't have the own 157841502Swpaul * bit set. When we actually transmit the frame, the 157941502Swpaul * status word will have _only_ the own bit set, so 158041502Swpaul * the txeoc handler will be able to tell if it needs 158141502Swpaul * to initiate another transmission to flush out pending 158241502Swpaul * frames. 158341502Swpaul */ 158441502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 158541502Swpaul } 158641502Swpaul 158741502Swpaul /* 158841502Swpaul * Set a timeout in case the chip goes out to lunch. 158941502Swpaul */ 159041502Swpaul ifp->if_timer = 5; 159167087Swpaul WB_UNLOCK(sc); 159241502Swpaul 159341502Swpaul return; 159441502Swpaul} 159541502Swpaul 1596102336Salfredstatic void 1597102336Salfredwb_init(xsc) 159841502Swpaul void *xsc; 159941502Swpaul{ 160041502Swpaul struct wb_softc *sc = xsc; 160141502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160267087Swpaul int i; 160350675Swpaul struct mii_data *mii; 160441502Swpaul 160567087Swpaul WB_LOCK(sc); 160650675Swpaul mii = device_get_softc(sc->wb_miibus); 160741502Swpaul 160841502Swpaul /* 160941502Swpaul * Cancel pending I/O and free all RX/TX buffers. 161041502Swpaul */ 161141502Swpaul wb_stop(sc); 161241502Swpaul wb_reset(sc); 161341502Swpaul 161441502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 161541502Swpaul 161641502Swpaul /* 161741502Swpaul * Set cache alignment and burst length. 161841502Swpaul */ 161950675Swpaul#ifdef foo 162041502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 162141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 162241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 162350675Swpaul#endif 162441502Swpaul 162550675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 162650675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 162750675Swpaul switch(sc->wb_cachesize) { 162850675Swpaul case 32: 162950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 163050675Swpaul break; 163150675Swpaul case 16: 163250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 163350675Swpaul break; 163450675Swpaul case 8: 163550675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 163650675Swpaul break; 163750675Swpaul case 0: 163850675Swpaul default: 163950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 164050675Swpaul break; 164150675Swpaul } 164250675Swpaul 164341502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 164441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 164541502Swpaul 164641502Swpaul /* Init our MAC address */ 164741502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 164841502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 164941502Swpaul } 165041502Swpaul 165141502Swpaul /* Init circular RX list. */ 165241502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 165341502Swpaul printf("wb%d: initialization failed: no " 165441502Swpaul "memory for rx buffers\n", sc->wb_unit); 165541502Swpaul wb_stop(sc); 165667087Swpaul WB_UNLOCK(sc); 165741502Swpaul return; 165841502Swpaul } 165941502Swpaul 166041502Swpaul /* Init TX descriptors. */ 166141502Swpaul wb_list_tx_init(sc); 166241502Swpaul 166341502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 166441502Swpaul if (ifp->if_flags & IFF_PROMISC) { 166541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166641502Swpaul } else { 166741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166841502Swpaul } 166941502Swpaul 167041502Swpaul /* 167141502Swpaul * Set capture broadcast bit to capture broadcast frames. 167241502Swpaul */ 167341502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 167441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167541502Swpaul } else { 167641502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167741502Swpaul } 167841502Swpaul 167941502Swpaul /* 168041502Swpaul * Program the multicast filter, if necessary. 168141502Swpaul */ 168241502Swpaul wb_setmulti(sc); 168341502Swpaul 168441502Swpaul /* 168541502Swpaul * Load the address of the RX list. 168641502Swpaul */ 168741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 168841502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 168941502Swpaul 169041502Swpaul /* 169141502Swpaul * Enable interrupts. 169241502Swpaul */ 169341502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 169441502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 169541502Swpaul 169641502Swpaul /* Enable receiver and transmitter. */ 169741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 169841502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 169941502Swpaul 170041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170141502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 170241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170341502Swpaul 170450675Swpaul mii_mediachg(mii); 170541502Swpaul 170641502Swpaul ifp->if_flags |= IFF_RUNNING; 170741502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 170841502Swpaul 170950675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 171067087Swpaul WB_UNLOCK(sc); 171150675Swpaul 171241502Swpaul return; 171341502Swpaul} 171441502Swpaul 171541502Swpaul/* 171641502Swpaul * Set media options. 171741502Swpaul */ 1718102336Salfredstatic int 1719102336Salfredwb_ifmedia_upd(ifp) 172041502Swpaul struct ifnet *ifp; 172141502Swpaul{ 172241502Swpaul struct wb_softc *sc; 172341502Swpaul 172441502Swpaul sc = ifp->if_softc; 172541502Swpaul 172650675Swpaul if (ifp->if_flags & IFF_UP) 172750675Swpaul wb_init(sc); 172841502Swpaul 172941502Swpaul return(0); 173041502Swpaul} 173141502Swpaul 173241502Swpaul/* 173341502Swpaul * Report current media status. 173441502Swpaul */ 1735102336Salfredstatic void 1736102336Salfredwb_ifmedia_sts(ifp, ifmr) 173741502Swpaul struct ifnet *ifp; 173841502Swpaul struct ifmediareq *ifmr; 173941502Swpaul{ 174041502Swpaul struct wb_softc *sc; 174150675Swpaul struct mii_data *mii; 174241502Swpaul 174341502Swpaul sc = ifp->if_softc; 174441502Swpaul 174550675Swpaul mii = device_get_softc(sc->wb_miibus); 174641502Swpaul 174750675Swpaul mii_pollstat(mii); 174850675Swpaul ifmr->ifm_active = mii->mii_media_active; 174950675Swpaul ifmr->ifm_status = mii->mii_media_status; 175041502Swpaul 175141502Swpaul return; 175241502Swpaul} 175341502Swpaul 1754102336Salfredstatic int 1755102336Salfredwb_ioctl(ifp, command, data) 175641502Swpaul struct ifnet *ifp; 175741502Swpaul u_long command; 175841502Swpaul caddr_t data; 175941502Swpaul{ 176041502Swpaul struct wb_softc *sc = ifp->if_softc; 176150675Swpaul struct mii_data *mii; 176241502Swpaul struct ifreq *ifr = (struct ifreq *) data; 176367087Swpaul int error = 0; 176441502Swpaul 176567087Swpaul WB_LOCK(sc); 176641502Swpaul 176741502Swpaul switch(command) { 176841502Swpaul case SIOCSIFFLAGS: 176941502Swpaul if (ifp->if_flags & IFF_UP) { 177041502Swpaul wb_init(sc); 177141502Swpaul } else { 177241502Swpaul if (ifp->if_flags & IFF_RUNNING) 177341502Swpaul wb_stop(sc); 177441502Swpaul } 177541502Swpaul error = 0; 177641502Swpaul break; 177741502Swpaul case SIOCADDMULTI: 177841502Swpaul case SIOCDELMULTI: 177941502Swpaul wb_setmulti(sc); 178041502Swpaul error = 0; 178141502Swpaul break; 178241502Swpaul case SIOCGIFMEDIA: 178341502Swpaul case SIOCSIFMEDIA: 178450675Swpaul mii = device_get_softc(sc->wb_miibus); 178550675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 178641502Swpaul break; 178741502Swpaul default: 1788106936Ssam error = ether_ioctl(ifp, command, data); 178941502Swpaul break; 179041502Swpaul } 179141502Swpaul 179267087Swpaul WB_UNLOCK(sc); 179341502Swpaul 179441502Swpaul return(error); 179541502Swpaul} 179641502Swpaul 1797102336Salfredstatic void 1798102336Salfredwb_watchdog(ifp) 179941502Swpaul struct ifnet *ifp; 180041502Swpaul{ 180141502Swpaul struct wb_softc *sc; 180241502Swpaul 180341502Swpaul sc = ifp->if_softc; 180441502Swpaul 180567087Swpaul WB_LOCK(sc); 180641502Swpaul ifp->if_oerrors++; 180741502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 180850675Swpaul#ifdef foo 180941502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 181041502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 181141502Swpaul sc->wb_unit); 181250675Swpaul#endif 181341502Swpaul wb_stop(sc); 181441502Swpaul wb_reset(sc); 181541502Swpaul wb_init(sc); 181641502Swpaul 181741502Swpaul if (ifp->if_snd.ifq_head != NULL) 181841502Swpaul wb_start(ifp); 181967087Swpaul WB_UNLOCK(sc); 182041502Swpaul 182141502Swpaul return; 182241502Swpaul} 182341502Swpaul 182441502Swpaul/* 182541502Swpaul * Stop the adapter and free any mbufs allocated to the 182641502Swpaul * RX and TX lists. 182741502Swpaul */ 1828102336Salfredstatic void 1829102336Salfredwb_stop(sc) 183041502Swpaul struct wb_softc *sc; 183141502Swpaul{ 183241502Swpaul register int i; 183341502Swpaul struct ifnet *ifp; 183441502Swpaul 183567087Swpaul WB_LOCK(sc); 183641502Swpaul ifp = &sc->arpcom.ac_if; 183741502Swpaul ifp->if_timer = 0; 183841502Swpaul 183950675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 184050675Swpaul 184141502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 184241502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 184341502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 184441502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 184541502Swpaul 184641502Swpaul /* 184741502Swpaul * Free data in the RX lists. 184841502Swpaul */ 184941502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 185041502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 185141502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 185241502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 185341502Swpaul } 185441502Swpaul } 185541502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 185641502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 185741502Swpaul 185841502Swpaul /* 185941502Swpaul * Free the TX list buffers. 186041502Swpaul */ 186141502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 186241502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 186341502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 186441502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 186541502Swpaul } 186641502Swpaul } 186741502Swpaul 186841502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 186941502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 187041502Swpaul 187141502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 187267087Swpaul WB_UNLOCK(sc); 187341502Swpaul 187441502Swpaul return; 187541502Swpaul} 187641502Swpaul 187741502Swpaul/* 187841502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 187941502Swpaul * get confused by errant DMAs when rebooting. 188041502Swpaul */ 1881102336Salfredstatic void 1882102336Salfredwb_shutdown(dev) 188349611Swpaul device_t dev; 188441502Swpaul{ 188549611Swpaul struct wb_softc *sc; 188641502Swpaul 188749611Swpaul sc = device_get_softc(dev); 188841502Swpaul wb_stop(sc); 188941502Swpaul 189041502Swpaul return; 189141502Swpaul} 1892