if_wb.c revision 106936
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_wb.c 106936 2002-11-14 23:49:09Z sam $ 3341502Swpaul */ 3441502Swpaul 3541502Swpaul/* 3641502Swpaul * Winbond fast ethernet PCI NIC driver 3741502Swpaul * 3841502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 3941502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4041502Swpaul * Winbond itself and some made by Linksys. 4141502Swpaul * 4241502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4341502Swpaul * Electrical Engineering Department 4441502Swpaul * Columbia University, New York City 4541502Swpaul */ 4641502Swpaul 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8648745Swpaul#include "opt_bdg.h" 8741502Swpaul 8841502Swpaul#include <sys/param.h> 8941502Swpaul#include <sys/systm.h> 9041502Swpaul#include <sys/sockio.h> 9141502Swpaul#include <sys/mbuf.h> 9241502Swpaul#include <sys/malloc.h> 9341502Swpaul#include <sys/kernel.h> 9441502Swpaul#include <sys/socket.h> 9550675Swpaul#include <sys/queue.h> 9641502Swpaul 9741502Swpaul#include <net/if.h> 9841502Swpaul#include <net/if_arp.h> 9941502Swpaul#include <net/ethernet.h> 10041502Swpaul#include <net/if_dl.h> 10141502Swpaul#include <net/if_media.h> 10241502Swpaul 10341502Swpaul#include <net/bpf.h> 10441502Swpaul 10541502Swpaul#include <vm/vm.h> /* for vtophys */ 10641502Swpaul#include <vm/pmap.h> /* for vtophys */ 10741502Swpaul#include <machine/bus_memio.h> 10841502Swpaul#include <machine/bus_pio.h> 10941502Swpaul#include <machine/bus.h> 11049611Swpaul#include <machine/resource.h> 11149611Swpaul#include <sys/bus.h> 11249611Swpaul#include <sys/rman.h> 11341502Swpaul 11441502Swpaul#include <pci/pcireg.h> 11541502Swpaul#include <pci/pcivar.h> 11641502Swpaul 11750675Swpaul#include <dev/mii/mii.h> 11850675Swpaul#include <dev/mii/miivar.h> 11950675Swpaul 12051089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12150675Swpaul#include "miibus_if.h" 12250675Swpaul 12341502Swpaul#define WB_USEIOSPACE 12441502Swpaul 12541502Swpaul#include <pci/if_wbreg.h> 12641502Swpaul 12759758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 12859758Speter 12941502Swpaul#ifndef lint 13041633Sarchiestatic const char rcsid[] = 13150477Speter "$FreeBSD: head/sys/pci/if_wb.c 106936 2002-11-14 23:49:09Z sam $"; 13241502Swpaul#endif 13341502Swpaul 13441502Swpaul/* 13541502Swpaul * Various supported device vendors/types and their names. 13641502Swpaul */ 13741502Swpaulstatic struct wb_type wb_devs[] = { 13841502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13941502Swpaul "Winbond W89C840F 10/100BaseTX" }, 14041502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 14141502Swpaul "Compex RL100-ATX 10/100baseTX" }, 14241502Swpaul { 0, 0, NULL } 14341502Swpaul}; 14441502Swpaul 14592739Salfredstatic int wb_probe (device_t); 14692739Salfredstatic int wb_attach (device_t); 14792739Salfredstatic int wb_detach (device_t); 14841502Swpaul 14998995Salfredstatic void wb_bfree (void *addr, void *args); 15092739Salfredstatic int wb_newbuf (struct wb_softc *, 15148745Swpaul struct wb_chain_onefrag *, 15292739Salfred struct mbuf *); 15392739Salfredstatic int wb_encap (struct wb_softc *, struct wb_chain *, 15492739Salfred struct mbuf *); 15541502Swpaul 15692739Salfredstatic void wb_rxeof (struct wb_softc *); 15792739Salfredstatic void wb_rxeoc (struct wb_softc *); 15892739Salfredstatic void wb_txeof (struct wb_softc *); 15992739Salfredstatic void wb_txeoc (struct wb_softc *); 16092739Salfredstatic void wb_intr (void *); 16192739Salfredstatic void wb_tick (void *); 16292739Salfredstatic void wb_start (struct ifnet *); 16392739Salfredstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 16492739Salfredstatic void wb_init (void *); 16592739Salfredstatic void wb_stop (struct wb_softc *); 16692739Salfredstatic void wb_watchdog (struct ifnet *); 16792739Salfredstatic void wb_shutdown (device_t); 16892739Salfredstatic int wb_ifmedia_upd (struct ifnet *); 16992739Salfredstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 17041502Swpaul 17192739Salfredstatic void wb_eeprom_putbyte (struct wb_softc *, int); 17292739Salfredstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 17392739Salfredstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 17492739Salfredstatic void wb_mii_sync (struct wb_softc *); 17592739Salfredstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 17692739Salfredstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 17792739Salfredstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 17841502Swpaul 17992739Salfredstatic void wb_setcfg (struct wb_softc *, u_int32_t); 18092739Salfredstatic u_int8_t wb_calchash (caddr_t); 18192739Salfredstatic void wb_setmulti (struct wb_softc *); 18292739Salfredstatic void wb_reset (struct wb_softc *); 18392739Salfredstatic void wb_fixmedia (struct wb_softc *); 18492739Salfredstatic int wb_list_rx_init (struct wb_softc *); 18592739Salfredstatic int wb_list_tx_init (struct wb_softc *); 18641502Swpaul 18792739Salfredstatic int wb_miibus_readreg (device_t, int, int); 18892739Salfredstatic int wb_miibus_writereg (device_t, int, int, int); 18992739Salfredstatic void wb_miibus_statchg (device_t); 19050675Swpaul 19149611Swpaul#ifdef WB_USEIOSPACE 19249611Swpaul#define WB_RES SYS_RES_IOPORT 19349611Swpaul#define WB_RID WB_PCI_LOIO 19449611Swpaul#else 19549611Swpaul#define WB_RES SYS_RES_MEMORY 19649611Swpaul#define WB_RID WB_PCI_LOMEM 19749611Swpaul#endif 19849611Swpaul 19949611Swpaulstatic device_method_t wb_methods[] = { 20049611Swpaul /* Device interface */ 20149611Swpaul DEVMETHOD(device_probe, wb_probe), 20249611Swpaul DEVMETHOD(device_attach, wb_attach), 20349611Swpaul DEVMETHOD(device_detach, wb_detach), 20449611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20550675Swpaul 20650675Swpaul /* bus interface, for miibus */ 20750675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20850675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20950675Swpaul 21050675Swpaul /* MII interface */ 21150675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 21250675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21350675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21449611Swpaul { 0, 0 } 21549611Swpaul}; 21649611Swpaul 21749611Swpaulstatic driver_t wb_driver = { 21851455Swpaul "wb", 21949611Swpaul wb_methods, 22049611Swpaul sizeof(struct wb_softc) 22149611Swpaul}; 22249611Swpaul 22349611Swpaulstatic devclass_t wb_devclass; 22449611Swpaul 22551533SwpaulDRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 22651473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22749611Swpaul 22841502Swpaul#define WB_SETBIT(sc, reg, x) \ 22941502Swpaul CSR_WRITE_4(sc, reg, \ 230105221Sphk CSR_READ_4(sc, reg) | (x)) 23141502Swpaul 23241502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23341502Swpaul CSR_WRITE_4(sc, reg, \ 234105221Sphk CSR_READ_4(sc, reg) & ~(x)) 23541502Swpaul 23641502Swpaul#define SIO_SET(x) \ 23741502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 238105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23941502Swpaul 24041502Swpaul#define SIO_CLR(x) \ 24141502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 242105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 24341502Swpaul 24441502Swpaul/* 24541502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24641502Swpaul */ 247102336Salfredstatic void 248102336Salfredwb_eeprom_putbyte(sc, addr) 24941502Swpaul struct wb_softc *sc; 25042718Swpaul int addr; 25141502Swpaul{ 25241502Swpaul register int d, i; 25341502Swpaul 25441502Swpaul d = addr | WB_EECMD_READ; 25541502Swpaul 25641502Swpaul /* 25741502Swpaul * Feed in each bit and stobe the clock. 25841502Swpaul */ 25941502Swpaul for (i = 0x400; i; i >>= 1) { 26041502Swpaul if (d & i) { 26141502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 26241502Swpaul } else { 26341502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26441502Swpaul } 26541502Swpaul DELAY(100); 26641502Swpaul SIO_SET(WB_SIO_EE_CLK); 26741502Swpaul DELAY(150); 26841502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26941502Swpaul DELAY(100); 27041502Swpaul } 27141502Swpaul 27241502Swpaul return; 27341502Swpaul} 27441502Swpaul 27541502Swpaul/* 27641502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27741502Swpaul */ 278102336Salfredstatic void 279102336Salfredwb_eeprom_getword(sc, addr, dest) 28041502Swpaul struct wb_softc *sc; 28142718Swpaul int addr; 28241502Swpaul u_int16_t *dest; 28341502Swpaul{ 28441502Swpaul register int i; 28541502Swpaul u_int16_t word = 0; 28641502Swpaul 28741502Swpaul /* Enter EEPROM access mode. */ 28841502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28941502Swpaul 29041502Swpaul /* 29141502Swpaul * Send address of word we want to read. 29241502Swpaul */ 29341502Swpaul wb_eeprom_putbyte(sc, addr); 29441502Swpaul 29541502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29641502Swpaul 29741502Swpaul /* 29841502Swpaul * Start reading bits from EEPROM. 29941502Swpaul */ 30041502Swpaul for (i = 0x8000; i; i >>= 1) { 30141502Swpaul SIO_SET(WB_SIO_EE_CLK); 30241502Swpaul DELAY(100); 30341502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30441502Swpaul word |= i; 30541502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30641502Swpaul DELAY(100); 30741502Swpaul } 30841502Swpaul 30941502Swpaul /* Turn off EEPROM access mode. */ 31041502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 31141502Swpaul 31241502Swpaul *dest = word; 31341502Swpaul 31441502Swpaul return; 31541502Swpaul} 31641502Swpaul 31741502Swpaul/* 31841502Swpaul * Read a sequence of words from the EEPROM. 31941502Swpaul */ 320102336Salfredstatic void 321102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 32241502Swpaul struct wb_softc *sc; 32341502Swpaul caddr_t dest; 32441502Swpaul int off; 32541502Swpaul int cnt; 32641502Swpaul int swap; 32741502Swpaul{ 32841502Swpaul int i; 32941502Swpaul u_int16_t word = 0, *ptr; 33041502Swpaul 33141502Swpaul for (i = 0; i < cnt; i++) { 33241502Swpaul wb_eeprom_getword(sc, off + i, &word); 33341502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33441502Swpaul if (swap) 33541502Swpaul *ptr = ntohs(word); 33641502Swpaul else 33741502Swpaul *ptr = word; 33841502Swpaul } 33941502Swpaul 34041502Swpaul return; 34141502Swpaul} 34241502Swpaul 34341502Swpaul/* 34441502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34541502Swpaul */ 346102336Salfredstatic void 347102336Salfredwb_mii_sync(sc) 34841502Swpaul struct wb_softc *sc; 34941502Swpaul{ 35041502Swpaul register int i; 35141502Swpaul 35241502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35341502Swpaul 35441502Swpaul for (i = 0; i < 32; i++) { 35541502Swpaul SIO_SET(WB_SIO_MII_CLK); 35641502Swpaul DELAY(1); 35741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35841502Swpaul DELAY(1); 35941502Swpaul } 36041502Swpaul 36141502Swpaul return; 36241502Swpaul} 36341502Swpaul 36441502Swpaul/* 36541502Swpaul * Clock a series of bits through the MII. 36641502Swpaul */ 367102336Salfredstatic void 368102336Salfredwb_mii_send(sc, bits, cnt) 36941502Swpaul struct wb_softc *sc; 37041502Swpaul u_int32_t bits; 37141502Swpaul int cnt; 37241502Swpaul{ 37341502Swpaul int i; 37441502Swpaul 37541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37641502Swpaul 37741502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37841502Swpaul if (bits & i) { 37941502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 38041502Swpaul } else { 38141502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 38241502Swpaul } 38341502Swpaul DELAY(1); 38441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38541502Swpaul DELAY(1); 38641502Swpaul SIO_SET(WB_SIO_MII_CLK); 38741502Swpaul } 38841502Swpaul} 38941502Swpaul 39041502Swpaul/* 39141502Swpaul * Read an PHY register through the MII. 39241502Swpaul */ 393102336Salfredstatic int 394102336Salfredwb_mii_readreg(sc, frame) 39541502Swpaul struct wb_softc *sc; 39641502Swpaul struct wb_mii_frame *frame; 39741502Swpaul 39841502Swpaul{ 39967087Swpaul int i, ack; 40041502Swpaul 40167087Swpaul WB_LOCK(sc); 40241502Swpaul 40341502Swpaul /* 40441502Swpaul * Set up frame for RX. 40541502Swpaul */ 40641502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40741502Swpaul frame->mii_opcode = WB_MII_READOP; 40841502Swpaul frame->mii_turnaround = 0; 40941502Swpaul frame->mii_data = 0; 41041502Swpaul 41141502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 41241502Swpaul 41341502Swpaul /* 41441502Swpaul * Turn on data xmit. 41541502Swpaul */ 41641502Swpaul SIO_SET(WB_SIO_MII_DIR); 41741502Swpaul 41841502Swpaul wb_mii_sync(sc); 41941502Swpaul 42041502Swpaul /* 42141502Swpaul * Send command/address info. 42241502Swpaul */ 42341502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42441502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42541502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42641502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42741502Swpaul 42841502Swpaul /* Idle bit */ 42941502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 43041502Swpaul DELAY(1); 43141502Swpaul SIO_SET(WB_SIO_MII_CLK); 43241502Swpaul DELAY(1); 43341502Swpaul 43441502Swpaul /* Turn off xmit. */ 43541502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43641502Swpaul /* Check for ack */ 43741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43841502Swpaul DELAY(1); 43941502Swpaul SIO_SET(WB_SIO_MII_CLK); 44041502Swpaul DELAY(1); 44141502Swpaul ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 44241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44341502Swpaul DELAY(1); 44441502Swpaul SIO_SET(WB_SIO_MII_CLK); 44541502Swpaul DELAY(1); 44641502Swpaul 44741502Swpaul /* 44841502Swpaul * Now try reading data bits. If the ack failed, we still 44941502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 45041502Swpaul */ 45141502Swpaul if (ack) { 45241502Swpaul for(i = 0; i < 16; i++) { 45341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45441502Swpaul DELAY(1); 45541502Swpaul SIO_SET(WB_SIO_MII_CLK); 45641502Swpaul DELAY(1); 45741502Swpaul } 45841502Swpaul goto fail; 45941502Swpaul } 46041502Swpaul 46141502Swpaul for (i = 0x8000; i; i >>= 1) { 46241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46341502Swpaul DELAY(1); 46441502Swpaul if (!ack) { 46541502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46641502Swpaul frame->mii_data |= i; 46741502Swpaul DELAY(1); 46841502Swpaul } 46941502Swpaul SIO_SET(WB_SIO_MII_CLK); 47041502Swpaul DELAY(1); 47141502Swpaul } 47241502Swpaul 47341502Swpaulfail: 47441502Swpaul 47541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47641502Swpaul DELAY(1); 47741502Swpaul SIO_SET(WB_SIO_MII_CLK); 47841502Swpaul DELAY(1); 47941502Swpaul 48067087Swpaul WB_UNLOCK(sc); 48141502Swpaul 48241502Swpaul if (ack) 48341502Swpaul return(1); 48441502Swpaul return(0); 48541502Swpaul} 48641502Swpaul 48741502Swpaul/* 48841502Swpaul * Write to a PHY register through the MII. 48941502Swpaul */ 490102336Salfredstatic int 491102336Salfredwb_mii_writereg(sc, frame) 49241502Swpaul struct wb_softc *sc; 49341502Swpaul struct wb_mii_frame *frame; 49441502Swpaul 49541502Swpaul{ 49667087Swpaul WB_LOCK(sc); 49741502Swpaul 49841502Swpaul /* 49941502Swpaul * Set up frame for TX. 50041502Swpaul */ 50141502Swpaul 50241502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 50341502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50441502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50541502Swpaul 50641502Swpaul /* 50741502Swpaul * Turn on data output. 50841502Swpaul */ 50941502Swpaul SIO_SET(WB_SIO_MII_DIR); 51041502Swpaul 51141502Swpaul wb_mii_sync(sc); 51241502Swpaul 51341502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51441502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51541502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51641502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51741502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51841502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51941502Swpaul 52041502Swpaul /* Idle bit. */ 52141502Swpaul SIO_SET(WB_SIO_MII_CLK); 52241502Swpaul DELAY(1); 52341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52441502Swpaul DELAY(1); 52541502Swpaul 52641502Swpaul /* 52741502Swpaul * Turn off xmit. 52841502Swpaul */ 52941502Swpaul SIO_CLR(WB_SIO_MII_DIR); 53041502Swpaul 53167087Swpaul WB_UNLOCK(sc); 53241502Swpaul 53341502Swpaul return(0); 53441502Swpaul} 53541502Swpaul 536102336Salfredstatic int 537102336Salfredwb_miibus_readreg(dev, phy, reg) 53850675Swpaul device_t dev; 53950675Swpaul int phy, reg; 54050675Swpaul{ 54141502Swpaul struct wb_softc *sc; 54241502Swpaul struct wb_mii_frame frame; 54341502Swpaul 54450675Swpaul sc = device_get_softc(dev); 54550675Swpaul 54641502Swpaul bzero((char *)&frame, sizeof(frame)); 54741502Swpaul 54850675Swpaul frame.mii_phyaddr = phy; 54941502Swpaul frame.mii_regaddr = reg; 55041502Swpaul wb_mii_readreg(sc, &frame); 55141502Swpaul 55241502Swpaul return(frame.mii_data); 55341502Swpaul} 55441502Swpaul 555102336Salfredstatic int 556102336Salfredwb_miibus_writereg(dev, phy, reg, data) 55750675Swpaul device_t dev; 55850675Swpaul int phy, reg, data; 55950675Swpaul{ 56041502Swpaul struct wb_softc *sc; 56141502Swpaul struct wb_mii_frame frame; 56241502Swpaul 56350675Swpaul sc = device_get_softc(dev); 56450675Swpaul 56541502Swpaul bzero((char *)&frame, sizeof(frame)); 56641502Swpaul 56750675Swpaul frame.mii_phyaddr = phy; 56841502Swpaul frame.mii_regaddr = reg; 56941502Swpaul frame.mii_data = data; 57041502Swpaul 57141502Swpaul wb_mii_writereg(sc, &frame); 57241502Swpaul 57350675Swpaul return(0); 57450675Swpaul} 57550675Swpaul 576102336Salfredstatic void 577102336Salfredwb_miibus_statchg(dev) 57850675Swpaul device_t dev; 57950675Swpaul{ 58050675Swpaul struct wb_softc *sc; 58150675Swpaul struct mii_data *mii; 58250675Swpaul 58350675Swpaul sc = device_get_softc(dev); 58467087Swpaul WB_LOCK(sc); 58550675Swpaul mii = device_get_softc(sc->wb_miibus); 58650675Swpaul wb_setcfg(sc, mii->mii_media_active); 58767087Swpaul WB_UNLOCK(sc); 58850675Swpaul 58941502Swpaul return; 59041502Swpaul} 59141502Swpaul 59241502Swpaulstatic u_int8_t wb_calchash(addr) 59342718Swpaul caddr_t addr; 59441502Swpaul{ 59541502Swpaul u_int32_t crc, carry; 59641502Swpaul int i, j; 59741502Swpaul u_int8_t c; 59841502Swpaul 59941502Swpaul /* Compute CRC for the address value. */ 60041502Swpaul crc = 0xFFFFFFFF; /* initial value */ 60141502Swpaul 60241502Swpaul for (i = 0; i < 6; i++) { 60341502Swpaul c = *(addr + i); 60441502Swpaul for (j = 0; j < 8; j++) { 60541502Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 60641502Swpaul crc <<= 1; 60741502Swpaul c >>= 1; 60841502Swpaul if (carry) 60941502Swpaul crc = (crc ^ 0x04c11db6) | carry; 61041502Swpaul } 61141502Swpaul } 61241502Swpaul 61341502Swpaul /* 61441502Swpaul * return the filter bit position 61541502Swpaul * Note: I arrived at the following nonsense 61641502Swpaul * through experimentation. It's not the usual way to 61741502Swpaul * generate the bit position but it's the only thing 61841502Swpaul * I could come up with that works. 61941502Swpaul */ 62041502Swpaul return(~(crc >> 26) & 0x0000003F); 62141502Swpaul} 62241502Swpaul 62341502Swpaul/* 62441502Swpaul * Program the 64-bit multicast hash filter. 62541502Swpaul */ 626102336Salfredstatic void 627102336Salfredwb_setmulti(sc) 62841502Swpaul struct wb_softc *sc; 62941502Swpaul{ 63041502Swpaul struct ifnet *ifp; 63141502Swpaul int h = 0; 63241502Swpaul u_int32_t hashes[2] = { 0, 0 }; 63341502Swpaul struct ifmultiaddr *ifma; 63441502Swpaul u_int32_t rxfilt; 63541502Swpaul int mcnt = 0; 63641502Swpaul 63741502Swpaul ifp = &sc->arpcom.ac_if; 63841502Swpaul 63941502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 64041502Swpaul 64141502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 64241502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 64341502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 64441502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 64541502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 64641502Swpaul return; 64741502Swpaul } 64841502Swpaul 64941502Swpaul /* first, zot all the existing hash bits */ 65041502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 65141502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 65241502Swpaul 65341502Swpaul /* now program new ones */ 65472084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 65541502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 65641502Swpaul continue; 65741502Swpaul h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 65841502Swpaul if (h < 32) 65941502Swpaul hashes[0] |= (1 << h); 66041502Swpaul else 66141502Swpaul hashes[1] |= (1 << (h - 32)); 66241502Swpaul mcnt++; 66341502Swpaul } 66441502Swpaul 66541502Swpaul if (mcnt) 66641502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 66741502Swpaul else 66841502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 66941502Swpaul 67041502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 67141502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 67241502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 67341502Swpaul 67441502Swpaul return; 67541502Swpaul} 67641502Swpaul 67741502Swpaul/* 67841502Swpaul * The Winbond manual states that in order to fiddle with the 67941502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 68041502Swpaul * first have to put the transmit and/or receive logic in the idle state. 68141502Swpaul */ 682102336Salfredstatic void 683102336Salfredwb_setcfg(sc, media) 68441502Swpaul struct wb_softc *sc; 68550675Swpaul u_int32_t media; 68641502Swpaul{ 68741502Swpaul int i, restart = 0; 68841502Swpaul 68941502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 69041502Swpaul restart = 1; 69141502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 69241502Swpaul 69341502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69441502Swpaul DELAY(10); 69541502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 69641502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 69741502Swpaul break; 69841502Swpaul } 69941502Swpaul 70041502Swpaul if (i == WB_TIMEOUT) 70141502Swpaul printf("wb%d: failed to force tx and " 70241502Swpaul "rx to idle state\n", sc->wb_unit); 70341502Swpaul } 70441502Swpaul 70550675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 70650675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70750675Swpaul else 70841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70941502Swpaul 71050675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 71141502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71241502Swpaul else 71341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71441502Swpaul 71541502Swpaul if (restart) 71641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 71741502Swpaul 71841502Swpaul return; 71941502Swpaul} 72041502Swpaul 721102336Salfredstatic void 722102336Salfredwb_reset(sc) 72341502Swpaul struct wb_softc *sc; 72441502Swpaul{ 72541502Swpaul register int i; 72650675Swpaul struct mii_data *mii; 72741502Swpaul 72850675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 72950675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 73050675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 73150675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 73250675Swpaul 73341502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73450675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73541502Swpaul 73641502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 73741502Swpaul DELAY(10); 73841502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 73941502Swpaul break; 74041502Swpaul } 74141502Swpaul if (i == WB_TIMEOUT) 74241502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 74341502Swpaul 74441502Swpaul /* Wait a little while for the chip to get its brains in order. */ 74541502Swpaul DELAY(1000); 74641502Swpaul 74750675Swpaul if (sc->wb_miibus == NULL) 74850675Swpaul return; 74941502Swpaul 75050675Swpaul mii = device_get_softc(sc->wb_miibus); 75150675Swpaul if (mii == NULL) 75250675Swpaul return; 75350675Swpaul 75450675Swpaul if (mii->mii_instance) { 75550675Swpaul struct mii_softc *miisc; 75672012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 75750675Swpaul mii_phy_reset(miisc); 75850675Swpaul } 75950675Swpaul 76041502Swpaul return; 76141502Swpaul} 76241502Swpaul 763102336Salfredstatic void 764102336Salfredwb_fixmedia(sc) 76550675Swpaul struct wb_softc *sc; 76650675Swpaul{ 76750675Swpaul struct mii_data *mii = NULL; 76850675Swpaul struct ifnet *ifp; 76950675Swpaul u_int32_t media; 77050675Swpaul 77150675Swpaul if (sc->wb_miibus == NULL) 77250675Swpaul return; 77350675Swpaul 77450675Swpaul mii = device_get_softc(sc->wb_miibus); 77550675Swpaul ifp = &sc->arpcom.ac_if; 77650675Swpaul 77750675Swpaul mii_pollstat(mii); 77850675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 77950675Swpaul media = mii->mii_media_active & ~IFM_10_T; 78050675Swpaul media |= IFM_100_TX; 78150675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 78250675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 78350675Swpaul media |= IFM_10_T; 78450675Swpaul } else 78550675Swpaul return; 78650675Swpaul 78750675Swpaul ifmedia_set(&mii->mii_media, media); 78850675Swpaul 78950675Swpaul return; 79050675Swpaul} 79150675Swpaul 79241502Swpaul/* 79341502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 79441502Swpaul * IDs against our list and return a device name if we find a match. 79541502Swpaul */ 796102336Salfredstatic int 797102336Salfredwb_probe(dev) 79849611Swpaul device_t dev; 79941502Swpaul{ 80041502Swpaul struct wb_type *t; 80141502Swpaul 80241502Swpaul t = wb_devs; 80341502Swpaul 80441502Swpaul while(t->wb_name != NULL) { 80549611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 80649611Swpaul (pci_get_device(dev) == t->wb_did)) { 80749611Swpaul device_set_desc(dev, t->wb_name); 80849611Swpaul return(0); 80941502Swpaul } 81041502Swpaul t++; 81141502Swpaul } 81241502Swpaul 81349611Swpaul return(ENXIO); 81441502Swpaul} 81541502Swpaul 81641502Swpaul/* 81741502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 81841502Swpaul * setup and ethernet/BPF attach. 81941502Swpaul */ 820102336Salfredstatic int 821102336Salfredwb_attach(dev) 82249611Swpaul device_t dev; 82341502Swpaul{ 82441502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 82541502Swpaul u_int32_t command; 82641502Swpaul struct wb_softc *sc; 82741502Swpaul struct ifnet *ifp; 82849611Swpaul int unit, error = 0, rid; 82941502Swpaul 83049611Swpaul sc = device_get_softc(dev); 83149611Swpaul unit = device_get_unit(dev); 83241502Swpaul 83393818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 83493818Sjhb MTX_DEF | MTX_RECURSE); 83569583Swpaul WB_LOCK(sc); 83669583Swpaul 83741502Swpaul /* 83841502Swpaul * Handle power management nonsense. 83941502Swpaul */ 84041502Swpaul 84172813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 84272813Swpaul u_int32_t iobase, membase, irq; 84341502Swpaul 84472813Swpaul /* Save important PCI config data. */ 84572813Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 84672813Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 84772813Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 84841502Swpaul 84972813Swpaul /* Reset the power state. */ 85072813Swpaul printf("wb%d: chip is in D%d power mode " 85172813Swpaul "-- setting to D0\n", unit, 85272813Swpaul pci_get_powerstate(dev)); 85372813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 85441502Swpaul 85572813Swpaul /* Restore PCI config data. */ 85672813Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 85772813Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 85872813Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 85941502Swpaul } 86041502Swpaul 86141502Swpaul /* 86241502Swpaul * Map control/status registers. 86341502Swpaul */ 86472813Swpaul pci_enable_busmaster(dev); 86579472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 86679472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 86761041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 86841502Swpaul 86941502Swpaul#ifdef WB_USEIOSPACE 87041502Swpaul if (!(command & PCIM_CMD_PORTEN)) { 87141502Swpaul printf("wb%d: failed to enable I/O ports!\n", unit); 87249611Swpaul error = ENXIO; 87341502Swpaul goto fail; 87441502Swpaul } 87541502Swpaul#else 87641502Swpaul if (!(command & PCIM_CMD_MEMEN)) { 87741502Swpaul printf("wb%d: failed to enable memory mapping!\n", unit); 87849611Swpaul error = ENXIO; 87941502Swpaul goto fail; 88041502Swpaul } 88149611Swpaul#endif 88241502Swpaul 88349611Swpaul rid = WB_RID; 88449611Swpaul sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 88549611Swpaul 0, ~0, 1, RF_ACTIVE); 88649611Swpaul 88749611Swpaul if (sc->wb_res == NULL) { 88849611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 88949611Swpaul error = ENXIO; 89041502Swpaul goto fail; 89141502Swpaul } 89241502Swpaul 89349611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 89449611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 89549611Swpaul 89641502Swpaul /* Allocate interrupt */ 89749611Swpaul rid = 0; 89849611Swpaul sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 89949611Swpaul RF_SHAREABLE | RF_ACTIVE); 90049611Swpaul 90149611Swpaul if (sc->wb_irq == NULL) { 90241502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 90349611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 90449611Swpaul error = ENXIO; 90541502Swpaul goto fail; 90641502Swpaul } 90741502Swpaul 90849611Swpaul error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 90949611Swpaul wb_intr, sc, &sc->wb_intrhand); 91049611Swpaul 91149611Swpaul if (error) { 91249611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 91349611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 91449611Swpaul printf("wb%d: couldn't set up irq\n", unit); 91549611Swpaul goto fail; 91649611Swpaul } 91750675Swpaul 91850675Swpaul /* Save the cache line size. */ 91950675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 92050675Swpaul 92141502Swpaul /* Reset the adapter. */ 92241502Swpaul wb_reset(sc); 92341502Swpaul 92441502Swpaul /* 92541502Swpaul * Get station address from the EEPROM. 92641502Swpaul */ 92741502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 92841502Swpaul 92941502Swpaul /* 93041502Swpaul * A Winbond chip was detected. Inform the world. 93141502Swpaul */ 93241502Swpaul printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 93341502Swpaul 93441502Swpaul sc->wb_unit = unit; 93541502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 93641502Swpaul 93750675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 93851657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 93950675Swpaul 94050675Swpaul if (sc->wb_ldata == NULL) { 94141502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 94249611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 94349611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 94449611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 94549611Swpaul error = ENXIO; 94649611Swpaul goto fail; 94741502Swpaul } 94841502Swpaul 94941502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 95041502Swpaul 95141502Swpaul ifp = &sc->arpcom.ac_if; 95241502Swpaul ifp->if_softc = sc; 95341502Swpaul ifp->if_unit = unit; 95441502Swpaul ifp->if_name = "wb"; 95541502Swpaul ifp->if_mtu = ETHERMTU; 95641502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 95741502Swpaul ifp->if_ioctl = wb_ioctl; 95841502Swpaul ifp->if_output = ether_output; 95941502Swpaul ifp->if_start = wb_start; 96041502Swpaul ifp->if_watchdog = wb_watchdog; 96141502Swpaul ifp->if_init = wb_init; 96241502Swpaul ifp->if_baudrate = 10000000; 96343515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 96441502Swpaul 96550675Swpaul /* 96650675Swpaul * Do MII setup. 96750675Swpaul */ 96850675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 96950675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 97049611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 97149611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 97249611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 97349611Swpaul free(sc->wb_ldata_ptr, M_DEVBUF); 97449611Swpaul error = ENXIO; 97541502Swpaul goto fail; 97641502Swpaul } 97741502Swpaul 97841502Swpaul /* 97963090Sarchie * Call MI attach routine. 98041502Swpaul */ 981106936Ssam ether_ifattach(ifp, eaddr); 98267087Swpaul WB_UNLOCK(sc); 98367087Swpaul return(0); 98441502Swpaul 98541502Swpaulfail: 98650675Swpaul if (error) 98750675Swpaul device_delete_child(dev, sc->wb_miibus); 98867087Swpaul WB_UNLOCK(sc); 98967087Swpaul mtx_destroy(&sc->wb_mtx); 99050675Swpaul 99149611Swpaul return(error); 99241502Swpaul} 99341502Swpaul 994102336Salfredstatic int 995102336Salfredwb_detach(dev) 99649611Swpaul device_t dev; 99749611Swpaul{ 99849611Swpaul struct wb_softc *sc; 99949611Swpaul struct ifnet *ifp; 100049611Swpaul 100149611Swpaul sc = device_get_softc(dev); 100267087Swpaul WB_LOCK(sc); 100349611Swpaul ifp = &sc->arpcom.ac_if; 100449611Swpaul 100549611Swpaul wb_stop(sc); 1006106936Ssam ether_ifdetach(ifp); 100749611Swpaul 100850675Swpaul /* Delete any miibus and phy devices attached to this interface */ 100950675Swpaul bus_generic_detach(dev); 101050675Swpaul device_delete_child(dev, sc->wb_miibus); 101150675Swpaul 101249611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 101349611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 101449611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 101549611Swpaul 101649611Swpaul free(sc->wb_ldata_ptr, M_DEVBUF); 101749611Swpaul 101867087Swpaul WB_UNLOCK(sc); 101967087Swpaul mtx_destroy(&sc->wb_mtx); 102049611Swpaul 102149611Swpaul return(0); 102249611Swpaul} 102349611Swpaul 102441502Swpaul/* 102541502Swpaul * Initialize the transmit descriptors. 102641502Swpaul */ 1027102336Salfredstatic int 1028102336Salfredwb_list_tx_init(sc) 102941502Swpaul struct wb_softc *sc; 103041502Swpaul{ 103141502Swpaul struct wb_chain_data *cd; 103241502Swpaul struct wb_list_data *ld; 103341502Swpaul int i; 103441502Swpaul 103541502Swpaul cd = &sc->wb_cdata; 103641502Swpaul ld = sc->wb_ldata; 103741502Swpaul 103841502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 103941502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 104041502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 104141502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 104241502Swpaul &cd->wb_tx_chain[0]; 104341502Swpaul } else { 104441502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 104541502Swpaul &cd->wb_tx_chain[i + 1]; 104641502Swpaul } 104741502Swpaul } 104841502Swpaul 104941502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 105041502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 105141502Swpaul 105241502Swpaul return(0); 105341502Swpaul} 105441502Swpaul 105541502Swpaul 105641502Swpaul/* 105741502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 105841502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 105941502Swpaul * points back to the first. 106041502Swpaul */ 1061102336Salfredstatic int 1062102336Salfredwb_list_rx_init(sc) 106341502Swpaul struct wb_softc *sc; 106441502Swpaul{ 106541502Swpaul struct wb_chain_data *cd; 106641502Swpaul struct wb_list_data *ld; 106741502Swpaul int i; 106841502Swpaul 106941502Swpaul cd = &sc->wb_cdata; 107041502Swpaul ld = sc->wb_ldata; 107141502Swpaul 107241502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 107341502Swpaul cd->wb_rx_chain[i].wb_ptr = 107441502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 107550675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 107648745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 107741502Swpaul return(ENOBUFS); 107841502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 107941502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 108041502Swpaul ld->wb_rx_list[i].wb_next = 108141502Swpaul vtophys(&ld->wb_rx_list[0]); 108241502Swpaul } else { 108341502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 108441502Swpaul &cd->wb_rx_chain[i + 1]; 108541502Swpaul ld->wb_rx_list[i].wb_next = 108641502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 108741502Swpaul } 108841502Swpaul } 108941502Swpaul 109041502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 109141502Swpaul 109241502Swpaul return(0); 109341502Swpaul} 109441502Swpaul 1095102336Salfredstatic void 1096102336Salfredwb_bfree(buf, args) 109798995Salfred void *buf; 109864837Sdwmalone void *args; 109950675Swpaul{ 110050675Swpaul return; 110150675Swpaul} 110250675Swpaul 110341502Swpaul/* 110441502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 110541502Swpaul */ 1106102336Salfredstatic int 1107102336Salfredwb_newbuf(sc, c, m) 110841502Swpaul struct wb_softc *sc; 110941502Swpaul struct wb_chain_onefrag *c; 111048745Swpaul struct mbuf *m; 111141502Swpaul{ 111241502Swpaul struct mbuf *m_new = NULL; 111341502Swpaul 111448745Swpaul if (m == NULL) { 111548745Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 111687846Sluigi if (m_new == NULL) 111748745Swpaul return(ENOBUFS); 111864837Sdwmalone m_new->m_data = c->wb_buf; 111964837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 112068621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 112168621Sbmilekic EXT_NET_DRV); 112248745Swpaul } else { 112348745Swpaul m_new = m; 112450675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 112548745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 112641502Swpaul } 112741502Swpaul 112848745Swpaul m_adj(m_new, sizeof(u_int64_t)); 112948745Swpaul 113041502Swpaul c->wb_mbuf = m_new; 113141502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 113250675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 113341502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 113441502Swpaul 113541502Swpaul return(0); 113641502Swpaul} 113741502Swpaul 113841502Swpaul/* 113941502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 114041502Swpaul * the higher level protocols. 114141502Swpaul */ 1142102336Salfredstatic void 1143102336Salfredwb_rxeof(sc) 114441502Swpaul struct wb_softc *sc; 114541502Swpaul{ 114650675Swpaul struct mbuf *m = NULL; 114741502Swpaul struct ifnet *ifp; 114841502Swpaul struct wb_chain_onefrag *cur_rx; 114941502Swpaul int total_len = 0; 115041502Swpaul u_int32_t rxstat; 115141502Swpaul 115241502Swpaul ifp = &sc->arpcom.ac_if; 115341502Swpaul 115441502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 115541502Swpaul WB_RXSTAT_OWN)) { 115648745Swpaul struct mbuf *m0 = NULL; 115748745Swpaul 115841502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 115941502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 116050675Swpaul 116148745Swpaul m = cur_rx->wb_mbuf; 116241502Swpaul 116350675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 116450675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 116550675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 116650675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 116750675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 116841502Swpaul ifp->if_ierrors++; 116950675Swpaul wb_newbuf(sc, cur_rx, m); 117041502Swpaul printf("wb%x: receiver babbling: possible chip " 117141502Swpaul "bug, forcing reset\n", sc->wb_unit); 117250675Swpaul wb_fixmedia(sc); 117350675Swpaul wb_reset(sc); 117450675Swpaul wb_init(sc); 117541502Swpaul return; 117641502Swpaul } 117741502Swpaul 117842718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 117942718Swpaul ifp->if_ierrors++; 118048745Swpaul wb_newbuf(sc, cur_rx, m); 118150675Swpaul break; 118242718Swpaul } 118342718Swpaul 118441502Swpaul /* No errors; receive the packet. */ 118541502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 118641502Swpaul 118741502Swpaul /* 118841934Swpaul * XXX The Winbond chip includes the CRC with every 118941934Swpaul * received frame, and there's no way to turn this 119041934Swpaul * behavior off (at least, I can't find anything in 119141934Swpaul * the manual that explains how to do it) so we have 119241934Swpaul * to trim off the CRC manually. 119341934Swpaul */ 119441934Swpaul total_len -= ETHER_CRC_LEN; 119541934Swpaul 119678508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 119778508Sbmilekic NULL); 119848745Swpaul wb_newbuf(sc, cur_rx, m); 119948745Swpaul if (m0 == NULL) { 120048745Swpaul ifp->if_ierrors++; 120150675Swpaul break; 120241502Swpaul } 120348745Swpaul m = m0; 120441502Swpaul 120541502Swpaul ifp->if_ipackets++; 1206106936Ssam (*ifp->if_input)(ifp, m); 120741502Swpaul } 120841502Swpaul} 120941502Swpaul 1210105221Sphkstatic void 1211102336Salfredwb_rxeoc(sc) 121241502Swpaul struct wb_softc *sc; 121341502Swpaul{ 121441502Swpaul wb_rxeof(sc); 121541502Swpaul 121641502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 121741502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 121841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 121941502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 122041502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 122141502Swpaul 122241502Swpaul return; 122341502Swpaul} 122441502Swpaul 122541502Swpaul/* 122641502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 122741502Swpaul * the list buffers. 122841502Swpaul */ 1229102336Salfredstatic void 1230102336Salfredwb_txeof(sc) 123141502Swpaul struct wb_softc *sc; 123241502Swpaul{ 123341502Swpaul struct wb_chain *cur_tx; 123441502Swpaul struct ifnet *ifp; 123541502Swpaul 123641502Swpaul ifp = &sc->arpcom.ac_if; 123741502Swpaul 123841502Swpaul /* Clear the timeout timer. */ 123941502Swpaul ifp->if_timer = 0; 124041502Swpaul 124141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 124241502Swpaul return; 124341502Swpaul 124441502Swpaul /* 124541502Swpaul * Go through our tx list and free mbufs for those 124641502Swpaul * frames that have been transmitted. 124741502Swpaul */ 124841502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 124941502Swpaul u_int32_t txstat; 125041502Swpaul 125141502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 125241502Swpaul txstat = WB_TXSTATUS(cur_tx); 125341502Swpaul 125441502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 125541502Swpaul break; 125641502Swpaul 125741502Swpaul if (txstat & WB_TXSTAT_TXERR) { 125841502Swpaul ifp->if_oerrors++; 125941502Swpaul if (txstat & WB_TXSTAT_ABORT) 126041502Swpaul ifp->if_collisions++; 126141502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 126241502Swpaul ifp->if_collisions++; 126341502Swpaul } 126441502Swpaul 126541502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 126641502Swpaul 126741502Swpaul ifp->if_opackets++; 126841502Swpaul m_freem(cur_tx->wb_mbuf); 126941502Swpaul cur_tx->wb_mbuf = NULL; 127041502Swpaul 127141502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 127241502Swpaul sc->wb_cdata.wb_tx_head = NULL; 127341502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 127441502Swpaul break; 127541502Swpaul } 127641502Swpaul 127741502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 127841502Swpaul } 127941502Swpaul 128041502Swpaul return; 128141502Swpaul} 128241502Swpaul 128341502Swpaul/* 128441502Swpaul * TX 'end of channel' interrupt handler. 128541502Swpaul */ 1286102336Salfredstatic void 1287102336Salfredwb_txeoc(sc) 128841502Swpaul struct wb_softc *sc; 128941502Swpaul{ 129041502Swpaul struct ifnet *ifp; 129141502Swpaul 129241502Swpaul ifp = &sc->arpcom.ac_if; 129341502Swpaul 129441502Swpaul ifp->if_timer = 0; 129541502Swpaul 129641502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 129741502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 129841502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 129941502Swpaul } else { 130041502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 130141502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 130241502Swpaul ifp->if_timer = 5; 130341502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 130441502Swpaul } 130541502Swpaul } 130641502Swpaul 130741502Swpaul return; 130841502Swpaul} 130941502Swpaul 1310102336Salfredstatic void 1311102336Salfredwb_intr(arg) 131241502Swpaul void *arg; 131341502Swpaul{ 131441502Swpaul struct wb_softc *sc; 131541502Swpaul struct ifnet *ifp; 131641502Swpaul u_int32_t status; 131741502Swpaul 131841502Swpaul sc = arg; 131967087Swpaul WB_LOCK(sc); 132041502Swpaul ifp = &sc->arpcom.ac_if; 132141502Swpaul 132267087Swpaul if (!(ifp->if_flags & IFF_UP)) { 132367087Swpaul WB_UNLOCK(sc); 132441502Swpaul return; 132567087Swpaul } 132641502Swpaul 132741502Swpaul /* Disable interrupts. */ 132841502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 132941502Swpaul 133041502Swpaul for (;;) { 133141502Swpaul 133241502Swpaul status = CSR_READ_4(sc, WB_ISR); 133341502Swpaul if (status) 133441502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 133541502Swpaul 133641502Swpaul if ((status & WB_INTRS) == 0) 133741502Swpaul break; 133841502Swpaul 133941502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 134041502Swpaul ifp->if_ierrors++; 134141502Swpaul wb_reset(sc); 134250675Swpaul if (status & WB_ISR_RX_ERR) 134350675Swpaul wb_fixmedia(sc); 134441502Swpaul wb_init(sc); 134550675Swpaul continue; 134641502Swpaul } 134741502Swpaul 134850675Swpaul if (status & WB_ISR_RX_OK) 134950675Swpaul wb_rxeof(sc); 135050675Swpaul 135150675Swpaul if (status & WB_ISR_RX_IDLE) 135250675Swpaul wb_rxeoc(sc); 135350675Swpaul 135441502Swpaul if (status & WB_ISR_TX_OK) 135541502Swpaul wb_txeof(sc); 135641502Swpaul 135741502Swpaul if (status & WB_ISR_TX_NOBUF) 135841502Swpaul wb_txeoc(sc); 135941502Swpaul 136041502Swpaul if (status & WB_ISR_TX_IDLE) { 136141502Swpaul wb_txeof(sc); 136241502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 136341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 136541502Swpaul } 136641502Swpaul } 136741502Swpaul 136841502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 136941502Swpaul ifp->if_oerrors++; 137041502Swpaul wb_txeof(sc); 137141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 137241502Swpaul /* Jack up TX threshold */ 137341502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 137441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 137541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 137641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 137741502Swpaul } 137841502Swpaul 137941502Swpaul if (status & WB_ISR_BUS_ERR) { 138041502Swpaul wb_reset(sc); 138141502Swpaul wb_init(sc); 138241502Swpaul } 138341502Swpaul 138441502Swpaul } 138541502Swpaul 138641502Swpaul /* Re-enable interrupts. */ 138741502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 138841502Swpaul 138941502Swpaul if (ifp->if_snd.ifq_head != NULL) { 139041502Swpaul wb_start(ifp); 139141502Swpaul } 139241502Swpaul 139367087Swpaul WB_UNLOCK(sc); 139467087Swpaul 139541502Swpaul return; 139641502Swpaul} 139741502Swpaul 1398102336Salfredstatic void 1399102336Salfredwb_tick(xsc) 140050675Swpaul void *xsc; 140150675Swpaul{ 140250675Swpaul struct wb_softc *sc; 140350675Swpaul struct mii_data *mii; 140450675Swpaul 140550675Swpaul sc = xsc; 140667087Swpaul WB_LOCK(sc); 140750675Swpaul mii = device_get_softc(sc->wb_miibus); 140850675Swpaul 140950675Swpaul mii_tick(mii); 141050675Swpaul 141150675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 141250675Swpaul 141367087Swpaul WB_UNLOCK(sc); 141450685Swpaul 141550675Swpaul return; 141650675Swpaul} 141750675Swpaul 141841502Swpaul/* 141941502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 142041502Swpaul * pointers to the fragment pointers. 142141502Swpaul */ 1422102336Salfredstatic int 1423102336Salfredwb_encap(sc, c, m_head) 142441502Swpaul struct wb_softc *sc; 142541502Swpaul struct wb_chain *c; 142641502Swpaul struct mbuf *m_head; 142741502Swpaul{ 142841502Swpaul int frag = 0; 142941502Swpaul struct wb_desc *f = NULL; 143041502Swpaul int total_len; 143141502Swpaul struct mbuf *m; 143241502Swpaul 143341502Swpaul /* 143441502Swpaul * Start packing the mbufs in this chain into 143541502Swpaul * the fragment pointers. Stop when we run out 143641502Swpaul * of fragments or hit the end of the mbuf chain. 143741502Swpaul */ 143841502Swpaul m = m_head; 143941502Swpaul total_len = 0; 144041502Swpaul 144141502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 144241502Swpaul if (m->m_len != 0) { 144341502Swpaul if (frag == WB_MAXFRAGS) 144441502Swpaul break; 144541502Swpaul total_len += m->m_len; 144641502Swpaul f = &c->wb_ptr->wb_frag[frag]; 144741502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 144841502Swpaul if (frag == 0) { 144941502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 145041502Swpaul f->wb_status = 0; 145141502Swpaul } else 145241502Swpaul f->wb_status = WB_TXSTAT_OWN; 145341502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 145441502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 145541502Swpaul frag++; 145641502Swpaul } 145741502Swpaul } 145841502Swpaul 145941502Swpaul /* 146041502Swpaul * Handle special case: we used up all 16 fragments, 146141502Swpaul * but we have more mbufs left in the chain. Copy the 146241502Swpaul * data into an mbuf cluster. Note that we don't 146341502Swpaul * bother clearing the values in the other fragment 146441502Swpaul * pointers/counters; it wouldn't gain us anything, 146541502Swpaul * and would waste cycles. 146641502Swpaul */ 146741502Swpaul if (m != NULL) { 146841502Swpaul struct mbuf *m_new = NULL; 146941502Swpaul 147041502Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 147187846Sluigi if (m_new == NULL) 147241502Swpaul return(1); 147341502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 147441502Swpaul MCLGET(m_new, M_DONTWAIT); 147541502Swpaul if (!(m_new->m_flags & M_EXT)) { 147641502Swpaul m_freem(m_new); 147741502Swpaul return(1); 147841502Swpaul } 147941502Swpaul } 148041502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 148141502Swpaul mtod(m_new, caddr_t)); 148241502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 148341502Swpaul m_freem(m_head); 148441502Swpaul m_head = m_new; 148541502Swpaul f = &c->wb_ptr->wb_frag[0]; 148641502Swpaul f->wb_status = 0; 148741502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 148841502Swpaul f->wb_ctl = total_len = m_new->m_len; 148941502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 149041502Swpaul frag = 1; 149141502Swpaul } 149241502Swpaul 149341502Swpaul if (total_len < WB_MIN_FRAMELEN) { 149441502Swpaul f = &c->wb_ptr->wb_frag[frag]; 149541502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 149641502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 149741502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 149841502Swpaul f->wb_status = WB_TXSTAT_OWN; 149941502Swpaul frag++; 150041502Swpaul } 150141502Swpaul 150241502Swpaul c->wb_mbuf = m_head; 150341502Swpaul c->wb_lastdesc = frag - 1; 150441502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 150541502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 150641502Swpaul 150741502Swpaul return(0); 150841502Swpaul} 150941502Swpaul 151041502Swpaul/* 151141502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 151241502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 151341502Swpaul * copy of the pointers since the transmit list fragment pointers are 151441502Swpaul * physical addresses. 151541502Swpaul */ 151641502Swpaul 1517102336Salfredstatic void 1518102336Salfredwb_start(ifp) 151941502Swpaul struct ifnet *ifp; 152041502Swpaul{ 152141502Swpaul struct wb_softc *sc; 152241502Swpaul struct mbuf *m_head = NULL; 152341502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 152441502Swpaul 152541502Swpaul sc = ifp->if_softc; 152667087Swpaul WB_LOCK(sc); 152741502Swpaul 152841502Swpaul /* 152941502Swpaul * Check for an available queue slot. If there are none, 153041502Swpaul * punt. 153141502Swpaul */ 153241502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 153341502Swpaul ifp->if_flags |= IFF_OACTIVE; 153467087Swpaul WB_UNLOCK(sc); 153541502Swpaul return; 153641502Swpaul } 153741502Swpaul 153841502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 153941502Swpaul 154041502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 154141502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 154241502Swpaul if (m_head == NULL) 154341502Swpaul break; 154441502Swpaul 154541502Swpaul /* Pick a descriptor off the free list. */ 154641502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 154741502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 154841502Swpaul 154941502Swpaul /* Pack the data into the descriptor. */ 155041502Swpaul wb_encap(sc, cur_tx, m_head); 155141502Swpaul 155241502Swpaul if (cur_tx != start_tx) 155341502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 155441502Swpaul 155541502Swpaul /* 155641502Swpaul * If there's a BPF listener, bounce a copy of this frame 155741502Swpaul * to him. 155841502Swpaul */ 1559106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 156041502Swpaul } 156141502Swpaul 156241502Swpaul /* 156341526Swpaul * If there are no packets queued, bail. 156441526Swpaul */ 156567087Swpaul if (cur_tx == NULL) { 156667087Swpaul WB_UNLOCK(sc); 156741526Swpaul return; 156867087Swpaul } 156941526Swpaul 157041526Swpaul /* 157141502Swpaul * Place the request for the upload interrupt 157241502Swpaul * in the last descriptor in the chain. This way, if 157341502Swpaul * we're chaining several packets at once, we'll only 157441502Swpaul * get an interupt once for the whole chain rather than 157541502Swpaul * once for each packet. 157641502Swpaul */ 157741502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 157842718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 157941502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 158041502Swpaul 158141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 158241502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 158341502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 158441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 158541502Swpaul } else { 158641502Swpaul /* 158741502Swpaul * We need to distinguish between the case where 158841502Swpaul * the own bit is clear because the chip cleared it 158941502Swpaul * and where the own bit is clear because we haven't 159041502Swpaul * set it yet. The magic value WB_UNSET is just some 159141502Swpaul * ramdomly chosen number which doesn't have the own 159241502Swpaul * bit set. When we actually transmit the frame, the 159341502Swpaul * status word will have _only_ the own bit set, so 159441502Swpaul * the txeoc handler will be able to tell if it needs 159541502Swpaul * to initiate another transmission to flush out pending 159641502Swpaul * frames. 159741502Swpaul */ 159841502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 159941502Swpaul } 160041502Swpaul 160141502Swpaul /* 160241502Swpaul * Set a timeout in case the chip goes out to lunch. 160341502Swpaul */ 160441502Swpaul ifp->if_timer = 5; 160567087Swpaul WB_UNLOCK(sc); 160641502Swpaul 160741502Swpaul return; 160841502Swpaul} 160941502Swpaul 1610102336Salfredstatic void 1611102336Salfredwb_init(xsc) 161241502Swpaul void *xsc; 161341502Swpaul{ 161441502Swpaul struct wb_softc *sc = xsc; 161541502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 161667087Swpaul int i; 161750675Swpaul struct mii_data *mii; 161841502Swpaul 161967087Swpaul WB_LOCK(sc); 162050675Swpaul mii = device_get_softc(sc->wb_miibus); 162141502Swpaul 162241502Swpaul /* 162341502Swpaul * Cancel pending I/O and free all RX/TX buffers. 162441502Swpaul */ 162541502Swpaul wb_stop(sc); 162641502Swpaul wb_reset(sc); 162741502Swpaul 162841502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 162941502Swpaul 163041502Swpaul /* 163141502Swpaul * Set cache alignment and burst length. 163241502Swpaul */ 163350675Swpaul#ifdef foo 163441502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 163541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 163641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 163750675Swpaul#endif 163841502Swpaul 163950675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 164050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 164150675Swpaul switch(sc->wb_cachesize) { 164250675Swpaul case 32: 164350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 164450675Swpaul break; 164550675Swpaul case 16: 164650675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 164750675Swpaul break; 164850675Swpaul case 8: 164950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 165050675Swpaul break; 165150675Swpaul case 0: 165250675Swpaul default: 165350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 165450675Swpaul break; 165550675Swpaul } 165650675Swpaul 165741502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 165841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 165941502Swpaul 166041502Swpaul /* Init our MAC address */ 166141502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 166241502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 166341502Swpaul } 166441502Swpaul 166541502Swpaul /* Init circular RX list. */ 166641502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 166741502Swpaul printf("wb%d: initialization failed: no " 166841502Swpaul "memory for rx buffers\n", sc->wb_unit); 166941502Swpaul wb_stop(sc); 167067087Swpaul WB_UNLOCK(sc); 167141502Swpaul return; 167241502Swpaul } 167341502Swpaul 167441502Swpaul /* Init TX descriptors. */ 167541502Swpaul wb_list_tx_init(sc); 167641502Swpaul 167741502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 167841502Swpaul if (ifp->if_flags & IFF_PROMISC) { 167941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 168041502Swpaul } else { 168141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 168241502Swpaul } 168341502Swpaul 168441502Swpaul /* 168541502Swpaul * Set capture broadcast bit to capture broadcast frames. 168641502Swpaul */ 168741502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 168841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 168941502Swpaul } else { 169041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 169141502Swpaul } 169241502Swpaul 169341502Swpaul /* 169441502Swpaul * Program the multicast filter, if necessary. 169541502Swpaul */ 169641502Swpaul wb_setmulti(sc); 169741502Swpaul 169841502Swpaul /* 169941502Swpaul * Load the address of the RX list. 170041502Swpaul */ 170141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 170241502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 170341502Swpaul 170441502Swpaul /* 170541502Swpaul * Enable interrupts. 170641502Swpaul */ 170741502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 170841502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 170941502Swpaul 171041502Swpaul /* Enable receiver and transmitter. */ 171141502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 171241502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 171341502Swpaul 171441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 171541502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 171641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 171741502Swpaul 171850675Swpaul mii_mediachg(mii); 171941502Swpaul 172041502Swpaul ifp->if_flags |= IFF_RUNNING; 172141502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 172241502Swpaul 172350675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 172467087Swpaul WB_UNLOCK(sc); 172550675Swpaul 172641502Swpaul return; 172741502Swpaul} 172841502Swpaul 172941502Swpaul/* 173041502Swpaul * Set media options. 173141502Swpaul */ 1732102336Salfredstatic int 1733102336Salfredwb_ifmedia_upd(ifp) 173441502Swpaul struct ifnet *ifp; 173541502Swpaul{ 173641502Swpaul struct wb_softc *sc; 173741502Swpaul 173841502Swpaul sc = ifp->if_softc; 173941502Swpaul 174050675Swpaul if (ifp->if_flags & IFF_UP) 174150675Swpaul wb_init(sc); 174241502Swpaul 174341502Swpaul return(0); 174441502Swpaul} 174541502Swpaul 174641502Swpaul/* 174741502Swpaul * Report current media status. 174841502Swpaul */ 1749102336Salfredstatic void 1750102336Salfredwb_ifmedia_sts(ifp, ifmr) 175141502Swpaul struct ifnet *ifp; 175241502Swpaul struct ifmediareq *ifmr; 175341502Swpaul{ 175441502Swpaul struct wb_softc *sc; 175550675Swpaul struct mii_data *mii; 175641502Swpaul 175741502Swpaul sc = ifp->if_softc; 175841502Swpaul 175950675Swpaul mii = device_get_softc(sc->wb_miibus); 176041502Swpaul 176150675Swpaul mii_pollstat(mii); 176250675Swpaul ifmr->ifm_active = mii->mii_media_active; 176350675Swpaul ifmr->ifm_status = mii->mii_media_status; 176441502Swpaul 176541502Swpaul return; 176641502Swpaul} 176741502Swpaul 1768102336Salfredstatic int 1769102336Salfredwb_ioctl(ifp, command, data) 177041502Swpaul struct ifnet *ifp; 177141502Swpaul u_long command; 177241502Swpaul caddr_t data; 177341502Swpaul{ 177441502Swpaul struct wb_softc *sc = ifp->if_softc; 177550675Swpaul struct mii_data *mii; 177641502Swpaul struct ifreq *ifr = (struct ifreq *) data; 177767087Swpaul int error = 0; 177841502Swpaul 177967087Swpaul WB_LOCK(sc); 178041502Swpaul 178141502Swpaul switch(command) { 178241502Swpaul case SIOCSIFFLAGS: 178341502Swpaul if (ifp->if_flags & IFF_UP) { 178441502Swpaul wb_init(sc); 178541502Swpaul } else { 178641502Swpaul if (ifp->if_flags & IFF_RUNNING) 178741502Swpaul wb_stop(sc); 178841502Swpaul } 178941502Swpaul error = 0; 179041502Swpaul break; 179141502Swpaul case SIOCADDMULTI: 179241502Swpaul case SIOCDELMULTI: 179341502Swpaul wb_setmulti(sc); 179441502Swpaul error = 0; 179541502Swpaul break; 179641502Swpaul case SIOCGIFMEDIA: 179741502Swpaul case SIOCSIFMEDIA: 179850675Swpaul mii = device_get_softc(sc->wb_miibus); 179950675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 180041502Swpaul break; 180141502Swpaul default: 1802106936Ssam error = ether_ioctl(ifp, command, data); 180341502Swpaul break; 180441502Swpaul } 180541502Swpaul 180667087Swpaul WB_UNLOCK(sc); 180741502Swpaul 180841502Swpaul return(error); 180941502Swpaul} 181041502Swpaul 1811102336Salfredstatic void 1812102336Salfredwb_watchdog(ifp) 181341502Swpaul struct ifnet *ifp; 181441502Swpaul{ 181541502Swpaul struct wb_softc *sc; 181641502Swpaul 181741502Swpaul sc = ifp->if_softc; 181841502Swpaul 181967087Swpaul WB_LOCK(sc); 182041502Swpaul ifp->if_oerrors++; 182141502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 182250675Swpaul#ifdef foo 182341502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 182441502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 182541502Swpaul sc->wb_unit); 182650675Swpaul#endif 182741502Swpaul wb_stop(sc); 182841502Swpaul wb_reset(sc); 182941502Swpaul wb_init(sc); 183041502Swpaul 183141502Swpaul if (ifp->if_snd.ifq_head != NULL) 183241502Swpaul wb_start(ifp); 183367087Swpaul WB_UNLOCK(sc); 183441502Swpaul 183541502Swpaul return; 183641502Swpaul} 183741502Swpaul 183841502Swpaul/* 183941502Swpaul * Stop the adapter and free any mbufs allocated to the 184041502Swpaul * RX and TX lists. 184141502Swpaul */ 1842102336Salfredstatic void 1843102336Salfredwb_stop(sc) 184441502Swpaul struct wb_softc *sc; 184541502Swpaul{ 184641502Swpaul register int i; 184741502Swpaul struct ifnet *ifp; 184841502Swpaul 184967087Swpaul WB_LOCK(sc); 185041502Swpaul ifp = &sc->arpcom.ac_if; 185141502Swpaul ifp->if_timer = 0; 185241502Swpaul 185350675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 185450675Swpaul 185541502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 185641502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 185741502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 185841502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 185941502Swpaul 186041502Swpaul /* 186141502Swpaul * Free data in the RX lists. 186241502Swpaul */ 186341502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 186441502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 186541502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 186641502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 186741502Swpaul } 186841502Swpaul } 186941502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 187041502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 187141502Swpaul 187241502Swpaul /* 187341502Swpaul * Free the TX list buffers. 187441502Swpaul */ 187541502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 187641502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 187741502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 187841502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 187941502Swpaul } 188041502Swpaul } 188141502Swpaul 188241502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 188341502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 188441502Swpaul 188541502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 188667087Swpaul WB_UNLOCK(sc); 188741502Swpaul 188841502Swpaul return; 188941502Swpaul} 189041502Swpaul 189141502Swpaul/* 189241502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 189341502Swpaul * get confused by errant DMAs when rebooting. 189441502Swpaul */ 1895102336Salfredstatic void 1896102336Salfredwb_shutdown(dev) 189749611Swpaul device_t dev; 189841502Swpaul{ 189949611Swpaul struct wb_softc *sc; 190041502Swpaul 190149611Swpaul sc = device_get_softc(dev); 190241502Swpaul wb_stop(sc); 190341502Swpaul 190441502Swpaul return; 190541502Swpaul} 1906