vxgehal-mgmt.h revision 285830
1224110Sjchandra/*- 2224110Sjchandra * Copyright(c) 2002-2011 Exar Corp. 3224110Sjchandra * All rights reserved. 4224110Sjchandra * 5224110Sjchandra * Redistribution and use in source and binary forms, with or without 6224110Sjchandra * modification are permitted provided the following conditions are met: 7224110Sjchandra * 8224110Sjchandra * 1. Redistributions of source code must retain the above copyright notice, 9224110Sjchandra * this list of conditions and the following disclaimer. 10224110Sjchandra * 11224110Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12224110Sjchandra * notice, this list of conditions and the following disclaimer in the 13224110Sjchandra * documentation and/or other materials provided with the distribution. 14224110Sjchandra * 15224110Sjchandra * 3. Neither the name of the Exar Corporation nor the names of its 16224110Sjchandra * contributors may be used to endorse or promote products derived from 17224110Sjchandra * this software without specific prior written permission. 18224110Sjchandra * 19224110Sjchandra * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20224110Sjchandra * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21224110Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22224110Sjchandra * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23224110Sjchandra * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24224110Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25224110Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26224110Sjchandra * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27224110Sjchandra * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28225394Sjchandra * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29224110Sjchandra * POSSIBILITY OF SUCH DAMAGE. 30225394Sjchandra */ 31224110Sjchandra/*$FreeBSD: releng/10.2/sys/dev/vxge/include/vxgehal-mgmt.h 221167 2011-04-28 14:33:15Z gnn $*/ 32225394Sjchandra 33225394Sjchandra#ifndef VXGE_HAL_MGMT_H 34224110Sjchandra#define VXGE_HAL_MGMT_H 35224110Sjchandra 36225394Sjchandra__EXTERN_BEGIN_DECLS 37224110Sjchandra 38225394Sjchandra/* 39225394Sjchandra * struct vxge_hal_mgmt_about_info_t - About info. 40225394Sjchandra * @vendor: PCI Vendor ID. 41225394Sjchandra * @device: PCI Device ID. 42225394Sjchandra * @subsys_vendor: PCI Subsystem Vendor ID. 43225394Sjchandra * @subsys_device: PCI Subsystem Device ID. 44225394Sjchandra * @board_rev: PCI Board revision, e.g. 3 - for Xena 3. 45225394Sjchandra * @vendor_name: Exar Corp. 46225394Sjchandra * @chip_name: X3100. 47225394Sjchandra * @media: Fiber, copper. 48224110Sjchandra * @hal_major: HAL major version number. 49225394Sjchandra * @hal_minor: HAL minor version number. 50225394Sjchandra * @hal_fix: HAL fix number. 51225394Sjchandra * @hal_build: HAL build number. 52225394Sjchandra * @ll_major: Link-layer ULD major version number. 53225394Sjchandra * @ll_minor: Link-layer ULD minor version number. 54225394Sjchandra * @ll_fix: Link-layer ULD fix version number. 55224110Sjchandra * @ll_build: Link-layer ULD build number. 56225394Sjchandra */ 57225394Sjchandratypedef struct vxge_hal_mgmt_about_info_t { 58225394Sjchandra u16 vendor; 59225394Sjchandra u16 device; 60225394Sjchandra u16 subsys_vendor; 61224110Sjchandra u16 subsys_device; 62225394Sjchandra u8 board_rev; 63225394Sjchandra char vendor_name[16]; 64225394Sjchandra char chip_name[16]; 65225394Sjchandra char media[16]; 66225394Sjchandra char hal_major[4]; 67225394Sjchandra char hal_minor[4]; 68225394Sjchandra char hal_fix[4]; 69225394Sjchandra char hal_build[16]; 70224110Sjchandra char ll_major[4]; 71225394Sjchandra char ll_minor[4]; 72225394Sjchandra char ll_fix[4]; 73225394Sjchandra char ll_build[16]; 74225394Sjchandra} vxge_hal_mgmt_about_info_t; 75225394Sjchandra 76225394Sjchandra 77225394Sjchandra/* 78225394Sjchandra * vxge_hal_mgmt_about - Retrieve about info. 79225394Sjchandra * @devh: HAL device handle. 80225394Sjchandra * @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}. 81225394Sjchandra * @size: Pointer to buffer containing the Size of the @buffer_info. 82224110Sjchandra * HAL will return an error if the size is smaller than 83225394Sjchandra * sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field 84225394Sjchandra * 85225394Sjchandra * Retrieve information such as PCI device and vendor IDs, board 86225394Sjchandra * revision number, HAL version number, etc. 87225394Sjchandra * 88225394Sjchandra * Returns: VXGE_HAL_OK - success; 89225394Sjchandra * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 90224110Sjchandra * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 91225394Sjchandra * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 92225394Sjchandra * VXGE_HAL_FAIL - Failed to retrieve the information. 93225394Sjchandra * 94225394Sjchandra * See also: vxge_hal_mgmt_about_info_t {}. 95225394Sjchandra */ 96225394Sjchandravxge_hal_status_e 97225394Sjchandravxge_hal_mgmt_about(vxge_hal_device_h devh, 98224110Sjchandra vxge_hal_mgmt_about_info_t *about_info, 99225394Sjchandra u32 *size); 100225394Sjchandra 101225394Sjchandra/* 102225394Sjchandra * vxge_hal_mgmt_pci_config - Retrieve PCI configuration. 103225394Sjchandra * @devh: HAL device handle. 104225394Sjchandra * @buffer: Buffer for PCI configuration space. 105225394Sjchandra * @size: Pointer to buffer containing the Size of the @buffer. 106224110Sjchandra * HAL will return an error if the size is smaller than 107225394Sjchandra * sizeof(vxge_hal_pci_config_t) and returns required size in this field 108225394Sjchandra * 109225394Sjchandra * Get PCI configuration. Permits to retrieve at run-time configuration 110225394Sjchandra * values that were used to configure the device at load-time. 111225394Sjchandra * 112225394Sjchandra * Returns: VXGE_HAL_OK - success. 113225394Sjchandra * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 114225394Sjchandra * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 115225394Sjchandra * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 116224110Sjchandra * 117225394Sjchandra */ 118225394Sjchandravxge_hal_status_e 119225394Sjchandravxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size); 120225394Sjchandra 121225394Sjchandra/* 122225394Sjchandra * struct vxge_hal_mgmt_pm_cap_t - Power Management Capabilities 123225394Sjchandra * @pm_cap_ver: Version 124225394Sjchandra * @pm_cap_pme_clock: PME clock required 125225394Sjchandra * @pm_cap_aux_power: Auxilliary power support 126224110Sjchandra * @pm_cap_dsi: Device specific initialization 127225394Sjchandra * @pm_cap_aux_current: auxiliary current requirements 128225394Sjchandra * @pm_cap_cap_d0: D1 power state support 129225394Sjchandra * @pm_cap_cap_d1: D2 power state support 130225394Sjchandra * @pm_cap_pme_d0: PME# can be asserted from D3hot 131225394Sjchandra * @pm_cap_pme_d1: PME# can be asserted from D3hot 132225394Sjchandra * @pm_cap_pme_d2: PME# can be asserted from D3hot 133225394Sjchandra * @pm_cap_pme_d3_hot: PME# can be asserted from D3hot 134225394Sjchandra * @pm_cap_pme_d3_cold: PME# can be asserted from D3cold 135225394Sjchandra * @pm_ctrl_state: Current power state (D0 to D3) 136225394Sjchandra * @pm_ctrl_no_soft_reset: Devices transitioning from D3hot to D0 137225394Sjchandra * @pm_ctrl_pme_enable: PME pin enable 138225394Sjchandra * @pm_ctrl_pme_data_sel: Data select 139225394Sjchandra * @pm_ctrl_pme_data_scale: Data scale 140225394Sjchandra * @pm_ctrl_pme_status: PME pin status 141225394Sjchandra * @pm_ppb_ext_b2_b3: Stop clock when in D3hot 142225394Sjchandra * @pm_ppb_ext_ecc_en: Bus power/clock control enable 143225394Sjchandra * @pm_data_reg: state dependent data requested by pm_ctrl_pme_data_sel 144225394Sjchandra * 145225394Sjchandra * Power Management Capabilities structure 146225394Sjchandra */ 147225394Sjchandratypedef struct vxge_hal_mgmt_pm_cap_t { 148225394Sjchandra u32 pm_cap_ver; 149225394Sjchandra u32 pm_cap_pme_clock; 150225394Sjchandra u32 pm_cap_aux_power; 151225394Sjchandra u32 pm_cap_dsi; 152225394Sjchandra u32 pm_cap_aux_current; 153225394Sjchandra u32 pm_cap_cap_d0; 154225394Sjchandra u32 pm_cap_cap_d1; 155225394Sjchandra u32 pm_cap_pme_d0; 156225394Sjchandra u32 pm_cap_pme_d1; 157225394Sjchandra u32 pm_cap_pme_d2; 158225394Sjchandra u32 pm_cap_pme_d3_hot; 159225394Sjchandra u32 pm_cap_pme_d3_cold; 160225394Sjchandra u32 pm_ctrl_state; 161225394Sjchandra u32 pm_ctrl_no_soft_reset; 162225394Sjchandra u32 pm_ctrl_pme_enable; 163225394Sjchandra u32 pm_ctrl_pme_data_sel; 164225394Sjchandra u32 pm_ctrl_pme_data_scale; 165225394Sjchandra u32 pm_ctrl_pme_status; 166225394Sjchandra u32 pm_ppb_ext_b2_b3; 167225394Sjchandra u32 pm_ppb_ext_ecc_en; 168225394Sjchandra u32 pm_data_reg; 169225394Sjchandra} vxge_hal_mgmt_pm_cap_t; 170225394Sjchandra 171225394Sjchandra/* 172225394Sjchandra * vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities 173225394Sjchandra * @devh: HAL device handle. 174225394Sjchandra * @pm_cap: Power Management Capabilities 175225394Sjchandra * 176225394Sjchandra * Return the pm capabilities 177224110Sjchandra */ 178225394Sjchandravxge_hal_status_e 179225394Sjchandravxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh, 180225394Sjchandra vxge_hal_mgmt_pm_cap_t *pm_cap); 181225394Sjchandra 182225394Sjchandra/* 183225394Sjchandra * struct vxge_hal_mgmt_sid_cap_t - Slot ID Capabilities 184224110Sjchandra * @sid_number_of_slots: Number of solts 185225394Sjchandra * @sid_first_in_chasis: First in chasis flag 186225394Sjchandra * @sid_chasis_number: Chasis Number 187225394Sjchandra * 188225394Sjchandra * Slot ID Capabilities structure 189225394Sjchandra */ 190225394Sjchandratypedef struct vxge_hal_mgmt_sid_cap_t { 191224110Sjchandra u32 sid_number_of_slots; 192225394Sjchandra u32 sid_first_in_chasis; 193224110Sjchandra u32 sid_chasis_number; 194225394Sjchandra} vxge_hal_mgmt_sid_cap_t; 195225394Sjchandra 196225394Sjchandra/* 197225394Sjchandra * vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities 198225394Sjchandra * @devh: HAL device handle. 199225394Sjchandra * @sid_cap: Slot Id Capabilities 200225394Sjchandra * 201225394Sjchandra * Return the pm capabilities 202225394Sjchandra */ 203224110Sjchandravxge_hal_status_e 204225394Sjchandravxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh, 205225394Sjchandra vxge_hal_mgmt_sid_cap_t *sid_cap); 206225394Sjchandra 207225394Sjchandra/* 208225394Sjchandra * struct vxge_hal_mgmt_msi_cap_t - MSI Capabilities 209225394Sjchandra * @enable: 1 - MSI enabled, 0 - MSI not enabled 210225394Sjchandra * @is_pvm_capable: 1 - PVM capable, 0 - Not PVM Capable (valid for get only) 211224110Sjchandra * @is_64bit_addr_capable: 1 - 64 bit address capable, 0 - 32 bit address only 212225394Sjchandra * (valid for get only) 213225394Sjchandra * @vectors_allocated: Number of vectors allocated 214225394Sjchandra * 000-1 vectors 215225394Sjchandra * 001-2 vectors 216225394Sjchandra * 010-4 vectors 217225394Sjchandra * 011-8 vectors 218225394Sjchandra * 100-16 vectors 219225394Sjchandra * 101-32 vectors 220225394Sjchandra * @max_vectors_capable: Maximum number of vectors that can be allocated 221225394Sjchandra * (valid for get only) 222225394Sjchandra * 000-1 vectors 223225394Sjchandra * 001-2 vectors 224225394Sjchandra * 010-4 vectors 225225394Sjchandra * 011-8 vectors 226225394Sjchandra * 100-16 vectors 227225394Sjchandra * 101-32 vectors 228225394Sjchandra * @address: MSI address 229225394Sjchandra * @data: MSI Data 230224110Sjchandra * @mask_bits: For each Mask bit that is set, the function is prohibited from 231225394Sjchandra * sending the associated message 232225394Sjchandra * @pending_bits: For each Pending bit that is set, the function has a 233225394Sjchandra * pending associated message. 234224110Sjchandra * 235225394Sjchandra * MSI Capabilities structure 236225394Sjchandra */ 237225394Sjchandratypedef struct vxge_hal_mgmt_msi_cap_t { 238225394Sjchandra u32 enable; 239225394Sjchandra u32 is_pvm_capable; 240224110Sjchandra u32 is_64bit_addr_capable; 241225394Sjchandra u32 vectors_allocated; 242225394Sjchandra u32 max_vectors_capable; 243224110Sjchandra#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_1 0 244225394Sjchandra#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_2 1 245224110Sjchandra#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_4 2 246225394Sjchandra#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_8 3 247225394Sjchandra#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_16 4 248225394Sjchandra#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_32 5 249224110Sjchandra u64 address; 250225394Sjchandra u16 data; 251225394Sjchandra u32 mask_bits; 252225394Sjchandra u32 pending_bits; 253225394Sjchandra} vxge_hal_mgmt_msi_cap_t; 254225394Sjchandra 255225394Sjchandra/* 256224110Sjchandra * vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities 257225394Sjchandra * @devh: HAL device handle. 258225394Sjchandra * @msi_cap: MSI Capabilities 259225394Sjchandra * 260225394Sjchandra * Return the msi capabilities 261224110Sjchandra */ 262224110Sjchandravxge_hal_status_e 263225394Sjchandravxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh, 264225394Sjchandra vxge_hal_mgmt_msi_cap_t *msi_cap); 265224110Sjchandra 266225394Sjchandra/* 267224110Sjchandra * vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities 268224110Sjchandra * @devh: HAL device handle. 269225394Sjchandra * @msi_cap: MSI Capabilities 270225394Sjchandra * 271224110Sjchandra * Sets the msi capabilities 272225394Sjchandra */ 273225394Sjchandravxge_hal_status_e 274224110Sjchandravxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh, 275225394Sjchandra vxge_hal_mgmt_msi_cap_t *msi_cap); 276225394Sjchandra 277225394Sjchandra/* 278225394Sjchandra * struct vxge_hal_mgmt_msix_cap_t - MSIX Capabilities 279225394Sjchandra * @enable: 1 - MSIX enabled, 0 - MSIX not enabled 280225394Sjchandra * @mask_all_vect: 1 - Mask all vectors, 0 - Do not mask all vectors 281224110Sjchandra * @table_size: MSIX Table Size-1 282225394Sjchandra * @table_offset: Offset of the table from the table_bir 283224110Sjchandra * @table_bir: Table Bar address register number 0-BAR0, 2-BAR1, 4-BAR2 284224110Sjchandra * @pba_offset: Offset of the PBA from the pba_bir 285225394Sjchandra * @pba_bir: PBA Bar address register number 0-BAR0, 2-BAR1, 4-BAR2 286225394Sjchandra * 287224110Sjchandra * MSIS Capabilities structure 288225394Sjchandra */ 289224110Sjchandratypedef struct vxge_hal_mgmt_msix_cap_t { 290224110Sjchandra u32 enable; 291225394Sjchandra u32 mask_all_vect; 292225394Sjchandra u32 table_size; 293224110Sjchandra u32 table_offset; 294225394Sjchandra u32 table_bir; 295224110Sjchandra#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR0 0 296224110Sjchandra#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR1 2 297225394Sjchandra#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR2 4 298225394Sjchandra u32 pba_offset; 299224110Sjchandra u32 pba_bir; 300225394Sjchandra#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR0 0 301224110Sjchandra#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR1 2 302225394Sjchandra#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR2 4 303225394Sjchandra} vxge_hal_mgmt_msix_cap_t; 304224110Sjchandra 305224110Sjchandra/* 306225394Sjchandra * vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities 307225394Sjchandra * @devh: HAL device handle. 308224110Sjchandra * @msix_cap: MSIX Capabilities 309225394Sjchandra * 310224110Sjchandra * Return the msix capabilities 311225394Sjchandra */ 312225394Sjchandravxge_hal_status_e 313225394Sjchandravxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh, 314224110Sjchandra vxge_hal_mgmt_msix_cap_t *msix_cap); 315224110Sjchandra 316225394Sjchandra/* 317225394Sjchandra * struct vxge_hal_pci_err_cap_t - PCI Error Capabilities 318224110Sjchandra * @pci_err_header: Error header 319225394Sjchandra * @pci_err_uncor_status: Uncorrectable error status 320224110Sjchandra * 0x00000001 - Training 321225394Sjchandra * 0x00000010 - Data Link Protocol 322225394Sjchandra * 0x00001000 - Poisoned TLP 323225394Sjchandra * 0x00002000 - Flow Control Protocol 324225394Sjchandra * 0x00004000 - Completion Timeout 325225394Sjchandra * 0x00008000 - Completer Abort 326224110Sjchandra * 0x00010000 - Unexpected Completion 327224110Sjchandra * 0x00020000 - Receiver Overflow 328225394Sjchandra * 0x00040000 - Malformed TLP 329225394Sjchandra * 0x00080000 - ECRC Error Status 330225394Sjchandra * 0x00100000 - Unsupported Request 331224110Sjchandra * @pci_err_uncor_mask: Uncorrectable mask 332225394Sjchandra * @pci_err_uncor_server: Uncorrectable server 333224110Sjchandra * @pci_err_cor_status: Correctable status 334225394Sjchandra * 0x00000001 - Receiver Error Status 335225394Sjchandra * 0x00000040 - Bad TLP Status 336225394Sjchandra * 0x00000080 - Bad DLLP Status 337225394Sjchandra * 0x00000100 - REPLAY_NUM Rollover 338224110Sjchandra * 0x00001000 - Replay Timer Timeout 339225394Sjchandra * VXGE_HAL_PCI_ERR_COR_MASK 20 340224110Sjchandra * @pci_err_cap: Error capability 341224110Sjchandra * 0x00000020 - ECRC Generation Capable 342225394Sjchandra * 0x00000040 - ECRC Generation Enable 343225394Sjchandra * 0x00000080 - ECRC Check Capable 344225394Sjchandra * 0x00000100 - ECRC Check Enable 345224110Sjchandra * @err_header_log: Error header log 346225394Sjchandra * @unused: Reserved 347225394Sjchandra * @pci_err_root_command: Error root command 348225394Sjchandra * @pci_err_root_status: Error root status 349224110Sjchandra * @pci_err_root_cor_src: Error root correctible source 350224110Sjchandra * @pci_err_root_src: Error root source 351225394Sjchandra * 352225394Sjchandra * MSIS Capabilities structure 353225394Sjchandra */ 354225394Sjchandratypedef struct vxge_hal_pci_err_cap_t { 355225394Sjchandra u32 pci_err_header; 356224110Sjchandra u32 pci_err_uncor_status; 357225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_TRAIN 0x00000001 /* Training */ 358225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_DLP 0x00000010 /* Data Link Protocol */ 359224110Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 360225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_FCP 0x00002000 /* Flow Ctrl Protocol */ 361224110Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 362224110Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 363225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_UNX_COMP 0x00010000 /* Unexpected Compl */ 364225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 365224110Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 366225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_ECRC 0x00080000 /* ECRC Error Status */ 367225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_UNC_UNSUP 0x00100000 /* Unsupported Request */ 368224110Sjchandra u32 pci_err_uncor_mask; 369225394Sjchandra u32 pci_err_uncor_server; 370225394Sjchandra u32 pci_err_cor_status; 371225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_COR_RCVR 0x00000001 /* Recv Err Status */ 372225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 373225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 374225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_COR_REP_ROLL 0x00000100 /* REPLAY Rollover */ 375225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_COR_REP_TIMER 0x00001000 /* Replay Timeout */ 376225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_COR_MASK 20 /* Corrble Err Mask */ 377224110Sjchandra u32 pci_err_cap; 378224110Sjchandra#define VXGE_HAL_PCI_ERR_CAP_CAP_FEP(x) ((x) & 31) /* First Err Ptr */ 379225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENC 0x00000020 /* ECRC Gen Capable */ 380225394Sjchandra#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENE 0x00000040 /* ECRC Gen Enable */ 381#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKC 0x00000080 /* ECRC Chk Capable */ 382#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKE 0x00000100 /* ECRC Chk Enable */ 383 u32 err_header_log; 384#define VXGE_HAL_PCI_ERR_CAP_HEADER_LOG(x) ((x) >> 31) /* Error Hdr Log */ 385 u32 unused[3]; 386 u32 pci_err_root_command; 387 u32 pci_err_root_status; 388 u32 pci_err_root_cor_src; 389 u32 pci_err_root_src; 390} vxge_hal_pci_err_cap_t; 391 392/* 393 * vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities 394 * @devh: HAL device handle. 395 * @err_cap: PCI-E Extended Error Capabilities 396 * 397 * Return the PCI-E Extended Error capabilities 398 */ 399vxge_hal_status_e 400vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh, 401 vxge_hal_pci_err_cap_t *err_cap); 402 403/* 404 * vxge_hal_mgmt_driver_config - Retrieve driver configuration. 405 * @drv_config: Device configuration, see vxge_hal_driver_config_t {}. 406 * @size: Pointer to buffer containing the Size of the @drv_config. 407 * HAL will return an error if the size is smaller than 408 * sizeof(vxge_hal_driver_config_t) and returns required size in this field 409 * 410 * Get driver configuration. Permits to retrieve at run-time configuration 411 * values that were used to configure the device at load-time. 412 * 413 * Returns: VXGE_HAL_OK - success. 414 * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized. 415 * VXGE_HAL_ERR_VERSION_CONFLICT - Version is not maching. 416 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 417 * 418 * See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config(). 419 */ 420vxge_hal_status_e 421vxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size); 422 423#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 424 425/* 426 * vxge_hal_mgmt_trace_read - Read trace buffer contents. 427 * @buffer: Buffer to store the trace buffer contents. 428 * @buf_size: Size of the buffer. 429 * @offset: Offset in the internal trace buffer to read data. 430 * @read_length: Size of the valid data in the buffer. 431 * 432 * Read HAL trace buffer contents starting from the offset 433 * upto the size of the buffer or till EOF is reached. 434 * 435 * Returns: VXGE_HAL_OK - success. 436 * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer. 437 * 438 */ 439vxge_hal_status_e 440vxge_hal_mgmt_trace_read(char *buffer, 441 unsigned buf_size, 442 unsigned *offset, 443 unsigned *read_length); 444 445#endif 446 447/* 448 * vxge_hal_mgmt_device_config - Retrieve device configuration. 449 * @devh: HAL device handle. 450 * @dev_config: Device configuration, see vxge_hal_device_config_t {}. 451 * @size: Pointer to buffer containing the Size of the @dev_config. 452 * HAL will return an error if the size is smaller than 453 * sizeof(vxge_hal_device_config_t) and returns required size in this field 454 * 455 * Get device configuration. Permits to retrieve at run-time configuration 456 * values that were used to initialize and configure the device. 457 * 458 * Returns: VXGE_HAL_OK - success. 459 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 460 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 461 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 462 * 463 * See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config(). 464 */ 465vxge_hal_status_e 466vxge_hal_mgmt_device_config(vxge_hal_device_h devh, 467 vxge_hal_device_config_t *dev_config, u32 *size); 468 469 470/* 471 * vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified 472 * offset. 473 * @devh: HAL device handle. 474 * @offset: Offset in the 256 byte PCI configuration space. 475 * @value_bits: 8, 16, or 32 (bits) to read. 476 * @value: Value returned by HAL. 477 * 478 * Read PCI configuration, given device and offset in the PCI space. 479 * 480 * Returns: VXGE_HAL_OK - success. 481 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 482 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not 483 * valid. 484 * VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid 485 * values(8/16/32). 486 * 487 */ 488vxge_hal_status_e 489vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset, 490 int value_bits, u32 *value); 491 492/* 493 * enum vxge_hal_mgmt_reg_type_e - Register types. 494 * 495 * @vxge_hal_mgmt_reg_type_legacy: Legacy registers 496 * @vxge_hal_mgmt_reg_type_toc: TOC Registers 497 * @vxge_hal_mgmt_reg_type_common: Common Registers 498 * @vxge_hal_mgmt_reg_type_memrepair: Memrepair Registers 499 * @vxge_hal_mgmt_reg_type_pcicfgmgmt: pci cfg management registers 500 * @vxge_hal_mgmt_reg_type_mrpcim: mrpcim registers 501 * @vxge_hal_mgmt_reg_type_srpcim: srpcim registers 502 * @vxge_hal_mgmt_reg_type_vpmgmt: vpath management registers 503 * @vxge_hal_mgmt_reg_type_vpath: vpath registers 504 * 505 * Register type enumaration 506 */ 507typedef enum vxge_hal_mgmt_reg_type_e { 508 vxge_hal_mgmt_reg_type_legacy = 0, 509 vxge_hal_mgmt_reg_type_toc = 1, 510 vxge_hal_mgmt_reg_type_common = 2, 511 vxge_hal_mgmt_reg_type_memrepair = 3, 512 vxge_hal_mgmt_reg_type_pcicfgmgmt = 4, 513 vxge_hal_mgmt_reg_type_mrpcim = 5, 514 vxge_hal_mgmt_reg_type_srpcim = 6, 515 vxge_hal_mgmt_reg_type_vpmgmt = 7, 516 vxge_hal_mgmt_reg_type_vpath = 8 517} vxge_hal_mgmt_reg_type_e; 518 519/* 520 * vxge_hal_mgmt_reg_read - Read X3100 register. 521 * @devh: HAL device handle. 522 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 523 * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 524 * ignored for others 525 * @offset: Register offset in the register space qualified by the type and 526 * index. 527 * @value: Register value. Returned by HAL. 528 * Read X3100 register. 529 * 530 * Returns: VXGE_HAL_OK - success. 531 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 532 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 533 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 534 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 535 * 536 */ 537vxge_hal_status_e 538vxge_hal_mgmt_reg_read(vxge_hal_device_h devh, 539 vxge_hal_mgmt_reg_type_e type, 540 u32 index, 541 u32 offset, 542 u64 *value); 543 544/* 545 * vxge_hal_mgmt_reg_Write - Write X3100 register. 546 * @devh: HAL device handle. 547 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 548 * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 549 * ignored for others 550 * @offset: Register offset in the register space qualified by the type and 551 * index. 552 * @value: Register value to be written. 553 * Write X3100 register. 554 * 555 * Returns: VXGE_HAL_OK - success. 556 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 557 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 558 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 559 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 560 * 561 */ 562vxge_hal_status_e 563vxge_hal_mgmt_reg_write(vxge_hal_device_h devh, 564 vxge_hal_mgmt_reg_type_e type, 565 u32 index, 566 u32 offset, 567 u64 value); 568 569/* 570 * vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset 571 * from bar0. 572 * @devh: HAL device handle. 573 * @offset: Register offset from bar0 574 * @value: Register value. Returned by HAL. 575 * Read X3100 register. 576 * 577 * Returns: VXGE_HAL_OK - success. 578 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 579 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 580 * 581 */ 582vxge_hal_status_e 583vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh, 584 u32 offset, 585 u64 *value); 586 587/* 588 * vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset 589 * from bar1. 590 * @devh: HAL device handle. 591 * @offset: Register offset from bar1 592 * @value: Register value. Returned by HAL. 593 * Read X3100 register. 594 * 595 * Returns: VXGE_HAL_OK - success. 596 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 597 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 598 * 599 */ 600vxge_hal_status_e 601vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh, 602 u32 offset, 603 u64 *value); 604 605/* 606 * vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset 607 * from bar0. 608 * @devh: HAL device handle. 609 * @offset: Register offset from bar0 610 * @value: Register value to be written. 611 * Write X3100 register. 612 * 613 * Returns: VXGE_HAL_OK - success. 614 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 615 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 616 * 617 */ 618vxge_hal_status_e 619vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh, 620 u32 offset, 621 u64 value); 622 623/* 624 * vxge_hal_mgmt_register_config - Retrieve register configuration. 625 * @devh: HAL device handle. 626 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 627 * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 628 * ignored for others 629 * @config: Device configuration, see vxge_hal_device_config_t {}. 630 * @size: Pointer to buffer containing the Size of the @reg_config. 631 * HAL will return an error if the size is smaller than 632 * requested register space and returns required size in this field 633 * 634 * Get register configuration. Permits to retrieve register values. 635 * 636 * Returns: VXGE_HAL_OK - success. 637 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 638 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 639 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 640 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 641 * 642 */ 643vxge_hal_status_e 644vxge_hal_mgmt_register_config(vxge_hal_device_h devh, 645 vxge_hal_mgmt_reg_type_e type, 646 u32 vp_id, 647 u8 *config, 648 u32 *size); 649 650/* 651 * vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port 652 * @devh: HAL device handle. 653 * @port: Port number 654 * 655 * This routine only gets the temperature for XFP modules. Also, updating of the 656 * NVRAM can sometimes fail and so the reading we might get may not be uptodate. 657 */ 658u32 vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port); 659 660/* 661 * vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback 662 * @devh: HAL device handle. 663 * @port: Port number 664 * @enable:Boolean set to 1 to enable and 0 to disable. 665 * 666 * Enable or disable PMA loopback. 667 * Return value: 668 * 0 on success. 669 */ 670vxge_hal_status_e 671vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable); 672 673/* 674 * vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback 675 * @devh: HAL device handle. 676 * @port: Port number 677 * @enable:Boolean set to 1 to enable and 0 to disable. 678 * 679 * Enable or disable xgmii loopback. 680 * Return value: 681 * 0 on success. 682 */ 683vxge_hal_status_e 684vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable); 685 686__EXTERN_END_DECLS 687 688#endif /* VXGE_HAL_MGMT_H */ 689