1222578Shselasky/* $FreeBSD: releng/10.2/sys/dev/usb/serial/umcs.h 252123 2013-06-23 20:19:51Z thomas $ */ 2222578Shselasky/*- 3222578Shselasky * Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>. 4222578Shselasky * All rights reserved. 5222578Shselasky * 6222578Shselasky * Redistribution and use in source and binary forms, with or without 7222578Shselasky * modification, are permitted provided that the following conditions 8222578Shselasky * are met: 9222578Shselasky * 1. Redistributions of source code must retain the above copyright 10222578Shselasky * notice, this list of conditions and the following disclaimer. 11222578Shselasky * 2. Redistributions in binary form must reproduce the above copyright 12222578Shselasky * notice, this list of conditions and the following disclaimer in the 13222578Shselasky * documentation and/or other materials provided with the distribution. 14222578Shselasky * 15222578Shselasky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16222578Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17222578Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18222578Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19222578Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20222578Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21222578Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22222578Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23222578Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24222578Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25222578Shselasky * SUCH DAMAGE. 26222578Shselasky */ 27222578Shselasky#ifndef _UMCS7840_H_ 28222578Shselasky#define _UMCS7840_H_ 29222578Shselasky 30222578Shselasky#define UMCS7840_MAX_PORTS 4 31222578Shselasky 32222578Shselasky#define UMCS7840_READ_LENGTH 1 /* bytes */ 33222578Shselasky#define UMCS7840_CTRL_TIMEOUT 500 /* ms */ 34222578Shselasky 35222578Shselasky/* Read/Wrtire registers vendor commands */ 36222578Shselasky#define MCS7840_RDREQ 0x0d 37222578Shselasky#define MCS7840_WRREQ 0x0e 38222578Shselasky 39222578Shselasky/* Read/Wrtie EEPROM values */ 40222578Shselasky#define MCS7840_EEPROM_RW_WVALUE 0x0900 41222578Shselasky 42222578Shselasky/* 43222578Shselasky * All these registers are documented only in full datasheet, 44222578Shselasky * which can be requested from MosChip tech support. 45222578Shselasky */ 46222578Shselasky#define MCS7840_DEV_REG_SP1 0x00 /* Options for for UART 1, R/W */ 47222578Shselasky#define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1, 48222578Shselasky * R/W */ 49222578Shselasky#define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong 50222578Shselasky * register, R/W */ 51222578Shselasky#define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong 52222578Shselasky * register, R/W */ 53222578Shselasky/* DCRx_1 Registers goes here (see below, they are documented) */ 54222578Shselasky#define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits, 55222578Shselasky * undocumented, see notes 56222578Shselasky * below R/W */ 57222578Shselasky#define MCS7840_DEV_REG_SP2 0x08 /* Options for for UART 2, R/W */ 58222578Shselasky#define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2, 59222578Shselasky * R/W */ 60222578Shselasky#define MCS7840_DEV_REG_SP3 0x0a /* Options for for UART 3, R/W */ 61222578Shselasky#define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3, 62222578Shselasky * R/W */ 63222578Shselasky#define MCS7840_DEV_REG_SP4 0x0c /* Options for for UART 4, R/W */ 64222578Shselasky#define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4, 65222578Shselasky * R/W */ 66222578Shselasky#define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */ 67222578Shselasky#define MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */ 68222578Shselasky#define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */ 69222578Shselasky#define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt 70222578Shselasky * endpoint control, R/W */ 71222578Shselasky#define MCS7840_DEV_REG_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */ 72222578Shselasky#define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 & 73222578Shselasky * 2, R/W */ 74222578Shselasky#define MCS7840_DEV_REG_CLOCK_SELECT34 0x14 /* Clock source for ports 3 & 75222578Shselasky * 4, R/W */ 76222578Shselasky#define MCS7840_DEV_REG_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */ 77222578Shselasky/* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */ 78222578Shselasky#define MCS7840_DEV_REG_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */ 79222578Shselasky#define MCS7840_DEV_REG_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */ 80222578Shselasky#define MCS7840_DEV_REG_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */ 81222578Shselasky#define MCS7840_DEV_REG_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */ 82222578Shselasky#define MCS7840_DEV_REG_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */ 83222578Shselasky#define MCS7840_DEV_REG_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */ 84222578Shselasky#define MCS7840_DEV_REG_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */ 85222578Shselasky#define MCS7840_DEV_REG_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */ 86222578Shselasky#define MCS7840_DEV_REG_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */ 87222578Shselasky#define MCS7840_DEV_REG_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */ 88222578Shselasky#define MCS7840_DEV_REG_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */ 89222578Shselasky#define MCS7840_DEV_REG_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */ 90222578Shselasky#define MCS7840_DEV_REG_MODE 0x2b /* Hardware configuration, 91222578Shselasky * R/Only */ 92222578Shselasky#define MCS7840_DEV_REG_SP1_ICG 0x2c /* Inter character gap 93222578Shselasky * configuration for Port 1, 94222578Shselasky * R/W */ 95222578Shselasky#define MCS7840_DEV_REG_SP2_ICG 0x2d /* Inter character gap 96222578Shselasky * configuration for Port 2, 97222578Shselasky * R/W */ 98222578Shselasky#define MCS7840_DEV_REG_SP3_ICG 0x2e /* Inter character gap 99222578Shselasky * configuration for Port 3, 100222578Shselasky * R/W */ 101222578Shselasky#define MCS7840_DEV_REG_SP4_ICG 0x2f /* Inter character gap 102222578Shselasky * configuration for Port 4, 103222578Shselasky * R/W */ 104222578Shselasky#define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 & 105222578Shselasky * 2, R/W */ 106222578Shselasky#define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 & 107222578Shselasky * 4, R/W */ 108222578Shselasky#define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port 109222578Shselasky * 1, contains number of 110222578Shselasky * availiable bytes, R/Only */ 111222578Shselasky#define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port 112222578Shselasky * 1, contains number of 113222578Shselasky * availiable bytes, R/Only */ 114222578Shselasky#define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port 115222578Shselasky * 2, contains number of 116222578Shselasky * availiable bytes, R/Only */ 117222578Shselasky#define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port 118222578Shselasky * 2, contains number of 119222578Shselasky * availiable bytes, R/Only */ 120222578Shselasky#define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port 121222578Shselasky * 3, contains number of 122222578Shselasky * availiable bytes, R/Only */ 123222578Shselasky#define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port 124222578Shselasky * 3, contains number of 125222578Shselasky * availiable bytes, R/Only */ 126222578Shselasky#define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port 127222578Shselasky * 4, contains number of 128222578Shselasky * availiable bytes, R/Only */ 129222578Shselasky#define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port 130222578Shselasky * 4, contains number of 131222578Shselasky * availiable bytes, R/Only */ 132222578Shselasky#define MCS7840_DEV_REG_ZERO_PERIOD1 0x3a /* Period between zero out 133222578Shselasky * frames for Port 1, R/W */ 134222578Shselasky#define MCS7840_DEV_REG_ZERO_PERIOD2 0x3b /* Period between zero out 135222578Shselasky * frames for Port 1, R/W */ 136222578Shselasky#define MCS7840_DEV_REG_ZERO_PERIOD3 0x3c /* Period between zero out 137222578Shselasky * frames for Port 1, R/W */ 138222578Shselasky#define MCS7840_DEV_REG_ZERO_PERIOD4 0x3d /* Period between zero out 139222578Shselasky * frames for Port 1, R/W */ 140222578Shselasky#define MCS7840_DEV_REG_ZERO_ENABLE 0x3e /* Enable/disable of zero out 141222578Shselasky * frames, R/W */ 142222578Shselasky#define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshhold 143222578Shselasky * value for Bulk-Out for Port 144222578Shselasky * 1, R/W */ 145222578Shselasky#define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshhold 146222578Shselasky * value for Bulk-Out and 147222578Shselasky * enable flag for Port 1, R/W */ 148222578Shselasky#define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshhold 149222578Shselasky * value for Bulk-Out for Port 150222578Shselasky * 2, R/W */ 151222578Shselasky#define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshhold 152222578Shselasky * value for Bulk-Out and 153222578Shselasky * enable flag for Port 2, R/W */ 154222578Shselasky#define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshhold 155222578Shselasky * value for Bulk-Out for Port 156222578Shselasky * 3, R/W */ 157222578Shselasky#define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshhold 158222578Shselasky * value for Bulk-Out and 159222578Shselasky * enable flag for Port 3, R/W */ 160222578Shselasky#define MCS7840_DEV_REG_THR_VAL_LOW4 0x45 /* Low 8 bits of threshhold 161222578Shselasky * value for Bulk-Out for Port 162222578Shselasky * 4, R/W */ 163222578Shselasky#define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshhold 164222578Shselasky * value for Bulk-Out and 165222578Shselasky * enable flag for Port 4, R/W */ 166222578Shselasky 167222578Shselasky/* Bits for SPx registers */ 168222578Shselasky#define MCS7840_DEV_SPx_LOOP_PIPES 0x01 /* Loop Bulk-Out FIFO to the 169222578Shselasky * Bulk-In FIFO, default = 0 */ 170222578Shselasky#define MCS7840_DEV_SPx_SKIP_ERR_DATA 0x02 /* Drop data bytes from UART, 171222578Shselasky * which were recevied with 172222578Shselasky * errors, default = 0 */ 173222578Shselasky#define MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */ 174222578Shselasky#define MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */ 175222578Shselasky#define MCS7840_DEV_SPx_CLOCK_MASK 0x70 /* Mask to extract Baud CLK 176222578Shselasky * source */ 177222578Shselasky#define MCS7840_DEV_SPx_CLOCK_X1 0x00 /* CLK = 1.8432Mhz, max speed 178222578Shselasky * = 115200 bps, default */ 179222578Shselasky#define MCS7840_DEV_SPx_CLOCK_X2 0x10 /* CLK = 3.6864Mhz, max speed 180222578Shselasky * = 230400 bps */ 181222578Shselasky#define MCS7840_DEV_SPx_CLOCK_X35 0x20 /* CLK = 6.4512Mhz, max speed 182222578Shselasky * = 403200 bps */ 183222578Shselasky#define MCS7840_DEV_SPx_CLOCK_X4 0x30 /* CLK = 7.3728Mhz, max speed 184222578Shselasky * = 460800 bps */ 185222578Shselasky#define MCS7840_DEV_SPx_CLOCK_X7 0x40 /* CLK = 12.9024Mhz, max speed 186222578Shselasky * = 806400 bps */ 187222578Shselasky#define MCS7840_DEV_SPx_CLOCK_X8 0x50 /* CLK = 14.7456Mhz, max speed 188222578Shselasky * = 921600 bps */ 189222578Shselasky#define MCS7840_DEV_SPx_CLOCK_24MHZ 0x60 /* CLK = 24.0000Mhz, max speed 190222578Shselasky * = 1.5 Mbps */ 191222578Shselasky#define MCS7840_DEV_SPx_CLOCK_48MHZ 0x70 /* CLK = 48.0000Mhz, max speed 192222578Shselasky * = 3.0 Mbps */ 193222578Shselasky#define MCS7840_DEV_SPx_CLOCK_SHIFT 4 /* Value 0..7 can be shifted 194222578Shselasky * to get clock value */ 195222578Shselasky#define MCS7840_DEV_SPx_UART_RESET 0x80 /* Reset UART */ 196222578Shselasky 197222578Shselasky/* Bits for CONTROLx registers */ 198222578Shselasky#define MCS7840_DEV_CONTROLx_HWFC 0x01 /* Enable hardware flow 199222578Shselasky * control (when power 200222578Shselasky * down? It is unclear 201222578Shselasky * in documents), 202222578Shselasky * default = 0 */ 203222578Shselasky#define MCS7840_DEV_CONTROLx_UNUNSED1 0x02 /* Reserved */ 204222578Shselasky#define MCS7840_DEV_CONTROLx_CTS_ENABLE 0x04 /* CTS changes are 205222578Shselasky * translated to MSR, 206222578Shselasky * default = 0 */ 207222578Shselasky#define MCS7840_DEV_CONTROLx_UNUSED2 0x08 /* Reserved for ports 208222578Shselasky * 2,3,4 */ 209222578Shselasky#define MCS7840_DEV_CONTROL1_DRIVER_DONE 0x08 /* USB enumerating is 210222578Shselasky * finished, USB 211222578Shselasky * enumeration memory 212222578Shselasky * can be used as FIFOs */ 213222578Shselasky#define MCS7840_DEV_CONTROLx_RX_NEGATE 0x10 /* Negate RX input, 214222578Shselasky * works for IrDA mode 215222578Shselasky * only, default = 0 */ 216222578Shselasky#define MCS7840_DEV_CONTROLx_RX_DISABLE 0x20 /* Disable RX logic, 217222578Shselasky * works only for 218222578Shselasky * RS-232/RS-485 mode, 219222578Shselasky * default = 0 */ 220222578Shselasky#define MCS7840_DEV_CONTROLx_FSM_CONTROL 0x40 /* Disable RX FSM when 221222578Shselasky * TX is in progress, 222222578Shselasky * works for IrDA mode 223222578Shselasky * only, default = 0 */ 224222578Shselasky#define MCS7840_DEV_CONTROLx_UNUSED3 0x80 /* Reserved */ 225222578Shselasky 226222578Shselasky/* 227222578Shselasky * Bits for PINPONGx registers 228222578Shselasky * These registers control how often two input buffers 229222578Shselasky * for Bulk-In FIFOs are swapped. One of buffers is used 230222578Shselasky * for USB trnasfer, other for receiving data from UART. 231222578Shselasky * Exact meaning of 15 bit value in these registers is unknown 232222578Shselasky */ 233222578Shselasky#define MCS7840_DEV_PINPONGHIGH_MULT 128 /* Only 7 bits in PINPONGLOW 234222578Shselasky * register */ 235222578Shselasky#define MCS7840_DEV_PINPONGLOW_BITS 7 /* Only 7 bits in PINPONGLOW 236222578Shselasky * register */ 237222578Shselasky 238222578Shselasky/* 239222578Shselasky * THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but e-mail from tech support 240222578Shselasky * confirms, that it is register for GPIO_0 and GPIO_1 data input/output. 241222578Shselasky * Chips has 2 GPIO, but first one (lower bit) MUST be used by device 242222578Shselasky * authors as "number of port" indicator, grounded (0) for two-port 243222578Shselasky * devices and pulled-up to 1 for 4-port devices. 244222578Shselasky */ 245222578Shselasky#define MCS7840_DEV_GPIO_4PORTS 0x01 /* Device has 4 ports 246222578Shselasky * configured */ 247222578Shselasky#define MCS7840_DEV_GPIO_GPIO_0 0x01 /* The same as above */ 248222578Shselasky#define MCS7840_DEV_GPIO_GPIO_1 0x02 /* GPIO_1 data */ 249222578Shselasky 250222578Shselasky/* 251222578Shselasky * Constants for PLL dividers 252222578Shselasky * Ouptut frequency of PLL is: 253222578Shselasky * Fout = (N/M) * Fin. 254222578Shselasky * Default PLL input frequency Fin is 12Mhz (on-chip). 255222578Shselasky */ 256222578Shselasky#define MCS7840_DEV_PLL_DIV_M_BITS 6 /* Number of useful bits for M 257222578Shselasky * divider */ 258222578Shselasky#define MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */ 259222578Shselasky#define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is 260222578Shselasky * forbidden */ 261222578Shselasky#define MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */ 262222578Shselasky#define MCS7840_DEV_PLL_DIV_M_MAX 63 /* Maximum value for M */ 263222578Shselasky#define MCS7840_DEV_PLL_DIV_N_BITS 6 /* Number of useful bits for N 264222578Shselasky * divider */ 265222578Shselasky#define MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */ 266222578Shselasky#define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is 267222578Shselasky * forbidden */ 268222578Shselasky#define MCS7840_DEV_PLL_DIV_N_DEF 8 /* Default value for N */ 269222578Shselasky#define MCS7840_DEV_PLL_DIV_N_MAX 63 /* Maximum value for N */ 270222578Shselasky 271222578Shselasky/* Bits for CLOCK_MUX register */ 272222578Shselasky#define MCS7840_DEV_CLOCK_MUX_INPUTMASK 0x03 /* Mask to extract PLL clock 273222578Shselasky * input */ 274222578Shselasky#define MCS7840_DEV_CLOCK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */ 275222578Shselasky#define MCS7840_DEV_CLOCK_MUX_INEXTRN 0x01 /* External (device-depended) 276222578Shselasky * PLL input */ 277222578Shselasky#define MCS7840_DEV_CLOCK_MUX_INRSV1 0x02 /* Reserved */ 278222578Shselasky#define MCS7840_DEV_CLOCK_MUX_INRSV2 0x03 /* Reserved */ 279222578Shselasky#define MCS7840_DEV_CLOCK_MUX_PLLHIGH 0x04 /* 0 = PLL Output is 280222578Shselasky * 20MHz-100MHz (default), 1 = 281222578Shselasky * 100MHz-300MHz range */ 282222578Shselasky#define MCS7840_DEV_CLOCK_MUX_INTRFIFOS 0x08 /* Enable additional 8 bytes 283222578Shselasky * fro Interrupt USB pipe with 284222578Shselasky * USB FIFOs statuses, default 285222578Shselasky * = 0 */ 286222578Shselasky#define MCS7840_DEV_CLOCK_MUX_RESERVED1 0x10 /* Unused */ 287222578Shselasky#define MCS7840_DEV_CLOCK_MUX_RESERVED2 0x20 /* Unused */ 288222578Shselasky#define MCS7840_DEV_CLOCK_MUX_RESERVED3 0x40 /* Unused */ 289222578Shselasky#define MCS7840_DEV_CLOCK_MUX_RESERVED4 0x80 /* Unused */ 290222578Shselasky 291222578Shselasky/* Bits for CLOCK_SELECTxx registers */ 292222578Shselasky#define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in 293222578Shselasky * CLOCK_SELECT12 */ 294222578Shselasky#define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in 295222578Shselasky * CLOCK_SELECT12 */ 296222578Shselasky#define MCS7840_DEV_CLOCK_SELECT2_MASK 0x38 /* Bits for port 2 in 297222578Shselasky * CLOCK_SELECT12 */ 298222578Shselasky#define MCS7840_DEV_CLOCK_SELECT2_SHIFT 3 /* Shift for port 2 in 299222578Shselasky * CLOCK_SELECT12 */ 300222578Shselasky#define MCS7840_DEV_CLOCK_SELECT3_MASK 0x07 /* Bits for port 3 in 301222578Shselasky * CLOCK_SELECT23 */ 302222578Shselasky#define MCS7840_DEV_CLOCK_SELECT3_SHIFT 0 /* Shift for port 3 in 303222578Shselasky * CLOCK_SELECT23 */ 304222578Shselasky#define MCS7840_DEV_CLOCK_SELECT4_MASK 0x38 /* Bits for port 4 in 305222578Shselasky * CLOCK_SELECT23 */ 306222578Shselasky#define MCS7840_DEV_CLOCK_SELECT4_SHIFT 3 /* Shift for port 4 in 307222578Shselasky * CLOCK_SELECT23 */ 308222578Shselasky#define MCS7840_DEV_CLOCK_SELECT_STD 0x00 /* STANDARD baudrate derived 309222578Shselasky * from 96Mhz, default for all 310222578Shselasky * ports */ 311222578Shselasky#define MCS7840_DEV_CLOCK_SELECT_30MHZ 0x01 /* 30Mhz */ 312222578Shselasky#define MCS7840_DEV_CLOCK_SELECT_96MHZ 0x02 /* 96Mhz direct */ 313222578Shselasky#define MCS7840_DEV_CLOCK_SELECT_120MHZ 0x03 /* 120Mhz */ 314222578Shselasky#define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N 315222578Shselasky * dividers) */ 316222578Shselasky#define MCS7840_DEV_CLOCK_SELECT_EXT 0x05 /* External clock input 317222578Shselasky * (device-dependend) */ 318222578Shselasky#define MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */ 319222578Shselasky#define MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */ 320222578Shselasky 321222578Shselasky/* Bits for MODE register */ 322222578Shselasky#define MCS7840_DEV_MODE_RESERVED1 0x01 /* Unused */ 323222578Shselasky#define MCS7840_DEV_MODE_RESET 0x02 /* 0: RESET = Active High 324222578Shselasky * (default), 1: Reserved (?) */ 325222578Shselasky#define MCS7840_DEV_MODE_SER_PRSNT 0x04 /* 0: Reserved, 1: Do not use 326222578Shselasky * hardocded values (default) 327222578Shselasky * (?) */ 328222578Shselasky#define MCS7840_DEV_MODE_PLLBYPASS 0x08 /* 1: PLL output is bypassed, 329222578Shselasky * default = 0 */ 330222578Shselasky#define MCS7840_DEV_MODE_PORBYPASS 0x10 /* 1: Power-On Reset is 331222578Shselasky * bypassed, default = 0 */ 332222578Shselasky#define MCS7840_DEV_MODE_SELECT24S 0x20 /* 0: 4 Serial Ports / IrDA 333222578Shselasky * active, 1: 2 Serial Ports / 334222578Shselasky * IrDA active */ 335222578Shselasky#define MCS7840_DEV_MODE_EEPROMWR 0x40 /* EEPROM write is enabled, 336222578Shselasky * default */ 337222578Shselasky#define MCS7840_DEV_MODE_IRDA 0x80 /* IrDA mode is activated 338222578Shselasky * (could be turned on), 339222578Shselasky * default */ 340222578Shselasky 341222578Shselasky/* Bits for SPx ICG */ 342222578Shselasky#define MCS7840_DEV_SPx_ICG_DEF 0x24 /* All 8 bits is used as 343222578Shselasky * number of BAUD clocks of 344222578Shselasky * pause */ 345222578Shselasky 346222578Shselasky/* 347222578Shselasky * Bits for RX_SAMPLINGxx registers 348222578Shselasky * These registers control when bit value will be sampled within 349222578Shselasky * the baud period. 350222578Shselasky * 0 is very beginning of period, 15 is very end, 7 is the middle. 351222578Shselasky */ 352222578Shselasky#define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in 353222578Shselasky * RX_SAMPLING12 */ 354222578Shselasky#define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in 355222578Shselasky * RX_SAMPLING12 */ 356222578Shselasky#define MCS7840_DEV_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in 357222578Shselasky * RX_SAMPLING12 */ 358222578Shselasky#define MCS7840_DEV_RX_SAMPLING2_SHIFT 4 /* Shift for port 2 in 359222578Shselasky * RX_SAMPLING12 */ 360222578Shselasky#define MCS7840_DEV_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in 361222578Shselasky * RX_SAMPLING23 */ 362222578Shselasky#define MCS7840_DEV_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in 363222578Shselasky * RX_SAMPLING23 */ 364222578Shselasky#define MCS7840_DEV_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in 365222578Shselasky * RX_SAMPLING23 */ 366222578Shselasky#define MCS7840_DEV_RX_SAMPLING4_SHIFT 4 /* Shift for port 4 in 367222578Shselasky * RX_SAMPLING23 */ 368222578Shselasky#define MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */ 369222578Shselasky#define MCS7840_DEV_RX_SAMPLINGx_DEF 7 /* Default for any RX 370222578Shselasky * Sampling, center of period */ 371222578Shselasky#define MCS7840_DEV_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */ 372222578Shselasky 373222578Shselasky/* Bits for ZERO_PERIODx */ 374222578Shselasky#define MCS7840_DEV_ZERO_PERIODx_DEF 20 /* Number of Bulk-in requests 375222578Shselasky * befor sending zero-sized 376222578Shselasky * reply */ 377222578Shselasky 378222578Shselasky/* Bits for ZERO_ENABLE */ 379222578Shselasky#define MCS7840_DEV_ZERO_ENABLE_PORT1 0x01 /* Enable of sending 380222578Shselasky * zero-sized replies for port 381222578Shselasky * 1, default */ 382222578Shselasky#define MCS7840_DEV_ZERO_ENABLE_PORT2 0x02 /* Enable of sending 383222578Shselasky * zero-sized replies for port 384222578Shselasky * 2, default */ 385222578Shselasky#define MCS7840_DEV_ZERO_ENABLE_PORT3 0x04 /* Enable of sending 386222578Shselasky * zero-sized replies for port 387222578Shselasky * 3, default */ 388222578Shselasky#define MCS7840_DEV_ZERO_ENABLE_PORT4 0x08 /* Enable of sending 389222578Shselasky * zero-sized replies for port 390222578Shselasky * 4, default */ 391222578Shselasky 392222578Shselasky/* Bits for THR_VAL_HIGHx */ 393222578Shselasky#define MCS7840_DEV_THR_VAL_HIGH_MASK 0x01 /* Only one bit is used */ 394222578Shselasky#define MCS7840_DEV_THR_VAL_HIGH_MUL 256 /* This one bit is means "256" */ 395222578Shselasky#define MCS7840_DEV_THR_VAL_HIGH_SHIFT 8 /* This one bit is means "256" */ 396222578Shselasky#define MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */ 397222578Shselasky 398222578Shselasky/* These are documented in "public" datasheet */ 399222578Shselasky#define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port 400222578Shselasky * 1, R/W */ 401222578Shselasky#define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port 402222578Shselasky * 1, R/W */ 403222578Shselasky#define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port 404222578Shselasky * 1, R/W */ 405222578Shselasky#define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port 406222578Shselasky * 2, R/W */ 407222578Shselasky#define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port 408222578Shselasky * 2, R/W */ 409222578Shselasky#define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port 410222578Shselasky * 2, R/W */ 411222578Shselasky#define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port 412222578Shselasky * 3, R/W */ 413222578Shselasky#define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port 414222578Shselasky * 3, R/W */ 415222578Shselasky#define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port 416222578Shselasky * 3, R/W */ 417222578Shselasky#define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port 418222578Shselasky * 4, R/W */ 419222578Shselasky#define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port 420222578Shselasky * 4, R/W */ 421222578Shselasky#define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port 422222578Shselasky * 4, R/W */ 423222578Shselasky 424222578Shselasky/* Bits of DCR0 registers, documented in datasheet */ 425222578Shselasky#define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transiver 426222578Shselasky * when USB Suspend is 427222578Shselasky * engaged, default = 1 */ 428222578Shselasky#define MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */ 429222578Shselasky#define MCS7840_DEV_DCR0_GPIO_MODE_MASK 0x0c /* GPIO Mode bits, WORKS 430222578Shselasky * ONLY FOR PORT 1 */ 431222578Shselasky#define MCS7840_DEV_DCR0_GPIO_MODE_IN 0x00 /* GPIO Mode - Input 432222578Shselasky * (0b00), WORKS ONLY 433222578Shselasky * FOR PORT 1 */ 434222578Shselasky#define MCS7840_DEV_DCR0_GPIO_MODE_OUT 0x08 /* GPIO Mode - Input 435222578Shselasky * (0b10), WORKS ONLY 436222578Shselasky * FOR PORT 1 */ 437222578Shselasky#define MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH 0x10 /* RTS Active is HIGH, 438222578Shselasky * default = 0 (low) */ 439222578Shselasky#define MCS7840_DEV_DCR0_RTS_AUTO 0x20 /* RTS is controlled by 440222578Shselasky * state of TX buffer, 441222578Shselasky * default = 0 442222578Shselasky * (controlled by MCR) */ 443222578Shselasky#define MCS7840_DEV_DCR0_IRDA 0x40 /* IrDA mode */ 444222578Shselasky#define MCS7840_DEV_DCR0_RESERVED2 0x80 /* Unused */ 445222578Shselasky 446222578Shselasky/* Bits of DCR1 registers, documented in datasheet */ 447222578Shselasky#define MCS7840_DEV_DCR1_GPIO_CURRENT_MASK 0x03 /* Mask to extract GPIO 448222578Shselasky * current value, WORKS 449222578Shselasky * ONLY FOR PORT 1 */ 450222578Shselasky#define MCS7840_DEV_DCR1_GPIO_CURRENT_6MA 0x00 /* GPIO output current 451222578Shselasky * 6mA, WORKS ONLY FOR 452222578Shselasky * PORT 1 */ 453222578Shselasky#define MCS7840_DEV_DCR1_GPIO_CURRENT_8MA 0x01 /* GPIO output current 454222578Shselasky * 8mA, defauilt, WORKS 455222578Shselasky * ONLY FOR PORT 1 */ 456222578Shselasky#define MCS7840_DEV_DCR1_GPIO_CURRENT_10MA 0x02 /* GPIO output current 457222578Shselasky * 10mA, WORKS ONLY FOR 458222578Shselasky * PORT 1 */ 459222578Shselasky#define MCS7840_DEV_DCR1_GPIO_CURRENT_12MA 0x03 /* GPIO output current 460222578Shselasky * 12mA, WORKS ONLY FOR 461222578Shselasky * PORT 1 */ 462222578Shselasky#define MCS7840_DEV_DCR1_UART_CURRENT_MASK 0x0c /* Mask to extract UART 463222578Shselasky * signals current value */ 464222578Shselasky#define MCS7840_DEV_DCR1_UART_CURRENT_6MA 0x00 /* UART output current 465222578Shselasky * 6mA */ 466222578Shselasky#define MCS7840_DEV_DCR1_UART_CURRENT_8MA 0x04 /* UART output current 467222578Shselasky * 8mA, defauilt */ 468222578Shselasky#define MCS7840_DEV_DCR1_UART_CURRENT_10MA 0x08 /* UART output current 469222578Shselasky * 10mA */ 470222578Shselasky#define MCS7840_DEV_DCR1_UART_CURRENT_12MA 0x0c /* UART output current 471222578Shselasky * 12mA */ 472222578Shselasky#define MCS7840_DEV_DCR1_WAKEUP_DISABLE 0x10 /* Disable Remote USB 473222578Shselasky * Wakeup */ 474222578Shselasky#define MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE 0x20 /* Disable PLL power 475222578Shselasky * down when not needed, 476222578Shselasky * WORKS ONLY FOR PORT 1 */ 477222578Shselasky#define MCS7840_DEV_DCR1_LONG_INTERRUPT 0x40 /* Enable 13 bytes of 478222578Shselasky * interrupt data, with 479222578Shselasky * FIFO statistics, 480222578Shselasky * WORKS ONLY FOR PORT 1 */ 481222578Shselasky#define MCS7840_DEV_DCR1_RESERVED1 0x80 /* Unused */ 482222578Shselasky 483222578Shselasky/* 484222578Shselasky * Bits of DCR2 registers, documented in datasheet 485222578Shselasky * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and 486222578Shselasky * DCR1_WAKEUP_DISABLE = 0 (wakeup enabled). 487222578Shselasky */ 488222578Shselasky#define MCS7840_DEV_DCR2_WAKEUP_CTS 0x01 /* Wakeup on CTS change, 489222578Shselasky * default = 0 */ 490222578Shselasky#define MCS7840_DEV_DCR2_WAKEUP_DCD 0x02 /* Wakeup on DCD change, 491222578Shselasky * default = 0 */ 492222578Shselasky#define MCS7840_DEV_DCR2_WAKEUP_RI 0x04 /* Wakeup on RI change, 493222578Shselasky * default = 1 */ 494222578Shselasky#define MCS7840_DEV_DCR2_WAKEUP_DSR 0x08 /* Wakeup on DSR change, 495222578Shselasky * default = 0 */ 496222578Shselasky#define MCS7840_DEV_DCR2_WAKEUP_RXD 0x10 /* Wakeup on RX Data change, 497222578Shselasky * default = 0 */ 498222578Shselasky#define MCS7840_DEV_DCR2_WAKEUP_RESUME 0x20 /* Wakeup issues RESUME 499222578Shselasky * signal, DISCONNECT 500222578Shselasky * otherwise, default = 1 */ 501222578Shselasky#define MCS7840_DEV_DCR2_RESERVED1 0x40 /* Unused */ 502222578Shselasky#define MCS7840_DEV_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1: 503222578Shselasky * Pin 12 Active High, default 504222578Shselasky * = 0 */ 505222578Shselasky 506222578Shselasky/* Interrupt endpoint bytes & bits */ 507222578Shselasky#define MCS7840_IEP_FIFO_STATUS_INDEX 5 508222578Shselasky/* 509222578Shselasky * Thesse can be calculated as "1 << portnumber" for Bulk-out and 510222578Shselasky * "1 << (portnumber+1)" for Bulk-in 511222578Shselasky */ 512222578Shselasky#define MCS7840_IEP_BO_PORT1_HASDATA 0x01 513222578Shselasky#define MCS7840_IEP_BI_PORT1_HASDATA 0x02 514222578Shselasky#define MCS7840_IEP_BO_PORT2_HASDATA 0x04 515222578Shselasky#define MCS7840_IEP_BI_PORT2_HASDATA 0x08 516222578Shselasky#define MCS7840_IEP_BO_PORT3_HASDATA 0x10 517222578Shselasky#define MCS7840_IEP_BI_PORT3_HASDATA 0x20 518222578Shselasky#define MCS7840_IEP_BO_PORT4_HASDATA 0x40 519222578Shselasky#define MCS7840_IEP_BI_PORT4_HASDATA 0x80 520222578Shselasky 521222578Shselasky/* Documented UART registers (fully compatible with 16550 UART) */ 522222578Shselasky#define MCS7840_UART_REG_THR 0x00 /* Transmitter Holding 523222578Shselasky * Register W/Only */ 524222578Shselasky#define MCS7840_UART_REG_RHR 0x00 /* Receiver Holding Register 525222578Shselasky * R/Only */ 526222578Shselasky#define MCS7840_UART_REG_IER 0x01 /* Interrupt enable register - 527222578Shselasky * R/W */ 528222578Shselasky#define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register - 529222578Shselasky * W/Only */ 530222578Shselasky#define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Registter 531222578Shselasky * R/Only */ 532222578Shselasky#define MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */ 533222578Shselasky#define MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */ 534222578Shselasky#define MCS7840_UART_REG_LSR 0x05 /* Line status register R/Only */ 535222578Shselasky#define MCS7840_UART_REG_MSR 0x06 /* Modem status register 536222578Shselasky * R/Only */ 537222578Shselasky#define MCS7840_UART_REG_SCRATCHPAD 0x07 /* Scratch pad register */ 538222578Shselasky 539222578Shselasky#define MCS7840_UART_REG_DLL 0x00 /* Low bits of BAUD divider */ 540222578Shselasky#define MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */ 541222578Shselasky 542222578Shselasky/* IER bits */ 543222578Shselasky#define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */ 544222578Shselasky#define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */ 545222578Shselasky#define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */ 546222578Shselasky#define MCS7840_UART_IER_MODEM 0x08 /* Modem status change 547222578Shselasky * interrumpt mask */ 548222578Shselasky#define MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */ 549222578Shselasky 550222578Shselasky/* FCR bits */ 551222578Shselasky#define MCS7840_UART_FCR_ENABLE 0x01 /* Enable FIFO */ 552222578Shselasky#define MCS7840_UART_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */ 553222578Shselasky#define MCS7840_UART_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */ 554222578Shselasky#define MCS7840_UART_FCR_RTLMASK 0xa0 /* Mask to select RHR 555222578Shselasky * Interrupt Trigger level */ 556222578Shselasky#define MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */ 557222578Shselasky#define MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */ 558222578Shselasky#define MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */ 559222578Shselasky#define MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */ 560222578Shselasky 561222578Shselasky/* ISR bits */ 562222578Shselasky#define MCS7840_UART_ISR_NOPENDING 0x01 /* No interrupt pending */ 563222578Shselasky#define MCS7840_UART_ISR_INTMASK 0x3f /* Mask to select interrupt 564222578Shselasky * source */ 565222578Shselasky#define MCS7840_UART_ISR_RXERR 0x06 /* Recevir error */ 566222578Shselasky#define MCS7840_UART_ISR_RXHASDATA 0x04 /* Recevier has data */ 567222578Shselasky#define MCS7840_UART_ISR_RXTIMEOUT 0x0c /* Recevier timeout */ 568222578Shselasky#define MCS7840_UART_ISR_TXEMPTY 0x02 /* Transmitter empty */ 569222578Shselasky#define MCS7840_UART_ISR_MSCHANGE 0x00 /* Modem status change */ 570222578Shselasky 571222578Shselasky/* LCR bits */ 572222578Shselasky#define MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */ 573222578Shselasky#define MCS7840_UART_LCR_DATALEN5 0x00 /* 5 data bits */ 574222578Shselasky#define MCS7840_UART_LCR_DATALEN6 0x01 /* 6 data bits */ 575222578Shselasky#define MCS7840_UART_LCR_DATALEN7 0x02 /* 7 data bits */ 576222578Shselasky#define MCS7840_UART_LCR_DATALEN8 0x03 /* 8 data bits */ 577222578Shselasky 578222578Shselasky#define MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */ 579222578Shselasky#define MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */ 580222578Shselasky#define MCS7840_UART_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on 581222578Shselasky * data length */ 582222578Shselasky 583222578Shselasky#define MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */ 584222578Shselasky#define MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */ 585222578Shselasky#define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ 586222578Shselasky#define MCS7840_UART_LCR_PARITYEVEN 0x10 /* Parity Even */ 587222578Shselasky#define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ 588222578Shselasky#define MCS7840_UART_LCR_PARITYFORCE 0x20 /* Force parity odd/even */ 589222578Shselasky 590222578Shselasky#define MCS7840_UART_LCR_BREAK 0x40 /* Send BREAK */ 591222578Shselasky#define MCS7840_UART_LCR_DIVISORS 0x80 /* Map DLL/DLM instead of 592222578Shselasky * xHR/IER */ 593222578Shselasky 594222578Shselasky/* LSR bits */ 595222578Shselasky#define MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */ 596222578Shselasky#define MCS7840_UART_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */ 597222578Shselasky#define MCS7840_UART_LSR_PARITYERR 0x04 /* Parity error */ 598222578Shselasky#define MCS7840_UART_LSR_FRAMEERR 0x10 /* Framing error */ 599252123Sthomas#define MCS7840_UART_LSR_BREAKERR 0x20 /* BREAK signal received */ 600222578Shselasky#define MCS7840_UART_LSR_THREMPTY 0x40 /* THR register is empty, 601222578Shselasky * ready for transmit */ 602222578Shselasky#define MCS7840_UART_LSR_HASERR 0x80 /* Has error in receiver FIFO */ 603222578Shselasky 604222578Shselasky/* MCR bits */ 605222578Shselasky#define MCS7840_UART_MCR_DTR 0x01 /* Force DTR to be active 606222578Shselasky * (low) */ 607222578Shselasky#define MCS7840_UART_MCR_RTS 0x02 /* Force RTS to be active 608222578Shselasky * (low) */ 609222578Shselasky#define MCS7840_UART_MCR_IE 0x04 /* Enable interrupts (from 610222578Shselasky * code, not documented) */ 611222578Shselasky#define MCS7840_UART_MCR_LOOPBACK 0x10 /* Enable local loopback test 612222578Shselasky * mode */ 613222578Shselasky#define MCS7840_UART_MCR_CTSRTS 0x20 /* Enable CTS/RTS flow control 614222578Shselasky * in 550 (FIFO) mode */ 615222578Shselasky#define MCS7840_UART_MCR_DTRDSR 0x40 /* Enable DTR/DSR flow control 616222578Shselasky * in 550 (FIFO) mode */ 617222578Shselasky#define MCS7840_UART_MCR_DCD 0x80 /* Enable DCD flow control in 618222578Shselasky * 550 (FIFO) mode */ 619222578Shselasky 620222578Shselasky/* MSR bits */ 621222578Shselasky#define MCS7840_UART_MSR_DELTACTS 0x01 /* CTS was changed since last 622222578Shselasky * read */ 623222578Shselasky#define MCS7840_UART_MSR_DELTADSR 0x02 /* DSR was changed since last 624222578Shselasky * read */ 625222578Shselasky#define MCS7840_UART_MSR_DELTARI 0x04 /* RI was changed from low to 626222578Shselasky * high since last read */ 627222578Shselasky#define MCS7840_UART_MSR_DELTADCD 0x08 /* DCD was changed since last 628222578Shselasky * read */ 629222578Shselasky#define MCS7840_UART_MSR_NEGCTS 0x10 /* Negated CTS signal */ 630222578Shselasky#define MCS7840_UART_MSR_NEGDSR 0x20 /* Negated DSR signal */ 631222578Shselasky#define MCS7840_UART_MSR_NEGRI 0x40 /* Negated RI signal */ 632222578Shselasky#define MCS7840_UART_MSR_NEGDCD 0x80 /* Negated DCD signal */ 633222578Shselasky 634222578Shselasky/* SCRATCHPAD bits */ 635222578Shselasky#define MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */ 636222578Shselasky#define MCS7840_UART_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High 637222578Shselasky * = RX */ 638222578Shselasky#define MCS7840_UART_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High 639222578Shselasky * = TX */ 640222578Shselasky 641222578Shselasky#define MCS7840_CONFIG_INDEX 0 642222578Shselasky#define MCS7840_IFACE_INDEX 0 643222578Shselasky 644222578Shselasky#endif 645