if_ruereg.h revision 196219
1238104Sdes/*- 2238104Sdes * Copyright (c) 2001-2003, Shunsuke Akiyama <akiyama@FreeBSD.org>. 3238104Sdes * All rights reserved. 4238104Sdes * 5269257Sdes * Redistribution and use in source and binary forms, with or without 6238104Sdes * modification, are permitted provided that the following conditions 7238104Sdes * are met: 8238104Sdes * 1. Redistributions of source code must retain the above copyright 9238104Sdes * notice, this list of conditions and the following disclaimer. 10238104Sdes * 2. Redistributions in binary form must reproduce the above copyright 11238104Sdes * notice, this list of conditions and the following disclaimer in the 12238104Sdes * documentation and/or other materials provided with the distribution. 13238104Sdes * 14238104Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15238104Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16269257Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17269257Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18269257Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19269257Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20238104Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21238104Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22238104Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23238104Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24238104Sdes * SUCH DAMAGE. 25238104Sdes * 26238104Sdes * $FreeBSD: head/sys/dev/usb/net/if_ruereg.h 196219 2009-08-14 20:03:53Z jhb $ 27238104Sdes */ 28246854Sdes 29238104Sdes#define RUE_CONFIG_IDX 0 /* config number 1 */ 30238104Sdes#define RUE_IFACE_IDX 0 31238104Sdes 32238104Sdes#define RUE_INTR_PKTLEN 0x8 33238104Sdes 34238104Sdes#define RUE_TIMEOUT 50 35238104Sdes#define RUE_MIN_FRAMELEN 60 36238104Sdes 37238104Sdes/* Registers. */ 38238104Sdes#define RUE_IDR0 0x0120 39238104Sdes#define RUE_IDR1 0x0121 40238104Sdes#define RUE_IDR2 0x0122 41238104Sdes#define RUE_IDR3 0x0123 42238104Sdes#define RUE_IDR4 0x0124 43238104Sdes#define RUE_IDR5 0x0125 44238104Sdes 45238104Sdes#define RUE_MAR0 0x0126 46238104Sdes#define RUE_MAR1 0x0127 47246854Sdes#define RUE_MAR2 0x0128 48238104Sdes#define RUE_MAR3 0x0129 49238104Sdes#define RUE_MAR4 0x012A 50238104Sdes#define RUE_MAR5 0x012B 51238104Sdes#define RUE_MAR6 0x012C 52238104Sdes#define RUE_MAR7 0x012D 53238104Sdes 54238104Sdes#define RUE_CR 0x012E /* B, R/W */ 55238104Sdes#define RUE_CR_SOFT_RST 0x10 56238104Sdes#define RUE_CR_RE 0x08 57238104Sdes#define RUE_CR_TE 0x04 58238104Sdes#define RUE_CR_EP3CLREN 0x02 59238104Sdes 60238104Sdes#define RUE_TCR 0x012F /* B, R/W */ 61238104Sdes#define RUE_TCR_TXRR1 0x80 62269257Sdes#define RUE_TCR_TXRR0 0x40 63269257Sdes#define RUE_TCR_IFG1 0x10 64238104Sdes#define RUE_TCR_IFG0 0x08 65238104Sdes#define RUE_TCR_NOCRC 0x01 66238104Sdes#define RUE_TCR_CONFIG (RUE_TCR_TXRR1 | RUE_TCR_TXRR0 | \ 67238104Sdes RUE_TCR_IFG1 | RUE_TCR_IFG0) 68238104Sdes 69269257Sdes#define RUE_RCR 0x0130 /* W, R/W */ 70238104Sdes#define RUE_RCR_TAIL 0x80 71238104Sdes#define RUE_RCR_AER 0x40 72238104Sdes#define RUE_RCR_AR 0x20 73238104Sdes#define RUE_RCR_AM 0x10 74269257Sdes#define RUE_RCR_AB 0x08 75238104Sdes#define RUE_RCR_AD 0x04 76238104Sdes#define RUE_RCR_AAM 0x02 77238104Sdes#define RUE_RCR_AAP 0x01 78238104Sdes#define RUE_RCR_CONFIG (RUE_RCR_TAIL | RUE_RCR_AD) 79238104Sdes 80238104Sdes#define RUE_TSR 0x0132 81238104Sdes#define RUE_RSR 0x0133 82246854Sdes#define RUE_CON0 0x0135 83238104Sdes#define RUE_CON1 0x0136 84246854Sdes#define RUE_MSR 0x0137 85246854Sdes#define RUE_PHYADD 0x0138 86238104Sdes#define RUE_PHYDAT 0x0139 87238104Sdes 88238104Sdes#define RUE_PHYCNT 0x013B /* B, R/W */ 89238104Sdes#define RUE_PHYCNT_PHYOWN 0x40 90246854Sdes#define RUE_PHYCNT_RWCR 0x20 91246854Sdes 92238104Sdes#define RUE_GPPC 0x013D 93238104Sdes#define RUE_WAKECNT 0x013E 94238104Sdes 95238104Sdes#define RUE_BMCR 0x0140 96238104Sdes#define RUE_BMCR_SPD_SET 0x2000 97238104Sdes#define RUE_BMCR_DUPLEX 0x0100 98238104Sdes 99269257Sdes#define RUE_BMSR 0x0142 100269257Sdes 101238104Sdes#define RUE_ANAR 0x0144 /* W, R/W */ 102238104Sdes#define RUE_ANAR_PAUSE 0x0400 103238104Sdes 104238104Sdes#define RUE_ANLP 0x0146 /* W, R/O */ 105238104Sdes#define RUE_ANLP_PAUSE 0x0400 106269257Sdes 107238104Sdes#define RUE_AER 0x0148 108238104Sdes 109238104Sdes#define RUE_NWAYT 0x014A 110238104Sdes#define RUE_CSCR 0x014C 111238104Sdes 112238104Sdes#define RUE_CRC0 0x014E 113238104Sdes#define RUE_CRC1 0x0150 114238104Sdes#define RUE_CRC2 0x0152 115238104Sdes#define RUE_CRC3 0x0154 116238104Sdes#define RUE_CRC4 0x0156 117238104Sdes 118238104Sdes#define RUE_BYTEMASK0 0x0158 119238104Sdes#define RUE_BYTEMASK1 0x0160 120238104Sdes#define RUE_BYTEMASK2 0x0168 121238104Sdes#define RUE_BYTEMASK3 0x0170 122238104Sdes#define RUE_BYTEMASK4 0x0178 123238104Sdes 124238104Sdes#define RUE_PHY1 0x0180 125238104Sdes#define RUE_PHY2 0x0184 126238104Sdes 127238104Sdes#define RUE_TW1 0x0186 128238104Sdes 129238104Sdes#define RUE_REG_MIN 0x0120 130238104Sdes#define RUE_REG_MAX 0x0189 131238104Sdes 132238104Sdes/* EEPROM address declarations. */ 133238104Sdes#define RUE_EEPROM_BASE 0x1200 134238104Sdes#define RUE_EEPROM_IDR0 (RUE_EEPROM_BASE + 0x02) 135238104Sdes#define RUE_EEPROM_IDR1 (RUE_EEPROM_BASE + 0x03) 136238104Sdes#define RUE_EEPROM_IDR2 (RUE_EEPROM_BASE + 0x03) 137238104Sdes#define RUE_EEPROM_IDR3 (RUE_EEPROM_BASE + 0x03) 138238104Sdes#define RUE_EEPROM_IDR4 (RUE_EEPROM_BASE + 0x03) 139238104Sdes#define RUE_EEPROM_IDR5 (RUE_EEPROM_BASE + 0x03) 140238104Sdes#define RUE_EEPROM_INTERVAL (RUE_EEPROM_BASE + 0x17) 141238104Sdes 142238104Sdes#define RUE_RXSTAT_VALID (0x01 << 12) 143238104Sdes#define RUE_RXSTAT_RUNT (0x02 << 12) 144238104Sdes#define RUE_RXSTAT_PMATCH (0x04 << 12) 145238104Sdes#define RUE_RXSTAT_MCAST (0x08 << 12) 146238104Sdes 147238104Sdes#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 148238104Sdes 149246854Sdesstruct rue_intrpkt { 150238104Sdes uint8_t rue_tsr; 151238104Sdes uint8_t rue_rsr; 152238104Sdes uint8_t rue_gep_msr; 153238104Sdes uint8_t rue_waksr; 154238104Sdes uint8_t rue_txok_cnt; 155238104Sdes uint8_t rue_rxlost_cnt; 156238104Sdes uint8_t rue_crcerr_cnt; 157238104Sdes uint8_t rue_col_cnt; 158238104Sdes} __packed; 159246854Sdes 160238104Sdesstruct rue_type { 161238104Sdes uint16_t rue_vid; 162238104Sdes uint16_t rue_did; 163238104Sdes}; 164238104Sdes 165238104Sdesenum { 166238104Sdes RUE_BULK_DT_WR, 167238104Sdes RUE_BULK_DT_RD, 168238104Sdes RUE_INTR_DT_RD, 169238104Sdes RUE_N_TRANSFER, 170238104Sdes}; 171238104Sdes 172238104Sdesstruct rue_softc { 173238104Sdes struct usb_ether sc_ue; 174238104Sdes struct mtx sc_mtx; 175238104Sdes struct usb_xfer *sc_xfer[RUE_N_TRANSFER]; 176238104Sdes 177238104Sdes int sc_flags; 178246854Sdes#define RUE_FLAG_LINK 0x0001 179246854Sdes}; 180246854Sdes 181246854Sdes#define RUE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 182238104Sdes#define RUE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 183238104Sdes#define RUE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 184238104Sdes