if_axe.c revision 216284
1/*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 216284 2010-12-08 01:24:05Z yongari $"); 35 36/* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51/* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70/* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79#include <sys/stdint.h> 80#include <sys/stddef.h> 81#include <sys/param.h> 82#include <sys/queue.h> 83#include <sys/types.h> 84#include <sys/systm.h> 85#include <sys/kernel.h> 86#include <sys/bus.h> 87#include <sys/linker_set.h> 88#include <sys/module.h> 89#include <sys/lock.h> 90#include <sys/mutex.h> 91#include <sys/condvar.h> 92#include <sys/sysctl.h> 93#include <sys/sx.h> 94#include <sys/unistd.h> 95#include <sys/callout.h> 96#include <sys/malloc.h> 97#include <sys/priv.h> 98 99#include <dev/usb/usb.h> 100#include <dev/usb/usbdi.h> 101#include <dev/usb/usbdi_util.h> 102#include "usbdevs.h" 103 104#define USB_DEBUG_VAR axe_debug 105#include <dev/usb/usb_debug.h> 106#include <dev/usb/usb_process.h> 107 108#include <dev/usb/net/usb_ethernet.h> 109#include <dev/usb/net/if_axereg.h> 110 111/* 112 * AXE_178_MAX_FRAME_BURST 113 * max frame burst size for Ax88178 and Ax88772 114 * 0 2048 bytes 115 * 1 4096 bytes 116 * 2 8192 bytes 117 * 3 16384 bytes 118 * use the largest your system can handle without USB stalling. 119 * 120 * NB: 88772 parts appear to generate lots of input errors with 121 * a 2K rx buffer and 8K is only slightly faster than 4K on an 122 * EHCI port on a T42 so change at your own risk. 123 */ 124#define AXE_178_MAX_FRAME_BURST 1 125 126#ifdef USB_DEBUG 127static int axe_debug = 0; 128 129SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 130SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0, 131 "Debug level"); 132#endif 133 134/* 135 * Various supported device vendors/products. 136 */ 137static const struct usb_device_id axe_devs[] = { 138#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 139 AXE_DEV(ABOCOM, UF200, 0), 140 AXE_DEV(ACERCM, EP1427X2, 0), 141 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 142 AXE_DEV(ASIX, AX88172, 0), 143 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 144 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 145 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 146 AXE_DEV(ATEN, UC210T, 0), 147 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 148 AXE_DEV(BILLIONTON, USB2AR, 0), 149 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 150 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 151 AXE_DEV(DLINK, DUBE100, 0), 152 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 153 AXE_DEV(GOODWAY, GWUSB2E, 0), 154 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 155 AXE_DEV(JVC, MP_PRX1, 0), 156 AXE_DEV(LINKSYS2, USB200M, 0), 157 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 158 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 159 AXE_DEV(MELCO, LUAU2KTX, 0), 160 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 161 AXE_DEV(NETGEAR, FA120, 0), 162 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 163 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 164 AXE_DEV(SITECOM, LN029, 0), 165 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 166 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 167#undef AXE_DEV 168}; 169 170static device_probe_t axe_probe; 171static device_attach_t axe_attach; 172static device_detach_t axe_detach; 173 174static usb_callback_t axe_bulk_read_callback; 175static usb_callback_t axe_bulk_write_callback; 176 177static miibus_readreg_t axe_miibus_readreg; 178static miibus_writereg_t axe_miibus_writereg; 179static miibus_statchg_t axe_miibus_statchg; 180 181static uether_fn_t axe_attach_post; 182static uether_fn_t axe_init; 183static uether_fn_t axe_stop; 184static uether_fn_t axe_start; 185static uether_fn_t axe_tick; 186static uether_fn_t axe_setmulti; 187static uether_fn_t axe_setpromisc; 188 189static int axe_ifmedia_upd(struct ifnet *); 190static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191static int axe_cmd(struct axe_softc *, int, int, int, void *); 192static void axe_ax88178_init(struct axe_softc *); 193static void axe_ax88772_init(struct axe_softc *); 194static void axe_ax88772a_init(struct axe_softc *); 195static int axe_get_phyno(struct axe_softc *, int); 196 197static const struct usb_config axe_config[AXE_N_TRANSFER] = { 198 199 [AXE_BULK_DT_WR] = { 200 .type = UE_BULK, 201 .endpoint = UE_ADDR_ANY, 202 .direction = UE_DIR_OUT, 203 .frames = 16, 204 .bufsize = 16 * MCLBYTES, 205 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 206 .callback = axe_bulk_write_callback, 207 .timeout = 10000, /* 10 seconds */ 208 }, 209 210 [AXE_BULK_DT_RD] = { 211 .type = UE_BULK, 212 .endpoint = UE_ADDR_ANY, 213 .direction = UE_DIR_IN, 214 .bufsize = 16384, /* bytes */ 215 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 216 .callback = axe_bulk_read_callback, 217 .timeout = 0, /* no timeout */ 218 }, 219}; 220 221static device_method_t axe_methods[] = { 222 /* Device interface */ 223 DEVMETHOD(device_probe, axe_probe), 224 DEVMETHOD(device_attach, axe_attach), 225 DEVMETHOD(device_detach, axe_detach), 226 227 /* bus interface */ 228 DEVMETHOD(bus_print_child, bus_generic_print_child), 229 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 230 231 /* MII interface */ 232 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 233 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 234 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 235 236 {0, 0} 237}; 238 239static driver_t axe_driver = { 240 .name = "axe", 241 .methods = axe_methods, 242 .size = sizeof(struct axe_softc), 243}; 244 245static devclass_t axe_devclass; 246 247DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 248DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 249MODULE_DEPEND(axe, uether, 1, 1, 1); 250MODULE_DEPEND(axe, usb, 1, 1, 1); 251MODULE_DEPEND(axe, ether, 1, 1, 1); 252MODULE_DEPEND(axe, miibus, 1, 1, 1); 253MODULE_VERSION(axe, 1); 254 255static const struct usb_ether_methods axe_ue_methods = { 256 .ue_attach_post = axe_attach_post, 257 .ue_start = axe_start, 258 .ue_init = axe_init, 259 .ue_stop = axe_stop, 260 .ue_tick = axe_tick, 261 .ue_setmulti = axe_setmulti, 262 .ue_setpromisc = axe_setpromisc, 263 .ue_mii_upd = axe_ifmedia_upd, 264 .ue_mii_sts = axe_ifmedia_sts, 265}; 266 267static int 268axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 269{ 270 struct usb_device_request req; 271 usb_error_t err; 272 273 AXE_LOCK_ASSERT(sc, MA_OWNED); 274 275 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 276 UT_WRITE_VENDOR_DEVICE : 277 UT_READ_VENDOR_DEVICE); 278 req.bRequest = AXE_CMD_CMD(cmd); 279 USETW(req.wValue, val); 280 USETW(req.wIndex, index); 281 USETW(req.wLength, AXE_CMD_LEN(cmd)); 282 283 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 284 285 return (err); 286} 287 288static int 289axe_miibus_readreg(device_t dev, int phy, int reg) 290{ 291 struct axe_softc *sc = device_get_softc(dev); 292 uint16_t val; 293 int locked; 294 295 if (sc->sc_phyno != phy) 296 return (0); 297 298 locked = mtx_owned(&sc->sc_mtx); 299 if (!locked) 300 AXE_LOCK(sc); 301 302 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 303 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 304 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 305 306 val = le16toh(val); 307 if (AXE_IS_772(sc) && reg == MII_BMSR) { 308 /* 309 * BMSR of AX88772 indicates that it supports extended 310 * capability but the extended status register is 311 * revered for embedded ethernet PHY. So clear the 312 * extended capability bit of BMSR. 313 */ 314 val &= ~BMSR_EXTCAP; 315 } 316 317 if (!locked) 318 AXE_UNLOCK(sc); 319 return (val); 320} 321 322static int 323axe_miibus_writereg(device_t dev, int phy, int reg, int val) 324{ 325 struct axe_softc *sc = device_get_softc(dev); 326 int locked; 327 328 val = htole32(val); 329 330 if (sc->sc_phyno != phy) 331 return (0); 332 333 locked = mtx_owned(&sc->sc_mtx); 334 if (!locked) 335 AXE_LOCK(sc); 336 337 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 338 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 339 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 340 341 if (!locked) 342 AXE_UNLOCK(sc); 343 return (0); 344} 345 346static void 347axe_miibus_statchg(device_t dev) 348{ 349 struct axe_softc *sc = device_get_softc(dev); 350 struct mii_data *mii = GET_MII(sc); 351 struct ifnet *ifp; 352 uint16_t val; 353 int err, locked; 354 355 locked = mtx_owned(&sc->sc_mtx); 356 if (!locked) 357 AXE_LOCK(sc); 358 359 ifp = uether_getifp(&sc->sc_ue); 360 if (mii == NULL || ifp == NULL || 361 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 362 goto done; 363 364 sc->sc_flags &= ~AXE_FLAG_LINK; 365 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 366 (IFM_ACTIVE | IFM_AVALID)) { 367 switch (IFM_SUBTYPE(mii->mii_media_active)) { 368 case IFM_10_T: 369 case IFM_100_TX: 370 sc->sc_flags |= AXE_FLAG_LINK; 371 break; 372 case IFM_1000_T: 373 if ((sc->sc_flags & AXE_FLAG_178) == 0) 374 break; 375 sc->sc_flags |= AXE_FLAG_LINK; 376 break; 377 default: 378 break; 379 } 380 } 381 382 /* Lost link, do nothing. */ 383 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 384 goto done; 385 386 val = 0; 387 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 388 val |= AXE_MEDIA_FULL_DUPLEX; 389 if (AXE_IS_178_FAMILY(sc)) { 390 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 391 if ((sc->sc_flags & AXE_FLAG_178) != 0) 392 val |= AXE_178_MEDIA_ENCK; 393 switch (IFM_SUBTYPE(mii->mii_media_active)) { 394 case IFM_1000_T: 395 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 396 break; 397 case IFM_100_TX: 398 val |= AXE_178_MEDIA_100TX; 399 break; 400 case IFM_10_T: 401 /* doesn't need to be handled */ 402 break; 403 } 404 } 405 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 406 if (err) 407 device_printf(dev, "media change failed, error %d\n", err); 408done: 409 if (!locked) 410 AXE_UNLOCK(sc); 411} 412 413/* 414 * Set media options. 415 */ 416static int 417axe_ifmedia_upd(struct ifnet *ifp) 418{ 419 struct axe_softc *sc = ifp->if_softc; 420 struct mii_data *mii = GET_MII(sc); 421 int error; 422 423 AXE_LOCK_ASSERT(sc, MA_OWNED); 424 425 if (mii->mii_instance) { 426 struct mii_softc *miisc; 427 428 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 429 mii_phy_reset(miisc); 430 } 431 error = mii_mediachg(mii); 432 return (error); 433} 434 435/* 436 * Report current media status. 437 */ 438static void 439axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 440{ 441 struct axe_softc *sc = ifp->if_softc; 442 struct mii_data *mii = GET_MII(sc); 443 444 AXE_LOCK(sc); 445 mii_pollstat(mii); 446 AXE_UNLOCK(sc); 447 ifmr->ifm_active = mii->mii_media_active; 448 ifmr->ifm_status = mii->mii_media_status; 449} 450 451static void 452axe_setmulti(struct usb_ether *ue) 453{ 454 struct axe_softc *sc = uether_getsc(ue); 455 struct ifnet *ifp = uether_getifp(ue); 456 struct ifmultiaddr *ifma; 457 uint32_t h = 0; 458 uint16_t rxmode; 459 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 460 461 AXE_LOCK_ASSERT(sc, MA_OWNED); 462 463 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 464 rxmode = le16toh(rxmode); 465 466 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 467 rxmode |= AXE_RXCMD_ALLMULTI; 468 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 469 return; 470 } 471 rxmode &= ~AXE_RXCMD_ALLMULTI; 472 473 if_maddr_rlock(ifp); 474 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 475 { 476 if (ifma->ifma_addr->sa_family != AF_LINK) 477 continue; 478 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 479 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 480 hashtbl[h / 8] |= 1 << (h % 8); 481 } 482 if_maddr_runlock(ifp); 483 484 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 485 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 486} 487 488static int 489axe_get_phyno(struct axe_softc *sc, int sel) 490{ 491 int phyno; 492 493 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 494 case PHY_TYPE_100_HOME: 495 case PHY_TYPE_GIG: 496 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 497 break; 498 case PHY_TYPE_SPECIAL: 499 /* FALLTHROUGH */ 500 case PHY_TYPE_RSVD: 501 /* FALLTHROUGH */ 502 case PHY_TYPE_NON_SUP: 503 /* FALLTHROUGH */ 504 default: 505 phyno = -1; 506 break; 507 } 508 509 return (phyno); 510} 511 512#define AXE_GPIO_WRITE(x, y) do { \ 513 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 514 uether_pause(ue, (y)); \ 515} while (0) 516 517static void 518axe_ax88178_init(struct axe_softc *sc) 519{ 520 struct usb_ether *ue; 521 int gpio0, phymode; 522 uint16_t eeprom, val; 523 524 ue = &sc->sc_ue; 525 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 526 /* XXX magic */ 527 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 528 eeprom = le16toh(eeprom); 529 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 530 531 /* if EEPROM is invalid we have to use to GPIO0 */ 532 if (eeprom == 0xffff) { 533 phymode = AXE_PHY_MODE_MARVELL; 534 gpio0 = 1; 535 } else { 536 phymode = eeprom & 0x7f; 537 gpio0 = (eeprom & 0x80) ? 0 : 1; 538 } 539 540 if (bootverbose) 541 device_printf(sc->sc_ue.ue_dev, 542 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 543 phymode); 544 /* Program GPIOs depending on PHY hardware. */ 545 switch (phymode) { 546 case AXE_PHY_MODE_MARVELL: 547 if (gpio0 == 1) { 548 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 549 hz / 32); 550 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 551 hz / 32); 552 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 553 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 554 hz / 32); 555 } else 556 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 557 AXE_GPIO1_EN, hz / 32); 558 break; 559 case AXE_PHY_MODE_CICADA: 560 case AXE_PHY_MODE_CICADA_V2: 561 case AXE_PHY_MODE_CICADA_V2_ASIX: 562 if (gpio0 == 1) 563 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 564 AXE_GPIO0_EN, hz / 32); 565 else 566 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 567 AXE_GPIO1_EN, hz / 32); 568 break; 569 case AXE_PHY_MODE_AGERE: 570 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 571 AXE_GPIO1_EN, hz / 32); 572 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 573 AXE_GPIO2_EN, hz / 32); 574 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 575 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 576 AXE_GPIO2_EN, hz / 32); 577 break; 578 case AXE_PHY_MODE_REALTEK_8211CL: 579 case AXE_PHY_MODE_REALTEK_8211BN: 580 case AXE_PHY_MODE_REALTEK_8251CL: 581 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 582 AXE_GPIO1 | AXE_GPIO1_EN; 583 AXE_GPIO_WRITE(val, hz / 32); 584 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 585 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 586 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 587 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 588 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 589 0x1F, 0x0005); 590 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 591 0x0C, 0x0000); 592 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 593 0x0001); 594 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 595 0x01, val | 0x0080); 596 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 597 0x1F, 0x0000); 598 } 599 break; 600 default: 601 /* Unknown PHY model or no need to program GPIOs. */ 602 break; 603 } 604 605 /* soft reset */ 606 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 607 uether_pause(ue, hz / 4); 608 609 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 610 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 611 uether_pause(ue, hz / 4); 612 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 613 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 614 uether_pause(ue, hz / 4); 615 616 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 617} 618 619static void 620axe_ax88772_init(struct axe_softc *sc) 621{ 622 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 623 uether_pause(&sc->sc_ue, hz / 16); 624 625 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 626 /* ask for the embedded PHY */ 627 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 628 uether_pause(&sc->sc_ue, hz / 64); 629 630 /* power down and reset state, pin reset state */ 631 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 632 AXE_SW_RESET_CLEAR, NULL); 633 uether_pause(&sc->sc_ue, hz / 16); 634 635 /* power down/reset state, pin operating state */ 636 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 637 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 638 uether_pause(&sc->sc_ue, hz / 4); 639 640 /* power up, reset */ 641 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 642 643 /* power up, operating */ 644 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 645 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 646 } else { 647 /* ask for external PHY */ 648 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 649 uether_pause(&sc->sc_ue, hz / 64); 650 651 /* power down internal PHY */ 652 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 653 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 654 } 655 656 uether_pause(&sc->sc_ue, hz / 4); 657 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 658} 659 660static void 661axe_ax88772a_init(struct axe_softc *sc) 662{ 663 struct usb_ether *ue; 664 uint16_t eeprom; 665 666 ue = &sc->sc_ue; 667 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 668 eeprom = le16toh(eeprom); 669 /* Reload EEPROM. */ 670 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 671 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 672 /* Manually select internal(embedded) PHY - MAC mode. */ 673 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 674 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 675 NULL); 676 uether_pause(&sc->sc_ue, hz / 32); 677 } else { 678 /* 679 * Manually select external PHY - MAC mode. 680 * Reverse MII/RMII is for AX88772A PHY mode. 681 */ 682 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 683 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 684 uether_pause(&sc->sc_ue, hz / 32); 685 } 686 /* Take PHY out of power down. */ 687 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 688 AXE_SW_RESET_IPRL, NULL); 689 uether_pause(&sc->sc_ue, hz / 4); 690 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 691 uether_pause(&sc->sc_ue, hz); 692 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 693 uether_pause(&sc->sc_ue, hz / 32); 694 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 695 uether_pause(&sc->sc_ue, hz / 32); 696 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 697} 698 699#undef AXE_GPIO_WRITE 700 701static void 702axe_reset(struct axe_softc *sc) 703{ 704 struct usb_config_descriptor *cd; 705 usb_error_t err; 706 707 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 708 709 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 710 cd->bConfigurationValue); 711 if (err) 712 DPRINTF("reset failed (ignored)\n"); 713 714 /* Wait a little while for the chip to get its brains in order. */ 715 uether_pause(&sc->sc_ue, hz / 100); 716 717 /* Reinitialize controller to achieve full reset. */ 718 if (sc->sc_flags & AXE_FLAG_178) 719 axe_ax88178_init(sc); 720 else if (sc->sc_flags & AXE_FLAG_772) 721 axe_ax88772_init(sc); 722 else if (sc->sc_flags & AXE_FLAG_772A) 723 axe_ax88772a_init(sc); 724} 725 726static void 727axe_attach_post(struct usb_ether *ue) 728{ 729 struct axe_softc *sc = uether_getsc(ue); 730 731 /* 732 * Load PHY indexes first. Needed by axe_xxx_init(). 733 */ 734 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 735 if (bootverbose) 736 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 737 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 738 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 739 if (sc->sc_phyno == -1) 740 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 741 if (sc->sc_phyno == -1) { 742 device_printf(sc->sc_ue.ue_dev, 743 "no valid PHY address found, assuming PHY address 0\n"); 744 sc->sc_phyno = 0; 745 } 746 747 if (sc->sc_flags & AXE_FLAG_178) { 748 axe_ax88178_init(sc); 749 sc->sc_tx_bufsz = 16 * 1024; 750 } else if (sc->sc_flags & AXE_FLAG_772) { 751 axe_ax88772_init(sc); 752 sc->sc_tx_bufsz = 8 * 1024; 753 } else if (sc->sc_flags & AXE_FLAG_772A) { 754 axe_ax88772a_init(sc); 755 sc->sc_tx_bufsz = 8 * 1024; 756 } 757 758 /* 759 * Get station address. 760 */ 761 if (AXE_IS_178_FAMILY(sc)) 762 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 763 else 764 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 765 766 /* 767 * Fetch IPG values. 768 */ 769 if (sc->sc_flags & AXE_FLAG_772A) { 770 /* Set IPG values. */ 771 sc->sc_ipgs[0] = 0x15; 772 sc->sc_ipgs[1] = 0x16; 773 sc->sc_ipgs[2] = 0x1A; 774 } else 775 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 776} 777 778/* 779 * Probe for a AX88172 chip. 780 */ 781static int 782axe_probe(device_t dev) 783{ 784 struct usb_attach_arg *uaa = device_get_ivars(dev); 785 786 if (uaa->usb_mode != USB_MODE_HOST) 787 return (ENXIO); 788 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 789 return (ENXIO); 790 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 791 return (ENXIO); 792 793 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 794} 795 796/* 797 * Attach the interface. Allocate softc structures, do ifmedia 798 * setup and ethernet/BPF attach. 799 */ 800static int 801axe_attach(device_t dev) 802{ 803 struct usb_attach_arg *uaa = device_get_ivars(dev); 804 struct axe_softc *sc = device_get_softc(dev); 805 struct usb_ether *ue = &sc->sc_ue; 806 uint8_t iface_index; 807 int error; 808 809 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 810 811 device_set_usb_desc(dev); 812 813 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 814 815 iface_index = AXE_IFACE_IDX; 816 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 817 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 818 if (error) { 819 device_printf(dev, "allocating USB transfers failed\n"); 820 goto detach; 821 } 822 823 ue->ue_sc = sc; 824 ue->ue_dev = dev; 825 ue->ue_udev = uaa->device; 826 ue->ue_mtx = &sc->sc_mtx; 827 ue->ue_methods = &axe_ue_methods; 828 829 error = uether_ifattach(ue); 830 if (error) { 831 device_printf(dev, "could not attach interface\n"); 832 goto detach; 833 } 834 return (0); /* success */ 835 836detach: 837 axe_detach(dev); 838 return (ENXIO); /* failure */ 839} 840 841static int 842axe_detach(device_t dev) 843{ 844 struct axe_softc *sc = device_get_softc(dev); 845 struct usb_ether *ue = &sc->sc_ue; 846 847 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 848 uether_ifdetach(ue); 849 mtx_destroy(&sc->sc_mtx); 850 851 return (0); 852} 853 854#if (AXE_BULK_BUF_SIZE >= 0x10000) 855#error "Please update axe_bulk_read_callback()!" 856#endif 857 858static void 859axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 860{ 861 struct axe_softc *sc = usbd_xfer_softc(xfer); 862 struct usb_ether *ue = &sc->sc_ue; 863 struct ifnet *ifp = uether_getifp(ue); 864 struct axe_sframe_hdr hdr; 865 struct usb_page_cache *pc; 866 int err, pos, len; 867 int actlen; 868 869 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 870 871 switch (USB_GET_STATE(xfer)) { 872 case USB_ST_TRANSFERRED: 873 pos = 0; 874 len = 0; 875 err = 0; 876 877 pc = usbd_xfer_get_frame(xfer, 0); 878 if (AXE_IS_178_FAMILY(sc)) { 879 while (pos < actlen) { 880 if ((pos + sizeof(hdr)) > actlen) { 881 /* too little data */ 882 err = EINVAL; 883 break; 884 } 885 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 886 887 if ((hdr.len ^ hdr.ilen) != 0xFFFF) { 888 /* we lost sync */ 889 err = EINVAL; 890 break; 891 } 892 pos += sizeof(hdr); 893 894 len = le16toh(hdr.len); 895 if ((pos + len) > actlen) { 896 /* invalid length */ 897 err = EINVAL; 898 break; 899 } 900 uether_rxbuf(ue, pc, pos, len); 901 902 pos += len + (len % 2); 903 } 904 } else 905 uether_rxbuf(ue, pc, 0, actlen); 906 907 if (err != 0) 908 ifp->if_ierrors++; 909 910 /* FALLTHROUGH */ 911 case USB_ST_SETUP: 912tr_setup: 913 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 914 usbd_transfer_submit(xfer); 915 uether_rxflush(ue); 916 return; 917 918 default: /* Error */ 919 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 920 921 if (error != USB_ERR_CANCELLED) { 922 /* try to clear stall first */ 923 usbd_xfer_set_stall(xfer); 924 goto tr_setup; 925 } 926 return; 927 928 } 929} 930 931#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 932#error "Please update axe_bulk_write_callback()!" 933#endif 934 935static void 936axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 937{ 938 struct axe_softc *sc = usbd_xfer_softc(xfer); 939 struct axe_sframe_hdr hdr; 940 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 941 struct usb_page_cache *pc; 942 struct mbuf *m; 943 int nframes, pos; 944 945 switch (USB_GET_STATE(xfer)) { 946 case USB_ST_TRANSFERRED: 947 DPRINTFN(11, "transfer complete\n"); 948 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 949 /* FALLTHROUGH */ 950 case USB_ST_SETUP: 951tr_setup: 952 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 953 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 954 /* 955 * Don't send anything if there is no link or 956 * controller is busy. 957 */ 958 return; 959 } 960 961 for (nframes = 0; nframes < 16 && 962 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 963 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 964 if (m == NULL) 965 break; 966 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 967 nframes); 968 pos = 0; 969 pc = usbd_xfer_get_frame(xfer, nframes); 970 if (AXE_IS_178_FAMILY(sc)) { 971 hdr.len = htole16(m->m_pkthdr.len); 972 hdr.ilen = ~hdr.len; 973 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 974 pos += sizeof(hdr); 975 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 976 pos += m->m_pkthdr.len; 977 if ((pos % 512) == 0) { 978 hdr.len = 0; 979 hdr.ilen = 0xffff; 980 usbd_copy_in(pc, pos, &hdr, 981 sizeof(hdr)); 982 pos += sizeof(hdr); 983 } 984 } else { 985 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 986 pos += m->m_pkthdr.len; 987 } 988 989 /* 990 * XXX 991 * Update TX packet counter here. This is not 992 * correct way but it seems that there is no way 993 * to know how many packets are sent at the end 994 * of transfer because controller combines 995 * multiple writes into single one if there is 996 * room in TX buffer of controller. 997 */ 998 ifp->if_opackets++; 999 1000 /* 1001 * if there's a BPF listener, bounce a copy 1002 * of this frame to him: 1003 */ 1004 BPF_MTAP(ifp, m); 1005 1006 m_freem(m); 1007 1008 /* Set frame length. */ 1009 usbd_xfer_set_frame_len(xfer, nframes, pos); 1010 } 1011 if (nframes != 0) { 1012 usbd_xfer_set_frames(xfer, nframes); 1013 usbd_transfer_submit(xfer); 1014 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1015 } 1016 return; 1017 /* NOTREACHED */ 1018 default: /* Error */ 1019 DPRINTFN(11, "transfer error, %s\n", 1020 usbd_errstr(error)); 1021 1022 ifp->if_oerrors++; 1023 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1024 1025 if (error != USB_ERR_CANCELLED) { 1026 /* try to clear stall first */ 1027 usbd_xfer_set_stall(xfer); 1028 goto tr_setup; 1029 } 1030 return; 1031 1032 } 1033} 1034 1035static void 1036axe_tick(struct usb_ether *ue) 1037{ 1038 struct axe_softc *sc = uether_getsc(ue); 1039 struct mii_data *mii = GET_MII(sc); 1040 1041 AXE_LOCK_ASSERT(sc, MA_OWNED); 1042 1043 mii_tick(mii); 1044 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1045 axe_miibus_statchg(ue->ue_dev); 1046 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1047 axe_start(ue); 1048 } 1049} 1050 1051static void 1052axe_start(struct usb_ether *ue) 1053{ 1054 struct axe_softc *sc = uether_getsc(ue); 1055 1056 /* 1057 * start the USB transfers, if not already started: 1058 */ 1059 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1060 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1061} 1062 1063static void 1064axe_init(struct usb_ether *ue) 1065{ 1066 struct axe_softc *sc = uether_getsc(ue); 1067 struct ifnet *ifp = uether_getifp(ue); 1068 uint16_t rxmode; 1069 1070 AXE_LOCK_ASSERT(sc, MA_OWNED); 1071 1072 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1073 return; 1074 1075 /* Cancel pending I/O */ 1076 axe_stop(ue); 1077 1078 axe_reset(sc); 1079 1080 /* Set MAC address. */ 1081 if (AXE_IS_178_FAMILY(sc)) 1082 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1083 else 1084 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1085 1086 /* Set transmitter IPG values */ 1087 if (AXE_IS_178_FAMILY(sc)) 1088 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1089 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1090 else { 1091 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1092 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1093 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1094 } 1095 1096 /* Enable receiver, set RX mode */ 1097 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1098 if (AXE_IS_178_FAMILY(sc)) { 1099#if 0 1100 rxmode |= AXE_178_RXCMD_MFB_2048; /* chip default */ 1101#else 1102 /* 1103 * Default Rx buffer size is too small to get 1104 * maximum performance. 1105 */ 1106 rxmode |= AXE_178_RXCMD_MFB_16384; 1107#endif 1108 } else { 1109 rxmode |= AXE_172_RXCMD_UNICAST; 1110 } 1111 1112 /* If we want promiscuous mode, set the allframes bit. */ 1113 if (ifp->if_flags & IFF_PROMISC) 1114 rxmode |= AXE_RXCMD_PROMISC; 1115 1116 if (ifp->if_flags & IFF_BROADCAST) 1117 rxmode |= AXE_RXCMD_BROADCAST; 1118 1119 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1120 1121 /* Load the multicast filter. */ 1122 axe_setmulti(ue); 1123 1124 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1125 1126 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1127 /* Switch to selected media. */ 1128 axe_ifmedia_upd(ifp); 1129 axe_start(ue); 1130} 1131 1132static void 1133axe_setpromisc(struct usb_ether *ue) 1134{ 1135 struct axe_softc *sc = uether_getsc(ue); 1136 struct ifnet *ifp = uether_getifp(ue); 1137 uint16_t rxmode; 1138 1139 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1140 1141 rxmode = le16toh(rxmode); 1142 1143 if (ifp->if_flags & IFF_PROMISC) { 1144 rxmode |= AXE_RXCMD_PROMISC; 1145 } else { 1146 rxmode &= ~AXE_RXCMD_PROMISC; 1147 } 1148 1149 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1150 1151 axe_setmulti(ue); 1152} 1153 1154static void 1155axe_stop(struct usb_ether *ue) 1156{ 1157 struct axe_softc *sc = uether_getsc(ue); 1158 struct ifnet *ifp = uether_getifp(ue); 1159 1160 AXE_LOCK_ASSERT(sc, MA_OWNED); 1161 1162 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1163 sc->sc_flags &= ~AXE_FLAG_LINK; 1164 1165 /* 1166 * stop all the transfers, if not already stopped: 1167 */ 1168 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1169 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1170} 1171