xhci_pci.c revision 276965 
1/*-
2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: stable/10/sys/dev/usb/controller/xhci_pci.c 276965 2015-01-11 11:28:03Z hselasky $");
28
29#include <sys/stdint.h>
30#include <sys/stddef.h>
31#include <sys/param.h>
32#include <sys/queue.h>
33#include <sys/types.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/module.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/condvar.h>
41#include <sys/sysctl.h>
42#include <sys/sx.h>
43#include <sys/unistd.h>
44#include <sys/callout.h>
45#include <sys/malloc.h>
46#include <sys/priv.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50
51#include <dev/usb/usb_core.h>
52#include <dev/usb/usb_busdma.h>
53#include <dev/usb/usb_process.h>
54#include <dev/usb/usb_util.h>
55
56#include <dev/usb/usb_controller.h>
57#include <dev/usb/usb_bus.h>
58#include <dev/usb/usb_pci.h>
59#include <dev/usb/controller/xhci.h>
60#include <dev/usb/controller/xhcireg.h>
61#include "usb_if.h"
62
63static device_probe_t xhci_pci_probe;
64static device_attach_t xhci_pci_attach;
65static device_detach_t xhci_pci_detach;
66static usb_take_controller_t xhci_pci_take_controller;
67
68static device_method_t xhci_device_methods[] = {
69	/* device interface */
70	DEVMETHOD(device_probe, xhci_pci_probe),
71	DEVMETHOD(device_attach, xhci_pci_attach),
72	DEVMETHOD(device_detach, xhci_pci_detach),
73	DEVMETHOD(device_suspend, bus_generic_suspend),
74	DEVMETHOD(device_resume, bus_generic_resume),
75	DEVMETHOD(device_shutdown, bus_generic_shutdown),
76	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
77
78	DEVMETHOD_END
79};
80
81static driver_t xhci_driver = {
82	.name = "xhci",
83	.methods = xhci_device_methods,
84	.size = sizeof(struct xhci_softc),
85};
86
87static devclass_t xhci_devclass;
88
89DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, 0, 0);
90MODULE_DEPEND(xhci, usb, 1, 1, 1);
91
92
93static const char *
94xhci_pci_match(device_t self)
95{
96	uint32_t device_id = pci_get_devid(self);
97
98	switch (device_id) {
99	case 0x01941033:
100		return ("NEC uPD720200 USB 3.0 controller");
101
102	case 0x10421b21:
103		return ("ASMedia ASM1042 USB 3.0 controller");
104
105	case 0x9c318086:
106	case 0x1e318086:
107		return ("Intel Panther Point USB 3.0 controller");
108	case 0x8c318086:
109		return ("Intel Lynx Point USB 3.0 controller");
110	case 0x8cb18086:
111		return ("Intel Wildcat Point USB 3.0 controller");
112
113	default:
114		break;
115	}
116
117	if ((pci_get_class(self) == PCIC_SERIALBUS)
118	    && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
119	    && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
120		return ("XHCI (generic) USB 3.0 controller");
121	}
122	return (NULL);			/* dunno */
123}
124
125static int
126xhci_pci_probe(device_t self)
127{
128	const char *desc = xhci_pci_match(self);
129
130	if (desc) {
131		device_set_desc(self, desc);
132		return (0);
133	} else {
134		return (ENXIO);
135	}
136}
137
138static int xhci_use_msi = 1;
139TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
140
141static void
142xhci_interrupt_poll(void *_sc)
143{
144	struct xhci_softc *sc = _sc;
145	USB_BUS_UNLOCK(&sc->sc_bus);
146	xhci_interrupt(sc);
147	USB_BUS_LOCK(&sc->sc_bus);
148	usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
149}
150
151static int
152xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
153{
154	uint32_t temp;
155	uint32_t usb3_mask;
156	uint32_t usb2_mask;
157
158	temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
159	    pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
160
161	temp |= set;
162	temp &= ~clear;
163
164	/* Don't set bits which the hardware doesn't support */
165	usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
166	usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
167
168	pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
169	pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
170
171	device_printf(self, "Port routing mask set to 0x%08x\n", temp);
172
173	return (0);
174}
175
176static int
177xhci_pci_attach(device_t self)
178{
179	struct xhci_softc *sc = device_get_softc(self);
180	int count, err, rid;
181
182	/* XXX check for 64-bit capability */
183
184	if (xhci_init(sc, self)) {
185		device_printf(self, "Could not initialize softc\n");
186		goto error;
187	}
188
189	pci_enable_busmaster(self);
190
191	rid = PCI_XHCI_CBMEM;
192	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
193	    RF_ACTIVE);
194	if (!sc->sc_io_res) {
195		device_printf(self, "Could not map memory\n");
196		goto error;
197	}
198	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
199	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
200	sc->sc_io_size = rman_get_size(sc->sc_io_res);
201
202	usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
203
204	rid = 0;
205	if (xhci_use_msi) {
206		count = 1;
207		if (pci_alloc_msi(self, &count) == 0) {
208			if (bootverbose)
209				device_printf(self, "MSI enabled\n");
210			rid = 1;
211		}
212	}
213	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
214	    RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
215	if (sc->sc_irq_res == NULL) {
216		pci_release_msi(self);
217		device_printf(self, "Could not allocate IRQ\n");
218		/* goto error; FALLTHROUGH - use polling */
219	}
220	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
221	if (sc->sc_bus.bdev == NULL) {
222		device_printf(self, "Could not add USB device\n");
223		goto error;
224	}
225	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
226
227	sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
228
229	if (sc->sc_irq_res != NULL) {
230		err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
231		    NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
232		if (err != 0) {
233			bus_release_resource(self, SYS_RES_IRQ,
234			    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
235			sc->sc_irq_res = NULL;
236			pci_release_msi(self);
237			device_printf(self, "Could not setup IRQ, err=%d\n", err);
238			sc->sc_intr_hdl = NULL;
239		}
240	}
241	if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
242		if (xhci_use_polling() != 0) {
243			device_printf(self, "Interrupt polling at %dHz\n", hz);
244			USB_BUS_LOCK(&sc->sc_bus);
245			xhci_interrupt_poll(sc);
246			USB_BUS_UNLOCK(&sc->sc_bus);
247		} else
248			goto error;
249	}
250
251	/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
252	switch (pci_get_devid(self)) {
253	case 0x9c318086:	/* Panther Point */
254	case 0x1e318086:	/* Panther Point */
255	case 0x8c318086:	/* Lynx Point */
256	case 0x8cb18086:	/* Wildcat Point */
257		sc->sc_port_route = &xhci_pci_port_route;
258		sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
259		break;
260	default:
261		break;
262	}
263
264	xhci_pci_take_controller(self);
265
266	err = xhci_halt_controller(sc);
267
268	if (err == 0)
269		err = xhci_start_controller(sc);
270
271	if (err == 0)
272		err = device_probe_and_attach(sc->sc_bus.bdev);
273
274	if (err) {
275		device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
276		goto error;
277	}
278	return (0);
279
280error:
281	xhci_pci_detach(self);
282	return (ENXIO);
283}
284
285static int
286xhci_pci_detach(device_t self)
287{
288	struct xhci_softc *sc = device_get_softc(self);
289	device_t bdev;
290
291	if (sc->sc_bus.bdev != NULL) {
292		bdev = sc->sc_bus.bdev;
293		device_detach(bdev);
294		device_delete_child(self, bdev);
295	}
296	/* during module unload there are lots of children leftover */
297	device_delete_children(self);
298
299	if (sc->sc_io_res) {
300		usb_callout_drain(&sc->sc_callout);
301		xhci_halt_controller(sc);
302	}
303
304	pci_disable_busmaster(self);
305
306	if (sc->sc_irq_res && sc->sc_intr_hdl) {
307		bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
308		sc->sc_intr_hdl = NULL;
309	}
310	if (sc->sc_irq_res) {
311		bus_release_resource(self, SYS_RES_IRQ,
312		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
313		sc->sc_irq_res = NULL;
314		pci_release_msi(self);
315	}
316	if (sc->sc_io_res) {
317		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
318		    sc->sc_io_res);
319		sc->sc_io_res = NULL;
320	}
321
322	xhci_uninit(sc);
323
324	return (0);
325}
326
327static int
328xhci_pci_take_controller(device_t self)
329{
330	struct xhci_softc *sc = device_get_softc(self);
331	uint32_t cparams;
332	uint32_t eecp;
333	uint32_t eec;
334	uint16_t to;
335	uint8_t bios_sem;
336
337	cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
338
339	eec = -1;
340
341	/* Synchronise with the BIOS if it owns the controller. */
342	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
343	    eecp += XHCI_XECP_NEXT(eec) << 2) {
344		eec = XREAD4(sc, capa, eecp);
345
346		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
347			continue;
348		bios_sem = XREAD1(sc, capa, eecp +
349		    XHCI_XECP_BIOS_SEM);
350		if (bios_sem == 0)
351			continue;
352		device_printf(sc->sc_bus.bdev, "waiting for BIOS "
353		    "to give up control\n");
354		XWRITE1(sc, capa, eecp +
355		    XHCI_XECP_OS_SEM, 1);
356		to = 500;
357		while (1) {
358			bios_sem = XREAD1(sc, capa, eecp +
359			    XHCI_XECP_BIOS_SEM);
360			if (bios_sem == 0)
361				break;
362
363			if (--to == 0) {
364				device_printf(sc->sc_bus.bdev,
365				    "timed out waiting for BIOS\n");
366				break;
367			}
368			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
369		}
370	}
371	return (0);
372}
373