xhci_pci.c revision 268884 
1/*-
2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: stable/10/sys/dev/usb/controller/xhci_pci.c 268884 2014-07-19 19:56:23Z hselasky $");
28
29#include <sys/stdint.h>
30#include <sys/stddef.h>
31#include <sys/param.h>
32#include <sys/queue.h>
33#include <sys/types.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/module.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/condvar.h>
41#include <sys/sysctl.h>
42#include <sys/sx.h>
43#include <sys/unistd.h>
44#include <sys/callout.h>
45#include <sys/malloc.h>
46#include <sys/priv.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50
51#include <dev/usb/usb_core.h>
52#include <dev/usb/usb_busdma.h>
53#include <dev/usb/usb_process.h>
54#include <dev/usb/usb_util.h>
55
56#include <dev/usb/usb_controller.h>
57#include <dev/usb/usb_bus.h>
58#include <dev/usb/usb_pci.h>
59#include <dev/usb/controller/xhci.h>
60#include <dev/usb/controller/xhcireg.h>
61#include "usb_if.h"
62
63static device_probe_t xhci_pci_probe;
64static device_attach_t xhci_pci_attach;
65static device_detach_t xhci_pci_detach;
66static usb_take_controller_t xhci_pci_take_controller;
67
68static device_method_t xhci_device_methods[] = {
69	/* device interface */
70	DEVMETHOD(device_probe, xhci_pci_probe),
71	DEVMETHOD(device_attach, xhci_pci_attach),
72	DEVMETHOD(device_detach, xhci_pci_detach),
73	DEVMETHOD(device_suspend, bus_generic_suspend),
74	DEVMETHOD(device_resume, bus_generic_resume),
75	DEVMETHOD(device_shutdown, bus_generic_shutdown),
76	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
77
78	DEVMETHOD_END
79};
80
81static driver_t xhci_driver = {
82	.name = "xhci",
83	.methods = xhci_device_methods,
84	.size = sizeof(struct xhci_softc),
85};
86
87static devclass_t xhci_devclass;
88
89DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, 0, 0);
90MODULE_DEPEND(xhci, usb, 1, 1, 1);
91
92
93static const char *
94xhci_pci_match(device_t self)
95{
96	uint32_t device_id = pci_get_devid(self);
97
98	switch (device_id) {
99	case 0x01941033:
100		return ("NEC uPD720200 USB 3.0 controller");
101
102	case 0x10421b21:
103		return ("ASMedia ASM1042 USB 3.0 controller");
104
105	case 0x9c318086:
106	case 0x1e318086:
107		return ("Intel Panther Point USB 3.0 controller");
108	case 0x8c318086:
109		return ("Intel Lynx Point USB 3.0 controller");
110
111	default:
112		break;
113	}
114
115	if ((pci_get_class(self) == PCIC_SERIALBUS)
116	    && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
117	    && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
118		return ("XHCI (generic) USB 3.0 controller");
119	}
120	return (NULL);			/* dunno */
121}
122
123static int
124xhci_pci_probe(device_t self)
125{
126	const char *desc = xhci_pci_match(self);
127
128	if (desc) {
129		device_set_desc(self, desc);
130		return (0);
131	} else {
132		return (ENXIO);
133	}
134}
135
136static int xhci_use_msi = 1;
137TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
138
139static void
140xhci_interrupt_poll(void *_sc)
141{
142	struct xhci_softc *sc = _sc;
143	USB_BUS_UNLOCK(&sc->sc_bus);
144	xhci_interrupt(sc);
145	USB_BUS_LOCK(&sc->sc_bus);
146	usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
147}
148
149static int
150xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
151{
152	uint32_t temp;
153	uint32_t usb3_mask;
154	uint32_t usb2_mask;
155
156	temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
157	    pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
158
159	temp |= set;
160	temp &= ~clear;
161
162	/* Don't set bits which the hardware doesn't support */
163	usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
164	usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
165
166	pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
167	pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
168
169	device_printf(self, "Port routing mask set to 0x%08x\n", temp);
170
171	return (0);
172}
173
174static int
175xhci_pci_attach(device_t self)
176{
177	struct xhci_softc *sc = device_get_softc(self);
178	int count, err, rid;
179
180	/* XXX check for 64-bit capability */
181
182	if (xhci_init(sc, self)) {
183		device_printf(self, "Could not initialize softc\n");
184		goto error;
185	}
186
187	pci_enable_busmaster(self);
188
189	rid = PCI_XHCI_CBMEM;
190	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
191	    RF_ACTIVE);
192	if (!sc->sc_io_res) {
193		device_printf(self, "Could not map memory\n");
194		goto error;
195	}
196	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
197	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
198	sc->sc_io_size = rman_get_size(sc->sc_io_res);
199
200	usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
201
202	sc->sc_irq_rid = 0;
203	if (xhci_use_msi) {
204		count = pci_msi_count(self);
205		if (count >= 1) {
206			count = 1;
207			if (pci_alloc_msi(self, &count) == 0) {
208				if (bootverbose)
209					device_printf(self, "MSI enabled\n");
210				sc->sc_irq_rid = 1;
211			}
212		}
213	}
214	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ,
215	    &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE);
216	if (sc->sc_irq_res == NULL) {
217		device_printf(self, "Could not allocate IRQ\n");
218		/* goto error; FALLTHROUGH - use polling */
219	}
220	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
221	if (sc->sc_bus.bdev == NULL) {
222		device_printf(self, "Could not add USB device\n");
223		goto error;
224	}
225	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
226
227	sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
228
229	if (sc->sc_irq_res != NULL) {
230		err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
231		    NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
232		if (err != 0) {
233			device_printf(self, "Could not setup IRQ, err=%d\n", err);
234			sc->sc_intr_hdl = NULL;
235		}
236	}
237	if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL ||
238	    xhci_use_polling() != 0) {
239		device_printf(self, "Interrupt polling at %dHz\n", hz);
240		USB_BUS_LOCK(&sc->sc_bus);
241		xhci_interrupt_poll(sc);
242		USB_BUS_UNLOCK(&sc->sc_bus);
243	}
244
245	/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
246	switch (pci_get_devid(self)) {
247	case 0x9c318086:	/* Panther Point */
248	case 0x1e318086:	/* Panther Point */
249	case 0x8c318086:	/* Lynx Point */
250		sc->sc_port_route = &xhci_pci_port_route;
251		sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
252		break;
253	default:
254		break;
255	}
256
257	xhci_pci_take_controller(self);
258
259	err = xhci_halt_controller(sc);
260
261	if (err == 0)
262		err = xhci_start_controller(sc);
263
264	if (err == 0)
265		err = device_probe_and_attach(sc->sc_bus.bdev);
266
267	if (err) {
268		device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
269		goto error;
270	}
271	return (0);
272
273error:
274	xhci_pci_detach(self);
275	return (ENXIO);
276}
277
278static int
279xhci_pci_detach(device_t self)
280{
281	struct xhci_softc *sc = device_get_softc(self);
282	device_t bdev;
283
284	if (sc->sc_bus.bdev != NULL) {
285		bdev = sc->sc_bus.bdev;
286		device_detach(bdev);
287		device_delete_child(self, bdev);
288	}
289	/* during module unload there are lots of children leftover */
290	device_delete_children(self);
291
292	if (sc->sc_io_res) {
293		usb_callout_drain(&sc->sc_callout);
294		xhci_halt_controller(sc);
295	}
296
297	pci_disable_busmaster(self);
298
299	if (sc->sc_irq_res && sc->sc_intr_hdl) {
300		bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
301		sc->sc_intr_hdl = NULL;
302	}
303	if (sc->sc_irq_res) {
304		if (sc->sc_irq_rid == 1)
305			pci_release_msi(self);
306		bus_release_resource(self, SYS_RES_IRQ, sc->sc_irq_rid,
307		    sc->sc_irq_res);
308		sc->sc_irq_res = NULL;
309	}
310	if (sc->sc_io_res) {
311		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
312		    sc->sc_io_res);
313		sc->sc_io_res = NULL;
314	}
315
316	xhci_uninit(sc);
317
318	return (0);
319}
320
321static int
322xhci_pci_take_controller(device_t self)
323{
324	struct xhci_softc *sc = device_get_softc(self);
325	uint32_t cparams;
326	uint32_t eecp;
327	uint32_t eec;
328	uint16_t to;
329	uint8_t bios_sem;
330
331	cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
332
333	eec = -1;
334
335	/* Synchronise with the BIOS if it owns the controller. */
336	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
337	    eecp += XHCI_XECP_NEXT(eec) << 2) {
338		eec = XREAD4(sc, capa, eecp);
339
340		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
341			continue;
342		bios_sem = XREAD1(sc, capa, eecp +
343		    XHCI_XECP_BIOS_SEM);
344		if (bios_sem == 0)
345			continue;
346		device_printf(sc->sc_bus.bdev, "waiting for BIOS "
347		    "to give up control\n");
348		XWRITE1(sc, capa, eecp +
349		    XHCI_XECP_OS_SEM, 1);
350		to = 500;
351		while (1) {
352			bios_sem = XREAD1(sc, capa, eecp +
353			    XHCI_XECP_BIOS_SEM);
354			if (bios_sem == 0)
355				break;
356
357			if (--to == 0) {
358				device_printf(sc->sc_bus.bdev,
359				    "timed out waiting for BIOS\n");
360				break;
361			}
362			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
363		}
364	}
365	return (0);
366}
367