dwc_otgreg.h revision 239909
1115013Smarcel/* $FreeBSD: head/sys/dev/usb/controller/dwc_otgreg.h 239909 2012-08-30 16:19:05Z hselasky $ */ 2160157Smarcel 3121642Smarcel/*- 4121642Smarcel * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved. 5121642Smarcel * 6121642Smarcel * Redistribution and use in source and binary forms, with or without 7121642Smarcel * modification, are permitted provided that the following conditions 8121642Smarcel * are met: 9121642Smarcel * 1. Redistributions of source code must retain the above copyright 10121642Smarcel * notice, this list of conditions and the following disclaimer. 11115013Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12121642Smarcel * notice, this list of conditions and the following disclaimer in the 13121642Smarcel * documentation and/or other materials provided with the distribution. 14121642Smarcel * 15121642Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16121642Smarcel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17121642Smarcel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18121642Smarcel * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19121642Smarcel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20121642Smarcel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21121642Smarcel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22121642Smarcel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23121642Smarcel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24121642Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25115013Smarcel * SUCH DAMAGE. 26115013Smarcel */ 27115013Smarcel 28115013Smarcel#ifndef _DWC_OTGREG_H_ 29115013Smarcel#define _DWC_OTGREG_H_ 30115013Smarcel 31115013Smarcel#define DOTG_GOTGCTL 0x0000 32115013Smarcel#define DOTG_GOTGINT 0x0004 33115013Smarcel#define DOTG_GAHBCFG 0x0008 34115013Smarcel#define DOTG_GUSBCFG 0x000C 35115013Smarcel#define DOTG_GRSTCTL 0x0010 36115013Smarcel#define DOTG_GINTSTS 0x0014 37115013Smarcel#define DOTG_GINTMSK 0x0018 38115013Smarcel#define DOTG_GRXSTSRD 0x001C 39115013Smarcel#define DOTG_GRXSTSRH 0x001C 40115013Smarcel#define DOTG_GRXSTSPD 0x0020 41115013Smarcel#define DOTG_GRXSTSPH 0x0020 42115013Smarcel#define DOTG_GRXFSIZ 0x0024 43115013Smarcel#define DOTG_GNPTXFSIZ 0x0028 44115013Smarcel#define DOTG_GNPTXSTS 0x002C 45129059Smarcel#define DOTG_GI2CCTL 0x0030 46115013Smarcel#define DOTG_GPVNDCTL 0x0034 47115013Smarcel#define DOTG_GGPIO 0x0038 48115013Smarcel#define DOTG_GUID 0x003C 49115013Smarcel#define DOTG_GSNPSID 0x0040 50115013Smarcel#define DOTG_GHWCFG1 0x0044 51115013Smarcel#define DOTG_GHWCFG2 0x0048 52115013Smarcel#define DOTG_GHWCFG3 0x004C 53129059Smarcel#define DOTG_GHWCFG4 0x0050 54115013Smarcel#define DOTG_GLPMCFG 0x0054 55115013Smarcel#define DOTG_GPWRDN 0x0058 56115013Smarcel#define DOTG_GDFIFOCFG 0x005C 57115013Smarcel#define DOTG_GADPCTL 0x0060 58115013Smarcel 59115013Smarcel#define DOTG_HPTXFSIZ 0x0100 60115013Smarcel/* start from 0x104, but fifo0 not exists */ 61115013Smarcel#define DOTG_DPTXFSIZ(fifo) (0x0100 + (4*(fifo))) 62115013Smarcel#define DOTG_DIEPTXF(fifo) (0x0100 + (4*(fifo))) 63115013Smarcel 64129059Smarcel#define DOTG_HCFG 0x0400 65115013Smarcel#define DOTG_HFIR 0x0404 66115013Smarcel#define DOTG_HFNUM 0x0408 67115013Smarcel#define DOTG_HPTXSTS 0x0410 68129059Smarcel#define DOTG_HAINT 0x0414 69115013Smarcel#define DOTG_HAINTMSK 0x0418 70129059Smarcel#define DOTG_HPRT 0x0440 71129059Smarcel 72115013Smarcel#define DOTG_HCCHAR(ch) (0x0500 + (32*(ch))) 73115013Smarcel#define DOTG_HCSPLT(ch) (0x0504 + (32*(ch))) 74115013Smarcel#define DOTG_HCINT(ch) (0x0508 + (32*(ch))) 75115013Smarcel#define DOTG_HCINTMSK(ch) (0x050C + (32*(ch))) 76115013Smarcel#define DOTG_HCTSIZ(ch) (0x0510 + (32*(ch))) 77115013Smarcel#define DOTG_HCDMA(ch) (0x0514 + (32*(ch))) 78115013Smarcel#define DOTG_HCDMAI(ch) (0x0514 + (32*(ch))) 79160163Smarcel#define DOTG_HCDMAO(ch) (0x0514 + (32*(ch))) 80115013Smarcel#define DOTG_HCDMAB(ch) (0x051C + (32*(ch))) 81160163Smarcel 82160163Smarcel/* Device Mode */ 83115013Smarcel#define DOTG_DCFG 0x0800 84115013Smarcel#define DOTG_DCTL 0x0804 85115013Smarcel#define DOTG_DSTS 0x0808 86115013Smarcel#define DOTG_DIEPMSK 0x0810 87160157Smarcel#define DOTG_DOEPMSK 0x0814 88115013Smarcel#define DOTG_DAINT 0x0818 89115013Smarcel#define DOTG_DAINTMSK 0x081C 90115013Smarcel#define DOTG_DTKNQR1 0x0820 91115013Smarcel#define DOTG_DTKNQR2 0x0824 92115013Smarcel#define DOTG_DVBUSDIS 0x0828 93115013Smarcel#define DOTG_DVBUSPULSE 0x082C 94115013Smarcel#define DOTG_DTHRCTL 0x0830 95115013Smarcel#define DOTG_DTKNQR4 0x0834 96115013Smarcel#define DOTG_DIEPEMPMSK 0x0834 97115013Smarcel#define DOTG_DEACHINT 0x0838 98115013Smarcel#define DOTG_DEACHINTMSK 0x083C 99115013Smarcel#define DOTG_DIEPEACHINTMSK(ch) (0x0840 + (4*(ch))) 100160157Smarcel#define DOTG_DOEPEACHINTMSK(ch) (0x0880 + (4*(ch))) 101160157Smarcel 102160157Smarcel#define DOTG_DIEPCTL(ep) (0x0900 + (32*(ep))) 103115013Smarcel#define DOTG_DIEPINT(ep) (0x0908 + (32*(ep))) 104115013Smarcel#define DOTG_DIEPTSIZ(ep) (0x0910 + (32*(ep))) 105115013Smarcel#define DOTG_DIEPDMA(ep) (0x0914 + (32*(ep))) 106115013Smarcel#define DOTG_DTXFSTS(ep) (0x0918 + (32*(ep))) 107115013Smarcel#define DOTG_DIEPDMAB(ep) (0x091c + (32*(ep))) 108115013Smarcel 109115013Smarcel#define DOTG_DOEPCTL(ep) (0x0B00 + (32*(ep))) 110115013Smarcel#define DOTG_DOEPFN(ep) (0x0B04 + (32*(ep))) 111115013Smarcel#define DOTG_DOEPINT(ep) (0x0B08 + (32*(ep))) 112115013Smarcel#define DOTG_DOEPTSIZ(ep) (0x0B10 + (32*(ep))) 113115013Smarcel#define DOTG_DOEPDMA(ep) (0x0B14 + (32*(ep))) 114115013Smarcel#define DOTG_DOEPDMAB(ep) (0x0B1c + (32*(ep))) 115115013Smarcel/* End Device Mode */ 116115013Smarcel 117115013Smarcel/* Host Mode 118115013Smarcel#define DOTG_CTL_STATUS 0x0800 119129059Smarcel#define DOTG_DMA0_INB_CHN0 0x0818 120115013Smarcel#define DOTG_DMA0_INB_CHN1 0x0820 121115013Smarcel#define DOTG_DMA0_INB_CHN2 0x0828 122115013Smarcel#define DOTG_DVBUSDIS 0x0828 123115013Smarcel#define DOTG_DVBUSPULSE 0x082c 124115013Smarcel#define DOTG_DMA0_INB_CHN3 0x0830 125115013Smarcel#define DOTG_DMA0_INB_CHN4 0x0838 126129059Smarcel#define DOTG_DMA0_INB_CHN5 0x0840 127115013Smarcel#define DOTG_DMA0_INB_CHN6 0x0848 128115013Smarcel#define DOTG_DMA0_INB_CHN7 0x0850 129115013Smarcel#define DOTG_DMA0_OUTB_CHN0 0x0858 130115013Smarcel#define DOTG_DMA0_OUTB_CHN1 0x0860 131115013Smarcel#define DOTG_DMA0_OUTB_CHN2 0x0868 132115013Smarcel#define DOTG_DMA0_OUTB_CHN3 0x0870 133115013Smarcel#define DOTG_DMA0_OUTB_CHN4 0x0878 134115013Smarcel#define DOTG_DMA0_OUTB_CHN5 0x0880 135115013Smarcel#define DOTG_DMA0_OUTB_CHN6 0x0888 136115013Smarcel#define DOTG_DMA0_OUTB_CHN7 0x0890 137115013Smarcel End Host Mode */ 138115013Smarcel 139115013Smarcel/* Power and clock gating CSR */ 140160157Smarcel 141160157Smarcel#define DOTG_PCGCCTL 0x0E00 142115013Smarcel 143115013Smarcel/* FIFO access registers (PIO-mode) */ 144129059Smarcel 145115013Smarcel#define DOTG_DFIFO(n) (0x1000 + (0x1000 * (n))) 146115013Smarcel 147115013Smarcel#define GOTGCTL_CHIRP_ON (1<<27) 148115013Smarcel#define GOTGCTL_BSESVLD (1<<19) 149115013Smarcel#define GOTGCTL_ASESVLD (1<<18) 150115013Smarcel#define GOTGCTL_DBNCTIME (1<<17) 151115013Smarcel#define GOTGCTL_CONIDSTS (1<<16) 152129059Smarcel#define GOTGCTL_DEVHNPEN (1<<11) 153115013Smarcel#define GOTGCTL_HSTSETHNPEN (1<<10) 154115013Smarcel#define GOTGCTL_HNPREQ (1<<9) 155115013Smarcel#define GOTGCTL_HSTNEGSCS (1<<8) 156115013Smarcel#define GOTGCTL_SESREQ (1<<1) 157115013Smarcel#define GOTGCTL_SESREQSCS (1<<0) 158115013Smarcel 159115013Smarcel#define GOTGCTL_DBNCEDONE (1<<19) 160115013Smarcel#define GOTGCTL_ADEVTOUTCHG (1<<18) 161129059Smarcel#define GOTGCTL_HSTNEGDET (1<<17) 162115013Smarcel#define GOTGCTL_HSTNEGSUCSTSCHG (1<<9) 163115013Smarcel#define GOTGCTL_SESREQSUCSTSCHG (1<<8) 164115013Smarcel#define GOTGCTL_SESENDDET (1<<2) 165115013Smarcel 166115013Smarcel#define GAHBCFG_PTXFEMPLVL (1<<8) 167115013Smarcel#define GAHBCFG_NPTXFEMPLVL (1<<7) 168115013Smarcel#define GAHBCFG_DMAEN (1<<5) 169115013Smarcel#define GAHBCFG_HBSTLEN_MASK 0x0000001e 170160163Smarcel#define GAHBCFG_HBSTLEN_SHIFT 1 171115013Smarcel#define GAHBCFG_GLBLINTRMSK (1<<0) 172115013Smarcel 173160163Smarcel#define GUSBCFG_CORRUPTTXPACKET (1<<31) 174160163Smarcel#define GUSBCFG_FORCEDEVMODE (1<<30) 175115013Smarcel#define GUSBCFG_FORCEHOSTMODE (1<<29) 176160163Smarcel#define GUSBCFG_NO_PULLUP (1<<27) 177115013Smarcel#define GUSBCFG_IC_USB_CAP (1<<26) 178115013Smarcel#define GUSBCFG_TERMSELDLPULSE (1<<22) 179115013Smarcel#define GUSBCFG_ULPIEXTVBUSINDICATOR (1<<21) 180115013Smarcel#define GUSBCFG_ULPIEXTVBUSDRV (1<<20) 181115013Smarcel#define GUSBCFG_ULPICLKSUSM (1<<19) 182115013Smarcel#define GUSBCFG_ULPIAUTORES (1<<18) 183115013Smarcel#define GUSBCFG_ULPIFSLS (1<<17) 184115013Smarcel#define GUSBCFG_OTGI2CSEL (1<<16) 185115013Smarcel#define GUSBCFG_PHYLPWRCLKSEL (1<<15) 186115013Smarcel#define GUSBCFG_USBTRDTIM_MASK 0x00003c00 187115013Smarcel#define GUSBCFG_USBTRDTIM_SHIFT 10 188115013Smarcel#define GUSBCFG_TRD_TIM_SET(x) (((x) & 15) << 10) 189115013Smarcel#define GUSBCFG_HNPCAP (1<<9) 190115013Smarcel#define GUSBCFG_SRPCAP (1<<8) 191115013Smarcel#define GUSBCFG_DDRSEL (1<<7) 192115013Smarcel#define GUSBCFG_PHYSEL (1<<6) 193115013Smarcel#define GUSBCFG_FSINTF (1<<5) 194160163Smarcel#define GUSBCFG_ULPI_UTMI_SEL (1<<4) 195115013Smarcel#define GUSBCFG_PHYIF (1<<3) 196115013Smarcel#define GUSBCFG_TOUTCAL_MASK 0x00000007 197115013Smarcel#define GUSBCFG_TOUTCAL_SHIFT 0 198115013Smarcel 199160157Smarcel#define GRSTCTL_AHBIDLE (1<<31) 200160157Smarcel#define GRSTCTL_DMAREQ (1<<30) 201160157Smarcel#define GRSTCTL_TXFNUM_MASK 0x000007c0 202160157Smarcel#define GRSTCTL_TXFNUM_SHIFT 6 203115013Smarcel#define GRSTCTL_TXFIFO(n) (((n) & 31) << 6) 204115013Smarcel#define GRSTCTL_TXFFLSH (1<<5) 205115013Smarcel#define GRSTCTL_RXFFLSH (1<<4) 206115013Smarcel#define GRSTCTL_INTKNQFLSH (1<<3) 207115013Smarcel#define GRSTCTL_FRMCNTRRST (1<<2) 208115013Smarcel#define GRSTCTL_HSFTRST (1<<1) 209115013Smarcel#define GRSTCTL_CSFTRST (1<<0) 210115013Smarcel 211160157Smarcel#define GINTSTS_WKUPINT (1<<31) 212115013Smarcel#define GINTSTS_SESSREQINT (1<<30) 213160157Smarcel#define GINTSTS_DISCONNINT (1<<29) 214115013Smarcel#define GINTSTS_CONIDSTSCHNG (1<<28) 215115013Smarcel#define GINTSTS_LPM (1<<27) 216115013Smarcel#define GINTSTS_PTXFEMP (1<<26) 217129059Smarcel#define GINTSTS_HCHINT (1<<25) 218115013Smarcel#define GINTSTS_PRTINT (1<<24) 219115013Smarcel#define GINTSTS_RESETDET (1<<23) 220115013Smarcel#define GINTSTS_FETSUSP (1<<22) 221115013Smarcel#define GINTSTS_INCOMPLP (1<<21) 222115013Smarcel#define GINTSTS_INCOMPISOIN (1<<20) 223115013Smarcel#define GINTSTS_OEPINT (1<<19) 224115013Smarcel#define GINTSTS_IEPINT (1<<18) 225129059Smarcel#define GINTSTS_EPMIS (1<<17) 226115013Smarcel#define GINTSTS_RESTORE_DONE (1<<16) 227115013Smarcel#define GINTSTS_EOPF (1<<15) 228115013Smarcel#define GINTSTS_ISOOUTDROP (1<<14) 229115013Smarcel#define GINTSTS_ENUMDONE (1<<13) 230115013Smarcel#define GINTSTS_USBRST (1<<12) 231115013Smarcel#define GINTSTS_USBSUSP (1<<11) 232115013Smarcel#define GINTSTS_ERLYSUSP (1<<10) 233115013Smarcel#define GINTSTS_I2CINT (1<<9) 234129059Smarcel#define GINTSTS_ULPICKINT (1<<8) 235115013Smarcel#define GINTSTS_GOUTNAKEFF (1<<7) 236115013Smarcel#define GINTSTS_GINNAKEFF (1<<6) 237115013Smarcel#define GINTSTS_NPTXFEMP (1<<5) 238115013Smarcel#define GINTSTS_RXFLVL (1<<4) 239115013Smarcel#define GINTSTS_SOF (1<<3) 240115013Smarcel#define GINTSTS_OTGINT (1<<2) 241160163Smarcel#define GINTSTS_MODEMIS (1<<1) 242115013Smarcel#define GINTSTS_CURMOD (1<<0) 243115013Smarcel 244115013Smarcel#define GINTMSK_WKUPINTMSK (1<<31) 245115013Smarcel#define GINTMSK_SESSREQINTMSK (1<<30) 246115013Smarcel#define GINTMSK_DISCONNINTMSK (1<<29) 247115013Smarcel#define GINTMSK_CONIDSTSCHNGMSK (1<<28) 248115013Smarcel#define GINTMSK_PTXFEMPMSK (1<<26) 249115013Smarcel#define GINTMSK_HCHINTMSK (1<<25) 250115013Smarcel#define GINTMSK_PRTINTMSK (1<<24) 251115013Smarcel#define GINTMSK_FETSUSPMSK (1<<22) 252115013Smarcel#define GINTMSK_INCOMPLPMSK (1<<21) 253115013Smarcel#define GINTMSK_INCOMPISOINMSK (1<<20) 254115013Smarcel#define GINTMSK_OEPINTMSK (1<<19) 255115013Smarcel#define GINTMSK_IEPINTMSK (1<<18) 256115013Smarcel#define GINTMSK_EPMISMSK (1<<17) 257115013Smarcel#define GINTMSK_EOPFMSK (1<<15) 258115013Smarcel#define GINTMSK_ISOOUTDROPMSK (1<<14) 259115013Smarcel#define GINTMSK_ENUMDONEMSK (1<<13) 260115013Smarcel#define GINTMSK_USBRSTMSK (1<<12) 261115013Smarcel#define GINTMSK_USBSUSPMSK (1<<11) 262115013Smarcel#define GINTMSK_ERLYSUSPMSK (1<<10) 263115013Smarcel#define GINTMSK_I2CINTMSK (1<<9) 264115013Smarcel#define GINTMSK_ULPICKINTMSK (1<<8) 265115013Smarcel#define GINTMSK_GOUTNAKEFFMSK (1<<7) 266115013Smarcel#define GINTMSK_GINNAKEFFMSK (1<<6) 267115013Smarcel#define GINTMSK_NPTXFEMPMSK (1<<5) 268160157Smarcel#define GINTMSK_RXFLVLMSK (1<<4) 269115013Smarcel#define GINTMSK_SOFMSK (1<<3) 270115013Smarcel#define GINTMSK_OTGINTMSK (1<<2) 271115013Smarcel#define GINTMSK_MODEMISMSK (1<<1) 272115013Smarcel#define GINTMSK_CURMODMSK (1<<0) 273115013Smarcel 274#define GRXSTSRH_PKTSTS_MASK 0x001e0000 275#define GRXSTSRH_PKTSTS_SHIFT 17 276#define GRXSTSRH_DPID_MASK 0x00018000 277#define GRXSTSRH_DPID_SHIFT 15 278#define GRXSTSRH_BCNT_MASK 0x00007ff0 279#define GRXSTSRH_BCNT_SHIFT 4 280#define GRXSTSRH_CHNUM_MASK 0x0000000f 281#define GRXSTSRH_CHNUM_SHIFT 0 282 283#define GRXSTSRD_FN_MASK 0x01e00000 284#define GRXSTSRD_FN_GET(x) (((x) >> 21) & 15) 285#define GRXSTSRD_FN_SHIFT 21 286#define GRXSTSRD_PKTSTS_MASK 0x001e0000 287#define GRXSTSRD_PKTSTS_SHIFT 17 288#define GRXSTSRH_IN_DATA (2<<17) 289#define GRXSTSRH_IN_COMPLETE (3<<17) 290#define GRXSTSRH_DT_ERROR (5<<17) 291#define GRXSTSRH_HALTED (7<<17) 292#define GRXSTSRD_GLOB_OUT_NAK (1<<17) 293#define GRXSTSRD_OUT_DATA (2<<17) 294#define GRXSTSRD_OUT_COMPLETE (3<<17) 295#define GRXSTSRD_STP_COMPLETE (4<<17) 296#define GRXSTSRD_STP_DATA (6<<17) 297#define GRXSTSRD_DPID_MASK 0x00018000 298#define GRXSTSRD_DPID_SHIFT 15 299#define GRXSTSRD_DPID_DATA0 (0<<15) 300#define GRXSTSRD_DPID_DATA1 (2<<15) 301#define GRXSTSRD_DPID_DATA2 (1<<15) 302#define GRXSTSRD_PID_MDATA (3<<15) 303#define GRXSTSRD_BCNT_MASK 0x00007ff0 304#define GRXSTSRD_BCNT_GET(x) (((x) >> 4) & 0x7FF) 305#define GRXSTSRD_BCNT_SHIFT 4 306#define GRXSTSRD_CHNUM_MASK 0x0000000f 307#define GRXSTSRD_CHNUM_GET(x) ((x) & 15) 308#define GRXSTSRD_CHNUM_SHIFT 0 309 310#define GRXFSIZ_RXFDEP_MASK 0x0000ffff 311#define GRXFSIZ_RXFDEP_SHIFT 0 312 313#define GNPTXFSIZ_NPTXFDEP_MASK 0xffff0000 314#define GNPTXFSIZ_NPTXFDEP_SHIFT 0 315#define GNPTXFSIZ_NPTXFSTADDR_MASK 0x0000ffff 316#define GNPTXFSIZ_NPTXFSTADDR_SHIFT 16 317 318#define GNPTXSTS_NPTXQTOP_SHIFT 24 319#define GNPTXSTS_NPTXQTOP_MASK 0x7f000000 320#define GNPTXSTS_NPTXQSPCAVAIL_SHIFT 16 321#define GNPTXSTS_NPTXQSPCAVAIL_MASK 0x00ff0000 322#define GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0 323#define GNPTXSTS_NPTXFSPCAVAIL_MASK 0x0000ffff 324 325#define GI2CCTL_BSYDNE_SC (1<<31) 326#define GI2CCTL_RW (1<<30) 327#define GI2CCTL_I2CDATSE0 (1<<28) 328#define GI2CCTL_I2CDEVADR_SHIFT 26 329#define GI2CCTL_I2CDEVADR_MASK 0x0c000000 330#define GI2CCTL_I2CSUSPCTL (1<<25) 331#define GI2CCTL_ACK (1<<24) 332#define GI2CCTL_I2CEN (1<<23) 333#define GI2CCTL_ADDR_SHIFT 16 334#define GI2CCTL_ADDR_MASK 0x007f0000 335#define GI2CCTL_REGADDR_SHIFT 8 336#define GI2CCTL_REGADDR_MASK 0x0000ff00 337#define GI2CCTL_RWDATA_SHIFT 0 338#define GI2CCTL_RWDATA_MASK 0x000000ff 339 340#define GPVNDCTL_DISULPIDRVR (1<<31) 341#define GPVNDCTL_VSTSDONE (1<<27) 342#define GPVNDCTL_VSTSBSY (1<<26) 343#define GPVNDCTL_NEWREGREQ (1<<25) 344#define GPVNDCTL_REGWR (1<<22) 345#define GPVNDCTL_REGADDR_SHIFT 16 346#define GPVNDCTL_REGADDR_MASK 0x003f0000 347#define GPVNDCTL_VCTRL_SHIFT 8 348#define GPVNDCTL_VCTRL_MASK 0x0000ff00 349#define GPVNDCTL_REGDATA_SHIFT 0 350#define GPVNDCTL_REGDATA_MASK 0x000000ff 351 352#define GGPIO_GPO_SHIFT 16 353#define GGPIO_GPO_MASK 0xffff0000 354#define GGPIO_GPI_SHIFT 0 355#define GGPIO_GPI_MASK 0x0000ffff 356 357#define GHWCFG1_GET_DIR(x, n) (((x) >> (2 * (n))) & 3) 358#define GHWCFG1_BIDIR 0 359#define GHWCFG1_IN 1 360#define GHWCFG1_OUT 2 361 362#define GHWCFG2_TKNQDEPTH_SHIFT 26 363#define GHWCFG2_TKNQDEPTH_MASK 0x7c000000 364#define GHWCFG2_PTXQDEPTH_SHIFT 24 365#define GHWCFG2_PTXQDEPTH_MASK 0x03000000 366#define GHWCFG2_NPTXQDEPTH_SHIFT 22 367#define GHWCFG2_NPTXQDEPTH_MASK 0x00c00000 368#define GHWCFG2_MPI (1<<20) 369#define GHWCFG2_DYNFIFOSIZING (1<<19) 370#define GHWCFG2_PERIOSUPPORT (1<<18) 371#define GHWCFG2_NUMHSTCHNL_SHIFT 14 372#define GHWCFG2_NUMHSTCHNL_MASK 0x0003c000 373#define GHWCFG2_NUMHSTCHNL_GET(x) ((((x) >> 14) & 15) + 1) 374#define GHWCFG2_NUMDEVEPS_SHIFT 10 375#define GHWCFG2_NUMDEVEPS_MASK 0x00003c00 376#define GHWCFG2_NUMDEVEPS_GET(x) ((((x) >> 10) & 15) + 1) 377#define GHWCFG2_FSPHYTYPE_SHIFT 8 378#define GHWCFG2_FSPHYTYPE_MASK 0x00000300 379#define GHWCFG2_HSPHYTYPE_SHIFT 6 380#define GHWCFG2_HSPHYTYPE_MASK 0x000000c0 381#define GHWCFG2_SINGPNT (1<<5) 382#define GHWCFG2_OTGARCH_SHIFT 3 383#define GHWCFG2_OTGARCH_MASK 0x00000018 384#define GHWCFG2_OTGMODE_SHIFT 0 385#define GHWCFG2_OTGMODE_MASK 0x00000007 386 387#define GHWCFG3_DFIFODEPTH_SHIFT 16 388#define GHWCFG3_DFIFODEPTH_MASK 0xffff0000 389#define GHWCFG3_DFIFODEPTH_GET(x) ((x) >> 16) 390#define GHWCFG3_RSTTYPE (1<<11) 391#define GHWCFG3_OPTFEATURE (1<<10) 392#define GHWCFG3_VNDCTLSUPT (1<<9) 393#define GHWCFG3_I2CINTSEL (1<<8) 394#define GHWCFG3_OTGEN (1<<7) 395#define GHWCFG3_PKTSIZEWIDTH_SHIFT 4 396#define GHWCFG3_PKTSIZEWIDTH_MASK 0x00000070 397#define GHWCFG3_PKTSIZE_GET(x) (0x10<<(((x) >> 4) & 7)) 398#define GHWCFG3_XFERSIZEWIDTH_SHIFT 0 399#define GHWCFG3_XFERSIZEWIDTH_MASK 0x0000000f 400#define GHWCFG3_XFRRSIZE_GET(x) (0x400<<(((x) >> 0) & 15)) 401 402#define GHWCFG4_NUM_IN_EP_GET(x) ((((x) >> 26) & 15) + 1) 403#define GHWCFG4_SESSENDFLTR (1<<24) 404#define GHWCFG4_BVALIDFLTR (1<<23) 405#define GHWCFG4_AVALIDFLTR (1<<22) 406#define GHWCFG4_VBUSVALIDFLTR (1<<21) 407#define GHWCFG4_IDDGFLTR (1<<20) 408#define GHWCFG4_NUMCTLEPS_SHIFT 16 409#define GHWCFG4_NUMCTLEPS_MASK 0x000f0000 410#define GHWCFG4_NUMCTLEPS_GET(x) (((x) >> 16) & 15) 411#define GHWCFG4_PHYDATAWIDTH_SHIFT 14 412#define GHWCFG4_PHYDATAWIDTH_MASK 0x0000c000 413#define GHWCFG4_AHBFREQ (1<<5) 414#define GHWCFG4_ENABLEPWROPT (1<<4) 415#define GHWCFG4_NUMDEVPERIOEPS_SHIFT 0 416#define GHWCFG4_NUMDEVPERIOEPS_MASK 0x0000000f 417#define GHWCFG4_NUMDEVPERIOEPS_GET(x) (((x) >> 0) & 15) 418 419#define GLPMCFG_HSIC_CONN (1<<30) 420 421#define GPWRDN_BVALID (1<<22) 422#define GPWRDN_IDDIG (1<<21) 423#define GPWRDN_CONNDET_INT (1<<14) 424#define GPWRDN_CONNDET (1<<13) 425#define GPWRDN_DISCONN_INT (1<<12) 426#define GPWRDN_DISCONN (1<<11) 427#define GPWRDN_RESETDET_INT (1<<10) 428#define GPWRDN_RESETDET (1<<9) 429#define GPWRDN_LINESTATE_INT (1<<8) 430#define GPWRDN_LINESTATE (1<<7) 431#define GPWRDN_DISABLE_VBUS (1<<6) 432#define GPWRDN_POWER_DOWN (1<<5) 433#define GPWRDN_POWER_DOWN_RST (1<<4) 434#define GPWRDN_POWER_DOWN_CLAMP (1<<3) 435#define GPWRDN_RESTORE (1<<2) 436#define GPWRDN_PMU_ACTIVE (1<<1) 437#define GPWRDN_PMU_IRQ_SEL (1<<0) 438 439#define HPTXFSIZ_PTXFSIZE_SHIFT 16 440#define HPTXFSIZ_PTXFSIZE_MASK 0xffff0000 441#define HPTXFSIZ_PTXFSTADDR_SHIFT 0 442#define HPTXFSIZ_PTXFSTADDR_MASK 0x0000ffff 443 444#define DPTXFSIZN_DPTXFSIZE_SHIFT 16 445#define DPTXFSIZN_DPTXFSIZE_MASK 0xffff0000 446#define DPTXFSIZN_PTXFSTADDR_SHIFT 0 447#define DPTXFSIZN_PTXFSTADDR_MASK 0x0000ffff 448 449#define DIEPTXFN_INEPNTXFDEP_SHIFT 16 450#define DIEPTXFN_INEPNTXFDEP_MASK 0xffff0000 451#define DIEPTXFN_INEPNTXFSTADDR_SHIFT 0 452#define DIEPTXFN_INEPNTXFSTADDR_MASK 0x0000ffff 453 454#define HCFG_FSLSSUPP (1<<2) 455#define HCFG_FSLSPCLKSEL_SHIFT 0 456#define HCFG_FSLSPCLKSEL_MASK 0x00000003 457 458#define HFIR_FRINT_SHIFT 0 459#define HFIR_FRINT_MASK 0x0000ffff 460 461#define HFNUM_FRREM_SHIFT 16 462#define HFNUM_FRREM_MASK 0xffff0000 463#define HFNUM_FRNUM_SHIFT 0 464#define HFNUM_FRNUM_MASK 0x0000ffff 465 466#define HPTXSTS_PTXQTOP_SHIFT 24 467#define HPTXSTS_PTXQTOP_MASK 0xff000000 468#define HPTXSTS_PTXQSPCAVAIL_SHIFT 16 469#define HPTXSTS_PTXQSPCAVAIL_MASK 0x00ff0000 470#define HPTXSTS_PTXFSPCAVAIL_SHIFT 0 471#define HPTXSTS_PTXFSPCAVAIL_MASK 0x0000ffff 472 473#define HAINT_HAINT_SHIFT 0 474#define HAINT_HAINT_MASK 0x0000ffff 475#define HAINTMSK_HAINTMSK_SHIFT 0 476#define HAINTMSK_HAINTMSK_MASK 0x0000ffff 477 478#define HPRT_PRTSPD_SHIFT 17 479#define HPRT_PRTSPD_MASK 0x00060000 480#define HPRT_PRTSPD_HIGH 0 481#define HPRT_PRTSPD_FULL 1 482#define HPRT_PRTSPD_LOW 2 483#define HPRT_PRTSPD_MASK 0x00060000 484#define HPRT_PRTTSTCTL_SHIFT 13 485#define HPRT_PRTTSTCTL_MASK 0x0001e000 486#define HPRT_PRTPWR (1<<12) 487#define HPRT_PRTLNSTS_SHIFT 10 488#define HPRT_PRTLNSTS_MASK 0x00000c00 489#define HPRT_PRTRST (1<<8) 490#define HPRT_PRTSUSP (1<<7) 491#define HPRT_PRTRES (1<<6) 492#define HPRT_PRTOVRCURRCHNG (1<<5) 493#define HPRT_PRTOVRCURRACT (1<<4) 494#define HPRT_PRTENCHNG (1<<3) 495#define HPRT_PRTENA (1<<2) 496#define HPRT_PRTCONNDET (1<<1) 497#define HPRT_PRTCONNSTS (1<<0) 498 499#define HCCHAR_CHENA (1<<31) 500#define HCCHAR_CHDIS (1<<30) 501#define HCCHAR_ODDFRM (1<<29) 502#define HCCHAR_DEVADDR_SHIFT 22 503#define HCCHAR_DEVADDR_MASK 0x1fc00000 504#define HCCHAR_MC_EC_SHIFT 20 505#define HCCHAR_MC_EC_MASK 0x00300000 506#define HCCHAR_EC_SHIFT 20 507#define HCCHAR_EC_MASK 0x00300000 508#define HCCHAR_EPTYPE_SHIFT 18 509#define HCCHAR_EPTYPE_MASK 0x000c0000 510#define HCCHAR_LSPDDEV (1<<17) 511#define HCCHAR_EPDIR (1<<15) 512#define HCCHAR_EPDIR_IN (1<<15) 513#define HCCHAR_EPDIR_OUT 0 514#define HCCHAR_EPNUM_SHIFT 11 515#define HCCHAR_EPNUM_MASK 0x00007800 516#define HCCHAR_MPS_SHIFT 0 517#define HCCHAR_MPS_MASK 0x000007ff 518 519#define HCSPLT_SPLTENA (1<<31) 520#define HCSPLT_COMPSPLT (1<<16) 521#define HCSPLT_XACTPOS_SHIFT 14 522#define HCSPLT_XACTPOS_MASK 0x0000c000 523#define HCSPLT_HUBADDR_SHIFT 7 524#define HCSPLT_HUBADDR_MASK 0x00003f80 525#define HCSPLT_PRTADDR_SHIFT 0 526#define HCSPLT_PRTADDR_MASK 0x0000007f 527 528#define HCINT_DATATGLERR (1<<10) 529#define HCINT_FRMOVRUN (1<<9) 530#define HCINT_BBLERR (1<<8) 531#define HCINT_XACTERR (1<<7) 532#define HCINT_NYET (1<<6) 533#define HCINT_ACK (1<<5) 534#define HCINT_NAK (1<<4) 535#define HCINT_STALL (1<<3) 536#define HCINT_AHBERR (1<<2) 537#define HCINT_CHHLTD (1<<1) 538#define HCINT_XFERCOMPL (1<<0) 539 540#define HCINTMSK_DATATGLERRMSK (1<<10) 541#define HCINTMSK_FRMOVRUNMSK (1<<9) 542#define HCINTMSK_BBLERRMSK (1<<8) 543#define HCINTMSK_XACTERRMSK (1<<7) 544#define HCINTMSK_NYETMSK (1<<6) 545#define HCINTMSK_ACKMSK (1<<5) 546#define HCINTMSK_NAKMSK (1<<4) 547#define HCINTMSK_STALLMSK (1<<3) 548#define HCINTMSK_AHBERRMSK (1<<2) 549#define HCINTMSK_CHHLTDMSK (1<<1) 550#define HCINTMSK_XFERCOMPLMSK (1<<0) 551 552#define HCTSIZ_DOPNG (1<<31) 553#define HCTSIZ_PID_SHIFT 29 554#define HCTSIZ_PID_MASK 0x60000000 555#define HCTSIZ_PID_DATA0 0 556#define HCTSIZ_PID_DATA2 1 557#define HCTSIZ_PID_DATA1 2 558#define HCTSIZ_PID_MDATA 3 559#define HCTSIZ_PID_SETUP 3 560#define HCTSIZ_PKTCNT_SHIFT 19 561#define HCTSIZ_PKTCNT_MASK 0x1ff80000 562#define HCTSIZ_XFERSIZE_SHIFT 0 563#define HCTSIZ_XFERSIZE_MASK 0x0007ffff 564 565#define DCFG_EPMISCNT_SHIFT 18 566#define DCFG_EPMISCNT_MASK 0x007c0000 567#define DCFG_PERFRINT_SHIFT 11 568#define DCFG_PERFRINT_MASK 0x00001800 569#define DCFG_DEVADDR_SHIFT 4 570#define DCFG_DEVADDR_MASK 0x000007f0 571#define DCFG_DEVADDR_SET(x) (((x) & 0x7F) << 4) 572#define DCFG_NZSTSOUTHSHK (1<<2) 573#define DCFG_DEVSPD_SHIFT 0 574#define DCFG_DEVSPD_MASK 0x00000003 575#define DCFG_DEVSPD_SET(x) ((x) & 0x3) 576#define DCFG_DEVSPD_HI 0 577#define DCFG_DEVSPD_FULL20 1 578#define DCFG_DEVSPD_FULL10 3 579 580#define DCTL_PWRONPRGDONE (1<<11) 581#define DCTL_CGOUTNAK (1<<10) 582#define DCTL_SGOUTNAK (1<<9) 583#define DCTL_CGNPINNAK (1<<8) 584#define DCTL_SGNPINNAK (1<<7) 585#define DCTL_TSTCTL_SHIFT 4 586#define DCTL_TSTCTL_MASK 0x00000070 587#define DCTL_GOUTNAKSTS (1<<3) 588#define DCTL_GNPINNAKSTS (1<<2) 589#define DCTL_SFTDISCON (1<<1) 590#define DCTL_RMTWKUPSIG (1<<0) 591 592#define DSTS_SOFFN_SHIFT 8 593#define DSTS_SOFFN_MASK 0x003fff00 594#define DSTS_SOFFN_GET(x) (((x) >> 8) & 0x3FFF) 595#define DSTS_ERRTICERR (1<<3) 596#define DSTS_ENUMSPD_SHIFT 1 597#define DSTS_ENUMSPD_MASK 0x00000006 598#define DSTS_ENUMSPD_GET(x) (((x) >> 1) & 3) 599#define DSTS_ENUMSPD_HI 0 600#define DSTS_ENUMSPD_FULL20 1 601#define DSTS_ENUMSPD_LOW10 2 602#define DSTS_ENUMSPD_FULL10 3 603#define DSTS_SUSPSTS (1<<0) 604 605#define DIEPMSK_TXFIFOUNDRNMSK (1<<8) 606#define DIEPMSK_INEPNAKEFFMSK (1<<6) 607#define DIEPMSK_INTKNEPMISMSK (1<<5) 608#define DIEPMSK_INTKNTXFEMPMSK (1<<4) 609#define DIEPMSK_FIFOEMPTY (1<<4) 610#define DIEPMSK_TIMEOUTMSK (1<<3) 611#define DIEPMSK_AHBERRMSK (1<<2) 612#define DIEPMSK_EPDISBLDMSK (1<<1) 613#define DIEPMSK_XFERCOMPLMSK (1<<0) 614 615#define DOEPMSK_OUTPKTERRMSK (1<<8) 616#define DOEPMSK_BACK2BACKSETUP (1<<6) 617#define DOEPMSK_OUTTKNEPDISMSK (1<<4) 618#define DOEPMSK_FIFOEMPTY (1<<4) 619#define DOEPMSK_SETUPMSK (1<<3) 620#define DOEPMSK_AHBERRMSK (1<<2) 621#define DOEPMSK_EPDISBLDMSK (1<<1) 622#define DOEPMSK_XFERCOMPLMSK (1<<0) 623 624#define DIEPINT_TXFIFOUNDRN (1<<8) 625#define DIEPINT_INEPNAKEFF (1<<6) 626#define DIEPINT_INTKNEPMIS (1<<5) 627#define DIEPINT_INTKNTXFEMP (1<<4) 628#define DIEPINT_TIMEOUT (1<<3) 629#define DIEPINT_AHBERR (1<<2) 630#define DIEPINT_EPDISBLD (1<<1) 631#define DIEPINT_XFERCOMPL (1<<0) 632 633#define DOEPINT_OUTPKTERR (1<<8) 634#define DOEPINT_BACK2BACKSETUP (1<<6) 635#define DOEPINT_OUTTKNEPDIS (1<<4) 636#define DOEPINT_SETUP (1<<3) 637#define DOEPINT_AHBERR (1<<2) 638#define DOEPINT_EPDISBLD (1<<1) 639#define DOEPINT_XFERCOMPL (1<<0) 640 641#define DAINT_INEPINT_MASK 0xffff0000 642#define DAINT_INEPINT_SHIFT 0 643#define DAINT_OUTEPINT_MASK 0x0000ffff 644#define DAINT_OUTEPINT_SHIFT 16 645 646#define DAINTMSK_INEPINT_MASK 0xffff0000 647#define DAINTMSK_INEPINT_SHIFT 0 648#define DAINTMSK_OUTEPINT_MASK 0x0000ffff 649#define DAINTMSK_OUTEPINT_SHIFT 16 650 651#define DTKNQR1_EPTKN_SHIFT 8 652#define DTKNQR1_EPTKN_MASK 0xffffff00 653#define DTKNQR1_WRAPBIT (1<<7) 654#define DTKNQR1_INTKNWPTR_SHIFT 0 655#define DTKNQR1_INTKNWPTR_MASK 0x0000001f 656 657#define DVBUSDIS_DVBUSDIS_SHIFT 0 658#define DVBUSDIS_DVBUSDIS_MASK 0x0000ffff 659 660#define DVBUSPULSE_DVBUSPULSE_SHIFT 0 661#define DVBUSPULSE_DVBUSPULSE_MASK 0x00000fff 662 663#define DTHRCTL_ARBPRKEN (1<<27) 664#define DTHRCTL_RXTHRLEN_SHIFT 17 665#define DTHRCTL_RXTHRLEN_MASK 0x03fe0000 666#define DTHRCTL_RXTHREN (1<<16) 667#define DTHRCTL_TXTHRLEN_SHIFT 2 668#define DTHRCTL_TXTHRLEN_MASK 0x000007fc 669#define DTHRCTL_ISOTHREN (1<<1) 670#define DTHRCTL_NONISOTHREN (1<<0) 671 672#define DIEPEMPMSK_INEPTXFEMPMSK_SHIFT 0 673#define DIEPEMPMSK_INEPTXFEMPMSK_MASK 0x0000ffff 674 675#define DIEPCTL_EPENA (1<<31) 676#define DIEPCTL_EPDIS (1<<30) 677#define DIEPCTL_SETD1PID (1<<29) 678#define DIEPCTL_SETD0PID (1<<28) 679#define DIEPCTL_SNAK (1<<27) 680#define DIEPCTL_CNAK (1<<26) 681#define DIEPCTL_TXFNUM_SHIFT 22 682#define DIEPCTL_TXFNUM_MASK 0x03c00000 683#define DIEPCTL_TXFNUM_SET(n) (((n) & 15) << 22) 684#define DIEPCTL_STALL (1<<21) 685#define DIEPCTL_EPTYPE_SHIFT 18 686#define DIEPCTL_EPTYPE_MASK 0x000c0000 687#define DIEPCTL_EPTYPE_SET(n) (((n) & 3) << 18) 688#define DIEPCTL_EPTYPE_CONTROL 0 689#define DIEPCTL_EPTYPE_ISOC 1 690#define DIEPCTL_EPTYPE_BULK 2 691#define DIEPCTL_EPTYPE_INTERRUPT 3 692#define DIEPCTL_NAKSTS (1<<17) 693#define DIEPCTL_USBACTEP (1<<15) 694#define DIEPCTL_NEXTEP_SHIFT 11 695#define DIEPCTL_NEXTEP_MASK 0x00007800 696#define DIEPCTL_MPS_SHIFT 0 697#define DIEPCTL_MPS_MASK 0x000007ff 698#define DIEPCTL_MPS_SET(n) ((n) & 0x7FF) 699#define DIEPCTL_MPS_64 (0<<0) 700#define DIEPCTL_MPS_32 (1<<0) 701#define DIEPCTL_MPS_16 (2<<0) 702#define DIEPCTL_MPS_8 (3<<0) 703 704#define DOEPCTL_EPENA (1<<31) 705#define DOEPCTL_EPDIS (1<<30) 706#define DOEPCTL_SETD1PID (1<<29) 707#define DOEPCTL_SETD0PID (1<<28) 708#define DOEPCTL_SNAK (1<<27) 709#define DOEPCTL_CNAK (1<<26) 710#define DOEPCTL_FNUM_SET(n) (((n) & 15) << 22) 711#define DOEPCTL_STALL (1<<21) 712#define DOEPCTL_EPTYPE_SHIFT 18 713#define DOEPCTL_EPTYPE_MASK 0x000c0000 714#define DOEPCTL_EPTYPE_SET(n) (((n) & 3) << 18) 715#define DOEPCTL_NAKSTS (1<<17) 716#define DOEPCTL_USBACTEP (1<<15) 717#define DOEPCTL_MPS_SHIFT 0 718#define DOEPCTL_MPS_MASK 0x000007ff 719#define DOEPCTL_MPS_SET(n) ((n) & 0x7FF) 720#define DOEPCTL_MPS_64 (0<<0) 721#define DOEPCTL_MPS_32 (1<<0) 722#define DOEPCTL_MPS_16 (2<<0) 723#define DOEPCTL_MPS_8 (3<<0) 724 725/* common bits */ 726#define DXEPINT_TXFEMP (1<<7) 727#define DXEPINT_SETUP (1<<3) 728#define DXEPINT_XFER_COMPL (1<<0) 729 730#define DIEPTSIZ_XFERSIZE_MASK 0x0007ffff 731#define DIEPTSIZ_XFERSIZE_SHIFT 0 732#define DIEPTSIZ_PKTCNT_MASK 0x1ff80000 733#define DIEPTSIZ_PKTCNT_SHIFT 19 734#define DIEPTSIZ_MC_MASK 0x60000000 735#define DIEPTSIZ_MC_SHIFT 29 736 737#define DOEPTSIZ_XFERSIZE_MASK 0x0007ffff 738#define DOEPTSIZ_XFERSIZE_SHIFT 0 739#define DOEPTSIZ_PKTCNT_MASK 0x1ff80000 740#define DOEPTSIZ_PKTCNT_SHIFT 19 741#define DOEPTSIZ_MC_MASK 0x60000000 742#define DOEPTSIZ_MC_SHIFT 29 743 744/* common bits */ 745#define DXEPTSIZ_SET_MULTI(n) (((n) & 3) << 29) 746#define DXEPTSIZ_SET_NPKT(n) (((n) & 0x3FF) << 19) 747#define DXEPTSIZ_GET_NPKT(n) (((n) >> 19) & 0x3FF) 748#define DXEPTSIZ_SET_NBYTES(n) (((n) & 0x7FFFFF) << 0) 749#define DXEPTSIZ_GET_NBYTES(n) (((n) >> 0) & 0x7FFFFF) 750 751/* generic endpoint mask */ 752 753#define ENDPOINT_MASK(x,in) \ 754 ((in) ? (1U << ((x) & 15U)) : \ 755 (0x10000U << ((x) & 15U))) 756 757#endif /* _DWC_OTGREG_H_ */ 758