uart_dev_pl011.c revision 239919 
1/*-
2 * Copyright (c) 2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_pl011.c 239919 2012-08-30 20:31:53Z gonzo $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39#include "uart_if.h"
40
41#include <sys/kdb.h>
42
43/* PL011 UART registers and masks*/
44#define	UART_DR		0x00		/* Data register */
45#define	DR_FE		(1 << 8)	/* Framing error */
46#define	DR_PE		(1 << 9)	/* Parity error */
47#define	DR_BE		(1 << 10)	/* Break error */
48#define	DR_OE		(1 << 11)	/* Overrun error */
49
50#define	UART_FR		0x06		/* Flag register */
51#define	FR_RXFF		(1 << 6)	/* Receive FIFO/reg full */
52#define	FR_TXFE		(1 << 7)	/* Transmit FIFO/reg empty */
53
54#define	UART_IBRD	0x09		/* Integer baud rate register */
55#define	IBRD_BDIVINT	0xffff	/* Significant part of int. divisor value */
56
57#define	UART_FBRD	0x0a		/* Fractional baud rate register */
58#define	FBRD_BDIVFRAC	0x3f	/* Significant part of frac. divisor value */
59
60#define	UART_LCR_H	0x0b		/* Line control register */
61#define	LCR_H_WLEN8	(0x3 << 5)
62#define	LCR_H_WLEN7	(0x2 << 5)
63#define	LCR_H_WLEN6	(0x1 << 5)
64#define	LCR_H_FEN	(1 << 4)	/* FIFO mode enable */
65#define	LCR_H_STP2	(1 << 3)	/* 2 stop frames at the end */
66#define	LCR_H_EPS	(1 << 2)	/* Even parity select */
67#define	LCR_H_PEN	(1 << 1)	/* Parity enable */
68
69#define	UART_CR		0x0c		/* Control register */
70#define	CR_RXE		(1 << 9)	/* Receive enable */
71#define	CR_TXE		(1 << 8)	/* Transmit enable */
72#define	CR_UARTEN	(1 << 0)	/* UART enable */
73
74#define	UART_IMSC	0x0e		/* Interrupt mask set/clear register */
75#define	IMSC_MASK_ALL	0x7ff		/* Mask all interrupts */
76
77#define	UART_RIS	0x0f		/* Raw interrupt status register */
78#define	UART_RXREADY	(1 << 4)	/* RX buffer full */
79#define	UART_TXEMPTY	(1 << 5)	/* TX buffer empty */
80#define	RIS_FE		(1 << 7)	/* Framing error interrupt status */
81#define	RIS_PE		(1 << 8)	/* Parity error interrupt status */
82#define	RIS_BE		(1 << 9)	/* Break error interrupt status */
83#define	RIS_OE		(1 << 10)	/* Overrun interrupt status */
84
85#define	UART_MIS	0x10		/* Masked interrupt status register */
86#define	UART_ICR	0x11		/* Interrupt clear register */
87
88/*
89 * FIXME: actual register size is SoC-dependent, we need to handle it
90 */
91#define	__uart_getreg(bas, reg)		\
92	bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
93#define	__uart_setreg(bas, reg, value)	\
94	bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
95
96/*
97 * Low-level UART interface.
98 */
99static int uart_pl011_probe(struct uart_bas *bas);
100static void uart_pl011_init(struct uart_bas *bas, int, int, int, int);
101static void uart_pl011_term(struct uart_bas *bas);
102static void uart_pl011_putc(struct uart_bas *bas, int);
103static int uart_pl011_rxready(struct uart_bas *bas);
104static int uart_pl011_getc(struct uart_bas *bas, struct mtx *);
105
106static struct uart_ops uart_pl011_ops = {
107	.probe = uart_pl011_probe,
108	.init = uart_pl011_init,
109	.term = uart_pl011_term,
110	.putc = uart_pl011_putc,
111	.rxready = uart_pl011_rxready,
112	.getc = uart_pl011_getc,
113};
114
115static int
116uart_pl011_probe(struct uart_bas *bas)
117{
118
119	return (0);
120}
121
122static void
123uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
124    int parity)
125{
126	uint32_t ctrl, line;
127	uint32_t baud;
128
129	/* Mask all interrupts */
130	__uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
131	    ~IMSC_MASK_ALL);
132
133	/*
134	 * Zero all settings to make sure
135	 * UART is disabled and not configured
136	 */
137	ctrl = line = 0x0;
138	__uart_setreg(bas, UART_CR, ctrl);
139
140	/* As we know UART is disabled we may setup the line */
141	switch (databits) {
142	case 7:
143		line |= LCR_H_WLEN7;
144		break;
145	case 6:
146		line |= LCR_H_WLEN6;
147		break;
148	case 8:
149	default:
150		line |= LCR_H_WLEN8;
151		break;
152	}
153
154	/* TODO: Calculate divisors */
155	baud = (0x1 << 16) | 0x28;
156
157	if (stopbits == 2)
158		line |= LCR_H_STP2;
159	else
160		line &= ~LCR_H_STP2;
161
162	if (parity)
163		line |= LCR_H_PEN;
164	else
165		line &= ~LCR_H_PEN;
166
167	/* Configure the rest */
168	line &=  ~LCR_H_FEN;
169	ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
170
171	__uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 16)) & IBRD_BDIVINT);
172	__uart_setreg(bas, UART_FBRD, (uint32_t)(baud) & FBRD_BDIVFRAC);
173
174	/* Add config. to line before reenabling UART */
175	__uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) &
176	    ~0xff) | line);
177
178	__uart_setreg(bas, UART_CR, ctrl);
179}
180
181static void
182uart_pl011_term(struct uart_bas *bas)
183{
184}
185
186static void
187uart_pl011_putc(struct uart_bas *bas, int c)
188{
189
190	while (!(__uart_getreg(bas, UART_FR) & FR_TXFE))
191		;
192	__uart_setreg(bas, UART_DR, c & 0xff);
193}
194
195static int
196uart_pl011_rxready(struct uart_bas *bas)
197{
198
199	return (__uart_getreg(bas, UART_FR) & FR_RXFF);
200}
201
202static int
203uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx)
204{
205	int c;
206
207	while (!uart_pl011_rxready(bas))
208		;
209	c = __uart_getreg(bas, UART_DR) & 0xff;
210
211	return (c);
212}
213
214/*
215 * High-level UART interface.
216 */
217struct uart_pl011_softc {
218	struct uart_softc base;
219	uint8_t		fcr;
220	uint8_t		ier;
221	uint8_t		mcr;
222
223	uint8_t		ier_mask;
224	uint8_t		ier_rxbits;
225};
226
227static int uart_pl011_bus_attach(struct uart_softc *);
228static int uart_pl011_bus_detach(struct uart_softc *);
229static int uart_pl011_bus_flush(struct uart_softc *, int);
230static int uart_pl011_bus_getsig(struct uart_softc *);
231static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t);
232static int uart_pl011_bus_ipend(struct uart_softc *);
233static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int);
234static int uart_pl011_bus_probe(struct uart_softc *);
235static int uart_pl011_bus_receive(struct uart_softc *);
236static int uart_pl011_bus_setsig(struct uart_softc *, int);
237static int uart_pl011_bus_transmit(struct uart_softc *);
238
239static kobj_method_t uart_pl011_methods[] = {
240	KOBJMETHOD(uart_attach,		uart_pl011_bus_attach),
241	KOBJMETHOD(uart_detach,		uart_pl011_bus_detach),
242	KOBJMETHOD(uart_flush,		uart_pl011_bus_flush),
243	KOBJMETHOD(uart_getsig,		uart_pl011_bus_getsig),
244	KOBJMETHOD(uart_ioctl,		uart_pl011_bus_ioctl),
245	KOBJMETHOD(uart_ipend,		uart_pl011_bus_ipend),
246	KOBJMETHOD(uart_param,		uart_pl011_bus_param),
247	KOBJMETHOD(uart_probe,		uart_pl011_bus_probe),
248	KOBJMETHOD(uart_receive,	uart_pl011_bus_receive),
249	KOBJMETHOD(uart_setsig,		uart_pl011_bus_setsig),
250	KOBJMETHOD(uart_transmit,	uart_pl011_bus_transmit),
251	{ 0, 0 }
252};
253
254struct uart_class uart_pl011_class = {
255	"uart_pl011",
256	uart_pl011_methods,
257	sizeof(struct uart_pl011_softc),
258	.uc_ops = &uart_pl011_ops,
259	.uc_range = 0x48,
260	.uc_rclk = 0
261};
262
263static int
264uart_pl011_bus_attach(struct uart_softc *sc)
265{
266	struct uart_bas *bas;
267
268	bas = &sc->sc_bas;
269	/* Enable RX & TX interrupts */
270	__uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY));
271	/* Clear RX & TX interrupts */
272	__uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
273
274	sc->sc_rxfifosz = 1;
275	sc->sc_txfifosz = 1;
276
277	return (0);
278}
279
280static int
281uart_pl011_bus_detach(struct uart_softc *sc)
282{
283
284	return (0);
285}
286
287static int
288uart_pl011_bus_flush(struct uart_softc *sc, int what)
289{
290
291	return (0);
292}
293
294static int
295uart_pl011_bus_getsig(struct uart_softc *sc)
296{
297
298	return (0);
299}
300
301static int
302uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
303{
304	struct uart_bas *bas;
305	int error;
306
307	bas = &sc->sc_bas;
308	error = 0;
309	uart_lock(sc->sc_hwmtx);
310	switch (request) {
311	case UART_IOCTL_BREAK:
312		break;
313	case UART_IOCTL_BAUD:
314		*(int*)data = 115200;
315		break;
316	default:
317		error = EINVAL;
318		break;
319	}
320	uart_unlock(sc->sc_hwmtx);
321
322	return (error);
323}
324
325static int
326uart_pl011_bus_ipend(struct uart_softc *sc)
327{
328	struct uart_bas *bas;
329	int ipend;
330	uint32_t ints;
331
332	bas = &sc->sc_bas;
333	uart_lock(sc->sc_hwmtx);
334	ints = __uart_getreg(bas, UART_MIS);
335	ipend = 0;
336
337	if (ints & UART_RXREADY)
338		ipend |= SER_INT_RXREADY;
339	if (ints & RIS_BE)
340		ipend |= SER_INT_BREAK;
341	if (ints & RIS_OE)
342		ipend |= SER_INT_OVERRUN;
343	if (ints & UART_TXEMPTY) {
344		if (sc->sc_txbusy)
345			ipend |= SER_INT_TXIDLE;
346
347		__uart_setreg(bas, UART_IMSC, UART_RXREADY);
348	}
349
350	uart_unlock(sc->sc_hwmtx);
351
352	return (ipend);
353}
354
355static int
356uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits,
357    int stopbits, int parity)
358{
359
360	uart_lock(sc->sc_hwmtx);
361	uart_pl011_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
362	uart_unlock(sc->sc_hwmtx);
363
364	return (0);
365}
366
367static int
368uart_pl011_bus_probe(struct uart_softc *sc)
369{
370
371	device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
372
373	return (0);
374}
375
376static int
377uart_pl011_bus_receive(struct uart_softc *sc)
378{
379	struct uart_bas *bas;
380	int rx;
381	uint32_t ints, xc;
382
383	bas = &sc->sc_bas;
384	uart_lock(sc->sc_hwmtx);
385
386	ints = __uart_getreg(bas, UART_MIS);
387	while (ints & UART_RXREADY) {
388		if (uart_rx_full(sc)) {
389			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
390			break;
391		}
392		xc = __uart_getreg(bas, UART_DR);
393		rx = xc & 0xff;
394
395		if (xc & DR_FE)
396			rx |= UART_STAT_FRAMERR;
397		if (xc & DR_PE)
398			rx |= UART_STAT_PARERR;
399
400		__uart_setreg(bas, UART_ICR, UART_RXREADY);
401
402		uart_rx_put(sc, rx);
403		ints = __uart_getreg(bas, UART_MIS);
404	}
405
406	uart_unlock(sc->sc_hwmtx);
407
408	return (0);
409}
410
411static int
412uart_pl011_bus_setsig(struct uart_softc *sc, int sig)
413{
414
415	return (0);
416}
417
418static int
419uart_pl011_bus_transmit(struct uart_softc *sc)
420{
421	struct uart_bas *bas;
422	int i;
423
424	bas = &sc->sc_bas;
425	uart_lock(sc->sc_hwmtx);
426
427	for (i = 0; i < sc->sc_txdatasz; i++) {
428		__uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
429		uart_barrier(bas);
430	}
431	sc->sc_txbusy = 1;
432	__uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY));
433	uart_unlock(sc->sc_hwmtx);
434
435	return (0);
436}
437