if_ti.c revision 90548
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_ti.c 90548 2002-02-11 23:38:30Z silby $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include <sys/param.h> 82#include <sys/systm.h> 83#include <sys/sockio.h> 84#include <sys/mbuf.h> 85#include <sys/malloc.h> 86#include <sys/kernel.h> 87#include <sys/socket.h> 88#include <sys/queue.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95#include <net/if_types.h> 96#include <net/if_vlan_var.h> 97 98#include <net/bpf.h> 99 100#include <netinet/in_systm.h> 101#include <netinet/in.h> 102#include <netinet/ip.h> 103 104#include <vm/vm.h> /* for vtophys */ 105#include <vm/pmap.h> /* for vtophys */ 106#include <machine/bus_memio.h> 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <pci/pcireg.h> 113#include <pci/pcivar.h> 114 115#include <pci/if_tireg.h> 116#include <pci/ti_fw.h> 117#include <pci/ti_fw2.h> 118 119#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 120 121#if !defined(lint) 122static const char rcsid[] = 123 "$FreeBSD: head/sys/dev/ti/if_ti.c 90548 2002-02-11 23:38:30Z silby $"; 124#endif 125 126/* 127 * Various supported device vendors/types and their names. 128 */ 129 130static struct ti_type ti_devs[] = { 131 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 132 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 133 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 134 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 135 { TC_VENDORID, TC_DEVICEID_3C985, 136 "3Com 3c985-SX Gigabit Ethernet" }, 137 { NG_VENDORID, NG_DEVICEID_GA620, 138 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 139 { NG_VENDORID, NG_DEVICEID_GA620T, 140 "Netgear GA620 1000baseT Gigabit Ethernet" }, 141 { SGI_VENDORID, SGI_DEVICEID_TIGON, 142 "Silicon Graphics Gigabit Ethernet" }, 143 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 144 "Farallon PN9000SX Gigabit Ethernet" }, 145 { 0, 0, NULL } 146}; 147 148static int ti_probe __P((device_t)); 149static int ti_attach __P((device_t)); 150static int ti_detach __P((device_t)); 151static void ti_txeof __P((struct ti_softc *)); 152static void ti_rxeof __P((struct ti_softc *)); 153 154static void ti_stats_update __P((struct ti_softc *)); 155static int ti_encap __P((struct ti_softc *, struct mbuf *, 156 u_int32_t *)); 157 158static void ti_intr __P((void *)); 159static void ti_start __P((struct ifnet *)); 160static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 161static void ti_init __P((void *)); 162static void ti_init2 __P((struct ti_softc *)); 163static void ti_stop __P((struct ti_softc *)); 164static void ti_watchdog __P((struct ifnet *)); 165static void ti_shutdown __P((device_t)); 166static int ti_ifmedia_upd __P((struct ifnet *)); 167static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 168 169static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 170static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 171 int, u_int8_t *)); 172static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 173 174static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 175static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 176static void ti_setmulti __P((struct ti_softc *)); 177 178static void ti_mem __P((struct ti_softc *, u_int32_t, 179 u_int32_t, caddr_t)); 180static void ti_loadfw __P((struct ti_softc *)); 181static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 182static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 183 caddr_t, int)); 184static void ti_handle_events __P((struct ti_softc *)); 185static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 186static void *ti_jalloc __P((struct ti_softc *)); 187static void ti_jfree __P((caddr_t, void *)); 188static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 189static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 190static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 191static int ti_init_rx_ring_std __P((struct ti_softc *)); 192static void ti_free_rx_ring_std __P((struct ti_softc *)); 193static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 194static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 195static int ti_init_rx_ring_mini __P((struct ti_softc *)); 196static void ti_free_rx_ring_mini __P((struct ti_softc *)); 197static void ti_free_tx_ring __P((struct ti_softc *)); 198static int ti_init_tx_ring __P((struct ti_softc *)); 199 200static int ti_64bitslot_war __P((struct ti_softc *)); 201static int ti_chipinit __P((struct ti_softc *)); 202static int ti_gibinit __P((struct ti_softc *)); 203 204static device_method_t ti_methods[] = { 205 /* Device interface */ 206 DEVMETHOD(device_probe, ti_probe), 207 DEVMETHOD(device_attach, ti_attach), 208 DEVMETHOD(device_detach, ti_detach), 209 DEVMETHOD(device_shutdown, ti_shutdown), 210 { 0, 0 } 211}; 212 213static driver_t ti_driver = { 214 "ti", 215 ti_methods, 216 sizeof(struct ti_softc) 217}; 218 219static devclass_t ti_devclass; 220 221DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 222 223/* 224 * Send an instruction or address to the EEPROM, check for ACK. 225 */ 226static u_int32_t ti_eeprom_putbyte(sc, byte) 227 struct ti_softc *sc; 228 int byte; 229{ 230 register int i, ack = 0; 231 232 /* 233 * Make sure we're in TX mode. 234 */ 235 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 236 237 /* 238 * Feed in each bit and stobe the clock. 239 */ 240 for (i = 0x80; i; i >>= 1) { 241 if (byte & i) { 242 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 243 } else { 244 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 245 } 246 DELAY(1); 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 248 DELAY(1); 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 250 } 251 252 /* 253 * Turn off TX mode. 254 */ 255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 256 257 /* 258 * Check for ack. 259 */ 260 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 261 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 262 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 263 264 return(ack); 265} 266 267/* 268 * Read a byte of data stored in the EEPROM at address 'addr.' 269 * We have to send two address bytes since the EEPROM can hold 270 * more than 256 bytes of data. 271 */ 272static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 273 struct ti_softc *sc; 274 int addr; 275 u_int8_t *dest; 276{ 277 register int i; 278 u_int8_t byte = 0; 279 280 EEPROM_START; 281 282 /* 283 * Send write control code to EEPROM. 284 */ 285 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 286 printf("ti%d: failed to send write command, status: %x\n", 287 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 288 return(1); 289 } 290 291 /* 292 * Send first byte of address of byte we want to read. 293 */ 294 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 295 printf("ti%d: failed to send address, status: %x\n", 296 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 297 return(1); 298 } 299 /* 300 * Send second byte address of byte we want to read. 301 */ 302 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 303 printf("ti%d: failed to send address, status: %x\n", 304 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 305 return(1); 306 } 307 308 EEPROM_STOP; 309 EEPROM_START; 310 /* 311 * Send read control code to EEPROM. 312 */ 313 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 314 printf("ti%d: failed to send read command, status: %x\n", 315 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 316 return(1); 317 } 318 319 /* 320 * Start reading bits from EEPROM. 321 */ 322 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 323 for (i = 0x80; i; i >>= 1) { 324 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 325 DELAY(1); 326 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 327 byte |= i; 328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 329 DELAY(1); 330 } 331 332 EEPROM_STOP; 333 334 /* 335 * No ACK generated for read, so just return byte. 336 */ 337 338 *dest = byte; 339 340 return(0); 341} 342 343/* 344 * Read a sequence of bytes from the EEPROM. 345 */ 346static int ti_read_eeprom(sc, dest, off, cnt) 347 struct ti_softc *sc; 348 caddr_t dest; 349 int off; 350 int cnt; 351{ 352 int err = 0, i; 353 u_int8_t byte = 0; 354 355 for (i = 0; i < cnt; i++) { 356 err = ti_eeprom_getbyte(sc, off + i, &byte); 357 if (err) 358 break; 359 *(dest + i) = byte; 360 } 361 362 return(err ? 1 : 0); 363} 364 365/* 366 * NIC memory access function. Can be used to either clear a section 367 * of NIC local memory or (if buf is non-NULL) copy data into it. 368 */ 369static void ti_mem(sc, addr, len, buf) 370 struct ti_softc *sc; 371 u_int32_t addr, len; 372 caddr_t buf; 373{ 374 int segptr, segsize, cnt; 375 caddr_t ti_winbase, ptr; 376 377 segptr = addr; 378 cnt = len; 379 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 380 ptr = buf; 381 382 while(cnt) { 383 if (cnt < TI_WINLEN) 384 segsize = cnt; 385 else 386 segsize = TI_WINLEN - (segptr % TI_WINLEN); 387 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 388 if (buf == NULL) 389 bzero((char *)ti_winbase + (segptr & 390 (TI_WINLEN - 1)), segsize); 391 else { 392 bcopy((char *)ptr, (char *)ti_winbase + 393 (segptr & (TI_WINLEN - 1)), segsize); 394 ptr += segsize; 395 } 396 segptr += segsize; 397 cnt -= segsize; 398 } 399 400 return; 401} 402 403/* 404 * Load firmware image into the NIC. Check that the firmware revision 405 * is acceptable and see if we want the firmware for the Tigon 1 or 406 * Tigon 2. 407 */ 408static void ti_loadfw(sc) 409 struct ti_softc *sc; 410{ 411 switch(sc->ti_hwrev) { 412 case TI_HWREV_TIGON: 413 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 414 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 415 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 416 printf("ti%d: firmware revision mismatch; want " 417 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 418 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 419 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 420 tigonFwReleaseMinor, tigonFwReleaseFix); 421 return; 422 } 423 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 424 (caddr_t)tigonFwText); 425 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 426 (caddr_t)tigonFwData); 427 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 428 (caddr_t)tigonFwRodata); 429 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 430 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 431 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 432 break; 433 case TI_HWREV_TIGON_II: 434 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 435 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 436 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 437 printf("ti%d: firmware revision mismatch; want " 438 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 439 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 440 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 441 tigon2FwReleaseMinor, tigon2FwReleaseFix); 442 return; 443 } 444 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 445 (caddr_t)tigon2FwText); 446 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 447 (caddr_t)tigon2FwData); 448 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 449 (caddr_t)tigon2FwRodata); 450 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 451 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 452 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 453 break; 454 default: 455 printf("ti%d: can't load firmware: unknown hardware rev\n", 456 sc->ti_unit); 457 break; 458 } 459 460 return; 461} 462 463/* 464 * Send the NIC a command via the command ring. 465 */ 466static void ti_cmd(sc, cmd) 467 struct ti_softc *sc; 468 struct ti_cmd_desc *cmd; 469{ 470 u_int32_t index; 471 472 if (sc->ti_rdata->ti_cmd_ring == NULL) 473 return; 474 475 index = sc->ti_cmd_saved_prodidx; 476 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 477 TI_INC(index, TI_CMD_RING_CNT); 478 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 479 sc->ti_cmd_saved_prodidx = index; 480 481 return; 482} 483 484/* 485 * Send the NIC an extended command. The 'len' parameter specifies the 486 * number of command slots to include after the initial command. 487 */ 488static void ti_cmd_ext(sc, cmd, arg, len) 489 struct ti_softc *sc; 490 struct ti_cmd_desc *cmd; 491 caddr_t arg; 492 int len; 493{ 494 u_int32_t index; 495 register int i; 496 497 if (sc->ti_rdata->ti_cmd_ring == NULL) 498 return; 499 500 index = sc->ti_cmd_saved_prodidx; 501 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 502 TI_INC(index, TI_CMD_RING_CNT); 503 for (i = 0; i < len; i++) { 504 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 505 *(u_int32_t *)(&arg[i * 4])); 506 TI_INC(index, TI_CMD_RING_CNT); 507 } 508 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 509 sc->ti_cmd_saved_prodidx = index; 510 511 return; 512} 513 514/* 515 * Handle events that have triggered interrupts. 516 */ 517static void ti_handle_events(sc) 518 struct ti_softc *sc; 519{ 520 struct ti_event_desc *e; 521 522 if (sc->ti_rdata->ti_event_ring == NULL) 523 return; 524 525 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 526 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 527 switch(e->ti_event) { 528 case TI_EV_LINKSTAT_CHANGED: 529 sc->ti_linkstat = e->ti_code; 530 if (e->ti_code == TI_EV_CODE_LINK_UP) 531 printf("ti%d: 10/100 link up\n", sc->ti_unit); 532 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 533 printf("ti%d: gigabit link up\n", sc->ti_unit); 534 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 535 printf("ti%d: link down\n", sc->ti_unit); 536 break; 537 case TI_EV_ERROR: 538 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 539 printf("ti%d: invalid command\n", sc->ti_unit); 540 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 541 printf("ti%d: unknown command\n", sc->ti_unit); 542 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 543 printf("ti%d: bad config data\n", sc->ti_unit); 544 break; 545 case TI_EV_FIRMWARE_UP: 546 ti_init2(sc); 547 break; 548 case TI_EV_STATS_UPDATED: 549 ti_stats_update(sc); 550 break; 551 case TI_EV_RESET_JUMBO_RING: 552 case TI_EV_MCAST_UPDATED: 553 /* Who cares. */ 554 break; 555 default: 556 printf("ti%d: unknown event: %d\n", 557 sc->ti_unit, e->ti_event); 558 break; 559 } 560 /* Advance the consumer index. */ 561 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 562 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 563 } 564 565 return; 566} 567 568/* 569 * Memory management for the jumbo receive ring is a pain in the 570 * butt. We need to allocate at least 9018 bytes of space per frame, 571 * _and_ it has to be contiguous (unless you use the extended 572 * jumbo descriptor format). Using malloc() all the time won't 573 * work: malloc() allocates memory in powers of two, which means we 574 * would end up wasting a considerable amount of space by allocating 575 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 576 * to do our own memory management. 577 * 578 * The driver needs to allocate a contiguous chunk of memory at boot 579 * time. We then chop this up ourselves into 9K pieces and use them 580 * as external mbuf storage. 581 * 582 * One issue here is how much memory to allocate. The jumbo ring has 583 * 256 slots in it, but at 9K per slot than can consume over 2MB of 584 * RAM. This is a bit much, especially considering we also need 585 * RAM for the standard ring and mini ring (on the Tigon 2). To 586 * save space, we only actually allocate enough memory for 64 slots 587 * by default, which works out to between 500 and 600K. This can 588 * be tuned by changing a #define in if_tireg.h. 589 */ 590 591static int ti_alloc_jumbo_mem(sc) 592 struct ti_softc *sc; 593{ 594 caddr_t ptr; 595 register int i; 596 struct ti_jpool_entry *entry; 597 598 /* Grab a big chunk o' storage. */ 599 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 600 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 601 602 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 603 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 604 return(ENOBUFS); 605 } 606 607 SLIST_INIT(&sc->ti_jfree_listhead); 608 SLIST_INIT(&sc->ti_jinuse_listhead); 609 610 /* 611 * Now divide it up into 9K pieces and save the addresses 612 * in an array. 613 */ 614 ptr = sc->ti_cdata.ti_jumbo_buf; 615 for (i = 0; i < TI_JSLOTS; i++) { 616 sc->ti_cdata.ti_jslots[i] = ptr; 617 ptr += TI_JLEN; 618 entry = malloc(sizeof(struct ti_jpool_entry), 619 M_DEVBUF, M_NOWAIT); 620 if (entry == NULL) { 621 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 622 M_DEVBUF); 623 sc->ti_cdata.ti_jumbo_buf = NULL; 624 printf("ti%d: no memory for jumbo " 625 "buffer queue!\n", sc->ti_unit); 626 return(ENOBUFS); 627 } 628 entry->slot = i; 629 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 630 } 631 632 return(0); 633} 634 635/* 636 * Allocate a jumbo buffer. 637 */ 638static void *ti_jalloc(sc) 639 struct ti_softc *sc; 640{ 641 struct ti_jpool_entry *entry; 642 643 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 644 645 if (entry == NULL) { 646 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 647 return(NULL); 648 } 649 650 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 651 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 652 return(sc->ti_cdata.ti_jslots[entry->slot]); 653} 654 655/* 656 * Release a jumbo buffer. 657 */ 658static void ti_jfree(buf, args) 659 caddr_t buf; 660 void *args; 661{ 662 struct ti_softc *sc; 663 int i; 664 struct ti_jpool_entry *entry; 665 666 /* Extract the softc struct pointer. */ 667 sc = (struct ti_softc *)args; 668 669 if (sc == NULL) 670 panic("ti_jfree: didn't get softc pointer!"); 671 672 /* calculate the slot this buffer belongs to */ 673 i = ((vm_offset_t)buf 674 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 675 676 if ((i < 0) || (i >= TI_JSLOTS)) 677 panic("ti_jfree: asked to free buffer that we don't manage!"); 678 679 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 680 if (entry == NULL) 681 panic("ti_jfree: buffer not in use!"); 682 entry->slot = i; 683 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 684 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 685 686 return; 687} 688 689 690/* 691 * Intialize a standard receive ring descriptor. 692 */ 693static int ti_newbuf_std(sc, i, m) 694 struct ti_softc *sc; 695 int i; 696 struct mbuf *m; 697{ 698 struct mbuf *m_new = NULL; 699 struct ti_rx_desc *r; 700 701 if (m == NULL) { 702 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 703 if (m_new == NULL) 704 return(ENOBUFS); 705 706 MCLGET(m_new, M_DONTWAIT); 707 if (!(m_new->m_flags & M_EXT)) { 708 m_freem(m_new); 709 return(ENOBUFS); 710 } 711 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 712 } else { 713 m_new = m; 714 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 715 m_new->m_data = m_new->m_ext.ext_buf; 716 } 717 718 m_adj(m_new, ETHER_ALIGN); 719 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 720 r = &sc->ti_rdata->ti_rx_std_ring[i]; 721 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 722 r->ti_type = TI_BDTYPE_RECV_BD; 723 r->ti_flags = 0; 724 if (sc->arpcom.ac_if.if_hwassist) 725 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 726 r->ti_len = m_new->m_len; 727 r->ti_idx = i; 728 729 return(0); 730} 731 732/* 733 * Intialize a mini receive ring descriptor. This only applies to 734 * the Tigon 2. 735 */ 736static int ti_newbuf_mini(sc, i, m) 737 struct ti_softc *sc; 738 int i; 739 struct mbuf *m; 740{ 741 struct mbuf *m_new = NULL; 742 struct ti_rx_desc *r; 743 744 if (m == NULL) { 745 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 746 if (m_new == NULL) { 747 return(ENOBUFS); 748 } 749 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 750 } else { 751 m_new = m; 752 m_new->m_data = m_new->m_pktdat; 753 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 754 } 755 756 m_adj(m_new, ETHER_ALIGN); 757 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 758 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 759 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 760 r->ti_type = TI_BDTYPE_RECV_BD; 761 r->ti_flags = TI_BDFLAG_MINI_RING; 762 if (sc->arpcom.ac_if.if_hwassist) 763 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 764 r->ti_len = m_new->m_len; 765 r->ti_idx = i; 766 767 return(0); 768} 769 770/* 771 * Initialize a jumbo receive ring descriptor. This allocates 772 * a jumbo buffer from the pool managed internally by the driver. 773 */ 774static int ti_newbuf_jumbo(sc, i, m) 775 struct ti_softc *sc; 776 int i; 777 struct mbuf *m; 778{ 779 struct mbuf *m_new = NULL; 780 struct ti_rx_desc *r; 781 782 if (m == NULL) { 783 caddr_t *buf = NULL; 784 785 /* Allocate the mbuf. */ 786 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 787 if (m_new == NULL) { 788 return(ENOBUFS); 789 } 790 791 /* Allocate the jumbo buffer */ 792 buf = ti_jalloc(sc); 793 if (buf == NULL) { 794 m_freem(m_new); 795 printf("ti%d: jumbo allocation failed " 796 "-- packet dropped!\n", sc->ti_unit); 797 return(ENOBUFS); 798 } 799 800 /* Attach the buffer to the mbuf. */ 801 m_new->m_data = (void *) buf; 802 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 803 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 804 (struct ti_softc *)sc, 0, EXT_NET_DRV); 805 } else { 806 m_new = m; 807 m_new->m_data = m_new->m_ext.ext_buf; 808 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 809 } 810 811 m_adj(m_new, ETHER_ALIGN); 812 /* Set up the descriptor. */ 813 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 814 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 815 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 816 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 817 r->ti_flags = TI_BDFLAG_JUMBO_RING; 818 if (sc->arpcom.ac_if.if_hwassist) 819 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 820 r->ti_len = m_new->m_len; 821 r->ti_idx = i; 822 823 return(0); 824} 825 826/* 827 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 828 * that's 1MB or memory, which is a lot. For now, we fill only the first 829 * 256 ring entries and hope that our CPU is fast enough to keep up with 830 * the NIC. 831 */ 832static int ti_init_rx_ring_std(sc) 833 struct ti_softc *sc; 834{ 835 register int i; 836 struct ti_cmd_desc cmd; 837 838 for (i = 0; i < TI_SSLOTS; i++) { 839 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 840 return(ENOBUFS); 841 }; 842 843 TI_UPDATE_STDPROD(sc, i - 1); 844 sc->ti_std = i - 1; 845 846 return(0); 847} 848 849static void ti_free_rx_ring_std(sc) 850 struct ti_softc *sc; 851{ 852 register int i; 853 854 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 855 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 856 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 857 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 858 } 859 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 860 sizeof(struct ti_rx_desc)); 861 } 862 863 return; 864} 865 866static int ti_init_rx_ring_jumbo(sc) 867 struct ti_softc *sc; 868{ 869 register int i; 870 struct ti_cmd_desc cmd; 871 872 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 873 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 874 return(ENOBUFS); 875 }; 876 877 TI_UPDATE_JUMBOPROD(sc, i - 1); 878 sc->ti_jumbo = i - 1; 879 880 return(0); 881} 882 883static void ti_free_rx_ring_jumbo(sc) 884 struct ti_softc *sc; 885{ 886 register int i; 887 888 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 889 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 890 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 891 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 892 } 893 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 894 sizeof(struct ti_rx_desc)); 895 } 896 897 return; 898} 899 900static int ti_init_rx_ring_mini(sc) 901 struct ti_softc *sc; 902{ 903 register int i; 904 905 for (i = 0; i < TI_MSLOTS; i++) { 906 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 907 return(ENOBUFS); 908 }; 909 910 TI_UPDATE_MINIPROD(sc, i - 1); 911 sc->ti_mini = i - 1; 912 913 return(0); 914} 915 916static void ti_free_rx_ring_mini(sc) 917 struct ti_softc *sc; 918{ 919 register int i; 920 921 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 922 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 923 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 924 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 925 } 926 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 927 sizeof(struct ti_rx_desc)); 928 } 929 930 return; 931} 932 933static void ti_free_tx_ring(sc) 934 struct ti_softc *sc; 935{ 936 register int i; 937 938 if (sc->ti_rdata->ti_tx_ring == NULL) 939 return; 940 941 for (i = 0; i < TI_TX_RING_CNT; i++) { 942 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 943 m_freem(sc->ti_cdata.ti_tx_chain[i]); 944 sc->ti_cdata.ti_tx_chain[i] = NULL; 945 } 946 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 947 sizeof(struct ti_tx_desc)); 948 } 949 950 return; 951} 952 953static int ti_init_tx_ring(sc) 954 struct ti_softc *sc; 955{ 956 sc->ti_txcnt = 0; 957 sc->ti_tx_saved_considx = 0; 958 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 959 return(0); 960} 961 962/* 963 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 964 * but we have to support the old way too so that Tigon 1 cards will 965 * work. 966 */ 967void ti_add_mcast(sc, addr) 968 struct ti_softc *sc; 969 struct ether_addr *addr; 970{ 971 struct ti_cmd_desc cmd; 972 u_int16_t *m; 973 u_int32_t ext[2] = {0, 0}; 974 975 m = (u_int16_t *)&addr->octet[0]; 976 977 switch(sc->ti_hwrev) { 978 case TI_HWREV_TIGON: 979 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 980 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 981 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 982 break; 983 case TI_HWREV_TIGON_II: 984 ext[0] = htons(m[0]); 985 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 986 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 987 break; 988 default: 989 printf("ti%d: unknown hwrev\n", sc->ti_unit); 990 break; 991 } 992 993 return; 994} 995 996void ti_del_mcast(sc, addr) 997 struct ti_softc *sc; 998 struct ether_addr *addr; 999{ 1000 struct ti_cmd_desc cmd; 1001 u_int16_t *m; 1002 u_int32_t ext[2] = {0, 0}; 1003 1004 m = (u_int16_t *)&addr->octet[0]; 1005 1006 switch(sc->ti_hwrev) { 1007 case TI_HWREV_TIGON: 1008 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1009 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1010 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1011 break; 1012 case TI_HWREV_TIGON_II: 1013 ext[0] = htons(m[0]); 1014 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1015 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1016 break; 1017 default: 1018 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1019 break; 1020 } 1021 1022 return; 1023} 1024 1025/* 1026 * Configure the Tigon's multicast address filter. 1027 * 1028 * The actual multicast table management is a bit of a pain, thanks to 1029 * slight brain damage on the part of both Alteon and us. With our 1030 * multicast code, we are only alerted when the multicast address table 1031 * changes and at that point we only have the current list of addresses: 1032 * we only know the current state, not the previous state, so we don't 1033 * actually know what addresses were removed or added. The firmware has 1034 * state, but we can't get our grubby mits on it, and there is no 'delete 1035 * all multicast addresses' command. Hence, we have to maintain our own 1036 * state so we know what addresses have been programmed into the NIC at 1037 * any given time. 1038 */ 1039static void ti_setmulti(sc) 1040 struct ti_softc *sc; 1041{ 1042 struct ifnet *ifp; 1043 struct ifmultiaddr *ifma; 1044 struct ti_cmd_desc cmd; 1045 struct ti_mc_entry *mc; 1046 u_int32_t intrs; 1047 1048 ifp = &sc->arpcom.ac_if; 1049 1050 if (ifp->if_flags & IFF_ALLMULTI) { 1051 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1052 return; 1053 } else { 1054 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1055 } 1056 1057 /* Disable interrupts. */ 1058 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1059 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1060 1061 /* First, zot all the existing filters. */ 1062 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1063 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1064 ti_del_mcast(sc, &mc->mc_addr); 1065 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1066 free(mc, M_DEVBUF); 1067 } 1068 1069 /* Now program new ones. */ 1070 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1071 if (ifma->ifma_addr->sa_family != AF_LINK) 1072 continue; 1073 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1074 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1075 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1076 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1077 ti_add_mcast(sc, &mc->mc_addr); 1078 } 1079 1080 /* Re-enable interrupts. */ 1081 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1082 1083 return; 1084} 1085 1086/* 1087 * Check to see if the BIOS has configured us for a 64 bit slot when 1088 * we aren't actually in one. If we detect this condition, we can work 1089 * around it on the Tigon 2 by setting a bit in the PCI state register, 1090 * but for the Tigon 1 we must give up and abort the interface attach. 1091 */ 1092static int ti_64bitslot_war(sc) 1093 struct ti_softc *sc; 1094{ 1095 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1096 CSR_WRITE_4(sc, 0x600, 0); 1097 CSR_WRITE_4(sc, 0x604, 0); 1098 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1099 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1100 if (sc->ti_hwrev == TI_HWREV_TIGON) 1101 return(EINVAL); 1102 else { 1103 TI_SETBIT(sc, TI_PCI_STATE, 1104 TI_PCISTATE_32BIT_BUS); 1105 return(0); 1106 } 1107 } 1108 } 1109 1110 return(0); 1111} 1112 1113/* 1114 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1115 * self-test results. 1116 */ 1117static int ti_chipinit(sc) 1118 struct ti_softc *sc; 1119{ 1120 u_int32_t cacheline; 1121 u_int32_t pci_writemax = 0; 1122 1123 /* Initialize link to down state. */ 1124 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1125 1126 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1127 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1128 else 1129 sc->arpcom.ac_if.if_hwassist = 0; 1130 1131 /* Set endianness before we access any non-PCI registers. */ 1132#if BYTE_ORDER == BIG_ENDIAN 1133 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1134 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1135#else 1136 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1137 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1138#endif 1139 1140 /* Check the ROM failed bit to see if self-tests passed. */ 1141 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1142 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1143 return(ENODEV); 1144 } 1145 1146 /* Halt the CPU. */ 1147 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1148 1149 /* Figure out the hardware revision. */ 1150 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1151 case TI_REV_TIGON_I: 1152 sc->ti_hwrev = TI_HWREV_TIGON; 1153 break; 1154 case TI_REV_TIGON_II: 1155 sc->ti_hwrev = TI_HWREV_TIGON_II; 1156 break; 1157 default: 1158 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1159 return(ENODEV); 1160 } 1161 1162 /* Do special setup for Tigon 2. */ 1163 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1164 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1165 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1166 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1167 } 1168 1169 /* Set up the PCI state register. */ 1170 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1171 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1172 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1173 } 1174 1175 /* Clear the read/write max DMA parameters. */ 1176 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1177 TI_PCISTATE_READ_MAXDMA)); 1178 1179 /* Get cache line size. */ 1180 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1181 1182 /* 1183 * If the system has set enabled the PCI memory write 1184 * and invalidate command in the command register, set 1185 * the write max parameter accordingly. This is necessary 1186 * to use MWI with the Tigon 2. 1187 */ 1188 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1189 switch(cacheline) { 1190 case 1: 1191 case 4: 1192 case 8: 1193 case 16: 1194 case 32: 1195 case 64: 1196 break; 1197 default: 1198 /* Disable PCI memory write and invalidate. */ 1199 if (bootverbose) 1200 printf("ti%d: cache line size %d not " 1201 "supported; disabling PCI MWI\n", 1202 sc->ti_unit, cacheline); 1203 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1204 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1205 break; 1206 } 1207 } 1208 1209#ifdef __brokenalpha__ 1210 /* 1211 * From the Alteon sample driver: 1212 * Must insure that we do not cross an 8K (bytes) boundary 1213 * for DMA reads. Our highest limit is 1K bytes. This is a 1214 * restriction on some ALPHA platforms with early revision 1215 * 21174 PCI chipsets, such as the AlphaPC 164lx 1216 */ 1217 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1218#else 1219 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1220#endif 1221 1222 /* This sets the min dma param all the way up (0xff). */ 1223 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1224 1225 /* Configure DMA variables. */ 1226#if BYTE_ORDER == BIG_ENDIAN 1227 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1228 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1229 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1230 TI_OPMODE_DONT_FRAG_JUMBO); 1231#else 1232 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1233 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1234 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1235#endif 1236 1237 /* 1238 * Only allow 1 DMA channel to be active at a time. 1239 * I don't think this is a good idea, but without it 1240 * the firmware racks up lots of nicDmaReadRingFull 1241 * errors. This is not compatible with hardware checksums. 1242 */ 1243 if (sc->arpcom.ac_if.if_hwassist == 0) 1244 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1245 1246 /* Recommended settings from Tigon manual. */ 1247 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1248 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1249 1250 if (ti_64bitslot_war(sc)) { 1251 printf("ti%d: bios thinks we're in a 64 bit slot, " 1252 "but we aren't", sc->ti_unit); 1253 return(EINVAL); 1254 } 1255 1256 return(0); 1257} 1258 1259/* 1260 * Initialize the general information block and firmware, and 1261 * start the CPU(s) running. 1262 */ 1263static int ti_gibinit(sc) 1264 struct ti_softc *sc; 1265{ 1266 struct ti_rcb *rcb; 1267 int i; 1268 struct ifnet *ifp; 1269 1270 ifp = &sc->arpcom.ac_if; 1271 1272 /* Disable interrupts for now. */ 1273 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1274 1275 /* Tell the chip where to find the general information block. */ 1276 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1277 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1278 1279 /* Load the firmware into SRAM. */ 1280 ti_loadfw(sc); 1281 1282 /* Set up the contents of the general info and ring control blocks. */ 1283 1284 /* Set up the event ring and producer pointer. */ 1285 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1286 1287 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1288 rcb->ti_flags = 0; 1289 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1290 vtophys(&sc->ti_ev_prodidx); 1291 sc->ti_ev_prodidx.ti_idx = 0; 1292 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1293 sc->ti_ev_saved_considx = 0; 1294 1295 /* Set up the command ring and producer mailbox. */ 1296 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1297 1298 sc->ti_rdata->ti_cmd_ring = 1299 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1300 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1301 rcb->ti_flags = 0; 1302 rcb->ti_max_len = 0; 1303 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1304 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1305 } 1306 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1307 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1308 sc->ti_cmd_saved_prodidx = 0; 1309 1310 /* 1311 * Assign the address of the stats refresh buffer. 1312 * We re-use the current stats buffer for this to 1313 * conserve memory. 1314 */ 1315 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1316 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1317 1318 /* Set up the standard receive ring. */ 1319 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1320 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1321 rcb->ti_max_len = TI_FRAMELEN; 1322 rcb->ti_flags = 0; 1323 if (sc->arpcom.ac_if.if_hwassist) 1324 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1325 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1326 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1327 1328 /* Set up the jumbo receive ring. */ 1329 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1330 TI_HOSTADDR(rcb->ti_hostaddr) = 1331 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1332 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1333 rcb->ti_flags = 0; 1334 if (sc->arpcom.ac_if.if_hwassist) 1335 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1336 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1337 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1338 1339 /* 1340 * Set up the mini ring. Only activated on the 1341 * Tigon 2 but the slot in the config block is 1342 * still there on the Tigon 1. 1343 */ 1344 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1345 TI_HOSTADDR(rcb->ti_hostaddr) = 1346 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1347 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1348 if (sc->ti_hwrev == TI_HWREV_TIGON) 1349 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1350 else 1351 rcb->ti_flags = 0; 1352 if (sc->arpcom.ac_if.if_hwassist) 1353 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1354 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1355 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1356 1357 /* 1358 * Set up the receive return ring. 1359 */ 1360 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1361 TI_HOSTADDR(rcb->ti_hostaddr) = 1362 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1363 rcb->ti_flags = 0; 1364 rcb->ti_max_len = TI_RETURN_RING_CNT; 1365 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1366 vtophys(&sc->ti_return_prodidx); 1367 1368 /* 1369 * Set up the tx ring. Note: for the Tigon 2, we have the option 1370 * of putting the transmit ring in the host's address space and 1371 * letting the chip DMA it instead of leaving the ring in the NIC's 1372 * memory and accessing it through the shared memory region. We 1373 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1374 * so we have to revert to the shared memory scheme if we detect 1375 * a Tigon 1 chip. 1376 */ 1377 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1378 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1379 sc->ti_rdata->ti_tx_ring_nic = 1380 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1381 } 1382 bzero((char *)sc->ti_rdata->ti_tx_ring, 1383 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1384 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1385 if (sc->ti_hwrev == TI_HWREV_TIGON) 1386 rcb->ti_flags = 0; 1387 else 1388 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1389 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1390 if (sc->arpcom.ac_if.if_hwassist) 1391 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1392 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1393 rcb->ti_max_len = TI_TX_RING_CNT; 1394 if (sc->ti_hwrev == TI_HWREV_TIGON) 1395 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1396 else 1397 TI_HOSTADDR(rcb->ti_hostaddr) = 1398 vtophys(&sc->ti_rdata->ti_tx_ring); 1399 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1400 vtophys(&sc->ti_tx_considx); 1401 1402 /* Set up tuneables */ 1403 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1404 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1405 (sc->ti_rx_coal_ticks / 10)); 1406 else 1407 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1408 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1409 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1410 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1411 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1412 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1413 1414 /* Turn interrupts on. */ 1415 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1416 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1417 1418 /* Start CPU. */ 1419 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1420 1421 return(0); 1422} 1423 1424/* 1425 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1426 * against our list and return its name if we find a match. 1427 */ 1428static int ti_probe(dev) 1429 device_t dev; 1430{ 1431 struct ti_type *t; 1432 1433 t = ti_devs; 1434 1435 while(t->ti_name != NULL) { 1436 if ((pci_get_vendor(dev) == t->ti_vid) && 1437 (pci_get_device(dev) == t->ti_did)) { 1438 device_set_desc(dev, t->ti_name); 1439 return(0); 1440 } 1441 t++; 1442 } 1443 1444 return(ENXIO); 1445} 1446 1447static int ti_attach(dev) 1448 device_t dev; 1449{ 1450 u_int32_t command; 1451 struct ifnet *ifp; 1452 struct ti_softc *sc; 1453 int unit, error = 0, rid; 1454 1455 sc = device_get_softc(dev); 1456 unit = device_get_unit(dev); 1457 bzero(sc, sizeof(struct ti_softc)); 1458 1459 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1460 TI_LOCK(sc); 1461 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM; 1462 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 1463 1464 /* 1465 * Map control/status registers. 1466 */ 1467 pci_enable_busmaster(dev); 1468 pci_enable_io(dev, SYS_RES_MEMORY); 1469 command = pci_read_config(dev, PCIR_COMMAND, 4); 1470 1471 if (!(command & PCIM_CMD_MEMEN)) { 1472 printf("ti%d: failed to enable memory mapping!\n", unit); 1473 error = ENXIO; 1474 goto fail; 1475 } 1476 1477 rid = TI_PCI_LOMEM; 1478 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1479 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1480 1481 if (sc->ti_res == NULL) { 1482 printf ("ti%d: couldn't map memory\n", unit); 1483 error = ENXIO; 1484 goto fail; 1485 } 1486 1487 sc->ti_btag = rman_get_bustag(sc->ti_res); 1488 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1489 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1490 1491 /* Allocate interrupt */ 1492 rid = 0; 1493 1494 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1495 RF_SHAREABLE | RF_ACTIVE); 1496 1497 if (sc->ti_irq == NULL) { 1498 printf("ti%d: couldn't map interrupt\n", unit); 1499 error = ENXIO; 1500 goto fail; 1501 } 1502 1503 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1504 ti_intr, sc, &sc->ti_intrhand); 1505 1506 if (error) { 1507 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1508 bus_release_resource(dev, SYS_RES_MEMORY, 1509 TI_PCI_LOMEM, sc->ti_res); 1510 printf("ti%d: couldn't set up irq\n", unit); 1511 goto fail; 1512 } 1513 1514 sc->ti_unit = unit; 1515 1516 if (ti_chipinit(sc)) { 1517 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1518 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1519 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1520 bus_release_resource(dev, SYS_RES_MEMORY, 1521 TI_PCI_LOMEM, sc->ti_res); 1522 error = ENXIO; 1523 goto fail; 1524 } 1525 1526 /* Zero out the NIC's on-board SRAM. */ 1527 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1528 1529 /* Init again -- zeroing memory may have clobbered some registers. */ 1530 if (ti_chipinit(sc)) { 1531 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1532 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1533 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1534 bus_release_resource(dev, SYS_RES_MEMORY, 1535 TI_PCI_LOMEM, sc->ti_res); 1536 error = ENXIO; 1537 goto fail; 1538 } 1539 1540 /* 1541 * Get station address from the EEPROM. Note: the manual states 1542 * that the MAC address is at offset 0x8c, however the data is 1543 * stored as two longwords (since that's how it's loaded into 1544 * the NIC). This means the MAC address is actually preceded 1545 * by two zero bytes. We need to skip over those. 1546 */ 1547 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1548 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1549 printf("ti%d: failed to read station address\n", unit); 1550 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1551 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1552 bus_release_resource(dev, SYS_RES_MEMORY, 1553 TI_PCI_LOMEM, sc->ti_res); 1554 error = ENXIO; 1555 goto fail; 1556 } 1557 1558 /* 1559 * A Tigon chip was detected. Inform the world. 1560 */ 1561 printf("ti%d: Ethernet address: %6D\n", unit, 1562 sc->arpcom.ac_enaddr, ":"); 1563 1564 /* Allocate the general information block and ring buffers. */ 1565 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1566 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1567 1568 if (sc->ti_rdata == NULL) { 1569 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1570 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1571 bus_release_resource(dev, SYS_RES_MEMORY, 1572 TI_PCI_LOMEM, sc->ti_res); 1573 error = ENXIO; 1574 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1575 goto fail; 1576 } 1577 1578 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1579 1580 /* Try to allocate memory for jumbo buffers. */ 1581 if (ti_alloc_jumbo_mem(sc)) { 1582 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1583 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1584 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1585 bus_release_resource(dev, SYS_RES_MEMORY, 1586 TI_PCI_LOMEM, sc->ti_res); 1587 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1588 M_DEVBUF); 1589 error = ENXIO; 1590 goto fail; 1591 } 1592 1593 /* 1594 * We really need a better way to tell a 1000baseTX card 1595 * from a 1000baseSX one, since in theory there could be 1596 * OEMed 1000baseTX cards from lame vendors who aren't 1597 * clever enough to change the PCI ID. For the moment 1598 * though, the AceNIC is the only copper card available. 1599 */ 1600 if (pci_get_vendor(dev) == ALT_VENDORID && 1601 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1602 sc->ti_copper = 1; 1603 /* Ok, it's not the only copper card available. */ 1604 if (pci_get_vendor(dev) == NG_VENDORID && 1605 pci_get_device(dev) == NG_DEVICEID_GA620T) 1606 sc->ti_copper = 1; 1607 1608 /* Set default tuneable values. */ 1609 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1610 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1611 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1612 sc->ti_rx_max_coal_bds = 64; 1613 sc->ti_tx_max_coal_bds = 128; 1614 sc->ti_tx_buf_ratio = 21; 1615 1616 /* Set up ifnet structure */ 1617 ifp = &sc->arpcom.ac_if; 1618 ifp->if_softc = sc; 1619 ifp->if_unit = sc->ti_unit; 1620 ifp->if_name = "ti"; 1621 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1622 ifp->if_ioctl = ti_ioctl; 1623 ifp->if_output = ether_output; 1624 ifp->if_start = ti_start; 1625 ifp->if_watchdog = ti_watchdog; 1626 ifp->if_init = ti_init; 1627 ifp->if_mtu = ETHERMTU; 1628 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1629 1630 /* Set up ifmedia support. */ 1631 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1632 if (sc->ti_copper) { 1633 /* 1634 * Copper cards allow manual 10/100 mode selection, 1635 * but not manual 1000baseTX mode selection. Why? 1636 * Becuase currently there's no way to specify the 1637 * master/slave setting through the firmware interface, 1638 * so Alteon decided to just bag it and handle it 1639 * via autonegotiation. 1640 */ 1641 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1642 ifmedia_add(&sc->ifmedia, 1643 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1644 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1645 ifmedia_add(&sc->ifmedia, 1646 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1647 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 1648 ifmedia_add(&sc->ifmedia, 1649 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 1650 } else { 1651 /* Fiber cards don't support 10/100 modes. */ 1652 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1653 ifmedia_add(&sc->ifmedia, 1654 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1655 } 1656 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1657 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1658 1659 /* 1660 * Call MI attach routine. 1661 */ 1662 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1663 TI_UNLOCK(sc); 1664 return(0); 1665 1666fail: 1667 TI_UNLOCK(sc); 1668 mtx_destroy(&sc->ti_mtx); 1669 return(error); 1670} 1671 1672static int ti_detach(dev) 1673 device_t dev; 1674{ 1675 struct ti_softc *sc; 1676 struct ifnet *ifp; 1677 1678 1679 sc = device_get_softc(dev); 1680 TI_LOCK(sc); 1681 ifp = &sc->arpcom.ac_if; 1682 1683 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1684 ti_stop(sc); 1685 1686 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1687 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1688 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1689 1690 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1691 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1692 ifmedia_removeall(&sc->ifmedia); 1693 1694 TI_UNLOCK(sc); 1695 mtx_destroy(&sc->ti_mtx); 1696 1697 return(0); 1698} 1699 1700/* 1701 * Frame reception handling. This is called if there's a frame 1702 * on the receive return list. 1703 * 1704 * Note: we have to be able to handle three possibilities here: 1705 * 1) the frame is from the mini receive ring (can only happen) 1706 * on Tigon 2 boards) 1707 * 2) the frame is from the jumbo recieve ring 1708 * 3) the frame is from the standard receive ring 1709 */ 1710 1711static void ti_rxeof(sc) 1712 struct ti_softc *sc; 1713{ 1714 struct ifnet *ifp; 1715 struct ti_cmd_desc cmd; 1716 1717 ifp = &sc->arpcom.ac_if; 1718 1719 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1720 struct ti_rx_desc *cur_rx; 1721 u_int32_t rxidx; 1722 struct ether_header *eh; 1723 struct mbuf *m = NULL; 1724 u_int16_t vlan_tag = 0; 1725 int have_tag = 0; 1726 1727 cur_rx = 1728 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1729 rxidx = cur_rx->ti_idx; 1730 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1731 1732 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1733 have_tag = 1; 1734 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1735 } 1736 1737 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1738 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1739 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1740 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1741 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1742 ifp->if_ierrors++; 1743 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1744 continue; 1745 } 1746 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1747 ifp->if_ierrors++; 1748 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1749 continue; 1750 } 1751 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1752 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1753 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1754 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1755 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1756 ifp->if_ierrors++; 1757 ti_newbuf_mini(sc, sc->ti_mini, m); 1758 continue; 1759 } 1760 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1761 ifp->if_ierrors++; 1762 ti_newbuf_mini(sc, sc->ti_mini, m); 1763 continue; 1764 } 1765 } else { 1766 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1767 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1768 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1769 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1770 ifp->if_ierrors++; 1771 ti_newbuf_std(sc, sc->ti_std, m); 1772 continue; 1773 } 1774 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1775 ifp->if_ierrors++; 1776 ti_newbuf_std(sc, sc->ti_std, m); 1777 continue; 1778 } 1779 } 1780 1781 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1782 ifp->if_ipackets++; 1783 eh = mtod(m, struct ether_header *); 1784 m->m_pkthdr.rcvif = ifp; 1785 1786 /* Remove header from mbuf and pass it on. */ 1787 m_adj(m, sizeof(struct ether_header)); 1788 1789 if (ifp->if_hwassist) { 1790 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1791 CSUM_DATA_VALID; 1792 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1793 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1794 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1795 } 1796 1797 /* 1798 * If we received a packet with a vlan tag, pass it 1799 * to vlan_input() instead of ether_input(). 1800 */ 1801 if (have_tag) { 1802 VLAN_INPUT_TAG(eh, m, vlan_tag); 1803 have_tag = vlan_tag = 0; 1804 continue; 1805 } 1806 ether_input(ifp, eh, m); 1807 } 1808 1809 /* Only necessary on the Tigon 1. */ 1810 if (sc->ti_hwrev == TI_HWREV_TIGON) 1811 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1812 sc->ti_rx_saved_considx); 1813 1814 TI_UPDATE_STDPROD(sc, sc->ti_std); 1815 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1816 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1817 1818 return; 1819} 1820 1821static void ti_txeof(sc) 1822 struct ti_softc *sc; 1823{ 1824 struct ti_tx_desc *cur_tx = NULL; 1825 struct ifnet *ifp; 1826 1827 ifp = &sc->arpcom.ac_if; 1828 1829 /* 1830 * Go through our tx ring and free mbufs for those 1831 * frames that have been sent. 1832 */ 1833 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1834 u_int32_t idx = 0; 1835 1836 idx = sc->ti_tx_saved_considx; 1837 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1838 if (idx > 383) 1839 CSR_WRITE_4(sc, TI_WINBASE, 1840 TI_TX_RING_BASE + 6144); 1841 else if (idx > 255) 1842 CSR_WRITE_4(sc, TI_WINBASE, 1843 TI_TX_RING_BASE + 4096); 1844 else if (idx > 127) 1845 CSR_WRITE_4(sc, TI_WINBASE, 1846 TI_TX_RING_BASE + 2048); 1847 else 1848 CSR_WRITE_4(sc, TI_WINBASE, 1849 TI_TX_RING_BASE); 1850 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1851 } else 1852 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1853 if (cur_tx->ti_flags & TI_BDFLAG_END) 1854 ifp->if_opackets++; 1855 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1856 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1857 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1858 } 1859 sc->ti_txcnt--; 1860 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1861 ifp->if_timer = 0; 1862 } 1863 1864 if (cur_tx != NULL) 1865 ifp->if_flags &= ~IFF_OACTIVE; 1866 1867 return; 1868} 1869 1870static void ti_intr(xsc) 1871 void *xsc; 1872{ 1873 struct ti_softc *sc; 1874 struct ifnet *ifp; 1875 1876 sc = xsc; 1877 TI_LOCK(sc); 1878 ifp = &sc->arpcom.ac_if; 1879 1880#ifdef notdef 1881 /* Avoid this for now -- checking this register is expensive. */ 1882 /* Make sure this is really our interrupt. */ 1883 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 1884 TI_UNLOCK(sc); 1885 return; 1886 } 1887#endif 1888 1889 /* Ack interrupt and stop others from occuring. */ 1890 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1891 1892 if (ifp->if_flags & IFF_RUNNING) { 1893 /* Check RX return ring producer/consumer */ 1894 ti_rxeof(sc); 1895 1896 /* Check TX ring producer/consumer */ 1897 ti_txeof(sc); 1898 } 1899 1900 ti_handle_events(sc); 1901 1902 /* Re-enable interrupts. */ 1903 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1904 1905 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1906 ti_start(ifp); 1907 1908 TI_UNLOCK(sc); 1909 1910 return; 1911} 1912 1913static void ti_stats_update(sc) 1914 struct ti_softc *sc; 1915{ 1916 struct ifnet *ifp; 1917 1918 ifp = &sc->arpcom.ac_if; 1919 1920 ifp->if_collisions += 1921 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1922 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1923 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1924 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1925 ifp->if_collisions; 1926 1927 return; 1928} 1929 1930/* 1931 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1932 * pointers to descriptors. 1933 */ 1934static int ti_encap(sc, m_head, txidx) 1935 struct ti_softc *sc; 1936 struct mbuf *m_head; 1937 u_int32_t *txidx; 1938{ 1939 struct ti_tx_desc *f = NULL; 1940 struct mbuf *m; 1941 u_int32_t frag, cur, cnt = 0; 1942 u_int16_t csum_flags = 0; 1943 struct ifvlan *ifv = NULL; 1944 1945 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1946 m_head->m_pkthdr.rcvif != NULL && 1947 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1948 ifv = m_head->m_pkthdr.rcvif->if_softc; 1949 1950 m = m_head; 1951 cur = frag = *txidx; 1952 1953 if (m_head->m_pkthdr.csum_flags) { 1954 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1955 csum_flags |= TI_BDFLAG_IP_CKSUM; 1956 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1957 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1958 if (m_head->m_flags & M_LASTFRAG) 1959 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1960 else if (m_head->m_flags & M_FRAG) 1961 csum_flags |= TI_BDFLAG_IP_FRAG; 1962 } 1963 /* 1964 * Start packing the mbufs in this chain into 1965 * the fragment pointers. Stop when we run out 1966 * of fragments or hit the end of the mbuf chain. 1967 */ 1968 for (m = m_head; m != NULL; m = m->m_next) { 1969 if (m->m_len != 0) { 1970 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1971 if (frag > 383) 1972 CSR_WRITE_4(sc, TI_WINBASE, 1973 TI_TX_RING_BASE + 6144); 1974 else if (frag > 255) 1975 CSR_WRITE_4(sc, TI_WINBASE, 1976 TI_TX_RING_BASE + 4096); 1977 else if (frag > 127) 1978 CSR_WRITE_4(sc, TI_WINBASE, 1979 TI_TX_RING_BASE + 2048); 1980 else 1981 CSR_WRITE_4(sc, TI_WINBASE, 1982 TI_TX_RING_BASE); 1983 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 1984 } else 1985 f = &sc->ti_rdata->ti_tx_ring[frag]; 1986 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1987 break; 1988 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 1989 f->ti_len = m->m_len; 1990 f->ti_flags = csum_flags; 1991 1992 if (ifv != NULL) { 1993 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 1994 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 1995 } else { 1996 f->ti_vlan_tag = 0; 1997 } 1998 1999 /* 2000 * Sanity check: avoid coming within 16 descriptors 2001 * of the end of the ring. 2002 */ 2003 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2004 return(ENOBUFS); 2005 cur = frag; 2006 TI_INC(frag, TI_TX_RING_CNT); 2007 cnt++; 2008 } 2009 } 2010 2011 if (m != NULL) 2012 return(ENOBUFS); 2013 2014 if (frag == sc->ti_tx_saved_considx) 2015 return(ENOBUFS); 2016 2017 if (sc->ti_hwrev == TI_HWREV_TIGON) 2018 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2019 TI_BDFLAG_END; 2020 else 2021 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2022 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2023 sc->ti_txcnt += cnt; 2024 2025 *txidx = frag; 2026 2027 return(0); 2028} 2029 2030/* 2031 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2032 * to the mbuf data regions directly in the transmit descriptors. 2033 */ 2034static void ti_start(ifp) 2035 struct ifnet *ifp; 2036{ 2037 struct ti_softc *sc; 2038 struct mbuf *m_head = NULL; 2039 u_int32_t prodidx = 0; 2040 2041 sc = ifp->if_softc; 2042 TI_LOCK(sc); 2043 2044 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2045 2046 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2047 IF_DEQUEUE(&ifp->if_snd, m_head); 2048 if (m_head == NULL) 2049 break; 2050 2051 /* 2052 * XXX 2053 * safety overkill. If this is a fragmented packet chain 2054 * with delayed TCP/UDP checksums, then only encapsulate 2055 * it if we have enough descriptors to handle the entire 2056 * chain at once. 2057 * (paranoia -- may not actually be needed) 2058 */ 2059 if (m_head->m_flags & M_FIRSTFRAG && 2060 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2061 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2062 m_head->m_pkthdr.csum_data + 16) { 2063 IF_PREPEND(&ifp->if_snd, m_head); 2064 ifp->if_flags |= IFF_OACTIVE; 2065 break; 2066 } 2067 } 2068 2069 /* 2070 * Pack the data into the transmit ring. If we 2071 * don't have room, set the OACTIVE flag and wait 2072 * for the NIC to drain the ring. 2073 */ 2074 if (ti_encap(sc, m_head, &prodidx)) { 2075 IF_PREPEND(&ifp->if_snd, m_head); 2076 ifp->if_flags |= IFF_OACTIVE; 2077 break; 2078 } 2079 2080 /* 2081 * If there's a BPF listener, bounce a copy of this frame 2082 * to him. 2083 */ 2084 if (ifp->if_bpf) 2085 bpf_mtap(ifp, m_head); 2086 } 2087 2088 /* Transmit */ 2089 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2090 2091 /* 2092 * Set a timeout in case the chip goes out to lunch. 2093 */ 2094 ifp->if_timer = 5; 2095 TI_UNLOCK(sc); 2096 2097 return; 2098} 2099 2100static void ti_init(xsc) 2101 void *xsc; 2102{ 2103 struct ti_softc *sc = xsc; 2104 2105 /* Cancel pending I/O and flush buffers. */ 2106 ti_stop(sc); 2107 2108 TI_LOCK(sc); 2109 /* Init the gen info block, ring control blocks and firmware. */ 2110 if (ti_gibinit(sc)) { 2111 printf("ti%d: initialization failure\n", sc->ti_unit); 2112 TI_UNLOCK(sc); 2113 return; 2114 } 2115 2116 TI_UNLOCK(sc); 2117 2118 return; 2119} 2120 2121static void ti_init2(sc) 2122 struct ti_softc *sc; 2123{ 2124 struct ti_cmd_desc cmd; 2125 struct ifnet *ifp; 2126 u_int16_t *m; 2127 struct ifmedia *ifm; 2128 int tmp; 2129 2130 ifp = &sc->arpcom.ac_if; 2131 2132 /* Specify MTU and interface index. */ 2133 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2134 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2135 ETHER_HDR_LEN + ETHER_CRC_LEN); 2136 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2137 2138 /* Load our MAC address. */ 2139 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2140 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2141 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2142 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2143 2144 /* Enable or disable promiscuous mode as needed. */ 2145 if (ifp->if_flags & IFF_PROMISC) { 2146 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2147 } else { 2148 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2149 } 2150 2151 /* Program multicast filter. */ 2152 ti_setmulti(sc); 2153 2154 /* 2155 * If this is a Tigon 1, we should tell the 2156 * firmware to use software packet filtering. 2157 */ 2158 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2159 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2160 } 2161 2162 /* Init RX ring. */ 2163 ti_init_rx_ring_std(sc); 2164 2165 /* Init jumbo RX ring. */ 2166 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2167 ti_init_rx_ring_jumbo(sc); 2168 2169 /* 2170 * If this is a Tigon 2, we can also configure the 2171 * mini ring. 2172 */ 2173 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2174 ti_init_rx_ring_mini(sc); 2175 2176 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2177 sc->ti_rx_saved_considx = 0; 2178 2179 /* Init TX ring. */ 2180 ti_init_tx_ring(sc); 2181 2182 /* Tell firmware we're alive. */ 2183 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2184 2185 /* Enable host interrupts. */ 2186 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2187 2188 ifp->if_flags |= IFF_RUNNING; 2189 ifp->if_flags &= ~IFF_OACTIVE; 2190 2191 /* 2192 * Make sure to set media properly. We have to do this 2193 * here since we have to issue commands in order to set 2194 * the link negotiation and we can't issue commands until 2195 * the firmware is running. 2196 */ 2197 ifm = &sc->ifmedia; 2198 tmp = ifm->ifm_media; 2199 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2200 ti_ifmedia_upd(ifp); 2201 ifm->ifm_media = tmp; 2202 2203 return; 2204} 2205 2206/* 2207 * Set media options. 2208 */ 2209static int ti_ifmedia_upd(ifp) 2210 struct ifnet *ifp; 2211{ 2212 struct ti_softc *sc; 2213 struct ifmedia *ifm; 2214 struct ti_cmd_desc cmd; 2215 2216 sc = ifp->if_softc; 2217 ifm = &sc->ifmedia; 2218 2219 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2220 return(EINVAL); 2221 2222 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2223 case IFM_AUTO: 2224 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2225 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2226 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2227 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2228 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2229 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2230 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2231 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2232 break; 2233 case IFM_1000_SX: 2234 case IFM_1000_TX: 2235 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2236 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2237 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2238 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2239 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2240 } 2241 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2242 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2243 break; 2244 case IFM_100_FX: 2245 case IFM_10_FL: 2246 case IFM_100_TX: 2247 case IFM_10_T: 2248 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2249 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2250 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2251 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2252 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2253 } else { 2254 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2255 } 2256 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2257 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2258 } else { 2259 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2260 } 2261 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2262 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2263 break; 2264 } 2265 2266 return(0); 2267} 2268 2269/* 2270 * Report current media status. 2271 */ 2272static void ti_ifmedia_sts(ifp, ifmr) 2273 struct ifnet *ifp; 2274 struct ifmediareq *ifmr; 2275{ 2276 struct ti_softc *sc; 2277 u_int32_t media = 0; 2278 2279 sc = ifp->if_softc; 2280 2281 ifmr->ifm_status = IFM_AVALID; 2282 ifmr->ifm_active = IFM_ETHER; 2283 2284 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2285 return; 2286 2287 ifmr->ifm_status |= IFM_ACTIVE; 2288 2289 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2290 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2291 if (sc->ti_copper) 2292 ifmr->ifm_active |= IFM_1000_TX; 2293 else 2294 ifmr->ifm_active |= IFM_1000_SX; 2295 if (media & TI_GLNK_FULL_DUPLEX) 2296 ifmr->ifm_active |= IFM_FDX; 2297 else 2298 ifmr->ifm_active |= IFM_HDX; 2299 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2300 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2301 if (sc->ti_copper) { 2302 if (media & TI_LNK_100MB) 2303 ifmr->ifm_active |= IFM_100_TX; 2304 if (media & TI_LNK_10MB) 2305 ifmr->ifm_active |= IFM_10_T; 2306 } else { 2307 if (media & TI_LNK_100MB) 2308 ifmr->ifm_active |= IFM_100_FX; 2309 if (media & TI_LNK_10MB) 2310 ifmr->ifm_active |= IFM_10_FL; 2311 } 2312 if (media & TI_LNK_FULL_DUPLEX) 2313 ifmr->ifm_active |= IFM_FDX; 2314 if (media & TI_LNK_HALF_DUPLEX) 2315 ifmr->ifm_active |= IFM_HDX; 2316 } 2317 2318 return; 2319} 2320 2321static int ti_ioctl(ifp, command, data) 2322 struct ifnet *ifp; 2323 u_long command; 2324 caddr_t data; 2325{ 2326 struct ti_softc *sc = ifp->if_softc; 2327 struct ifreq *ifr = (struct ifreq *) data; 2328 int mask, error = 0; 2329 struct ti_cmd_desc cmd; 2330 2331 TI_LOCK(sc); 2332 2333 switch(command) { 2334 case SIOCSIFADDR: 2335 case SIOCGIFADDR: 2336 error = ether_ioctl(ifp, command, data); 2337 break; 2338 case SIOCSIFMTU: 2339 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2340 error = EINVAL; 2341 else { 2342 ifp->if_mtu = ifr->ifr_mtu; 2343 ti_init(sc); 2344 } 2345 break; 2346 case SIOCSIFFLAGS: 2347 if (ifp->if_flags & IFF_UP) { 2348 /* 2349 * If only the state of the PROMISC flag changed, 2350 * then just use the 'set promisc mode' command 2351 * instead of reinitializing the entire NIC. Doing 2352 * a full re-init means reloading the firmware and 2353 * waiting for it to start up, which may take a 2354 * second or two. 2355 */ 2356 if (ifp->if_flags & IFF_RUNNING && 2357 ifp->if_flags & IFF_PROMISC && 2358 !(sc->ti_if_flags & IFF_PROMISC)) { 2359 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2360 TI_CMD_CODE_PROMISC_ENB, 0); 2361 } else if (ifp->if_flags & IFF_RUNNING && 2362 !(ifp->if_flags & IFF_PROMISC) && 2363 sc->ti_if_flags & IFF_PROMISC) { 2364 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2365 TI_CMD_CODE_PROMISC_DIS, 0); 2366 } else 2367 ti_init(sc); 2368 } else { 2369 if (ifp->if_flags & IFF_RUNNING) { 2370 ti_stop(sc); 2371 } 2372 } 2373 sc->ti_if_flags = ifp->if_flags; 2374 error = 0; 2375 break; 2376 case SIOCADDMULTI: 2377 case SIOCDELMULTI: 2378 if (ifp->if_flags & IFF_RUNNING) { 2379 ti_setmulti(sc); 2380 error = 0; 2381 } 2382 break; 2383 case SIOCSIFMEDIA: 2384 case SIOCGIFMEDIA: 2385 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2386 break; 2387 case SIOCSIFCAP: 2388 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2389 if (mask & IFCAP_HWCSUM) { 2390 if (IFCAP_HWCSUM & ifp->if_capenable) 2391 ifp->if_capenable &= ~IFCAP_HWCSUM; 2392 else 2393 ifp->if_capenable |= IFCAP_HWCSUM; 2394 if (ifp->if_flags & IFF_RUNNING) 2395 ti_init(sc); 2396 } 2397 error = 0; 2398 break; 2399 default: 2400 error = EINVAL; 2401 break; 2402 } 2403 2404 TI_UNLOCK(sc); 2405 2406 return(error); 2407} 2408 2409static void ti_watchdog(ifp) 2410 struct ifnet *ifp; 2411{ 2412 struct ti_softc *sc; 2413 2414 sc = ifp->if_softc; 2415 TI_LOCK(sc); 2416 2417 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2418 ti_stop(sc); 2419 ti_init(sc); 2420 2421 ifp->if_oerrors++; 2422 TI_UNLOCK(sc); 2423 2424 return; 2425} 2426 2427/* 2428 * Stop the adapter and free any mbufs allocated to the 2429 * RX and TX lists. 2430 */ 2431static void ti_stop(sc) 2432 struct ti_softc *sc; 2433{ 2434 struct ifnet *ifp; 2435 struct ti_cmd_desc cmd; 2436 2437 TI_LOCK(sc); 2438 2439 ifp = &sc->arpcom.ac_if; 2440 2441 /* Disable host interrupts. */ 2442 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2443 /* 2444 * Tell firmware we're shutting down. 2445 */ 2446 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2447 2448 /* Halt and reinitialize. */ 2449 ti_chipinit(sc); 2450 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2451 ti_chipinit(sc); 2452 2453 /* Free the RX lists. */ 2454 ti_free_rx_ring_std(sc); 2455 2456 /* Free jumbo RX list. */ 2457 ti_free_rx_ring_jumbo(sc); 2458 2459 /* Free mini RX list. */ 2460 ti_free_rx_ring_mini(sc); 2461 2462 /* Free TX buffers. */ 2463 ti_free_tx_ring(sc); 2464 2465 sc->ti_ev_prodidx.ti_idx = 0; 2466 sc->ti_return_prodidx.ti_idx = 0; 2467 sc->ti_tx_considx.ti_idx = 0; 2468 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2469 2470 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2471 TI_UNLOCK(sc); 2472 2473 return; 2474} 2475 2476/* 2477 * Stop all chip I/O so that the kernel's probe routines don't 2478 * get confused by errant DMAs when rebooting. 2479 */ 2480static void ti_shutdown(dev) 2481 device_t dev; 2482{ 2483 struct ti_softc *sc; 2484 2485 sc = device_get_softc(dev); 2486 TI_LOCK(sc); 2487 ti_chipinit(sc); 2488 TI_UNLOCK(sc); 2489 2490 return; 2491} 2492