if_ti.c revision 68621
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_ti.c 68621 2000-11-11 23:08:22Z bmilekic $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "vlan.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90#include <sys/queue.h> 91 92#include <net/if.h> 93#include <net/if_arp.h> 94#include <net/ethernet.h> 95#include <net/if_dl.h> 96#include <net/if_media.h> 97 98#include <net/bpf.h> 99 100#if NVLAN > 0 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103#endif 104 105#include <netinet/in_systm.h> 106#include <netinet/in.h> 107#include <netinet/ip.h> 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/bus_memio.h> 112#include <machine/bus.h> 113#include <machine/resource.h> 114#include <sys/bus.h> 115#include <sys/rman.h> 116 117#include <pci/pcireg.h> 118#include <pci/pcivar.h> 119 120#include <pci/if_tireg.h> 121#include <pci/ti_fw.h> 122#include <pci/ti_fw2.h> 123 124#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 125 126#if !defined(lint) 127static const char rcsid[] = 128 "$FreeBSD: head/sys/dev/ti/if_ti.c 68621 2000-11-11 23:08:22Z bmilekic $"; 129#endif 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134 135static struct ti_type ti_devs[] = { 136 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 137 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 138 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 139 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 140 { TC_VENDORID, TC_DEVICEID_3C985, 141 "3Com 3c985-SX Gigabit Ethernet" }, 142 { NG_VENDORID, NG_DEVICEID_GA620, 143 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 144 { NG_VENDORID, NG_DEVICEID_GA620T, 145 "Netgear GA620 1000baseT Gigabit Ethernet" }, 146 { SGI_VENDORID, SGI_DEVICEID_TIGON, 147 "Silicon Graphics Gigabit Ethernet" }, 148 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 149 "Farallon PN9000SX Gigabit Ethernet" }, 150 { 0, 0, NULL } 151}; 152 153static int ti_probe __P((device_t)); 154static int ti_attach __P((device_t)); 155static int ti_detach __P((device_t)); 156static void ti_txeof __P((struct ti_softc *)); 157static void ti_rxeof __P((struct ti_softc *)); 158 159static void ti_stats_update __P((struct ti_softc *)); 160static int ti_encap __P((struct ti_softc *, struct mbuf *, 161 u_int32_t *)); 162 163static void ti_intr __P((void *)); 164static void ti_start __P((struct ifnet *)); 165static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 166static void ti_init __P((void *)); 167static void ti_init2 __P((struct ti_softc *)); 168static void ti_stop __P((struct ti_softc *)); 169static void ti_watchdog __P((struct ifnet *)); 170static void ti_shutdown __P((device_t)); 171static int ti_ifmedia_upd __P((struct ifnet *)); 172static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 173 174static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 175static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 176 int, u_int8_t *)); 177static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 178 179static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 180static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 181static void ti_setmulti __P((struct ti_softc *)); 182 183static void ti_mem __P((struct ti_softc *, u_int32_t, 184 u_int32_t, caddr_t)); 185static void ti_loadfw __P((struct ti_softc *)); 186static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 187static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 188 caddr_t, int)); 189static void ti_handle_events __P((struct ti_softc *)); 190static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 191static void *ti_jalloc __P((struct ti_softc *)); 192static void ti_jfree __P((caddr_t, void *)); 193static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 194static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 195static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 196static int ti_init_rx_ring_std __P((struct ti_softc *)); 197static void ti_free_rx_ring_std __P((struct ti_softc *)); 198static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 199static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 200static int ti_init_rx_ring_mini __P((struct ti_softc *)); 201static void ti_free_rx_ring_mini __P((struct ti_softc *)); 202static void ti_free_tx_ring __P((struct ti_softc *)); 203static int ti_init_tx_ring __P((struct ti_softc *)); 204 205static int ti_64bitslot_war __P((struct ti_softc *)); 206static int ti_chipinit __P((struct ti_softc *)); 207static int ti_gibinit __P((struct ti_softc *)); 208 209static device_method_t ti_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, ti_probe), 212 DEVMETHOD(device_attach, ti_attach), 213 DEVMETHOD(device_detach, ti_detach), 214 DEVMETHOD(device_shutdown, ti_shutdown), 215 { 0, 0 } 216}; 217 218static driver_t ti_driver = { 219 "ti", 220 ti_methods, 221 sizeof(struct ti_softc) 222}; 223 224static devclass_t ti_devclass; 225 226DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 227 228/* 229 * Send an instruction or address to the EEPROM, check for ACK. 230 */ 231static u_int32_t ti_eeprom_putbyte(sc, byte) 232 struct ti_softc *sc; 233 int byte; 234{ 235 register int i, ack = 0; 236 237 /* 238 * Make sure we're in TX mode. 239 */ 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 241 242 /* 243 * Feed in each bit and stobe the clock. 244 */ 245 for (i = 0x80; i; i >>= 1) { 246 if (byte & i) { 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 } else { 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 250 } 251 DELAY(1); 252 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 DELAY(1); 254 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 255 } 256 257 /* 258 * Turn off TX mode. 259 */ 260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 261 262 /* 263 * Check for ack. 264 */ 265 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 267 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 268 269 return(ack); 270} 271 272/* 273 * Read a byte of data stored in the EEPROM at address 'addr.' 274 * We have to send two address bytes since the EEPROM can hold 275 * more than 256 bytes of data. 276 */ 277static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 278 struct ti_softc *sc; 279 int addr; 280 u_int8_t *dest; 281{ 282 register int i; 283 u_int8_t byte = 0; 284 285 EEPROM_START; 286 287 /* 288 * Send write control code to EEPROM. 289 */ 290 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 291 printf("ti%d: failed to send write command, status: %x\n", 292 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 293 return(1); 294 } 295 296 /* 297 * Send first byte of address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 300 printf("ti%d: failed to send address, status: %x\n", 301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 /* 305 * Send second byte address of byte we want to read. 306 */ 307 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 308 printf("ti%d: failed to send address, status: %x\n", 309 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 310 return(1); 311 } 312 313 EEPROM_STOP; 314 EEPROM_START; 315 /* 316 * Send read control code to EEPROM. 317 */ 318 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 319 printf("ti%d: failed to send read command, status: %x\n", 320 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 321 return(1); 322 } 323 324 /* 325 * Start reading bits from EEPROM. 326 */ 327 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 328 for (i = 0x80; i; i >>= 1) { 329 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 330 DELAY(1); 331 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 332 byte |= i; 333 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 334 DELAY(1); 335 } 336 337 EEPROM_STOP; 338 339 /* 340 * No ACK generated for read, so just return byte. 341 */ 342 343 *dest = byte; 344 345 return(0); 346} 347 348/* 349 * Read a sequence of bytes from the EEPROM. 350 */ 351static int ti_read_eeprom(sc, dest, off, cnt) 352 struct ti_softc *sc; 353 caddr_t dest; 354 int off; 355 int cnt; 356{ 357 int err = 0, i; 358 u_int8_t byte = 0; 359 360 for (i = 0; i < cnt; i++) { 361 err = ti_eeprom_getbyte(sc, off + i, &byte); 362 if (err) 363 break; 364 *(dest + i) = byte; 365 } 366 367 return(err ? 1 : 0); 368} 369 370/* 371 * NIC memory access function. Can be used to either clear a section 372 * of NIC local memory or (if buf is non-NULL) copy data into it. 373 */ 374static void ti_mem(sc, addr, len, buf) 375 struct ti_softc *sc; 376 u_int32_t addr, len; 377 caddr_t buf; 378{ 379 int segptr, segsize, cnt; 380 caddr_t ti_winbase, ptr; 381 382 segptr = addr; 383 cnt = len; 384 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 385 ptr = buf; 386 387 while(cnt) { 388 if (cnt < TI_WINLEN) 389 segsize = cnt; 390 else 391 segsize = TI_WINLEN - (segptr % TI_WINLEN); 392 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 393 if (buf == NULL) 394 bzero((char *)ti_winbase + (segptr & 395 (TI_WINLEN - 1)), segsize); 396 else { 397 bcopy((char *)ptr, (char *)ti_winbase + 398 (segptr & (TI_WINLEN - 1)), segsize); 399 ptr += segsize; 400 } 401 segptr += segsize; 402 cnt -= segsize; 403 } 404 405 return; 406} 407 408/* 409 * Load firmware image into the NIC. Check that the firmware revision 410 * is acceptable and see if we want the firmware for the Tigon 1 or 411 * Tigon 2. 412 */ 413static void ti_loadfw(sc) 414 struct ti_softc *sc; 415{ 416 switch(sc->ti_hwrev) { 417 case TI_HWREV_TIGON: 418 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 419 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 420 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 421 printf("ti%d: firmware revision mismatch; want " 422 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 423 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 424 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 425 tigonFwReleaseMinor, tigonFwReleaseFix); 426 return; 427 } 428 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 429 (caddr_t)tigonFwText); 430 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 431 (caddr_t)tigonFwData); 432 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 433 (caddr_t)tigonFwRodata); 434 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 435 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 437 break; 438 case TI_HWREV_TIGON_II: 439 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 440 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 441 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 442 printf("ti%d: firmware revision mismatch; want " 443 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 444 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 445 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 446 tigon2FwReleaseMinor, tigon2FwReleaseFix); 447 return; 448 } 449 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 450 (caddr_t)tigon2FwText); 451 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 452 (caddr_t)tigon2FwData); 453 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 454 (caddr_t)tigon2FwRodata); 455 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 456 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 457 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 458 break; 459 default: 460 printf("ti%d: can't load firmware: unknown hardware rev\n", 461 sc->ti_unit); 462 break; 463 } 464 465 return; 466} 467 468/* 469 * Send the NIC a command via the command ring. 470 */ 471static void ti_cmd(sc, cmd) 472 struct ti_softc *sc; 473 struct ti_cmd_desc *cmd; 474{ 475 u_int32_t index; 476 477 if (sc->ti_rdata->ti_cmd_ring == NULL) 478 return; 479 480 index = sc->ti_cmd_saved_prodidx; 481 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 482 TI_INC(index, TI_CMD_RING_CNT); 483 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 484 sc->ti_cmd_saved_prodidx = index; 485 486 return; 487} 488 489/* 490 * Send the NIC an extended command. The 'len' parameter specifies the 491 * number of command slots to include after the initial command. 492 */ 493static void ti_cmd_ext(sc, cmd, arg, len) 494 struct ti_softc *sc; 495 struct ti_cmd_desc *cmd; 496 caddr_t arg; 497 int len; 498{ 499 u_int32_t index; 500 register int i; 501 502 if (sc->ti_rdata->ti_cmd_ring == NULL) 503 return; 504 505 index = sc->ti_cmd_saved_prodidx; 506 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 507 TI_INC(index, TI_CMD_RING_CNT); 508 for (i = 0; i < len; i++) { 509 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 510 *(u_int32_t *)(&arg[i * 4])); 511 TI_INC(index, TI_CMD_RING_CNT); 512 } 513 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 514 sc->ti_cmd_saved_prodidx = index; 515 516 return; 517} 518 519/* 520 * Handle events that have triggered interrupts. 521 */ 522static void ti_handle_events(sc) 523 struct ti_softc *sc; 524{ 525 struct ti_event_desc *e; 526 527 if (sc->ti_rdata->ti_event_ring == NULL) 528 return; 529 530 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 531 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 532 switch(e->ti_event) { 533 case TI_EV_LINKSTAT_CHANGED: 534 sc->ti_linkstat = e->ti_code; 535 if (e->ti_code == TI_EV_CODE_LINK_UP) 536 printf("ti%d: 10/100 link up\n", sc->ti_unit); 537 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 538 printf("ti%d: gigabit link up\n", sc->ti_unit); 539 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 540 printf("ti%d: link down\n", sc->ti_unit); 541 break; 542 case TI_EV_ERROR: 543 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 544 printf("ti%d: invalid command\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 546 printf("ti%d: unknown command\n", sc->ti_unit); 547 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 548 printf("ti%d: bad config data\n", sc->ti_unit); 549 break; 550 case TI_EV_FIRMWARE_UP: 551 ti_init2(sc); 552 break; 553 case TI_EV_STATS_UPDATED: 554 ti_stats_update(sc); 555 break; 556 case TI_EV_RESET_JUMBO_RING: 557 case TI_EV_MCAST_UPDATED: 558 /* Who cares. */ 559 break; 560 default: 561 printf("ti%d: unknown event: %d\n", 562 sc->ti_unit, e->ti_event); 563 break; 564 } 565 /* Advance the consumer index. */ 566 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 567 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 568 } 569 570 return; 571} 572 573/* 574 * Memory management for the jumbo receive ring is a pain in the 575 * butt. We need to allocate at least 9018 bytes of space per frame, 576 * _and_ it has to be contiguous (unless you use the extended 577 * jumbo descriptor format). Using malloc() all the time won't 578 * work: malloc() allocates memory in powers of two, which means we 579 * would end up wasting a considerable amount of space by allocating 580 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 581 * to do our own memory management. 582 * 583 * The driver needs to allocate a contiguous chunk of memory at boot 584 * time. We then chop this up ourselves into 9K pieces and use them 585 * as external mbuf storage. 586 * 587 * One issue here is how much memory to allocate. The jumbo ring has 588 * 256 slots in it, but at 9K per slot than can consume over 2MB of 589 * RAM. This is a bit much, especially considering we also need 590 * RAM for the standard ring and mini ring (on the Tigon 2). To 591 * save space, we only actually allocate enough memory for 64 slots 592 * by default, which works out to between 500 and 600K. This can 593 * be tuned by changing a #define in if_tireg.h. 594 */ 595 596static int ti_alloc_jumbo_mem(sc) 597 struct ti_softc *sc; 598{ 599 caddr_t ptr; 600 register int i; 601 struct ti_jpool_entry *entry; 602 603 /* Grab a big chunk o' storage. */ 604 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 605 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 606 607 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 608 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 609 return(ENOBUFS); 610 } 611 612 SLIST_INIT(&sc->ti_jfree_listhead); 613 SLIST_INIT(&sc->ti_jinuse_listhead); 614 615 /* 616 * Now divide it up into 9K pieces and save the addresses 617 * in an array. 618 */ 619 ptr = sc->ti_cdata.ti_jumbo_buf; 620 for (i = 0; i < TI_JSLOTS; i++) { 621 sc->ti_cdata.ti_jslots[i] = ptr; 622 ptr += TI_JLEN; 623 entry = malloc(sizeof(struct ti_jpool_entry), 624 M_DEVBUF, M_NOWAIT); 625 if (entry == NULL) { 626 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 627 M_DEVBUF); 628 sc->ti_cdata.ti_jumbo_buf = NULL; 629 printf("ti%d: no memory for jumbo " 630 "buffer queue!\n", sc->ti_unit); 631 return(ENOBUFS); 632 } 633 entry->slot = i; 634 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 635 } 636 637 return(0); 638} 639 640/* 641 * Allocate a jumbo buffer. 642 */ 643static void *ti_jalloc(sc) 644 struct ti_softc *sc; 645{ 646 struct ti_jpool_entry *entry; 647 648 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 649 650 if (entry == NULL) { 651 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 652 return(NULL); 653 } 654 655 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 656 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 657 return(sc->ti_cdata.ti_jslots[entry->slot]); 658} 659 660/* 661 * Release a jumbo buffer. 662 */ 663static void ti_jfree(buf, args) 664 caddr_t buf; 665 void *args; 666{ 667 struct ti_softc *sc; 668 int i; 669 struct ti_jpool_entry *entry; 670 671 /* Extract the softc struct pointer. */ 672 sc = (struct ti_softc *)args; 673 674 if (sc == NULL) 675 panic("ti_jfree: didn't get softc pointer!"); 676 677 /* calculate the slot this buffer belongs to */ 678 i = ((vm_offset_t)buf 679 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 680 681 if ((i < 0) || (i >= TI_JSLOTS)) 682 panic("ti_jfree: asked to free buffer that we don't manage!"); 683 684 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 685 if (entry == NULL) 686 panic("ti_jfree: buffer not in use!"); 687 entry->slot = i; 688 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 689 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 690 691 return; 692} 693 694 695/* 696 * Intialize a standard receive ring descriptor. 697 */ 698static int ti_newbuf_std(sc, i, m) 699 struct ti_softc *sc; 700 int i; 701 struct mbuf *m; 702{ 703 struct mbuf *m_new = NULL; 704 struct ti_rx_desc *r; 705 706 if (m == NULL) { 707 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 708 if (m_new == NULL) { 709 printf("ti%d: mbuf allocation failed " 710 "-- packet dropped!\n", sc->ti_unit); 711 return(ENOBUFS); 712 } 713 714 MCLGET(m_new, M_DONTWAIT); 715 if (!(m_new->m_flags & M_EXT)) { 716 printf("ti%d: cluster allocation failed " 717 "-- packet dropped!\n", sc->ti_unit); 718 m_freem(m_new); 719 return(ENOBUFS); 720 } 721 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 722 } else { 723 m_new = m; 724 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 725 m_new->m_data = m_new->m_ext.ext_buf; 726 } 727 728 m_adj(m_new, ETHER_ALIGN); 729 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 730 r = &sc->ti_rdata->ti_rx_std_ring[i]; 731 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 732 r->ti_type = TI_BDTYPE_RECV_BD; 733 r->ti_flags = 0; 734 if (sc->arpcom.ac_if.if_hwassist) 735 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 736 r->ti_len = m_new->m_len; 737 r->ti_idx = i; 738 739 return(0); 740} 741 742/* 743 * Intialize a mini receive ring descriptor. This only applies to 744 * the Tigon 2. 745 */ 746static int ti_newbuf_mini(sc, i, m) 747 struct ti_softc *sc; 748 int i; 749 struct mbuf *m; 750{ 751 struct mbuf *m_new = NULL; 752 struct ti_rx_desc *r; 753 754 if (m == NULL) { 755 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 756 if (m_new == NULL) { 757 printf("ti%d: mbuf allocation failed " 758 "-- packet dropped!\n", sc->ti_unit); 759 return(ENOBUFS); 760 } 761 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 762 } else { 763 m_new = m; 764 m_new->m_data = m_new->m_pktdat; 765 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 766 } 767 768 m_adj(m_new, ETHER_ALIGN); 769 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 770 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 771 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 772 r->ti_type = TI_BDTYPE_RECV_BD; 773 r->ti_flags = TI_BDFLAG_MINI_RING; 774 if (sc->arpcom.ac_if.if_hwassist) 775 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 776 r->ti_len = m_new->m_len; 777 r->ti_idx = i; 778 779 return(0); 780} 781 782/* 783 * Initialize a jumbo receive ring descriptor. This allocates 784 * a jumbo buffer from the pool managed internally by the driver. 785 */ 786static int ti_newbuf_jumbo(sc, i, m) 787 struct ti_softc *sc; 788 int i; 789 struct mbuf *m; 790{ 791 struct mbuf *m_new = NULL; 792 struct ti_rx_desc *r; 793 794 if (m == NULL) { 795 caddr_t *buf = NULL; 796 797 /* Allocate the mbuf. */ 798 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 799 if (m_new == NULL) { 800 printf("ti%d: mbuf allocation failed " 801 "-- packet dropped!\n", sc->ti_unit); 802 return(ENOBUFS); 803 } 804 805 /* Allocate the jumbo buffer */ 806 buf = ti_jalloc(sc); 807 if (buf == NULL) { 808 m_freem(m_new); 809 printf("ti%d: jumbo allocation failed " 810 "-- packet dropped!\n", sc->ti_unit); 811 return(ENOBUFS); 812 } 813 814 /* Attach the buffer to the mbuf. */ 815 m_new->m_data = (void *) buf; 816 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 817 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 818 (struct ti_softc *)sc, 0, EXT_NET_DRV); 819 } else { 820 m_new = m; 821 m_new->m_data = m_new->m_ext.ext_buf; 822 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 823 } 824 825 m_adj(m_new, ETHER_ALIGN); 826 /* Set up the descriptor. */ 827 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 828 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 829 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 830 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 831 r->ti_flags = TI_BDFLAG_JUMBO_RING; 832 if (sc->arpcom.ac_if.if_hwassist) 833 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 834 r->ti_len = m_new->m_len; 835 r->ti_idx = i; 836 837 return(0); 838} 839 840/* 841 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 842 * that's 1MB or memory, which is a lot. For now, we fill only the first 843 * 256 ring entries and hope that our CPU is fast enough to keep up with 844 * the NIC. 845 */ 846static int ti_init_rx_ring_std(sc) 847 struct ti_softc *sc; 848{ 849 register int i; 850 struct ti_cmd_desc cmd; 851 852 for (i = 0; i < TI_SSLOTS; i++) { 853 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 854 return(ENOBUFS); 855 }; 856 857 TI_UPDATE_STDPROD(sc, i - 1); 858 sc->ti_std = i - 1; 859 860 return(0); 861} 862 863static void ti_free_rx_ring_std(sc) 864 struct ti_softc *sc; 865{ 866 register int i; 867 868 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 869 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 870 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 871 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 872 } 873 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 874 sizeof(struct ti_rx_desc)); 875 } 876 877 return; 878} 879 880static int ti_init_rx_ring_jumbo(sc) 881 struct ti_softc *sc; 882{ 883 register int i; 884 struct ti_cmd_desc cmd; 885 886 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 887 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 888 return(ENOBUFS); 889 }; 890 891 TI_UPDATE_JUMBOPROD(sc, i - 1); 892 sc->ti_jumbo = i - 1; 893 894 return(0); 895} 896 897static void ti_free_rx_ring_jumbo(sc) 898 struct ti_softc *sc; 899{ 900 register int i; 901 902 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 903 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 904 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 905 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 906 } 907 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 908 sizeof(struct ti_rx_desc)); 909 } 910 911 return; 912} 913 914static int ti_init_rx_ring_mini(sc) 915 struct ti_softc *sc; 916{ 917 register int i; 918 919 for (i = 0; i < TI_MSLOTS; i++) { 920 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 921 return(ENOBUFS); 922 }; 923 924 TI_UPDATE_MINIPROD(sc, i - 1); 925 sc->ti_mini = i - 1; 926 927 return(0); 928} 929 930static void ti_free_rx_ring_mini(sc) 931 struct ti_softc *sc; 932{ 933 register int i; 934 935 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 936 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 937 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 938 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 939 } 940 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 941 sizeof(struct ti_rx_desc)); 942 } 943 944 return; 945} 946 947static void ti_free_tx_ring(sc) 948 struct ti_softc *sc; 949{ 950 register int i; 951 952 if (sc->ti_rdata->ti_tx_ring == NULL) 953 return; 954 955 for (i = 0; i < TI_TX_RING_CNT; i++) { 956 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 957 m_freem(sc->ti_cdata.ti_tx_chain[i]); 958 sc->ti_cdata.ti_tx_chain[i] = NULL; 959 } 960 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 961 sizeof(struct ti_tx_desc)); 962 } 963 964 return; 965} 966 967static int ti_init_tx_ring(sc) 968 struct ti_softc *sc; 969{ 970 sc->ti_txcnt = 0; 971 sc->ti_tx_saved_considx = 0; 972 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 973 return(0); 974} 975 976/* 977 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 978 * but we have to support the old way too so that Tigon 1 cards will 979 * work. 980 */ 981void ti_add_mcast(sc, addr) 982 struct ti_softc *sc; 983 struct ether_addr *addr; 984{ 985 struct ti_cmd_desc cmd; 986 u_int16_t *m; 987 u_int32_t ext[2] = {0, 0}; 988 989 m = (u_int16_t *)&addr->octet[0]; 990 991 switch(sc->ti_hwrev) { 992 case TI_HWREV_TIGON: 993 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 994 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 995 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 996 break; 997 case TI_HWREV_TIGON_II: 998 ext[0] = htons(m[0]); 999 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1000 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1001 break; 1002 default: 1003 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1004 break; 1005 } 1006 1007 return; 1008} 1009 1010void ti_del_mcast(sc, addr) 1011 struct ti_softc *sc; 1012 struct ether_addr *addr; 1013{ 1014 struct ti_cmd_desc cmd; 1015 u_int16_t *m; 1016 u_int32_t ext[2] = {0, 0}; 1017 1018 m = (u_int16_t *)&addr->octet[0]; 1019 1020 switch(sc->ti_hwrev) { 1021 case TI_HWREV_TIGON: 1022 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1023 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1024 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1025 break; 1026 case TI_HWREV_TIGON_II: 1027 ext[0] = htons(m[0]); 1028 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1029 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1030 break; 1031 default: 1032 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1033 break; 1034 } 1035 1036 return; 1037} 1038 1039/* 1040 * Configure the Tigon's multicast address filter. 1041 * 1042 * The actual multicast table management is a bit of a pain, thanks to 1043 * slight brain damage on the part of both Alteon and us. With our 1044 * multicast code, we are only alerted when the multicast address table 1045 * changes and at that point we only have the current list of addresses: 1046 * we only know the current state, not the previous state, so we don't 1047 * actually know what addresses were removed or added. The firmware has 1048 * state, but we can't get our grubby mits on it, and there is no 'delete 1049 * all multicast addresses' command. Hence, we have to maintain our own 1050 * state so we know what addresses have been programmed into the NIC at 1051 * any given time. 1052 */ 1053static void ti_setmulti(sc) 1054 struct ti_softc *sc; 1055{ 1056 struct ifnet *ifp; 1057 struct ifmultiaddr *ifma; 1058 struct ti_cmd_desc cmd; 1059 struct ti_mc_entry *mc; 1060 u_int32_t intrs; 1061 1062 ifp = &sc->arpcom.ac_if; 1063 1064 if (ifp->if_flags & IFF_ALLMULTI) { 1065 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1066 return; 1067 } else { 1068 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1069 } 1070 1071 /* Disable interrupts. */ 1072 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1073 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1074 1075 /* First, zot all the existing filters. */ 1076 while (sc->ti_mc_listhead.slh_first != NULL) { 1077 mc = sc->ti_mc_listhead.slh_first; 1078 ti_del_mcast(sc, &mc->mc_addr); 1079 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1080 free(mc, M_DEVBUF); 1081 } 1082 1083 /* Now program new ones. */ 1084 for (ifma = ifp->if_multiaddrs.lh_first; 1085 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1086 if (ifma->ifma_addr->sa_family != AF_LINK) 1087 continue; 1088 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1089 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1090 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1091 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1092 ti_add_mcast(sc, &mc->mc_addr); 1093 } 1094 1095 /* Re-enable interrupts. */ 1096 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1097 1098 return; 1099} 1100 1101/* 1102 * Check to see if the BIOS has configured us for a 64 bit slot when 1103 * we aren't actually in one. If we detect this condition, we can work 1104 * around it on the Tigon 2 by setting a bit in the PCI state register, 1105 * but for the Tigon 1 we must give up and abort the interface attach. 1106 */ 1107static int ti_64bitslot_war(sc) 1108 struct ti_softc *sc; 1109{ 1110 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1111 CSR_WRITE_4(sc, 0x600, 0); 1112 CSR_WRITE_4(sc, 0x604, 0); 1113 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1114 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1115 if (sc->ti_hwrev == TI_HWREV_TIGON) 1116 return(EINVAL); 1117 else { 1118 TI_SETBIT(sc, TI_PCI_STATE, 1119 TI_PCISTATE_32BIT_BUS); 1120 return(0); 1121 } 1122 } 1123 } 1124 1125 return(0); 1126} 1127 1128/* 1129 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1130 * self-test results. 1131 */ 1132static int ti_chipinit(sc) 1133 struct ti_softc *sc; 1134{ 1135 u_int32_t cacheline; 1136 u_int32_t pci_writemax = 0; 1137 1138 /* Initialize link to down state. */ 1139 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1140 1141 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1142 1143 /* Set endianness before we access any non-PCI registers. */ 1144#if BYTE_ORDER == BIG_ENDIAN 1145 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1146 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1147#else 1148 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1149 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1150#endif 1151 1152 /* Check the ROM failed bit to see if self-tests passed. */ 1153 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1154 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1155 return(ENODEV); 1156 } 1157 1158 /* Halt the CPU. */ 1159 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1160 1161 /* Figure out the hardware revision. */ 1162 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1163 case TI_REV_TIGON_I: 1164 sc->ti_hwrev = TI_HWREV_TIGON; 1165 break; 1166 case TI_REV_TIGON_II: 1167 sc->ti_hwrev = TI_HWREV_TIGON_II; 1168 break; 1169 default: 1170 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1171 return(ENODEV); 1172 } 1173 1174 /* Do special setup for Tigon 2. */ 1175 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1176 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1177 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1178 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1179 } 1180 1181 /* Set up the PCI state register. */ 1182 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1183 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1184 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1185 } 1186 1187 /* Clear the read/write max DMA parameters. */ 1188 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1189 TI_PCISTATE_READ_MAXDMA)); 1190 1191 /* Get cache line size. */ 1192 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1193 1194 /* 1195 * If the system has set enabled the PCI memory write 1196 * and invalidate command in the command register, set 1197 * the write max parameter accordingly. This is necessary 1198 * to use MWI with the Tigon 2. 1199 */ 1200 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1201 switch(cacheline) { 1202 case 1: 1203 case 4: 1204 case 8: 1205 case 16: 1206 case 32: 1207 case 64: 1208 break; 1209 default: 1210 /* Disable PCI memory write and invalidate. */ 1211 if (bootverbose) 1212 printf("ti%d: cache line size %d not " 1213 "supported; disabling PCI MWI\n", 1214 sc->ti_unit, cacheline); 1215 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1216 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1217 break; 1218 } 1219 } 1220 1221#ifdef __brokenalpha__ 1222 /* 1223 * From the Alteon sample driver: 1224 * Must insure that we do not cross an 8K (bytes) boundary 1225 * for DMA reads. Our highest limit is 1K bytes. This is a 1226 * restriction on some ALPHA platforms with early revision 1227 * 21174 PCI chipsets, such as the AlphaPC 164lx 1228 */ 1229 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1230#else 1231 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1232#endif 1233 1234 /* This sets the min dma param all the way up (0xff). */ 1235 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1236 1237 /* Configure DMA variables. */ 1238#if BYTE_ORDER == BIG_ENDIAN 1239 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1240 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1241 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1242 TI_OPMODE_DONT_FRAG_JUMBO); 1243#else 1244 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1245 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1246 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1247#endif 1248 1249 /* 1250 * Only allow 1 DMA channel to be active at a time. 1251 * I don't think this is a good idea, but without it 1252 * the firmware racks up lots of nicDmaReadRingFull 1253 * errors. This is not compatible with hardware checksums. 1254 */ 1255 if (sc->arpcom.ac_if.if_hwassist == 0) 1256 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1257 1258 /* Recommended settings from Tigon manual. */ 1259 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1260 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1261 1262 if (ti_64bitslot_war(sc)) { 1263 printf("ti%d: bios thinks we're in a 64 bit slot, " 1264 "but we aren't", sc->ti_unit); 1265 return(EINVAL); 1266 } 1267 1268 return(0); 1269} 1270 1271/* 1272 * Initialize the general information block and firmware, and 1273 * start the CPU(s) running. 1274 */ 1275static int ti_gibinit(sc) 1276 struct ti_softc *sc; 1277{ 1278 struct ti_rcb *rcb; 1279 int i; 1280 struct ifnet *ifp; 1281 1282 ifp = &sc->arpcom.ac_if; 1283 1284 /* Disable interrupts for now. */ 1285 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1286 1287 /* Tell the chip where to find the general information block. */ 1288 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1289 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1290 1291 /* Load the firmware into SRAM. */ 1292 ti_loadfw(sc); 1293 1294 /* Set up the contents of the general info and ring control blocks. */ 1295 1296 /* Set up the event ring and producer pointer. */ 1297 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1298 1299 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1300 rcb->ti_flags = 0; 1301 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1302 vtophys(&sc->ti_ev_prodidx); 1303 sc->ti_ev_prodidx.ti_idx = 0; 1304 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1305 sc->ti_ev_saved_considx = 0; 1306 1307 /* Set up the command ring and producer mailbox. */ 1308 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1309 1310 sc->ti_rdata->ti_cmd_ring = 1311 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1312 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1313 rcb->ti_flags = 0; 1314 rcb->ti_max_len = 0; 1315 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1316 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1317 } 1318 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1319 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1320 sc->ti_cmd_saved_prodidx = 0; 1321 1322 /* 1323 * Assign the address of the stats refresh buffer. 1324 * We re-use the current stats buffer for this to 1325 * conserve memory. 1326 */ 1327 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1328 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1329 1330 /* Set up the standard receive ring. */ 1331 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1332 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1333 rcb->ti_max_len = TI_FRAMELEN; 1334 rcb->ti_flags = 0; 1335 if (sc->arpcom.ac_if.if_hwassist) 1336 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1337 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1338#if NVLAN > 0 1339 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1340#endif 1341 1342 /* Set up the jumbo receive ring. */ 1343 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1344 TI_HOSTADDR(rcb->ti_hostaddr) = 1345 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1346 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1347 rcb->ti_flags = 0; 1348 if (sc->arpcom.ac_if.if_hwassist) 1349 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1350 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1351#if NVLAN > 0 1352 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1353#endif 1354 1355 /* 1356 * Set up the mini ring. Only activated on the 1357 * Tigon 2 but the slot in the config block is 1358 * still there on the Tigon 1. 1359 */ 1360 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1361 TI_HOSTADDR(rcb->ti_hostaddr) = 1362 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1363 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1364 if (sc->ti_hwrev == TI_HWREV_TIGON) 1365 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1366 else 1367 rcb->ti_flags = 0; 1368 if (sc->arpcom.ac_if.if_hwassist) 1369 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1370 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1371#if NVLAN > 0 1372 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1373#endif 1374 1375 /* 1376 * Set up the receive return ring. 1377 */ 1378 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1379 TI_HOSTADDR(rcb->ti_hostaddr) = 1380 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1381 rcb->ti_flags = 0; 1382 rcb->ti_max_len = TI_RETURN_RING_CNT; 1383 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1384 vtophys(&sc->ti_return_prodidx); 1385 1386 /* 1387 * Set up the tx ring. Note: for the Tigon 2, we have the option 1388 * of putting the transmit ring in the host's address space and 1389 * letting the chip DMA it instead of leaving the ring in the NIC's 1390 * memory and accessing it through the shared memory region. We 1391 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1392 * so we have to revert to the shared memory scheme if we detect 1393 * a Tigon 1 chip. 1394 */ 1395 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1396 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1397 sc->ti_rdata->ti_tx_ring_nic = 1398 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1399 } 1400 bzero((char *)sc->ti_rdata->ti_tx_ring, 1401 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1402 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1403 if (sc->ti_hwrev == TI_HWREV_TIGON) 1404 rcb->ti_flags = 0; 1405 else 1406 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1407#if NVLAN > 0 1408 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1409#endif 1410 if (sc->arpcom.ac_if.if_hwassist) 1411 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1412 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1413 rcb->ti_max_len = TI_TX_RING_CNT; 1414 if (sc->ti_hwrev == TI_HWREV_TIGON) 1415 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1416 else 1417 TI_HOSTADDR(rcb->ti_hostaddr) = 1418 vtophys(&sc->ti_rdata->ti_tx_ring); 1419 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1420 vtophys(&sc->ti_tx_considx); 1421 1422 /* Set up tuneables */ 1423 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1424 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1425 (sc->ti_rx_coal_ticks / 10)); 1426 else 1427 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1428 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1429 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1430 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1431 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1432 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1433 1434 /* Turn interrupts on. */ 1435 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1436 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1437 1438 /* Start CPU. */ 1439 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1440 1441 return(0); 1442} 1443 1444/* 1445 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1446 * against our list and return its name if we find a match. 1447 */ 1448static int ti_probe(dev) 1449 device_t dev; 1450{ 1451 struct ti_type *t; 1452 1453 t = ti_devs; 1454 1455 while(t->ti_name != NULL) { 1456 if ((pci_get_vendor(dev) == t->ti_vid) && 1457 (pci_get_device(dev) == t->ti_did)) { 1458 device_set_desc(dev, t->ti_name); 1459 return(0); 1460 } 1461 t++; 1462 } 1463 1464 return(ENXIO); 1465} 1466 1467static int ti_attach(dev) 1468 device_t dev; 1469{ 1470 u_int32_t command; 1471 struct ifnet *ifp; 1472 struct ti_softc *sc; 1473 int unit, error = 0, rid; 1474 1475 sc = device_get_softc(dev); 1476 unit = device_get_unit(dev); 1477 bzero(sc, sizeof(struct ti_softc)); 1478 1479 /* 1480 * Map control/status registers. 1481 */ 1482 command = pci_read_config(dev, PCIR_COMMAND, 4); 1483 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1484 pci_write_config(dev, PCIR_COMMAND, command, 4); 1485 command = pci_read_config(dev, PCIR_COMMAND, 4); 1486 1487 if (!(command & PCIM_CMD_MEMEN)) { 1488 printf("ti%d: failed to enable memory mapping!\n", unit); 1489 error = ENXIO; 1490 goto fail; 1491 } 1492 1493 rid = TI_PCI_LOMEM; 1494 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1495 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1496 1497 if (sc->ti_res == NULL) { 1498 printf ("ti%d: couldn't map memory\n", unit); 1499 error = ENXIO; 1500 goto fail; 1501 } 1502 1503 sc->ti_btag = rman_get_bustag(sc->ti_res); 1504 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1505 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1506 1507 /* Allocate interrupt */ 1508 rid = 0; 1509 1510 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1511 RF_SHAREABLE | RF_ACTIVE); 1512 1513 if (sc->ti_irq == NULL) { 1514 printf("ti%d: couldn't map interrupt\n", unit); 1515 error = ENXIO; 1516 goto fail; 1517 } 1518 1519 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1520 ti_intr, sc, &sc->ti_intrhand); 1521 1522 if (error) { 1523 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1524 bus_release_resource(dev, SYS_RES_MEMORY, 1525 TI_PCI_LOMEM, sc->ti_res); 1526 printf("ti%d: couldn't set up irq\n", unit); 1527 goto fail; 1528 } 1529 1530 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF); 1531 TI_LOCK(sc); 1532 1533 sc->ti_unit = unit; 1534 1535 if (ti_chipinit(sc)) { 1536 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1537 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1538 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1539 bus_release_resource(dev, SYS_RES_MEMORY, 1540 TI_PCI_LOMEM, sc->ti_res); 1541 error = ENXIO; 1542 goto fail; 1543 } 1544 1545 /* Zero out the NIC's on-board SRAM. */ 1546 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1547 1548 /* Init again -- zeroing memory may have clobbered some registers. */ 1549 if (ti_chipinit(sc)) { 1550 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1551 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1552 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1553 bus_release_resource(dev, SYS_RES_MEMORY, 1554 TI_PCI_LOMEM, sc->ti_res); 1555 error = ENXIO; 1556 goto fail; 1557 } 1558 1559 /* 1560 * Get station address from the EEPROM. Note: the manual states 1561 * that the MAC address is at offset 0x8c, however the data is 1562 * stored as two longwords (since that's how it's loaded into 1563 * the NIC). This means the MAC address is actually preceeded 1564 * by two zero bytes. We need to skip over those. 1565 */ 1566 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1567 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1568 printf("ti%d: failed to read station address\n", unit); 1569 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1570 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1571 bus_release_resource(dev, SYS_RES_MEMORY, 1572 TI_PCI_LOMEM, sc->ti_res); 1573 error = ENXIO; 1574 goto fail; 1575 } 1576 1577 /* 1578 * A Tigon chip was detected. Inform the world. 1579 */ 1580 printf("ti%d: Ethernet address: %6D\n", unit, 1581 sc->arpcom.ac_enaddr, ":"); 1582 1583 /* Allocate the general information block and ring buffers. */ 1584 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1585 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1586 1587 if (sc->ti_rdata == NULL) { 1588 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1589 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1590 bus_release_resource(dev, SYS_RES_MEMORY, 1591 TI_PCI_LOMEM, sc->ti_res); 1592 error = ENXIO; 1593 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1594 goto fail; 1595 } 1596 1597 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1598 1599 /* Try to allocate memory for jumbo buffers. */ 1600 if (ti_alloc_jumbo_mem(sc)) { 1601 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1602 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1603 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1604 bus_release_resource(dev, SYS_RES_MEMORY, 1605 TI_PCI_LOMEM, sc->ti_res); 1606 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1607 M_DEVBUF); 1608 error = ENXIO; 1609 goto fail; 1610 } 1611 1612 /* 1613 * We really need a better way to tell a 1000baseTX card 1614 * from a 1000baseSX one, since in theory there could be 1615 * OEMed 1000baseTX cards from lame vendors who aren't 1616 * clever enough to change the PCI ID. For the moment 1617 * though, the AceNIC is the only copper card available. 1618 */ 1619 if (pci_get_vendor(dev) == ALT_VENDORID && 1620 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1621 sc->ti_copper = 1; 1622 /* Ok, it's not the only copper card available. */ 1623 if (pci_get_vendor(dev) == NG_VENDORID && 1624 pci_get_device(dev) == NG_DEVICEID_GA620T) 1625 sc->ti_copper = 1; 1626 1627 /* Set default tuneable values. */ 1628 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1629 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1630 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1631 sc->ti_rx_max_coal_bds = 64; 1632 sc->ti_tx_max_coal_bds = 128; 1633 sc->ti_tx_buf_ratio = 21; 1634 1635 /* Set up ifnet structure */ 1636 ifp = &sc->arpcom.ac_if; 1637 ifp->if_softc = sc; 1638 ifp->if_unit = sc->ti_unit; 1639 ifp->if_name = "ti"; 1640 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1641 ifp->if_ioctl = ti_ioctl; 1642 ifp->if_output = ether_output; 1643 ifp->if_start = ti_start; 1644 ifp->if_watchdog = ti_watchdog; 1645 ifp->if_init = ti_init; 1646 ifp->if_mtu = ETHERMTU; 1647 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1648 1649 /* Set up ifmedia support. */ 1650 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1651 if (sc->ti_copper) { 1652 /* 1653 * Copper cards allow manual 10/100 mode selection, 1654 * but not manual 1000baseTX mode selection. Why? 1655 * Becuase currently there's no way to specify the 1656 * master/slave setting through the firmware interface, 1657 * so Alteon decided to just bag it and handle it 1658 * via autonegotiation. 1659 */ 1660 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1661 ifmedia_add(&sc->ifmedia, 1662 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1663 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1664 ifmedia_add(&sc->ifmedia, 1665 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1666 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 1667 ifmedia_add(&sc->ifmedia, 1668 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 1669 } else { 1670 /* Fiber cards don't support 10/100 modes. */ 1671 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1672 ifmedia_add(&sc->ifmedia, 1673 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1674 } 1675 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1676 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1677 1678 /* 1679 * Call MI attach routine. 1680 */ 1681 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1682 TI_UNLOCK(sc); 1683 return(0); 1684 1685fail: 1686 TI_UNLOCK(sc); 1687 mtx_destroy(&sc->ti_mtx); 1688 return(error); 1689} 1690 1691static int ti_detach(dev) 1692 device_t dev; 1693{ 1694 struct ti_softc *sc; 1695 struct ifnet *ifp; 1696 1697 1698 sc = device_get_softc(dev); 1699 TI_LOCK(sc); 1700 ifp = &sc->arpcom.ac_if; 1701 1702 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1703 ti_stop(sc); 1704 1705 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1706 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1707 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1708 1709 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1710 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1711 ifmedia_removeall(&sc->ifmedia); 1712 1713 TI_UNLOCK(sc); 1714 mtx_destroy(&sc->ti_mtx); 1715 1716 return(0); 1717} 1718 1719/* 1720 * Frame reception handling. This is called if there's a frame 1721 * on the receive return list. 1722 * 1723 * Note: we have to be able to handle three possibilities here: 1724 * 1) the frame is from the mini receive ring (can only happen) 1725 * on Tigon 2 boards) 1726 * 2) the frame is from the jumbo recieve ring 1727 * 3) the frame is from the standard receive ring 1728 */ 1729 1730static void ti_rxeof(sc) 1731 struct ti_softc *sc; 1732{ 1733 struct ifnet *ifp; 1734 struct ti_cmd_desc cmd; 1735 1736 ifp = &sc->arpcom.ac_if; 1737 1738 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1739 struct ti_rx_desc *cur_rx; 1740 u_int32_t rxidx; 1741 struct ether_header *eh; 1742 struct mbuf *m = NULL; 1743#if NVLAN > 0 1744 u_int16_t vlan_tag = 0; 1745 int have_tag = 0; 1746#endif 1747 1748 cur_rx = 1749 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1750 rxidx = cur_rx->ti_idx; 1751 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1752 1753#if NVLAN > 0 1754 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1755 have_tag = 1; 1756 vlan_tag = cur_rx->ti_vlan_tag; 1757 } 1758#endif 1759 1760 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1761 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1762 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1763 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1764 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1765 ifp->if_ierrors++; 1766 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1767 continue; 1768 } 1769 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1770 ifp->if_ierrors++; 1771 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1772 continue; 1773 } 1774 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1775 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1776 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1777 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1778 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1779 ifp->if_ierrors++; 1780 ti_newbuf_mini(sc, sc->ti_mini, m); 1781 continue; 1782 } 1783 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1784 ifp->if_ierrors++; 1785 ti_newbuf_mini(sc, sc->ti_mini, m); 1786 continue; 1787 } 1788 } else { 1789 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1790 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1791 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1792 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1793 ifp->if_ierrors++; 1794 ti_newbuf_std(sc, sc->ti_std, m); 1795 continue; 1796 } 1797 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1798 ifp->if_ierrors++; 1799 ti_newbuf_std(sc, sc->ti_std, m); 1800 continue; 1801 } 1802 } 1803 1804 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1805 ifp->if_ipackets++; 1806 eh = mtod(m, struct ether_header *); 1807 m->m_pkthdr.rcvif = ifp; 1808 1809 /* Remove header from mbuf and pass it on. */ 1810 m_adj(m, sizeof(struct ether_header)); 1811 1812 if (ifp->if_hwassist) { 1813 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1814 CSUM_DATA_VALID; 1815 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1816 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1817 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1818 } 1819 1820#if NVLAN > 0 1821 /* 1822 * If we received a packet with a vlan tag, pass it 1823 * to vlan_input() instead of ether_input(). 1824 */ 1825 if (have_tag) { 1826 vlan_input_tag(eh, m, vlan_tag); 1827 have_tag = vlan_tag = 0; 1828 continue; 1829 } 1830#endif 1831 ether_input(ifp, eh, m); 1832 } 1833 1834 /* Only necessary on the Tigon 1. */ 1835 if (sc->ti_hwrev == TI_HWREV_TIGON) 1836 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1837 sc->ti_rx_saved_considx); 1838 1839 TI_UPDATE_STDPROD(sc, sc->ti_std); 1840 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1841 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1842 1843 return; 1844} 1845 1846static void ti_txeof(sc) 1847 struct ti_softc *sc; 1848{ 1849 struct ti_tx_desc *cur_tx = NULL; 1850 struct ifnet *ifp; 1851 1852 ifp = &sc->arpcom.ac_if; 1853 1854 /* 1855 * Go through our tx ring and free mbufs for those 1856 * frames that have been sent. 1857 */ 1858 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1859 u_int32_t idx = 0; 1860 1861 idx = sc->ti_tx_saved_considx; 1862 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1863 if (idx > 383) 1864 CSR_WRITE_4(sc, TI_WINBASE, 1865 TI_TX_RING_BASE + 6144); 1866 else if (idx > 255) 1867 CSR_WRITE_4(sc, TI_WINBASE, 1868 TI_TX_RING_BASE + 4096); 1869 else if (idx > 127) 1870 CSR_WRITE_4(sc, TI_WINBASE, 1871 TI_TX_RING_BASE + 2048); 1872 else 1873 CSR_WRITE_4(sc, TI_WINBASE, 1874 TI_TX_RING_BASE); 1875 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1876 } else 1877 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1878 if (cur_tx->ti_flags & TI_BDFLAG_END) 1879 ifp->if_opackets++; 1880 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1881 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1882 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1883 } 1884 sc->ti_txcnt--; 1885 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1886 ifp->if_timer = 0; 1887 } 1888 1889 if (cur_tx != NULL) 1890 ifp->if_flags &= ~IFF_OACTIVE; 1891 1892 return; 1893} 1894 1895static void ti_intr(xsc) 1896 void *xsc; 1897{ 1898 struct ti_softc *sc; 1899 struct ifnet *ifp; 1900 1901 sc = xsc; 1902 TI_LOCK(sc); 1903 ifp = &sc->arpcom.ac_if; 1904 1905#ifdef notdef 1906 /* Avoid this for now -- checking this register is expensive. */ 1907 /* Make sure this is really our interrupt. */ 1908 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 1909 TI_UNLOCK(sc); 1910 return; 1911 } 1912#endif 1913 1914 /* Ack interrupt and stop others from occuring. */ 1915 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1916 1917 if (ifp->if_flags & IFF_RUNNING) { 1918 /* Check RX return ring producer/consumer */ 1919 ti_rxeof(sc); 1920 1921 /* Check TX ring producer/consumer */ 1922 ti_txeof(sc); 1923 } 1924 1925 ti_handle_events(sc); 1926 1927 /* Re-enable interrupts. */ 1928 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1929 1930 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1931 ti_start(ifp); 1932 1933 TI_UNLOCK(sc); 1934 1935 return; 1936} 1937 1938static void ti_stats_update(sc) 1939 struct ti_softc *sc; 1940{ 1941 struct ifnet *ifp; 1942 1943 ifp = &sc->arpcom.ac_if; 1944 1945 ifp->if_collisions += 1946 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1947 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1948 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1949 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1950 ifp->if_collisions; 1951 1952 return; 1953} 1954 1955/* 1956 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1957 * pointers to descriptors. 1958 */ 1959static int ti_encap(sc, m_head, txidx) 1960 struct ti_softc *sc; 1961 struct mbuf *m_head; 1962 u_int32_t *txidx; 1963{ 1964 struct ti_tx_desc *f = NULL; 1965 struct mbuf *m; 1966 u_int32_t frag, cur, cnt = 0; 1967 u_int16_t csum_flags = 0; 1968#if NVLAN > 0 1969 struct ifvlan *ifv = NULL; 1970 1971 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1972 m_head->m_pkthdr.rcvif != NULL && 1973 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1974 ifv = m_head->m_pkthdr.rcvif->if_softc; 1975#endif 1976 1977 m = m_head; 1978 cur = frag = *txidx; 1979 1980 if (m_head->m_pkthdr.csum_flags) { 1981 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1982 csum_flags |= TI_BDFLAG_IP_CKSUM; 1983 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1984 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1985 if (m_head->m_flags & M_LASTFRAG) 1986 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1987 else if (m_head->m_flags & M_FRAG) 1988 csum_flags |= TI_BDFLAG_IP_FRAG; 1989 } 1990 /* 1991 * Start packing the mbufs in this chain into 1992 * the fragment pointers. Stop when we run out 1993 * of fragments or hit the end of the mbuf chain. 1994 */ 1995 for (m = m_head; m != NULL; m = m->m_next) { 1996 if (m->m_len != 0) { 1997 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1998 if (frag > 383) 1999 CSR_WRITE_4(sc, TI_WINBASE, 2000 TI_TX_RING_BASE + 6144); 2001 else if (frag > 255) 2002 CSR_WRITE_4(sc, TI_WINBASE, 2003 TI_TX_RING_BASE + 4096); 2004 else if (frag > 127) 2005 CSR_WRITE_4(sc, TI_WINBASE, 2006 TI_TX_RING_BASE + 2048); 2007 else 2008 CSR_WRITE_4(sc, TI_WINBASE, 2009 TI_TX_RING_BASE); 2010 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2011 } else 2012 f = &sc->ti_rdata->ti_tx_ring[frag]; 2013 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2014 break; 2015 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2016 f->ti_len = m->m_len; 2017 f->ti_flags = csum_flags; 2018#if NVLAN > 0 2019 if (ifv != NULL) { 2020 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2021 f->ti_vlan_tag = ifv->ifv_tag; 2022 } else { 2023 f->ti_vlan_tag = 0; 2024 } 2025#endif 2026 /* 2027 * Sanity check: avoid coming within 16 descriptors 2028 * of the end of the ring. 2029 */ 2030 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2031 return(ENOBUFS); 2032 cur = frag; 2033 TI_INC(frag, TI_TX_RING_CNT); 2034 cnt++; 2035 } 2036 } 2037 2038 if (m != NULL) 2039 return(ENOBUFS); 2040 2041 if (frag == sc->ti_tx_saved_considx) 2042 return(ENOBUFS); 2043 2044 if (sc->ti_hwrev == TI_HWREV_TIGON) 2045 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2046 TI_BDFLAG_END; 2047 else 2048 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2049 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2050 sc->ti_txcnt += cnt; 2051 2052 *txidx = frag; 2053 2054 return(0); 2055} 2056 2057/* 2058 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2059 * to the mbuf data regions directly in the transmit descriptors. 2060 */ 2061static void ti_start(ifp) 2062 struct ifnet *ifp; 2063{ 2064 struct ti_softc *sc; 2065 struct mbuf *m_head = NULL; 2066 u_int32_t prodidx = 0; 2067 2068 sc = ifp->if_softc; 2069 TI_LOCK(sc); 2070 2071 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2072 2073 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2074 IF_DEQUEUE(&ifp->if_snd, m_head); 2075 if (m_head == NULL) 2076 break; 2077 2078 /* 2079 * XXX 2080 * safety overkill. If this is a fragmented packet chain 2081 * with delayed TCP/UDP checksums, then only encapsulate 2082 * it if we have enough descriptors to handle the entire 2083 * chain at once. 2084 * (paranoia -- may not actually be needed) 2085 */ 2086 if (m_head->m_flags & M_FIRSTFRAG && 2087 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2088 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2089 m_head->m_pkthdr.csum_data + 16) { 2090 IF_PREPEND(&ifp->if_snd, m_head); 2091 ifp->if_flags |= IFF_OACTIVE; 2092 break; 2093 } 2094 } 2095 2096 /* 2097 * Pack the data into the transmit ring. If we 2098 * don't have room, set the OACTIVE flag and wait 2099 * for the NIC to drain the ring. 2100 */ 2101 if (ti_encap(sc, m_head, &prodidx)) { 2102 IF_PREPEND(&ifp->if_snd, m_head); 2103 ifp->if_flags |= IFF_OACTIVE; 2104 break; 2105 } 2106 2107 /* 2108 * If there's a BPF listener, bounce a copy of this frame 2109 * to him. 2110 */ 2111 if (ifp->if_bpf) 2112 bpf_mtap(ifp, m_head); 2113 } 2114 2115 /* Transmit */ 2116 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2117 2118 /* 2119 * Set a timeout in case the chip goes out to lunch. 2120 */ 2121 ifp->if_timer = 5; 2122 TI_UNLOCK(sc); 2123 2124 return; 2125} 2126 2127static void ti_init(xsc) 2128 void *xsc; 2129{ 2130 struct ti_softc *sc = xsc; 2131 2132 /* Cancel pending I/O and flush buffers. */ 2133 ti_stop(sc); 2134 2135 TI_LOCK(sc); 2136 /* Init the gen info block, ring control blocks and firmware. */ 2137 if (ti_gibinit(sc)) { 2138 printf("ti%d: initialization failure\n", sc->ti_unit); 2139 TI_UNLOCK(sc); 2140 return; 2141 } 2142 2143 TI_UNLOCK(sc); 2144 2145 return; 2146} 2147 2148static void ti_init2(sc) 2149 struct ti_softc *sc; 2150{ 2151 struct ti_cmd_desc cmd; 2152 struct ifnet *ifp; 2153 u_int16_t *m; 2154 struct ifmedia *ifm; 2155 int tmp; 2156 2157 ifp = &sc->arpcom.ac_if; 2158 2159 /* Specify MTU and interface index. */ 2160 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2161 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2162 ETHER_HDR_LEN + ETHER_CRC_LEN); 2163 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2164 2165 /* Load our MAC address. */ 2166 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2167 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2168 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2169 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2170 2171 /* Enable or disable promiscuous mode as needed. */ 2172 if (ifp->if_flags & IFF_PROMISC) { 2173 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2174 } else { 2175 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2176 } 2177 2178 /* Program multicast filter. */ 2179 ti_setmulti(sc); 2180 2181 /* 2182 * If this is a Tigon 1, we should tell the 2183 * firmware to use software packet filtering. 2184 */ 2185 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2186 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2187 } 2188 2189 /* Init RX ring. */ 2190 ti_init_rx_ring_std(sc); 2191 2192 /* Init jumbo RX ring. */ 2193 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2194 ti_init_rx_ring_jumbo(sc); 2195 2196 /* 2197 * If this is a Tigon 2, we can also configure the 2198 * mini ring. 2199 */ 2200 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2201 ti_init_rx_ring_mini(sc); 2202 2203 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2204 sc->ti_rx_saved_considx = 0; 2205 2206 /* Init TX ring. */ 2207 ti_init_tx_ring(sc); 2208 2209 /* Tell firmware we're alive. */ 2210 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2211 2212 /* Enable host interrupts. */ 2213 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2214 2215 ifp->if_flags |= IFF_RUNNING; 2216 ifp->if_flags &= ~IFF_OACTIVE; 2217 2218 /* 2219 * Make sure to set media properly. We have to do this 2220 * here since we have to issue commands in order to set 2221 * the link negotiation and we can't issue commands until 2222 * the firmware is running. 2223 */ 2224 ifm = &sc->ifmedia; 2225 tmp = ifm->ifm_media; 2226 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2227 ti_ifmedia_upd(ifp); 2228 ifm->ifm_media = tmp; 2229 2230 return; 2231} 2232 2233/* 2234 * Set media options. 2235 */ 2236static int ti_ifmedia_upd(ifp) 2237 struct ifnet *ifp; 2238{ 2239 struct ti_softc *sc; 2240 struct ifmedia *ifm; 2241 struct ti_cmd_desc cmd; 2242 2243 sc = ifp->if_softc; 2244 ifm = &sc->ifmedia; 2245 2246 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2247 return(EINVAL); 2248 2249 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2250 case IFM_AUTO: 2251 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2252 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2253 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2254 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2255 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2256 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2257 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2258 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2259 break; 2260 case IFM_1000_SX: 2261 case IFM_1000_TX: 2262 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2263 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2264 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2265 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2266 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2267 } 2268 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2269 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2270 break; 2271 case IFM_100_FX: 2272 case IFM_10_FL: 2273 case IFM_100_TX: 2274 case IFM_10_T: 2275 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2276 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2277 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2278 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2279 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2280 } else { 2281 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2282 } 2283 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2284 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2285 } else { 2286 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2287 } 2288 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2289 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2290 break; 2291 } 2292 2293 return(0); 2294} 2295 2296/* 2297 * Report current media status. 2298 */ 2299static void ti_ifmedia_sts(ifp, ifmr) 2300 struct ifnet *ifp; 2301 struct ifmediareq *ifmr; 2302{ 2303 struct ti_softc *sc; 2304 u_int32_t media = 0; 2305 2306 sc = ifp->if_softc; 2307 2308 ifmr->ifm_status = IFM_AVALID; 2309 ifmr->ifm_active = IFM_ETHER; 2310 2311 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2312 return; 2313 2314 ifmr->ifm_status |= IFM_ACTIVE; 2315 2316 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2317 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2318 if (sc->ti_copper) 2319 ifmr->ifm_active |= IFM_1000_TX; 2320 else 2321 ifmr->ifm_active |= IFM_1000_SX; 2322 if (media & TI_GLNK_FULL_DUPLEX) 2323 ifmr->ifm_active |= IFM_FDX; 2324 else 2325 ifmr->ifm_active |= IFM_HDX; 2326 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2327 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2328 if (sc->ti_copper) { 2329 if (media & TI_LNK_100MB) 2330 ifmr->ifm_active |= IFM_100_TX; 2331 if (media & TI_LNK_10MB) 2332 ifmr->ifm_active |= IFM_10_T; 2333 } else { 2334 if (media & TI_LNK_100MB) 2335 ifmr->ifm_active |= IFM_100_FX; 2336 if (media & TI_LNK_10MB) 2337 ifmr->ifm_active |= IFM_10_FL; 2338 } 2339 if (media & TI_LNK_FULL_DUPLEX) 2340 ifmr->ifm_active |= IFM_FDX; 2341 if (media & TI_LNK_HALF_DUPLEX) 2342 ifmr->ifm_active |= IFM_HDX; 2343 } 2344 2345 return; 2346} 2347 2348static int ti_ioctl(ifp, command, data) 2349 struct ifnet *ifp; 2350 u_long command; 2351 caddr_t data; 2352{ 2353 struct ti_softc *sc = ifp->if_softc; 2354 struct ifreq *ifr = (struct ifreq *) data; 2355 int error = 0; 2356 struct ti_cmd_desc cmd; 2357 2358 TI_LOCK(sc); 2359 2360 switch(command) { 2361 case SIOCSIFADDR: 2362 case SIOCGIFADDR: 2363 error = ether_ioctl(ifp, command, data); 2364 break; 2365 case SIOCSIFMTU: 2366 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2367 error = EINVAL; 2368 else { 2369 ifp->if_mtu = ifr->ifr_mtu; 2370 ti_init(sc); 2371 } 2372 break; 2373 case SIOCSIFFLAGS: 2374 if (ifp->if_flags & IFF_UP) { 2375 /* 2376 * If only the state of the PROMISC flag changed, 2377 * then just use the 'set promisc mode' command 2378 * instead of reinitializing the entire NIC. Doing 2379 * a full re-init means reloading the firmware and 2380 * waiting for it to start up, which may take a 2381 * second or two. 2382 */ 2383 if (ifp->if_flags & IFF_RUNNING && 2384 ifp->if_flags & IFF_PROMISC && 2385 !(sc->ti_if_flags & IFF_PROMISC)) { 2386 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2387 TI_CMD_CODE_PROMISC_ENB, 0); 2388 } else if (ifp->if_flags & IFF_RUNNING && 2389 !(ifp->if_flags & IFF_PROMISC) && 2390 sc->ti_if_flags & IFF_PROMISC) { 2391 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2392 TI_CMD_CODE_PROMISC_DIS, 0); 2393 } else 2394 ti_init(sc); 2395 } else { 2396 if (ifp->if_flags & IFF_RUNNING) { 2397 ti_stop(sc); 2398 } 2399 } 2400 sc->ti_if_flags = ifp->if_flags; 2401 error = 0; 2402 break; 2403 case SIOCADDMULTI: 2404 case SIOCDELMULTI: 2405 if (ifp->if_flags & IFF_RUNNING) { 2406 ti_setmulti(sc); 2407 error = 0; 2408 } 2409 break; 2410 case SIOCSIFMEDIA: 2411 case SIOCGIFMEDIA: 2412 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2413 break; 2414 default: 2415 error = EINVAL; 2416 break; 2417 } 2418 2419 TI_UNLOCK(sc); 2420 2421 return(error); 2422} 2423 2424static void ti_watchdog(ifp) 2425 struct ifnet *ifp; 2426{ 2427 struct ti_softc *sc; 2428 2429 sc = ifp->if_softc; 2430 TI_LOCK(sc); 2431 2432 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2433 ti_stop(sc); 2434 ti_init(sc); 2435 2436 ifp->if_oerrors++; 2437 TI_UNLOCK(sc); 2438 2439 return; 2440} 2441 2442/* 2443 * Stop the adapter and free any mbufs allocated to the 2444 * RX and TX lists. 2445 */ 2446static void ti_stop(sc) 2447 struct ti_softc *sc; 2448{ 2449 struct ifnet *ifp; 2450 struct ti_cmd_desc cmd; 2451 2452 TI_LOCK(sc); 2453 2454 ifp = &sc->arpcom.ac_if; 2455 2456 /* Disable host interrupts. */ 2457 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2458 /* 2459 * Tell firmware we're shutting down. 2460 */ 2461 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2462 2463 /* Halt and reinitialize. */ 2464 ti_chipinit(sc); 2465 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2466 ti_chipinit(sc); 2467 2468 /* Free the RX lists. */ 2469 ti_free_rx_ring_std(sc); 2470 2471 /* Free jumbo RX list. */ 2472 ti_free_rx_ring_jumbo(sc); 2473 2474 /* Free mini RX list. */ 2475 ti_free_rx_ring_mini(sc); 2476 2477 /* Free TX buffers. */ 2478 ti_free_tx_ring(sc); 2479 2480 sc->ti_ev_prodidx.ti_idx = 0; 2481 sc->ti_return_prodidx.ti_idx = 0; 2482 sc->ti_tx_considx.ti_idx = 0; 2483 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2484 2485 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2486 TI_UNLOCK(sc); 2487 2488 return; 2489} 2490 2491/* 2492 * Stop all chip I/O so that the kernel's probe routines don't 2493 * get confused by errant DMAs when rebooting. 2494 */ 2495static void ti_shutdown(dev) 2496 device_t dev; 2497{ 2498 struct ti_softc *sc; 2499 2500 sc = device_get_softc(dev); 2501 TI_LOCK(sc); 2502 ti_chipinit(sc); 2503 TI_UNLOCK(sc); 2504 2505 return; 2506} 2507