if_ti.c revision 67164
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_ti.c 67164 2000-10-15 14:19:01Z phk $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "vlan.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90#include <sys/queue.h> 91 92#include <net/if.h> 93#include <net/if_arp.h> 94#include <net/ethernet.h> 95#include <net/if_dl.h> 96#include <net/if_media.h> 97 98#include <net/bpf.h> 99 100#if NVLAN > 0 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103#endif 104 105#include <netinet/in_systm.h> 106#include <netinet/in.h> 107#include <netinet/ip.h> 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/bus_memio.h> 112#include <machine/bus.h> 113#include <machine/resource.h> 114#include <sys/bus.h> 115#include <sys/rman.h> 116 117#include <pci/pcireg.h> 118#include <pci/pcivar.h> 119 120#include <pci/if_tireg.h> 121#include <pci/ti_fw.h> 122#include <pci/ti_fw2.h> 123 124#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 125 126#if !defined(lint) 127static const char rcsid[] = 128 "$FreeBSD: head/sys/dev/ti/if_ti.c 67164 2000-10-15 14:19:01Z phk $"; 129#endif 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134 135static struct ti_type ti_devs[] = { 136 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 137 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 138 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 139 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 140 { TC_VENDORID, TC_DEVICEID_3C985, 141 "3Com 3c985-SX Gigabit Ethernet" }, 142 { NG_VENDORID, NG_DEVICEID_GA620, 143 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 144 { NG_VENDORID, NG_DEVICEID_GA620T, 145 "Netgear GA620 1000baseT Gigabit Ethernet" }, 146 { SGI_VENDORID, SGI_DEVICEID_TIGON, 147 "Silicon Graphics Gigabit Ethernet" }, 148 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 149 "Farallon PN9000SX Gigabit Ethernet" }, 150 { 0, 0, NULL } 151}; 152 153static int ti_probe __P((device_t)); 154static int ti_attach __P((device_t)); 155static int ti_detach __P((device_t)); 156static void ti_txeof __P((struct ti_softc *)); 157static void ti_rxeof __P((struct ti_softc *)); 158 159static void ti_stats_update __P((struct ti_softc *)); 160static int ti_encap __P((struct ti_softc *, struct mbuf *, 161 u_int32_t *)); 162 163static void ti_intr __P((void *)); 164static void ti_start __P((struct ifnet *)); 165static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 166static void ti_init __P((void *)); 167static void ti_init2 __P((struct ti_softc *)); 168static void ti_stop __P((struct ti_softc *)); 169static void ti_watchdog __P((struct ifnet *)); 170static void ti_shutdown __P((device_t)); 171static int ti_ifmedia_upd __P((struct ifnet *)); 172static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 173 174static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 175static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 176 int, u_int8_t *)); 177static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 178 179static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 180static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 181static void ti_setmulti __P((struct ti_softc *)); 182 183static void ti_mem __P((struct ti_softc *, u_int32_t, 184 u_int32_t, caddr_t)); 185static void ti_loadfw __P((struct ti_softc *)); 186static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 187static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 188 caddr_t, int)); 189static void ti_handle_events __P((struct ti_softc *)); 190static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 191static void *ti_jalloc __P((struct ti_softc *)); 192static void ti_jfree __P((caddr_t, void *)); 193static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 194static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 195static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 196static int ti_init_rx_ring_std __P((struct ti_softc *)); 197static void ti_free_rx_ring_std __P((struct ti_softc *)); 198static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 199static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 200static int ti_init_rx_ring_mini __P((struct ti_softc *)); 201static void ti_free_rx_ring_mini __P((struct ti_softc *)); 202static void ti_free_tx_ring __P((struct ti_softc *)); 203static int ti_init_tx_ring __P((struct ti_softc *)); 204 205static int ti_64bitslot_war __P((struct ti_softc *)); 206static int ti_chipinit __P((struct ti_softc *)); 207static int ti_gibinit __P((struct ti_softc *)); 208 209static device_method_t ti_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, ti_probe), 212 DEVMETHOD(device_attach, ti_attach), 213 DEVMETHOD(device_detach, ti_detach), 214 DEVMETHOD(device_shutdown, ti_shutdown), 215 { 0, 0 } 216}; 217 218static driver_t ti_driver = { 219 "ti", 220 ti_methods, 221 sizeof(struct ti_softc) 222}; 223 224static devclass_t ti_devclass; 225 226DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 227 228/* 229 * Send an instruction or address to the EEPROM, check for ACK. 230 */ 231static u_int32_t ti_eeprom_putbyte(sc, byte) 232 struct ti_softc *sc; 233 int byte; 234{ 235 register int i, ack = 0; 236 237 /* 238 * Make sure we're in TX mode. 239 */ 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 241 242 /* 243 * Feed in each bit and stobe the clock. 244 */ 245 for (i = 0x80; i; i >>= 1) { 246 if (byte & i) { 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 } else { 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 250 } 251 DELAY(1); 252 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 DELAY(1); 254 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 255 } 256 257 /* 258 * Turn off TX mode. 259 */ 260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 261 262 /* 263 * Check for ack. 264 */ 265 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 267 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 268 269 return(ack); 270} 271 272/* 273 * Read a byte of data stored in the EEPROM at address 'addr.' 274 * We have to send two address bytes since the EEPROM can hold 275 * more than 256 bytes of data. 276 */ 277static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 278 struct ti_softc *sc; 279 int addr; 280 u_int8_t *dest; 281{ 282 register int i; 283 u_int8_t byte = 0; 284 285 EEPROM_START; 286 287 /* 288 * Send write control code to EEPROM. 289 */ 290 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 291 printf("ti%d: failed to send write command, status: %x\n", 292 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 293 return(1); 294 } 295 296 /* 297 * Send first byte of address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 300 printf("ti%d: failed to send address, status: %x\n", 301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 /* 305 * Send second byte address of byte we want to read. 306 */ 307 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 308 printf("ti%d: failed to send address, status: %x\n", 309 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 310 return(1); 311 } 312 313 EEPROM_STOP; 314 EEPROM_START; 315 /* 316 * Send read control code to EEPROM. 317 */ 318 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 319 printf("ti%d: failed to send read command, status: %x\n", 320 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 321 return(1); 322 } 323 324 /* 325 * Start reading bits from EEPROM. 326 */ 327 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 328 for (i = 0x80; i; i >>= 1) { 329 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 330 DELAY(1); 331 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 332 byte |= i; 333 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 334 DELAY(1); 335 } 336 337 EEPROM_STOP; 338 339 /* 340 * No ACK generated for read, so just return byte. 341 */ 342 343 *dest = byte; 344 345 return(0); 346} 347 348/* 349 * Read a sequence of bytes from the EEPROM. 350 */ 351static int ti_read_eeprom(sc, dest, off, cnt) 352 struct ti_softc *sc; 353 caddr_t dest; 354 int off; 355 int cnt; 356{ 357 int err = 0, i; 358 u_int8_t byte = 0; 359 360 for (i = 0; i < cnt; i++) { 361 err = ti_eeprom_getbyte(sc, off + i, &byte); 362 if (err) 363 break; 364 *(dest + i) = byte; 365 } 366 367 return(err ? 1 : 0); 368} 369 370/* 371 * NIC memory access function. Can be used to either clear a section 372 * of NIC local memory or (if buf is non-NULL) copy data into it. 373 */ 374static void ti_mem(sc, addr, len, buf) 375 struct ti_softc *sc; 376 u_int32_t addr, len; 377 caddr_t buf; 378{ 379 int segptr, segsize, cnt; 380 caddr_t ti_winbase, ptr; 381 382 segptr = addr; 383 cnt = len; 384 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 385 ptr = buf; 386 387 while(cnt) { 388 if (cnt < TI_WINLEN) 389 segsize = cnt; 390 else 391 segsize = TI_WINLEN - (segptr % TI_WINLEN); 392 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 393 if (buf == NULL) 394 bzero((char *)ti_winbase + (segptr & 395 (TI_WINLEN - 1)), segsize); 396 else { 397 bcopy((char *)ptr, (char *)ti_winbase + 398 (segptr & (TI_WINLEN - 1)), segsize); 399 ptr += segsize; 400 } 401 segptr += segsize; 402 cnt -= segsize; 403 } 404 405 return; 406} 407 408/* 409 * Load firmware image into the NIC. Check that the firmware revision 410 * is acceptable and see if we want the firmware for the Tigon 1 or 411 * Tigon 2. 412 */ 413static void ti_loadfw(sc) 414 struct ti_softc *sc; 415{ 416 switch(sc->ti_hwrev) { 417 case TI_HWREV_TIGON: 418 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 419 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 420 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 421 printf("ti%d: firmware revision mismatch; want " 422 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 423 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 424 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 425 tigonFwReleaseMinor, tigonFwReleaseFix); 426 return; 427 } 428 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 429 (caddr_t)tigonFwText); 430 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 431 (caddr_t)tigonFwData); 432 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 433 (caddr_t)tigonFwRodata); 434 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 435 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 437 break; 438 case TI_HWREV_TIGON_II: 439 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 440 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 441 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 442 printf("ti%d: firmware revision mismatch; want " 443 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 444 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 445 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 446 tigon2FwReleaseMinor, tigon2FwReleaseFix); 447 return; 448 } 449 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 450 (caddr_t)tigon2FwText); 451 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 452 (caddr_t)tigon2FwData); 453 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 454 (caddr_t)tigon2FwRodata); 455 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 456 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 457 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 458 break; 459 default: 460 printf("ti%d: can't load firmware: unknown hardware rev\n", 461 sc->ti_unit); 462 break; 463 } 464 465 return; 466} 467 468/* 469 * Send the NIC a command via the command ring. 470 */ 471static void ti_cmd(sc, cmd) 472 struct ti_softc *sc; 473 struct ti_cmd_desc *cmd; 474{ 475 u_int32_t index; 476 477 if (sc->ti_rdata->ti_cmd_ring == NULL) 478 return; 479 480 index = sc->ti_cmd_saved_prodidx; 481 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 482 TI_INC(index, TI_CMD_RING_CNT); 483 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 484 sc->ti_cmd_saved_prodidx = index; 485 486 return; 487} 488 489/* 490 * Send the NIC an extended command. The 'len' parameter specifies the 491 * number of command slots to include after the initial command. 492 */ 493static void ti_cmd_ext(sc, cmd, arg, len) 494 struct ti_softc *sc; 495 struct ti_cmd_desc *cmd; 496 caddr_t arg; 497 int len; 498{ 499 u_int32_t index; 500 register int i; 501 502 if (sc->ti_rdata->ti_cmd_ring == NULL) 503 return; 504 505 index = sc->ti_cmd_saved_prodidx; 506 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 507 TI_INC(index, TI_CMD_RING_CNT); 508 for (i = 0; i < len; i++) { 509 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 510 *(u_int32_t *)(&arg[i * 4])); 511 TI_INC(index, TI_CMD_RING_CNT); 512 } 513 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 514 sc->ti_cmd_saved_prodidx = index; 515 516 return; 517} 518 519/* 520 * Handle events that have triggered interrupts. 521 */ 522static void ti_handle_events(sc) 523 struct ti_softc *sc; 524{ 525 struct ti_event_desc *e; 526 527 if (sc->ti_rdata->ti_event_ring == NULL) 528 return; 529 530 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 531 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 532 switch(e->ti_event) { 533 case TI_EV_LINKSTAT_CHANGED: 534 sc->ti_linkstat = e->ti_code; 535 if (e->ti_code == TI_EV_CODE_LINK_UP) 536 printf("ti%d: 10/100 link up\n", sc->ti_unit); 537 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 538 printf("ti%d: gigabit link up\n", sc->ti_unit); 539 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 540 printf("ti%d: link down\n", sc->ti_unit); 541 break; 542 case TI_EV_ERROR: 543 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 544 printf("ti%d: invalid command\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 546 printf("ti%d: unknown command\n", sc->ti_unit); 547 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 548 printf("ti%d: bad config data\n", sc->ti_unit); 549 break; 550 case TI_EV_FIRMWARE_UP: 551 ti_init2(sc); 552 break; 553 case TI_EV_STATS_UPDATED: 554 ti_stats_update(sc); 555 break; 556 case TI_EV_RESET_JUMBO_RING: 557 case TI_EV_MCAST_UPDATED: 558 /* Who cares. */ 559 break; 560 default: 561 printf("ti%d: unknown event: %d\n", 562 sc->ti_unit, e->ti_event); 563 break; 564 } 565 /* Advance the consumer index. */ 566 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 567 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 568 } 569 570 return; 571} 572 573/* 574 * Memory management for the jumbo receive ring is a pain in the 575 * butt. We need to allocate at least 9018 bytes of space per frame, 576 * _and_ it has to be contiguous (unless you use the extended 577 * jumbo descriptor format). Using malloc() all the time won't 578 * work: malloc() allocates memory in powers of two, which means we 579 * would end up wasting a considerable amount of space by allocating 580 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 581 * to do our own memory management. 582 * 583 * The driver needs to allocate a contiguous chunk of memory at boot 584 * time. We then chop this up ourselves into 9K pieces and use them 585 * as external mbuf storage. 586 * 587 * One issue here is how much memory to allocate. The jumbo ring has 588 * 256 slots in it, but at 9K per slot than can consume over 2MB of 589 * RAM. This is a bit much, especially considering we also need 590 * RAM for the standard ring and mini ring (on the Tigon 2). To 591 * save space, we only actually allocate enough memory for 64 slots 592 * by default, which works out to between 500 and 600K. This can 593 * be tuned by changing a #define in if_tireg.h. 594 */ 595 596static int ti_alloc_jumbo_mem(sc) 597 struct ti_softc *sc; 598{ 599 caddr_t ptr; 600 register int i; 601 struct ti_jpool_entry *entry; 602 603 /* Grab a big chunk o' storage. */ 604 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 605 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 606 607 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 608 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 609 return(ENOBUFS); 610 } 611 612 SLIST_INIT(&sc->ti_jfree_listhead); 613 SLIST_INIT(&sc->ti_jinuse_listhead); 614 615 /* 616 * Now divide it up into 9K pieces and save the addresses 617 * in an array. Note that we play an evil trick here by using 618 * the first few bytes in the buffer to hold the the address 619 * of the softc structure for this interface. This is because 620 * ti_jfree() needs it, but it is called by the mbuf management 621 * code which will not pass it to us explicitly. 622 */ 623 ptr = sc->ti_cdata.ti_jumbo_buf; 624 for (i = 0; i < TI_JSLOTS; i++) { 625 u_int64_t **aptr; 626 aptr = (u_int64_t **)ptr; 627 aptr[0] = (u_int64_t *)sc; 628 ptr += sizeof(u_int64_t); 629 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 630 ptr += (TI_JLEN - sizeof(u_int64_t)); 631 entry = malloc(sizeof(struct ti_jpool_entry), 632 M_DEVBUF, M_NOWAIT); 633 if (entry == NULL) { 634 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 635 M_DEVBUF); 636 sc->ti_cdata.ti_jumbo_buf = NULL; 637 printf("ti%d: no memory for jumbo " 638 "buffer queue!\n", sc->ti_unit); 639 return(ENOBUFS); 640 } 641 entry->slot = i; 642 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 643 } 644 645 return(0); 646} 647 648/* 649 * Allocate a jumbo buffer. 650 */ 651static void *ti_jalloc(sc) 652 struct ti_softc *sc; 653{ 654 struct ti_jpool_entry *entry; 655 656 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 657 658 if (entry == NULL) { 659 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 660 return(NULL); 661 } 662 663 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 664 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 665 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 666} 667 668/* 669 * Release a jumbo buffer. 670 */ 671static void ti_jfree(buf, args) 672 caddr_t buf; 673 void *args; 674{ 675 struct ti_softc *sc; 676 u_int64_t **aptr; 677 int i; 678 struct ti_jpool_entry *entry; 679 680 /* Extract the softc struct pointer. */ 681 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 682 sc = (struct ti_softc *)(aptr[0]); 683 684 if (sc == NULL) 685 panic("ti_jfree: can't find softc pointer!"); 686 687 /* calculate the slot this buffer belongs to */ 688 i = ((vm_offset_t)aptr 689 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 690 691 if ((i < 0) || (i >= TI_JSLOTS)) 692 panic("ti_jfree: asked to free buffer that we don't manage!"); 693 694 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 695 if (entry == NULL) 696 panic("ti_jfree: buffer not in use!"); 697 entry->slot = i; 698 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 699 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 700 701 return; 702} 703 704 705/* 706 * Intialize a standard receive ring descriptor. 707 */ 708static int ti_newbuf_std(sc, i, m) 709 struct ti_softc *sc; 710 int i; 711 struct mbuf *m; 712{ 713 struct mbuf *m_new = NULL; 714 struct ti_rx_desc *r; 715 716 if (m == NULL) { 717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 718 if (m_new == NULL) { 719 printf("ti%d: mbuf allocation failed " 720 "-- packet dropped!\n", sc->ti_unit); 721 return(ENOBUFS); 722 } 723 724 MCLGET(m_new, M_DONTWAIT); 725 if (!(m_new->m_flags & M_EXT)) { 726 printf("ti%d: cluster allocation failed " 727 "-- packet dropped!\n", sc->ti_unit); 728 m_freem(m_new); 729 return(ENOBUFS); 730 } 731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 732 } else { 733 m_new = m; 734 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 735 m_new->m_data = m_new->m_ext.ext_buf; 736 } 737 738 m_adj(m_new, ETHER_ALIGN); 739 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 740 r = &sc->ti_rdata->ti_rx_std_ring[i]; 741 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 742 r->ti_type = TI_BDTYPE_RECV_BD; 743 r->ti_flags = 0; 744 if (sc->arpcom.ac_if.if_hwassist) 745 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 746 r->ti_len = m_new->m_len; 747 r->ti_idx = i; 748 749 return(0); 750} 751 752/* 753 * Intialize a mini receive ring descriptor. This only applies to 754 * the Tigon 2. 755 */ 756static int ti_newbuf_mini(sc, i, m) 757 struct ti_softc *sc; 758 int i; 759 struct mbuf *m; 760{ 761 struct mbuf *m_new = NULL; 762 struct ti_rx_desc *r; 763 764 if (m == NULL) { 765 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 766 if (m_new == NULL) { 767 printf("ti%d: mbuf allocation failed " 768 "-- packet dropped!\n", sc->ti_unit); 769 return(ENOBUFS); 770 } 771 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 772 } else { 773 m_new = m; 774 m_new->m_data = m_new->m_pktdat; 775 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 776 } 777 778 m_adj(m_new, ETHER_ALIGN); 779 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 780 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 781 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 782 r->ti_type = TI_BDTYPE_RECV_BD; 783 r->ti_flags = TI_BDFLAG_MINI_RING; 784 if (sc->arpcom.ac_if.if_hwassist) 785 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 786 r->ti_len = m_new->m_len; 787 r->ti_idx = i; 788 789 return(0); 790} 791 792/* 793 * Initialize a jumbo receive ring descriptor. This allocates 794 * a jumbo buffer from the pool managed internally by the driver. 795 */ 796static int ti_newbuf_jumbo(sc, i, m) 797 struct ti_softc *sc; 798 int i; 799 struct mbuf *m; 800{ 801 struct mbuf *m_new = NULL; 802 struct ti_rx_desc *r; 803 804 if (m == NULL) { 805 caddr_t *buf = NULL; 806 807 /* Allocate the mbuf. */ 808 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 809 if (m_new == NULL) { 810 printf("ti%d: mbuf allocation failed " 811 "-- packet dropped!\n", sc->ti_unit); 812 return(ENOBUFS); 813 } 814 815 /* Allocate the jumbo buffer */ 816 buf = ti_jalloc(sc); 817 if (buf == NULL) { 818 m_freem(m_new); 819 printf("ti%d: jumbo allocation failed " 820 "-- packet dropped!\n", sc->ti_unit); 821 return(ENOBUFS); 822 } 823 824 /* Attach the buffer to the mbuf. */ 825 m_new->m_data = (void *) buf; 826 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 827 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, NULL); 828 } else { 829 m_new = m; 830 m_new->m_data = m_new->m_ext.ext_buf; 831 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 832 } 833 834 m_adj(m_new, ETHER_ALIGN); 835 /* Set up the descriptor. */ 836 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 837 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 838 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 839 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 840 r->ti_flags = TI_BDFLAG_JUMBO_RING; 841 if (sc->arpcom.ac_if.if_hwassist) 842 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 843 r->ti_len = m_new->m_len; 844 r->ti_idx = i; 845 846 return(0); 847} 848 849/* 850 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 851 * that's 1MB or memory, which is a lot. For now, we fill only the first 852 * 256 ring entries and hope that our CPU is fast enough to keep up with 853 * the NIC. 854 */ 855static int ti_init_rx_ring_std(sc) 856 struct ti_softc *sc; 857{ 858 register int i; 859 struct ti_cmd_desc cmd; 860 861 for (i = 0; i < TI_SSLOTS; i++) { 862 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 863 return(ENOBUFS); 864 }; 865 866 TI_UPDATE_STDPROD(sc, i - 1); 867 sc->ti_std = i - 1; 868 869 return(0); 870} 871 872static void ti_free_rx_ring_std(sc) 873 struct ti_softc *sc; 874{ 875 register int i; 876 877 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 878 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 879 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 880 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 881 } 882 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 883 sizeof(struct ti_rx_desc)); 884 } 885 886 return; 887} 888 889static int ti_init_rx_ring_jumbo(sc) 890 struct ti_softc *sc; 891{ 892 register int i; 893 struct ti_cmd_desc cmd; 894 895 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 896 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 897 return(ENOBUFS); 898 }; 899 900 TI_UPDATE_JUMBOPROD(sc, i - 1); 901 sc->ti_jumbo = i - 1; 902 903 return(0); 904} 905 906static void ti_free_rx_ring_jumbo(sc) 907 struct ti_softc *sc; 908{ 909 register int i; 910 911 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 912 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 913 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 914 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 915 } 916 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 917 sizeof(struct ti_rx_desc)); 918 } 919 920 return; 921} 922 923static int ti_init_rx_ring_mini(sc) 924 struct ti_softc *sc; 925{ 926 register int i; 927 928 for (i = 0; i < TI_MSLOTS; i++) { 929 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 930 return(ENOBUFS); 931 }; 932 933 TI_UPDATE_MINIPROD(sc, i - 1); 934 sc->ti_mini = i - 1; 935 936 return(0); 937} 938 939static void ti_free_rx_ring_mini(sc) 940 struct ti_softc *sc; 941{ 942 register int i; 943 944 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 945 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 946 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 947 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 948 } 949 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 950 sizeof(struct ti_rx_desc)); 951 } 952 953 return; 954} 955 956static void ti_free_tx_ring(sc) 957 struct ti_softc *sc; 958{ 959 register int i; 960 961 if (sc->ti_rdata->ti_tx_ring == NULL) 962 return; 963 964 for (i = 0; i < TI_TX_RING_CNT; i++) { 965 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 966 m_freem(sc->ti_cdata.ti_tx_chain[i]); 967 sc->ti_cdata.ti_tx_chain[i] = NULL; 968 } 969 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 970 sizeof(struct ti_tx_desc)); 971 } 972 973 return; 974} 975 976static int ti_init_tx_ring(sc) 977 struct ti_softc *sc; 978{ 979 sc->ti_txcnt = 0; 980 sc->ti_tx_saved_considx = 0; 981 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 982 return(0); 983} 984 985/* 986 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 987 * but we have to support the old way too so that Tigon 1 cards will 988 * work. 989 */ 990void ti_add_mcast(sc, addr) 991 struct ti_softc *sc; 992 struct ether_addr *addr; 993{ 994 struct ti_cmd_desc cmd; 995 u_int16_t *m; 996 u_int32_t ext[2] = {0, 0}; 997 998 m = (u_int16_t *)&addr->octet[0]; 999 1000 switch(sc->ti_hwrev) { 1001 case TI_HWREV_TIGON: 1002 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1003 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1004 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1005 break; 1006 case TI_HWREV_TIGON_II: 1007 ext[0] = htons(m[0]); 1008 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1009 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1010 break; 1011 default: 1012 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1013 break; 1014 } 1015 1016 return; 1017} 1018 1019void ti_del_mcast(sc, addr) 1020 struct ti_softc *sc; 1021 struct ether_addr *addr; 1022{ 1023 struct ti_cmd_desc cmd; 1024 u_int16_t *m; 1025 u_int32_t ext[2] = {0, 0}; 1026 1027 m = (u_int16_t *)&addr->octet[0]; 1028 1029 switch(sc->ti_hwrev) { 1030 case TI_HWREV_TIGON: 1031 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1032 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1033 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1034 break; 1035 case TI_HWREV_TIGON_II: 1036 ext[0] = htons(m[0]); 1037 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1038 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1039 break; 1040 default: 1041 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1042 break; 1043 } 1044 1045 return; 1046} 1047 1048/* 1049 * Configure the Tigon's multicast address filter. 1050 * 1051 * The actual multicast table management is a bit of a pain, thanks to 1052 * slight brain damage on the part of both Alteon and us. With our 1053 * multicast code, we are only alerted when the multicast address table 1054 * changes and at that point we only have the current list of addresses: 1055 * we only know the current state, not the previous state, so we don't 1056 * actually know what addresses were removed or added. The firmware has 1057 * state, but we can't get our grubby mits on it, and there is no 'delete 1058 * all multicast addresses' command. Hence, we have to maintain our own 1059 * state so we know what addresses have been programmed into the NIC at 1060 * any given time. 1061 */ 1062static void ti_setmulti(sc) 1063 struct ti_softc *sc; 1064{ 1065 struct ifnet *ifp; 1066 struct ifmultiaddr *ifma; 1067 struct ti_cmd_desc cmd; 1068 struct ti_mc_entry *mc; 1069 u_int32_t intrs; 1070 1071 ifp = &sc->arpcom.ac_if; 1072 1073 if (ifp->if_flags & IFF_ALLMULTI) { 1074 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1075 return; 1076 } else { 1077 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1078 } 1079 1080 /* Disable interrupts. */ 1081 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1082 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1083 1084 /* First, zot all the existing filters. */ 1085 while (sc->ti_mc_listhead.slh_first != NULL) { 1086 mc = sc->ti_mc_listhead.slh_first; 1087 ti_del_mcast(sc, &mc->mc_addr); 1088 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1089 free(mc, M_DEVBUF); 1090 } 1091 1092 /* Now program new ones. */ 1093 for (ifma = ifp->if_multiaddrs.lh_first; 1094 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1095 if (ifma->ifma_addr->sa_family != AF_LINK) 1096 continue; 1097 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1098 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1099 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1100 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1101 ti_add_mcast(sc, &mc->mc_addr); 1102 } 1103 1104 /* Re-enable interrupts. */ 1105 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1106 1107 return; 1108} 1109 1110/* 1111 * Check to see if the BIOS has configured us for a 64 bit slot when 1112 * we aren't actually in one. If we detect this condition, we can work 1113 * around it on the Tigon 2 by setting a bit in the PCI state register, 1114 * but for the Tigon 1 we must give up and abort the interface attach. 1115 */ 1116static int ti_64bitslot_war(sc) 1117 struct ti_softc *sc; 1118{ 1119 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1120 CSR_WRITE_4(sc, 0x600, 0); 1121 CSR_WRITE_4(sc, 0x604, 0); 1122 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1123 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1124 if (sc->ti_hwrev == TI_HWREV_TIGON) 1125 return(EINVAL); 1126 else { 1127 TI_SETBIT(sc, TI_PCI_STATE, 1128 TI_PCISTATE_32BIT_BUS); 1129 return(0); 1130 } 1131 } 1132 } 1133 1134 return(0); 1135} 1136 1137/* 1138 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1139 * self-test results. 1140 */ 1141static int ti_chipinit(sc) 1142 struct ti_softc *sc; 1143{ 1144 u_int32_t cacheline; 1145 u_int32_t pci_writemax = 0; 1146 1147 /* Initialize link to down state. */ 1148 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1149 1150 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1151 1152 /* Set endianness before we access any non-PCI registers. */ 1153#if BYTE_ORDER == BIG_ENDIAN 1154 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1155 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1156#else 1157 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1158 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1159#endif 1160 1161 /* Check the ROM failed bit to see if self-tests passed. */ 1162 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1163 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1164 return(ENODEV); 1165 } 1166 1167 /* Halt the CPU. */ 1168 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1169 1170 /* Figure out the hardware revision. */ 1171 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1172 case TI_REV_TIGON_I: 1173 sc->ti_hwrev = TI_HWREV_TIGON; 1174 break; 1175 case TI_REV_TIGON_II: 1176 sc->ti_hwrev = TI_HWREV_TIGON_II; 1177 break; 1178 default: 1179 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1180 return(ENODEV); 1181 } 1182 1183 /* Do special setup for Tigon 2. */ 1184 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1185 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1186 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1187 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1188 } 1189 1190 /* Set up the PCI state register. */ 1191 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1192 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1193 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1194 } 1195 1196 /* Clear the read/write max DMA parameters. */ 1197 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1198 TI_PCISTATE_READ_MAXDMA)); 1199 1200 /* Get cache line size. */ 1201 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1202 1203 /* 1204 * If the system has set enabled the PCI memory write 1205 * and invalidate command in the command register, set 1206 * the write max parameter accordingly. This is necessary 1207 * to use MWI with the Tigon 2. 1208 */ 1209 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1210 switch(cacheline) { 1211 case 1: 1212 case 4: 1213 case 8: 1214 case 16: 1215 case 32: 1216 case 64: 1217 break; 1218 default: 1219 /* Disable PCI memory write and invalidate. */ 1220 if (bootverbose) 1221 printf("ti%d: cache line size %d not " 1222 "supported; disabling PCI MWI\n", 1223 sc->ti_unit, cacheline); 1224 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1225 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1226 break; 1227 } 1228 } 1229 1230#ifdef __brokenalpha__ 1231 /* 1232 * From the Alteon sample driver: 1233 * Must insure that we do not cross an 8K (bytes) boundary 1234 * for DMA reads. Our highest limit is 1K bytes. This is a 1235 * restriction on some ALPHA platforms with early revision 1236 * 21174 PCI chipsets, such as the AlphaPC 164lx 1237 */ 1238 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1239#else 1240 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1241#endif 1242 1243 /* This sets the min dma param all the way up (0xff). */ 1244 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1245 1246 /* Configure DMA variables. */ 1247#if BYTE_ORDER == BIG_ENDIAN 1248 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1249 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1250 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1251 TI_OPMODE_DONT_FRAG_JUMBO); 1252#else 1253 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1254 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1255 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1256#endif 1257 1258 /* 1259 * Only allow 1 DMA channel to be active at a time. 1260 * I don't think this is a good idea, but without it 1261 * the firmware racks up lots of nicDmaReadRingFull 1262 * errors. This is not compatible with hardware checksums. 1263 */ 1264 if (sc->arpcom.ac_if.if_hwassist == 0) 1265 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1266 1267 /* Recommended settings from Tigon manual. */ 1268 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1269 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1270 1271 if (ti_64bitslot_war(sc)) { 1272 printf("ti%d: bios thinks we're in a 64 bit slot, " 1273 "but we aren't", sc->ti_unit); 1274 return(EINVAL); 1275 } 1276 1277 return(0); 1278} 1279 1280/* 1281 * Initialize the general information block and firmware, and 1282 * start the CPU(s) running. 1283 */ 1284static int ti_gibinit(sc) 1285 struct ti_softc *sc; 1286{ 1287 struct ti_rcb *rcb; 1288 int i; 1289 struct ifnet *ifp; 1290 1291 ifp = &sc->arpcom.ac_if; 1292 1293 /* Disable interrupts for now. */ 1294 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1295 1296 /* Tell the chip where to find the general information block. */ 1297 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1298 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1299 1300 /* Load the firmware into SRAM. */ 1301 ti_loadfw(sc); 1302 1303 /* Set up the contents of the general info and ring control blocks. */ 1304 1305 /* Set up the event ring and producer pointer. */ 1306 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1307 1308 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1309 rcb->ti_flags = 0; 1310 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1311 vtophys(&sc->ti_ev_prodidx); 1312 sc->ti_ev_prodidx.ti_idx = 0; 1313 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1314 sc->ti_ev_saved_considx = 0; 1315 1316 /* Set up the command ring and producer mailbox. */ 1317 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1318 1319 sc->ti_rdata->ti_cmd_ring = 1320 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1321 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1322 rcb->ti_flags = 0; 1323 rcb->ti_max_len = 0; 1324 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1325 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1326 } 1327 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1328 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1329 sc->ti_cmd_saved_prodidx = 0; 1330 1331 /* 1332 * Assign the address of the stats refresh buffer. 1333 * We re-use the current stats buffer for this to 1334 * conserve memory. 1335 */ 1336 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1337 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1338 1339 /* Set up the standard receive ring. */ 1340 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1341 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1342 rcb->ti_max_len = TI_FRAMELEN; 1343 rcb->ti_flags = 0; 1344 if (sc->arpcom.ac_if.if_hwassist) 1345 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1346 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1347#if NVLAN > 0 1348 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1349#endif 1350 1351 /* Set up the jumbo receive ring. */ 1352 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1353 TI_HOSTADDR(rcb->ti_hostaddr) = 1354 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1355 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1356 rcb->ti_flags = 0; 1357 if (sc->arpcom.ac_if.if_hwassist) 1358 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1359 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1360#if NVLAN > 0 1361 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1362#endif 1363 1364 /* 1365 * Set up the mini ring. Only activated on the 1366 * Tigon 2 but the slot in the config block is 1367 * still there on the Tigon 1. 1368 */ 1369 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1370 TI_HOSTADDR(rcb->ti_hostaddr) = 1371 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1372 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1373 if (sc->ti_hwrev == TI_HWREV_TIGON) 1374 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1375 else 1376 rcb->ti_flags = 0; 1377 if (sc->arpcom.ac_if.if_hwassist) 1378 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1379 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1380#if NVLAN > 0 1381 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1382#endif 1383 1384 /* 1385 * Set up the receive return ring. 1386 */ 1387 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1388 TI_HOSTADDR(rcb->ti_hostaddr) = 1389 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1390 rcb->ti_flags = 0; 1391 rcb->ti_max_len = TI_RETURN_RING_CNT; 1392 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1393 vtophys(&sc->ti_return_prodidx); 1394 1395 /* 1396 * Set up the tx ring. Note: for the Tigon 2, we have the option 1397 * of putting the transmit ring in the host's address space and 1398 * letting the chip DMA it instead of leaving the ring in the NIC's 1399 * memory and accessing it through the shared memory region. We 1400 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1401 * so we have to revert to the shared memory scheme if we detect 1402 * a Tigon 1 chip. 1403 */ 1404 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1405 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1406 sc->ti_rdata->ti_tx_ring_nic = 1407 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1408 } 1409 bzero((char *)sc->ti_rdata->ti_tx_ring, 1410 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1411 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1412 if (sc->ti_hwrev == TI_HWREV_TIGON) 1413 rcb->ti_flags = 0; 1414 else 1415 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1416#if NVLAN > 0 1417 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1418#endif 1419 if (sc->arpcom.ac_if.if_hwassist) 1420 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1421 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1422 rcb->ti_max_len = TI_TX_RING_CNT; 1423 if (sc->ti_hwrev == TI_HWREV_TIGON) 1424 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1425 else 1426 TI_HOSTADDR(rcb->ti_hostaddr) = 1427 vtophys(&sc->ti_rdata->ti_tx_ring); 1428 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1429 vtophys(&sc->ti_tx_considx); 1430 1431 /* Set up tuneables */ 1432 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1433 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1434 (sc->ti_rx_coal_ticks / 10)); 1435 else 1436 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1437 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1438 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1439 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1440 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1441 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1442 1443 /* Turn interrupts on. */ 1444 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1445 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1446 1447 /* Start CPU. */ 1448 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1449 1450 return(0); 1451} 1452 1453/* 1454 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1455 * against our list and return its name if we find a match. 1456 */ 1457static int ti_probe(dev) 1458 device_t dev; 1459{ 1460 struct ti_type *t; 1461 1462 t = ti_devs; 1463 1464 while(t->ti_name != NULL) { 1465 if ((pci_get_vendor(dev) == t->ti_vid) && 1466 (pci_get_device(dev) == t->ti_did)) { 1467 device_set_desc(dev, t->ti_name); 1468 return(0); 1469 } 1470 t++; 1471 } 1472 1473 return(ENXIO); 1474} 1475 1476static int ti_attach(dev) 1477 device_t dev; 1478{ 1479 u_int32_t command; 1480 struct ifnet *ifp; 1481 struct ti_softc *sc; 1482 int unit, error = 0, rid; 1483 1484 sc = device_get_softc(dev); 1485 unit = device_get_unit(dev); 1486 bzero(sc, sizeof(struct ti_softc)); 1487 1488 /* 1489 * Map control/status registers. 1490 */ 1491 command = pci_read_config(dev, PCIR_COMMAND, 4); 1492 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1493 pci_write_config(dev, PCIR_COMMAND, command, 4); 1494 command = pci_read_config(dev, PCIR_COMMAND, 4); 1495 1496 if (!(command & PCIM_CMD_MEMEN)) { 1497 printf("ti%d: failed to enable memory mapping!\n", unit); 1498 error = ENXIO; 1499 goto fail; 1500 } 1501 1502 rid = TI_PCI_LOMEM; 1503 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1504 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1505 1506 if (sc->ti_res == NULL) { 1507 printf ("ti%d: couldn't map memory\n", unit); 1508 error = ENXIO; 1509 goto fail; 1510 } 1511 1512 sc->ti_btag = rman_get_bustag(sc->ti_res); 1513 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1514 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1515 1516 /* Allocate interrupt */ 1517 rid = 0; 1518 1519 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1520 RF_SHAREABLE | RF_ACTIVE); 1521 1522 if (sc->ti_irq == NULL) { 1523 printf("ti%d: couldn't map interrupt\n", unit); 1524 error = ENXIO; 1525 goto fail; 1526 } 1527 1528 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1529 ti_intr, sc, &sc->ti_intrhand); 1530 1531 if (error) { 1532 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1533 bus_release_resource(dev, SYS_RES_MEMORY, 1534 TI_PCI_LOMEM, sc->ti_res); 1535 printf("ti%d: couldn't set up irq\n", unit); 1536 goto fail; 1537 } 1538 1539 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF); 1540 TI_LOCK(sc); 1541 1542 sc->ti_unit = unit; 1543 1544 if (ti_chipinit(sc)) { 1545 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1546 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1547 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1548 bus_release_resource(dev, SYS_RES_MEMORY, 1549 TI_PCI_LOMEM, sc->ti_res); 1550 error = ENXIO; 1551 goto fail; 1552 } 1553 1554 /* Zero out the NIC's on-board SRAM. */ 1555 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1556 1557 /* Init again -- zeroing memory may have clobbered some registers. */ 1558 if (ti_chipinit(sc)) { 1559 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1560 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1561 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1562 bus_release_resource(dev, SYS_RES_MEMORY, 1563 TI_PCI_LOMEM, sc->ti_res); 1564 error = ENXIO; 1565 goto fail; 1566 } 1567 1568 /* 1569 * Get station address from the EEPROM. Note: the manual states 1570 * that the MAC address is at offset 0x8c, however the data is 1571 * stored as two longwords (since that's how it's loaded into 1572 * the NIC). This means the MAC address is actually preceeded 1573 * by two zero bytes. We need to skip over those. 1574 */ 1575 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1576 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1577 printf("ti%d: failed to read station address\n", unit); 1578 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1579 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1580 bus_release_resource(dev, SYS_RES_MEMORY, 1581 TI_PCI_LOMEM, sc->ti_res); 1582 error = ENXIO; 1583 goto fail; 1584 } 1585 1586 /* 1587 * A Tigon chip was detected. Inform the world. 1588 */ 1589 printf("ti%d: Ethernet address: %6D\n", unit, 1590 sc->arpcom.ac_enaddr, ":"); 1591 1592 /* Allocate the general information block and ring buffers. */ 1593 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1594 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1595 1596 if (sc->ti_rdata == NULL) { 1597 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1598 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1599 bus_release_resource(dev, SYS_RES_MEMORY, 1600 TI_PCI_LOMEM, sc->ti_res); 1601 error = ENXIO; 1602 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1603 goto fail; 1604 } 1605 1606 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1607 1608 /* Try to allocate memory for jumbo buffers. */ 1609 if (ti_alloc_jumbo_mem(sc)) { 1610 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1611 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1612 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1613 bus_release_resource(dev, SYS_RES_MEMORY, 1614 TI_PCI_LOMEM, sc->ti_res); 1615 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1616 M_DEVBUF); 1617 error = ENXIO; 1618 goto fail; 1619 } 1620 1621 /* 1622 * We really need a better way to tell a 1000baseTX card 1623 * from a 1000baseSX one, since in theory there could be 1624 * OEMed 1000baseTX cards from lame vendors who aren't 1625 * clever enough to change the PCI ID. For the moment 1626 * though, the AceNIC is the only copper card available. 1627 */ 1628 if (pci_get_vendor(dev) == ALT_VENDORID && 1629 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1630 sc->ti_copper = 1; 1631 /* Ok, it's not the only copper card available. */ 1632 if (pci_get_vendor(dev) == NG_VENDORID && 1633 pci_get_device(dev) == NG_DEVICEID_GA620T) 1634 sc->ti_copper = 1; 1635 1636 /* Set default tuneable values. */ 1637 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1638 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1639 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1640 sc->ti_rx_max_coal_bds = 64; 1641 sc->ti_tx_max_coal_bds = 128; 1642 sc->ti_tx_buf_ratio = 21; 1643 1644 /* Set up ifnet structure */ 1645 ifp = &sc->arpcom.ac_if; 1646 ifp->if_softc = sc; 1647 ifp->if_unit = sc->ti_unit; 1648 ifp->if_name = "ti"; 1649 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1650 ifp->if_ioctl = ti_ioctl; 1651 ifp->if_output = ether_output; 1652 ifp->if_start = ti_start; 1653 ifp->if_watchdog = ti_watchdog; 1654 ifp->if_init = ti_init; 1655 ifp->if_mtu = ETHERMTU; 1656 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1657 1658 /* Set up ifmedia support. */ 1659 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1660 if (sc->ti_copper) { 1661 /* 1662 * Copper cards allow manual 10/100 mode selection, 1663 * but not manual 1000baseTX mode selection. Why? 1664 * Becuase currently there's no way to specify the 1665 * master/slave setting through the firmware interface, 1666 * so Alteon decided to just bag it and handle it 1667 * via autonegotiation. 1668 */ 1669 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1670 ifmedia_add(&sc->ifmedia, 1671 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1672 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1673 ifmedia_add(&sc->ifmedia, 1674 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1675 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 1676 ifmedia_add(&sc->ifmedia, 1677 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 1678 } else { 1679 /* Fiber cards don't support 10/100 modes. */ 1680 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1681 ifmedia_add(&sc->ifmedia, 1682 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1683 } 1684 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1685 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1686 1687 /* 1688 * Call MI attach routine. 1689 */ 1690 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1691 TI_UNLOCK(sc); 1692 return(0); 1693 1694fail: 1695 TI_UNLOCK(sc); 1696 mtx_destroy(&sc->ti_mtx); 1697 return(error); 1698} 1699 1700static int ti_detach(dev) 1701 device_t dev; 1702{ 1703 struct ti_softc *sc; 1704 struct ifnet *ifp; 1705 1706 1707 sc = device_get_softc(dev); 1708 TI_LOCK(sc); 1709 ifp = &sc->arpcom.ac_if; 1710 1711 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1712 ti_stop(sc); 1713 1714 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1715 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1716 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1717 1718 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1719 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1720 ifmedia_removeall(&sc->ifmedia); 1721 1722 TI_UNLOCK(sc); 1723 mtx_destroy(&sc->ti_mtx); 1724 1725 return(0); 1726} 1727 1728/* 1729 * Frame reception handling. This is called if there's a frame 1730 * on the receive return list. 1731 * 1732 * Note: we have to be able to handle three possibilities here: 1733 * 1) the frame is from the mini receive ring (can only happen) 1734 * on Tigon 2 boards) 1735 * 2) the frame is from the jumbo recieve ring 1736 * 3) the frame is from the standard receive ring 1737 */ 1738 1739static void ti_rxeof(sc) 1740 struct ti_softc *sc; 1741{ 1742 struct ifnet *ifp; 1743 struct ti_cmd_desc cmd; 1744 1745 ifp = &sc->arpcom.ac_if; 1746 1747 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1748 struct ti_rx_desc *cur_rx; 1749 u_int32_t rxidx; 1750 struct ether_header *eh; 1751 struct mbuf *m = NULL; 1752#if NVLAN > 0 1753 u_int16_t vlan_tag = 0; 1754 int have_tag = 0; 1755#endif 1756 1757 cur_rx = 1758 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1759 rxidx = cur_rx->ti_idx; 1760 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1761 1762#if NVLAN > 0 1763 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1764 have_tag = 1; 1765 vlan_tag = cur_rx->ti_vlan_tag; 1766 } 1767#endif 1768 1769 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1770 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1771 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1772 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1773 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1774 ifp->if_ierrors++; 1775 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1776 continue; 1777 } 1778 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1779 ifp->if_ierrors++; 1780 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1781 continue; 1782 } 1783 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1784 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1785 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1786 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1787 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1788 ifp->if_ierrors++; 1789 ti_newbuf_mini(sc, sc->ti_mini, m); 1790 continue; 1791 } 1792 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1793 ifp->if_ierrors++; 1794 ti_newbuf_mini(sc, sc->ti_mini, m); 1795 continue; 1796 } 1797 } else { 1798 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1799 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1800 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1801 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1802 ifp->if_ierrors++; 1803 ti_newbuf_std(sc, sc->ti_std, m); 1804 continue; 1805 } 1806 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1807 ifp->if_ierrors++; 1808 ti_newbuf_std(sc, sc->ti_std, m); 1809 continue; 1810 } 1811 } 1812 1813 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1814 ifp->if_ipackets++; 1815 eh = mtod(m, struct ether_header *); 1816 m->m_pkthdr.rcvif = ifp; 1817 1818 /* Remove header from mbuf and pass it on. */ 1819 m_adj(m, sizeof(struct ether_header)); 1820 1821 if (ifp->if_hwassist) { 1822 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1823 CSUM_DATA_VALID; 1824 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1825 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1826 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1827 } 1828 1829#if NVLAN > 0 1830 /* 1831 * If we received a packet with a vlan tag, pass it 1832 * to vlan_input() instead of ether_input(). 1833 */ 1834 if (have_tag) { 1835 vlan_input_tag(eh, m, vlan_tag); 1836 have_tag = vlan_tag = 0; 1837 continue; 1838 } 1839#endif 1840 ether_input(ifp, eh, m); 1841 } 1842 1843 /* Only necessary on the Tigon 1. */ 1844 if (sc->ti_hwrev == TI_HWREV_TIGON) 1845 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1846 sc->ti_rx_saved_considx); 1847 1848 TI_UPDATE_STDPROD(sc, sc->ti_std); 1849 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1850 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1851 1852 return; 1853} 1854 1855static void ti_txeof(sc) 1856 struct ti_softc *sc; 1857{ 1858 struct ti_tx_desc *cur_tx = NULL; 1859 struct ifnet *ifp; 1860 1861 ifp = &sc->arpcom.ac_if; 1862 1863 /* 1864 * Go through our tx ring and free mbufs for those 1865 * frames that have been sent. 1866 */ 1867 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1868 u_int32_t idx = 0; 1869 1870 idx = sc->ti_tx_saved_considx; 1871 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1872 if (idx > 383) 1873 CSR_WRITE_4(sc, TI_WINBASE, 1874 TI_TX_RING_BASE + 6144); 1875 else if (idx > 255) 1876 CSR_WRITE_4(sc, TI_WINBASE, 1877 TI_TX_RING_BASE + 4096); 1878 else if (idx > 127) 1879 CSR_WRITE_4(sc, TI_WINBASE, 1880 TI_TX_RING_BASE + 2048); 1881 else 1882 CSR_WRITE_4(sc, TI_WINBASE, 1883 TI_TX_RING_BASE); 1884 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1885 } else 1886 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1887 if (cur_tx->ti_flags & TI_BDFLAG_END) 1888 ifp->if_opackets++; 1889 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1890 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1891 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1892 } 1893 sc->ti_txcnt--; 1894 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1895 ifp->if_timer = 0; 1896 } 1897 1898 if (cur_tx != NULL) 1899 ifp->if_flags &= ~IFF_OACTIVE; 1900 1901 return; 1902} 1903 1904static void ti_intr(xsc) 1905 void *xsc; 1906{ 1907 struct ti_softc *sc; 1908 struct ifnet *ifp; 1909 1910 sc = xsc; 1911 TI_LOCK(sc); 1912 ifp = &sc->arpcom.ac_if; 1913 1914#ifdef notdef 1915 /* Avoid this for now -- checking this register is expensive. */ 1916 /* Make sure this is really our interrupt. */ 1917 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 1918 TI_UNLOCK(sc); 1919 return; 1920 } 1921#endif 1922 1923 /* Ack interrupt and stop others from occuring. */ 1924 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1925 1926 if (ifp->if_flags & IFF_RUNNING) { 1927 /* Check RX return ring producer/consumer */ 1928 ti_rxeof(sc); 1929 1930 /* Check TX ring producer/consumer */ 1931 ti_txeof(sc); 1932 } 1933 1934 ti_handle_events(sc); 1935 1936 /* Re-enable interrupts. */ 1937 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1938 1939 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1940 ti_start(ifp); 1941 1942 TI_UNLOCK(sc); 1943 1944 return; 1945} 1946 1947static void ti_stats_update(sc) 1948 struct ti_softc *sc; 1949{ 1950 struct ifnet *ifp; 1951 1952 ifp = &sc->arpcom.ac_if; 1953 1954 ifp->if_collisions += 1955 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1956 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1957 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1958 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1959 ifp->if_collisions; 1960 1961 return; 1962} 1963 1964/* 1965 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1966 * pointers to descriptors. 1967 */ 1968static int ti_encap(sc, m_head, txidx) 1969 struct ti_softc *sc; 1970 struct mbuf *m_head; 1971 u_int32_t *txidx; 1972{ 1973 struct ti_tx_desc *f = NULL; 1974 struct mbuf *m; 1975 u_int32_t frag, cur, cnt = 0; 1976 u_int16_t csum_flags = 0; 1977#if NVLAN > 0 1978 struct ifvlan *ifv = NULL; 1979 1980 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1981 m_head->m_pkthdr.rcvif != NULL && 1982 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1983 ifv = m_head->m_pkthdr.rcvif->if_softc; 1984#endif 1985 1986 m = m_head; 1987 cur = frag = *txidx; 1988 1989 if (m_head->m_pkthdr.csum_flags) { 1990 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1991 csum_flags |= TI_BDFLAG_IP_CKSUM; 1992 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1993 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1994 if (m_head->m_flags & M_LASTFRAG) 1995 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1996 else if (m_head->m_flags & M_FRAG) 1997 csum_flags |= TI_BDFLAG_IP_FRAG; 1998 } 1999 /* 2000 * Start packing the mbufs in this chain into 2001 * the fragment pointers. Stop when we run out 2002 * of fragments or hit the end of the mbuf chain. 2003 */ 2004 for (m = m_head; m != NULL; m = m->m_next) { 2005 if (m->m_len != 0) { 2006 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2007 if (frag > 383) 2008 CSR_WRITE_4(sc, TI_WINBASE, 2009 TI_TX_RING_BASE + 6144); 2010 else if (frag > 255) 2011 CSR_WRITE_4(sc, TI_WINBASE, 2012 TI_TX_RING_BASE + 4096); 2013 else if (frag > 127) 2014 CSR_WRITE_4(sc, TI_WINBASE, 2015 TI_TX_RING_BASE + 2048); 2016 else 2017 CSR_WRITE_4(sc, TI_WINBASE, 2018 TI_TX_RING_BASE); 2019 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2020 } else 2021 f = &sc->ti_rdata->ti_tx_ring[frag]; 2022 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2023 break; 2024 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2025 f->ti_len = m->m_len; 2026 f->ti_flags = csum_flags; 2027#if NVLAN > 0 2028 if (ifv != NULL) { 2029 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2030 f->ti_vlan_tag = ifv->ifv_tag; 2031 } else { 2032 f->ti_vlan_tag = 0; 2033 } 2034#endif 2035 /* 2036 * Sanity check: avoid coming within 16 descriptors 2037 * of the end of the ring. 2038 */ 2039 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2040 return(ENOBUFS); 2041 cur = frag; 2042 TI_INC(frag, TI_TX_RING_CNT); 2043 cnt++; 2044 } 2045 } 2046 2047 if (m != NULL) 2048 return(ENOBUFS); 2049 2050 if (frag == sc->ti_tx_saved_considx) 2051 return(ENOBUFS); 2052 2053 if (sc->ti_hwrev == TI_HWREV_TIGON) 2054 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2055 TI_BDFLAG_END; 2056 else 2057 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2058 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2059 sc->ti_txcnt += cnt; 2060 2061 *txidx = frag; 2062 2063 return(0); 2064} 2065 2066/* 2067 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2068 * to the mbuf data regions directly in the transmit descriptors. 2069 */ 2070static void ti_start(ifp) 2071 struct ifnet *ifp; 2072{ 2073 struct ti_softc *sc; 2074 struct mbuf *m_head = NULL; 2075 u_int32_t prodidx = 0; 2076 2077 sc = ifp->if_softc; 2078 TI_LOCK(sc); 2079 2080 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2081 2082 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2083 IF_DEQUEUE(&ifp->if_snd, m_head); 2084 if (m_head == NULL) 2085 break; 2086 2087 /* 2088 * XXX 2089 * safety overkill. If this is a fragmented packet chain 2090 * with delayed TCP/UDP checksums, then only encapsulate 2091 * it if we have enough descriptors to handle the entire 2092 * chain at once. 2093 * (paranoia -- may not actually be needed) 2094 */ 2095 if (m_head->m_flags & M_FIRSTFRAG && 2096 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2097 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2098 m_head->m_pkthdr.csum_data + 16) { 2099 IF_PREPEND(&ifp->if_snd, m_head); 2100 ifp->if_flags |= IFF_OACTIVE; 2101 break; 2102 } 2103 } 2104 2105 /* 2106 * Pack the data into the transmit ring. If we 2107 * don't have room, set the OACTIVE flag and wait 2108 * for the NIC to drain the ring. 2109 */ 2110 if (ti_encap(sc, m_head, &prodidx)) { 2111 IF_PREPEND(&ifp->if_snd, m_head); 2112 ifp->if_flags |= IFF_OACTIVE; 2113 break; 2114 } 2115 2116 /* 2117 * If there's a BPF listener, bounce a copy of this frame 2118 * to him. 2119 */ 2120 if (ifp->if_bpf) 2121 bpf_mtap(ifp, m_head); 2122 } 2123 2124 /* Transmit */ 2125 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2126 2127 /* 2128 * Set a timeout in case the chip goes out to lunch. 2129 */ 2130 ifp->if_timer = 5; 2131 TI_UNLOCK(sc); 2132 2133 return; 2134} 2135 2136static void ti_init(xsc) 2137 void *xsc; 2138{ 2139 struct ti_softc *sc = xsc; 2140 2141 /* Cancel pending I/O and flush buffers. */ 2142 ti_stop(sc); 2143 2144 TI_LOCK(sc); 2145 /* Init the gen info block, ring control blocks and firmware. */ 2146 if (ti_gibinit(sc)) { 2147 printf("ti%d: initialization failure\n", sc->ti_unit); 2148 TI_UNLOCK(sc); 2149 return; 2150 } 2151 2152 TI_UNLOCK(sc); 2153 2154 return; 2155} 2156 2157static void ti_init2(sc) 2158 struct ti_softc *sc; 2159{ 2160 struct ti_cmd_desc cmd; 2161 struct ifnet *ifp; 2162 u_int16_t *m; 2163 struct ifmedia *ifm; 2164 int tmp; 2165 2166 ifp = &sc->arpcom.ac_if; 2167 2168 /* Specify MTU and interface index. */ 2169 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2170 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2171 ETHER_HDR_LEN + ETHER_CRC_LEN); 2172 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2173 2174 /* Load our MAC address. */ 2175 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2176 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2177 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2178 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2179 2180 /* Enable or disable promiscuous mode as needed. */ 2181 if (ifp->if_flags & IFF_PROMISC) { 2182 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2183 } else { 2184 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2185 } 2186 2187 /* Program multicast filter. */ 2188 ti_setmulti(sc); 2189 2190 /* 2191 * If this is a Tigon 1, we should tell the 2192 * firmware to use software packet filtering. 2193 */ 2194 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2195 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2196 } 2197 2198 /* Init RX ring. */ 2199 ti_init_rx_ring_std(sc); 2200 2201 /* Init jumbo RX ring. */ 2202 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2203 ti_init_rx_ring_jumbo(sc); 2204 2205 /* 2206 * If this is a Tigon 2, we can also configure the 2207 * mini ring. 2208 */ 2209 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2210 ti_init_rx_ring_mini(sc); 2211 2212 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2213 sc->ti_rx_saved_considx = 0; 2214 2215 /* Init TX ring. */ 2216 ti_init_tx_ring(sc); 2217 2218 /* Tell firmware we're alive. */ 2219 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2220 2221 /* Enable host interrupts. */ 2222 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2223 2224 ifp->if_flags |= IFF_RUNNING; 2225 ifp->if_flags &= ~IFF_OACTIVE; 2226 2227 /* 2228 * Make sure to set media properly. We have to do this 2229 * here since we have to issue commands in order to set 2230 * the link negotiation and we can't issue commands until 2231 * the firmware is running. 2232 */ 2233 ifm = &sc->ifmedia; 2234 tmp = ifm->ifm_media; 2235 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2236 ti_ifmedia_upd(ifp); 2237 ifm->ifm_media = tmp; 2238 2239 return; 2240} 2241 2242/* 2243 * Set media options. 2244 */ 2245static int ti_ifmedia_upd(ifp) 2246 struct ifnet *ifp; 2247{ 2248 struct ti_softc *sc; 2249 struct ifmedia *ifm; 2250 struct ti_cmd_desc cmd; 2251 2252 sc = ifp->if_softc; 2253 ifm = &sc->ifmedia; 2254 2255 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2256 return(EINVAL); 2257 2258 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2259 case IFM_AUTO: 2260 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2261 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2262 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2263 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2264 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2265 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2266 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2267 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2268 break; 2269 case IFM_1000_SX: 2270 case IFM_1000_TX: 2271 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2272 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2273 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2274 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2275 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2276 } 2277 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2278 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2279 break; 2280 case IFM_100_FX: 2281 case IFM_10_FL: 2282 case IFM_100_TX: 2283 case IFM_10_T: 2284 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2285 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2286 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2287 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2288 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2289 } else { 2290 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2291 } 2292 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2293 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2294 } else { 2295 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2296 } 2297 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2298 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2299 break; 2300 } 2301 2302 return(0); 2303} 2304 2305/* 2306 * Report current media status. 2307 */ 2308static void ti_ifmedia_sts(ifp, ifmr) 2309 struct ifnet *ifp; 2310 struct ifmediareq *ifmr; 2311{ 2312 struct ti_softc *sc; 2313 u_int32_t media = 0; 2314 2315 sc = ifp->if_softc; 2316 2317 ifmr->ifm_status = IFM_AVALID; 2318 ifmr->ifm_active = IFM_ETHER; 2319 2320 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2321 return; 2322 2323 ifmr->ifm_status |= IFM_ACTIVE; 2324 2325 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2326 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2327 if (sc->ti_copper) 2328 ifmr->ifm_active |= IFM_1000_TX; 2329 else 2330 ifmr->ifm_active |= IFM_1000_SX; 2331 if (media & TI_GLNK_FULL_DUPLEX) 2332 ifmr->ifm_active |= IFM_FDX; 2333 else 2334 ifmr->ifm_active |= IFM_HDX; 2335 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2336 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2337 if (sc->ti_copper) { 2338 if (media & TI_LNK_100MB) 2339 ifmr->ifm_active |= IFM_100_TX; 2340 if (media & TI_LNK_10MB) 2341 ifmr->ifm_active |= IFM_10_T; 2342 } else { 2343 if (media & TI_LNK_100MB) 2344 ifmr->ifm_active |= IFM_100_FX; 2345 if (media & TI_LNK_10MB) 2346 ifmr->ifm_active |= IFM_10_FL; 2347 } 2348 if (media & TI_LNK_FULL_DUPLEX) 2349 ifmr->ifm_active |= IFM_FDX; 2350 if (media & TI_LNK_HALF_DUPLEX) 2351 ifmr->ifm_active |= IFM_HDX; 2352 } 2353 2354 return; 2355} 2356 2357static int ti_ioctl(ifp, command, data) 2358 struct ifnet *ifp; 2359 u_long command; 2360 caddr_t data; 2361{ 2362 struct ti_softc *sc = ifp->if_softc; 2363 struct ifreq *ifr = (struct ifreq *) data; 2364 int error = 0; 2365 struct ti_cmd_desc cmd; 2366 2367 TI_LOCK(sc); 2368 2369 switch(command) { 2370 case SIOCSIFADDR: 2371 case SIOCGIFADDR: 2372 error = ether_ioctl(ifp, command, data); 2373 break; 2374 case SIOCSIFMTU: 2375 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2376 error = EINVAL; 2377 else { 2378 ifp->if_mtu = ifr->ifr_mtu; 2379 ti_init(sc); 2380 } 2381 break; 2382 case SIOCSIFFLAGS: 2383 if (ifp->if_flags & IFF_UP) { 2384 /* 2385 * If only the state of the PROMISC flag changed, 2386 * then just use the 'set promisc mode' command 2387 * instead of reinitializing the entire NIC. Doing 2388 * a full re-init means reloading the firmware and 2389 * waiting for it to start up, which may take a 2390 * second or two. 2391 */ 2392 if (ifp->if_flags & IFF_RUNNING && 2393 ifp->if_flags & IFF_PROMISC && 2394 !(sc->ti_if_flags & IFF_PROMISC)) { 2395 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2396 TI_CMD_CODE_PROMISC_ENB, 0); 2397 } else if (ifp->if_flags & IFF_RUNNING && 2398 !(ifp->if_flags & IFF_PROMISC) && 2399 sc->ti_if_flags & IFF_PROMISC) { 2400 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2401 TI_CMD_CODE_PROMISC_DIS, 0); 2402 } else 2403 ti_init(sc); 2404 } else { 2405 if (ifp->if_flags & IFF_RUNNING) { 2406 ti_stop(sc); 2407 } 2408 } 2409 sc->ti_if_flags = ifp->if_flags; 2410 error = 0; 2411 break; 2412 case SIOCADDMULTI: 2413 case SIOCDELMULTI: 2414 if (ifp->if_flags & IFF_RUNNING) { 2415 ti_setmulti(sc); 2416 error = 0; 2417 } 2418 break; 2419 case SIOCSIFMEDIA: 2420 case SIOCGIFMEDIA: 2421 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2422 break; 2423 default: 2424 error = EINVAL; 2425 break; 2426 } 2427 2428 TI_UNLOCK(sc); 2429 2430 return(error); 2431} 2432 2433static void ti_watchdog(ifp) 2434 struct ifnet *ifp; 2435{ 2436 struct ti_softc *sc; 2437 2438 sc = ifp->if_softc; 2439 TI_LOCK(sc); 2440 2441 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2442 ti_stop(sc); 2443 ti_init(sc); 2444 2445 ifp->if_oerrors++; 2446 TI_UNLOCK(sc); 2447 2448 return; 2449} 2450 2451/* 2452 * Stop the adapter and free any mbufs allocated to the 2453 * RX and TX lists. 2454 */ 2455static void ti_stop(sc) 2456 struct ti_softc *sc; 2457{ 2458 struct ifnet *ifp; 2459 struct ti_cmd_desc cmd; 2460 2461 TI_LOCK(sc); 2462 2463 ifp = &sc->arpcom.ac_if; 2464 2465 /* Disable host interrupts. */ 2466 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2467 /* 2468 * Tell firmware we're shutting down. 2469 */ 2470 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2471 2472 /* Halt and reinitialize. */ 2473 ti_chipinit(sc); 2474 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2475 ti_chipinit(sc); 2476 2477 /* Free the RX lists. */ 2478 ti_free_rx_ring_std(sc); 2479 2480 /* Free jumbo RX list. */ 2481 ti_free_rx_ring_jumbo(sc); 2482 2483 /* Free mini RX list. */ 2484 ti_free_rx_ring_mini(sc); 2485 2486 /* Free TX buffers. */ 2487 ti_free_tx_ring(sc); 2488 2489 sc->ti_ev_prodidx.ti_idx = 0; 2490 sc->ti_return_prodidx.ti_idx = 0; 2491 sc->ti_tx_considx.ti_idx = 0; 2492 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2493 2494 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2495 TI_UNLOCK(sc); 2496 2497 return; 2498} 2499 2500/* 2501 * Stop all chip I/O so that the kernel's probe routines don't 2502 * get confused by errant DMAs when rebooting. 2503 */ 2504static void ti_shutdown(dev) 2505 device_t dev; 2506{ 2507 struct ti_softc *sc; 2508 2509 sc = device_get_softc(dev); 2510 TI_LOCK(sc); 2511 ti_chipinit(sc); 2512 TI_UNLOCK(sc); 2513 2514 return; 2515} 2516