if_ti.c revision 56206
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ti/if_ti.c 56206 2000-01-18 00:26:29Z wpaul $ 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include "vlan.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90#include <sys/queue.h> 91 92#include <net/if.h> 93#include <net/if_arp.h> 94#include <net/ethernet.h> 95#include <net/if_dl.h> 96#include <net/if_media.h> 97 98#include <net/bpf.h> 99 100#if NVLAN > 0 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103#endif 104 105#include <netinet/in_systm.h> 106#include <netinet/in.h> 107#include <netinet/ip.h> 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/clock.h> /* for DELAY */ 112#include <machine/bus_memio.h> 113#include <machine/bus.h> 114#include <machine/resource.h> 115#include <sys/bus.h> 116#include <sys/rman.h> 117 118#include <pci/pcireg.h> 119#include <pci/pcivar.h> 120 121#include <pci/if_tireg.h> 122#include <pci/ti_fw.h> 123#include <pci/ti_fw2.h> 124 125#ifdef M_HWCKSUM 126/*#define TI_CSUM_OFFLOAD*/ 127#endif 128 129#if !defined(lint) 130static const char rcsid[] = 131 "$FreeBSD: head/sys/dev/ti/if_ti.c 56206 2000-01-18 00:26:29Z wpaul $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137 138static struct ti_type ti_devs[] = { 139 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 140 "Alteon AceNIC Gigabit Ethernet" }, 141 { TC_VENDORID, TC_DEVICEID_3C985, 142 "3Com 3c985-SX Gigabit Ethernet" }, 143 { NG_VENDORID, NG_DEVICEID_GA620, 144 "Netgear GA620 Gigabit Ethernet" }, 145 { SGI_VENDORID, SGI_DEVICEID_TIGON, 146 "Silicon Graphics Gigabit Ethernet" }, 147 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 148 "Farallon PN9000SX Gigabit Ethernet" }, 149 { 0, 0, NULL } 150}; 151 152static int ti_probe __P((device_t)); 153static int ti_attach __P((device_t)); 154static int ti_detach __P((device_t)); 155static void ti_txeof __P((struct ti_softc *)); 156static void ti_rxeof __P((struct ti_softc *)); 157 158static void ti_stats_update __P((struct ti_softc *)); 159static int ti_encap __P((struct ti_softc *, struct mbuf *, 160 u_int32_t *)); 161 162static void ti_intr __P((void *)); 163static void ti_start __P((struct ifnet *)); 164static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 165static void ti_init __P((void *)); 166static void ti_init2 __P((struct ti_softc *)); 167static void ti_stop __P((struct ti_softc *)); 168static void ti_watchdog __P((struct ifnet *)); 169static void ti_shutdown __P((device_t)); 170static int ti_ifmedia_upd __P((struct ifnet *)); 171static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 172 173static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 174static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 175 int, u_int8_t *)); 176static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 177 178static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 179static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 180static void ti_setmulti __P((struct ti_softc *)); 181 182static void ti_mem __P((struct ti_softc *, u_int32_t, 183 u_int32_t, caddr_t)); 184static void ti_loadfw __P((struct ti_softc *)); 185static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 186static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 187 caddr_t, int)); 188static void ti_handle_events __P((struct ti_softc *)); 189static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 190static void *ti_jalloc __P((struct ti_softc *)); 191static void ti_jfree __P((caddr_t, u_int)); 192static void ti_jref __P((caddr_t, u_int)); 193static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 194static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 195static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 196static int ti_init_rx_ring_std __P((struct ti_softc *)); 197static void ti_free_rx_ring_std __P((struct ti_softc *)); 198static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 199static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 200static int ti_init_rx_ring_mini __P((struct ti_softc *)); 201static void ti_free_rx_ring_mini __P((struct ti_softc *)); 202static void ti_free_tx_ring __P((struct ti_softc *)); 203static int ti_init_tx_ring __P((struct ti_softc *)); 204 205static int ti_64bitslot_war __P((struct ti_softc *)); 206static int ti_chipinit __P((struct ti_softc *)); 207static int ti_gibinit __P((struct ti_softc *)); 208 209static device_method_t ti_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, ti_probe), 212 DEVMETHOD(device_attach, ti_attach), 213 DEVMETHOD(device_detach, ti_detach), 214 DEVMETHOD(device_shutdown, ti_shutdown), 215 { 0, 0 } 216}; 217 218static driver_t ti_driver = { 219 "ti", 220 ti_methods, 221 sizeof(struct ti_softc) 222}; 223 224static devclass_t ti_devclass; 225 226DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 227 228/* 229 * Send an instruction or address to the EEPROM, check for ACK. 230 */ 231static u_int32_t ti_eeprom_putbyte(sc, byte) 232 struct ti_softc *sc; 233 int byte; 234{ 235 register int i, ack = 0; 236 237 /* 238 * Make sure we're in TX mode. 239 */ 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 241 242 /* 243 * Feed in each bit and stobe the clock. 244 */ 245 for (i = 0x80; i; i >>= 1) { 246 if (byte & i) { 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 } else { 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 250 } 251 DELAY(1); 252 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 DELAY(1); 254 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 255 } 256 257 /* 258 * Turn off TX mode. 259 */ 260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 261 262 /* 263 * Check for ack. 264 */ 265 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 267 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 268 269 return(ack); 270} 271 272/* 273 * Read a byte of data stored in the EEPROM at address 'addr.' 274 * We have to send two address bytes since the EEPROM can hold 275 * more than 256 bytes of data. 276 */ 277static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 278 struct ti_softc *sc; 279 int addr; 280 u_int8_t *dest; 281{ 282 register int i; 283 u_int8_t byte = 0; 284 285 EEPROM_START; 286 287 /* 288 * Send write control code to EEPROM. 289 */ 290 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 291 printf("ti%d: failed to send write command, status: %x\n", 292 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 293 return(1); 294 } 295 296 /* 297 * Send first byte of address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 300 printf("ti%d: failed to send address, status: %x\n", 301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 /* 305 * Send second byte address of byte we want to read. 306 */ 307 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 308 printf("ti%d: failed to send address, status: %x\n", 309 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 310 return(1); 311 } 312 313 EEPROM_STOP; 314 EEPROM_START; 315 /* 316 * Send read control code to EEPROM. 317 */ 318 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 319 printf("ti%d: failed to send read command, status: %x\n", 320 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 321 return(1); 322 } 323 324 /* 325 * Start reading bits from EEPROM. 326 */ 327 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 328 for (i = 0x80; i; i >>= 1) { 329 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 330 DELAY(1); 331 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 332 byte |= i; 333 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 334 DELAY(1); 335 } 336 337 EEPROM_STOP; 338 339 /* 340 * No ACK generated for read, so just return byte. 341 */ 342 343 *dest = byte; 344 345 return(0); 346} 347 348/* 349 * Read a sequence of bytes from the EEPROM. 350 */ 351static int ti_read_eeprom(sc, dest, off, cnt) 352 struct ti_softc *sc; 353 caddr_t dest; 354 int off; 355 int cnt; 356{ 357 int err = 0, i; 358 u_int8_t byte = 0; 359 360 for (i = 0; i < cnt; i++) { 361 err = ti_eeprom_getbyte(sc, off + i, &byte); 362 if (err) 363 break; 364 *(dest + i) = byte; 365 } 366 367 return(err ? 1 : 0); 368} 369 370/* 371 * NIC memory access function. Can be used to either clear a section 372 * of NIC local memory or (if buf is non-NULL) copy data into it. 373 */ 374static void ti_mem(sc, addr, len, buf) 375 struct ti_softc *sc; 376 u_int32_t addr, len; 377 caddr_t buf; 378{ 379 int segptr, segsize, cnt; 380 caddr_t ti_winbase, ptr; 381 382 segptr = addr; 383 cnt = len; 384 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 385 ptr = buf; 386 387 while(cnt) { 388 if (cnt < TI_WINLEN) 389 segsize = cnt; 390 else 391 segsize = TI_WINLEN - (segptr % TI_WINLEN); 392 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 393 if (buf == NULL) 394 bzero((char *)ti_winbase + (segptr & 395 (TI_WINLEN - 1)), segsize); 396 else { 397 bcopy((char *)ptr, (char *)ti_winbase + 398 (segptr & (TI_WINLEN - 1)), segsize); 399 ptr += segsize; 400 } 401 segptr += segsize; 402 cnt -= segsize; 403 } 404 405 return; 406} 407 408/* 409 * Load firmware image into the NIC. Check that the firmware revision 410 * is acceptable and see if we want the firmware for the Tigon 1 or 411 * Tigon 2. 412 */ 413static void ti_loadfw(sc) 414 struct ti_softc *sc; 415{ 416 switch(sc->ti_hwrev) { 417 case TI_HWREV_TIGON: 418 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 419 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 420 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 421 printf("ti%d: firmware revision mismatch; want " 422 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 423 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 424 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 425 tigonFwReleaseMinor, tigonFwReleaseFix); 426 return; 427 } 428 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 429 (caddr_t)tigonFwText); 430 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 431 (caddr_t)tigonFwData); 432 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 433 (caddr_t)tigonFwRodata); 434 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 435 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 437 break; 438 case TI_HWREV_TIGON_II: 439 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 440 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 441 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 442 printf("ti%d: firmware revision mismatch; want " 443 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 444 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 445 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 446 tigon2FwReleaseMinor, tigon2FwReleaseFix); 447 return; 448 } 449 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 450 (caddr_t)tigon2FwText); 451 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 452 (caddr_t)tigon2FwData); 453 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 454 (caddr_t)tigon2FwRodata); 455 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 456 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 457 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 458 break; 459 default: 460 printf("ti%d: can't load firmware: unknown hardware rev\n", 461 sc->ti_unit); 462 break; 463 } 464 465 return; 466} 467 468/* 469 * Send the NIC a command via the command ring. 470 */ 471static void ti_cmd(sc, cmd) 472 struct ti_softc *sc; 473 struct ti_cmd_desc *cmd; 474{ 475 u_int32_t index; 476 477 if (sc->ti_rdata->ti_cmd_ring == NULL) 478 return; 479 480 index = sc->ti_cmd_saved_prodidx; 481 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 482 TI_INC(index, TI_CMD_RING_CNT); 483 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 484 sc->ti_cmd_saved_prodidx = index; 485 486 return; 487} 488 489/* 490 * Send the NIC an extended command. The 'len' parameter specifies the 491 * number of command slots to include after the initial command. 492 */ 493static void ti_cmd_ext(sc, cmd, arg, len) 494 struct ti_softc *sc; 495 struct ti_cmd_desc *cmd; 496 caddr_t arg; 497 int len; 498{ 499 u_int32_t index; 500 register int i; 501 502 if (sc->ti_rdata->ti_cmd_ring == NULL) 503 return; 504 505 index = sc->ti_cmd_saved_prodidx; 506 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 507 TI_INC(index, TI_CMD_RING_CNT); 508 for (i = 0; i < len; i++) { 509 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 510 *(u_int32_t *)(&arg[i * 4])); 511 TI_INC(index, TI_CMD_RING_CNT); 512 } 513 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 514 sc->ti_cmd_saved_prodidx = index; 515 516 return; 517} 518 519/* 520 * Handle events that have triggered interrupts. 521 */ 522static void ti_handle_events(sc) 523 struct ti_softc *sc; 524{ 525 struct ti_event_desc *e; 526 527 if (sc->ti_rdata->ti_event_ring == NULL) 528 return; 529 530 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 531 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 532 switch(e->ti_event) { 533 case TI_EV_LINKSTAT_CHANGED: 534 sc->ti_linkstat = e->ti_code; 535 if (e->ti_code == TI_EV_CODE_LINK_UP) 536 printf("ti%d: 10/100 link up\n", sc->ti_unit); 537 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 538 printf("ti%d: gigabit link up\n", sc->ti_unit); 539 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 540 printf("ti%d: link down\n", sc->ti_unit); 541 break; 542 case TI_EV_ERROR: 543 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 544 printf("ti%d: invalid command\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 546 printf("ti%d: unknown command\n", sc->ti_unit); 547 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 548 printf("ti%d: bad config data\n", sc->ti_unit); 549 break; 550 case TI_EV_FIRMWARE_UP: 551 ti_init2(sc); 552 break; 553 case TI_EV_STATS_UPDATED: 554 ti_stats_update(sc); 555 break; 556 case TI_EV_RESET_JUMBO_RING: 557 case TI_EV_MCAST_UPDATED: 558 /* Who cares. */ 559 break; 560 default: 561 printf("ti%d: unknown event: %d\n", 562 sc->ti_unit, e->ti_event); 563 break; 564 } 565 /* Advance the consumer index. */ 566 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 567 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 568 } 569 570 return; 571} 572 573/* 574 * Memory management for the jumbo receive ring is a pain in the 575 * butt. We need to allocate at least 9018 bytes of space per frame, 576 * _and_ it has to be contiguous (unless you use the extended 577 * jumbo descriptor format). Using malloc() all the time won't 578 * work: malloc() allocates memory in powers of two, which means we 579 * would end up wasting a considerable amount of space by allocating 580 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 581 * to do our own memory management. 582 * 583 * The driver needs to allocate a contiguous chunk of memory at boot 584 * time. We then chop this up ourselves into 9K pieces and use them 585 * as external mbuf storage. 586 * 587 * One issue here is how much memory to allocate. The jumbo ring has 588 * 256 slots in it, but at 9K per slot than can consume over 2MB of 589 * RAM. This is a bit much, especially considering we also need 590 * RAM for the standard ring and mini ring (on the Tigon 2). To 591 * save space, we only actually allocate enough memory for 64 slots 592 * by default, which works out to between 500 and 600K. This can 593 * be tuned by changing a #define in if_tireg.h. 594 */ 595 596static int ti_alloc_jumbo_mem(sc) 597 struct ti_softc *sc; 598{ 599 caddr_t ptr; 600 register int i; 601 struct ti_jpool_entry *entry; 602 603 /* Grab a big chunk o' storage. */ 604 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 605 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 606 607 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 608 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 609 return(ENOBUFS); 610 } 611 612 SLIST_INIT(&sc->ti_jfree_listhead); 613 SLIST_INIT(&sc->ti_jinuse_listhead); 614 615 /* 616 * Now divide it up into 9K pieces and save the addresses 617 * in an array. Note that we play an evil trick here by using 618 * the first few bytes in the buffer to hold the the address 619 * of the softc structure for this interface. This is because 620 * ti_jfree() needs it, but it is called by the mbuf management 621 * code which will not pass it to us explicitly. 622 */ 623 ptr = sc->ti_cdata.ti_jumbo_buf; 624 for (i = 0; i < TI_JSLOTS; i++) { 625 u_int64_t **aptr; 626 aptr = (u_int64_t **)ptr; 627 aptr[0] = (u_int64_t *)sc; 628 ptr += sizeof(u_int64_t); 629 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 630 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 631 ptr += (TI_JLEN - sizeof(u_int64_t)); 632 entry = malloc(sizeof(struct ti_jpool_entry), 633 M_DEVBUF, M_NOWAIT); 634 if (entry == NULL) { 635 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 636 sc->ti_cdata.ti_jumbo_buf = NULL; 637 printf("ti%d: no memory for jumbo " 638 "buffer queue!\n", sc->ti_unit); 639 return(ENOBUFS); 640 } 641 entry->slot = i; 642 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 643 } 644 645 return(0); 646} 647 648/* 649 * Allocate a jumbo buffer. 650 */ 651static void *ti_jalloc(sc) 652 struct ti_softc *sc; 653{ 654 struct ti_jpool_entry *entry; 655 656 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 657 658 if (entry == NULL) { 659 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 660 return(NULL); 661 } 662 663 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 664 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 665 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 666 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 667} 668 669/* 670 * Adjust usage count on a jumbo buffer. In general this doesn't 671 * get used much because our jumbo buffers don't get passed around 672 * too much, but it's implemented for correctness. 673 */ 674static void ti_jref(buf, size) 675 caddr_t buf; 676 u_int size; 677{ 678 struct ti_softc *sc; 679 u_int64_t **aptr; 680 register int i; 681 682 /* Extract the softc struct pointer. */ 683 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 684 sc = (struct ti_softc *)(aptr[0]); 685 686 if (sc == NULL) 687 panic("ti_jref: can't find softc pointer!"); 688 689 if (size != TI_JUMBO_FRAMELEN) 690 panic("ti_jref: adjusting refcount of buf of wrong size!"); 691 692 /* calculate the slot this buffer belongs to */ 693 694 i = ((vm_offset_t)aptr 695 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 696 697 if ((i < 0) || (i >= TI_JSLOTS)) 698 panic("ti_jref: asked to reference buffer " 699 "that we don't manage!"); 700 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 701 panic("ti_jref: buffer already free!"); 702 else 703 sc->ti_cdata.ti_jslots[i].ti_inuse++; 704 705 return; 706} 707 708/* 709 * Release a jumbo buffer. 710 */ 711static void ti_jfree(buf, size) 712 caddr_t buf; 713 u_int size; 714{ 715 struct ti_softc *sc; 716 u_int64_t **aptr; 717 int i; 718 struct ti_jpool_entry *entry; 719 720 /* Extract the softc struct pointer. */ 721 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 722 sc = (struct ti_softc *)(aptr[0]); 723 724 if (sc == NULL) 725 panic("ti_jfree: can't find softc pointer!"); 726 727 if (size != TI_JUMBO_FRAMELEN) 728 panic("ti_jfree: freeing buffer of wrong size!"); 729 730 /* calculate the slot this buffer belongs to */ 731 732 i = ((vm_offset_t)aptr 733 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 734 735 if ((i < 0) || (i >= TI_JSLOTS)) 736 panic("ti_jfree: asked to free buffer that we don't manage!"); 737 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 738 panic("ti_jfree: buffer already free!"); 739 else { 740 sc->ti_cdata.ti_jslots[i].ti_inuse--; 741 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 742 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 743 if (entry == NULL) 744 panic("ti_jfree: buffer not in use!"); 745 entry->slot = i; 746 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 747 jpool_entries); 748 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 749 entry, jpool_entries); 750 } 751 } 752 753 return; 754} 755 756 757/* 758 * Intialize a standard receive ring descriptor. 759 */ 760static int ti_newbuf_std(sc, i, m) 761 struct ti_softc *sc; 762 int i; 763 struct mbuf *m; 764{ 765 struct mbuf *m_new = NULL; 766 struct ti_rx_desc *r; 767 768 if (m == NULL) { 769 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 770 if (m_new == NULL) { 771 printf("ti%d: mbuf allocation failed " 772 "-- packet dropped!\n", sc->ti_unit); 773 return(ENOBUFS); 774 } 775 776 MCLGET(m_new, M_DONTWAIT); 777 if (!(m_new->m_flags & M_EXT)) { 778 printf("ti%d: cluster allocation failed " 779 "-- packet dropped!\n", sc->ti_unit); 780 m_freem(m_new); 781 return(ENOBUFS); 782 } 783 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 784 } else { 785 m_new = m; 786 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 787 m_new->m_data = m_new->m_ext.ext_buf; 788 } 789 790 m_adj(m_new, ETHER_ALIGN); 791 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 792 r = &sc->ti_rdata->ti_rx_std_ring[i]; 793 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 794 r->ti_type = TI_BDTYPE_RECV_BD; 795#ifdef TI_CSUM_OFFLOAD 796 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 797#else 798 r->ti_flags = 0; 799#endif 800 r->ti_len = m_new->m_len; 801 r->ti_idx = i; 802 803 return(0); 804} 805 806/* 807 * Intialize a mini receive ring descriptor. This only applies to 808 * the Tigon 2. 809 */ 810static int ti_newbuf_mini(sc, i, m) 811 struct ti_softc *sc; 812 int i; 813 struct mbuf *m; 814{ 815 struct mbuf *m_new = NULL; 816 struct ti_rx_desc *r; 817 818 if (m == NULL) { 819 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 820 if (m_new == NULL) { 821 printf("ti%d: mbuf allocation failed " 822 "-- packet dropped!\n", sc->ti_unit); 823 return(ENOBUFS); 824 } 825 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 826 } else { 827 m_new = m; 828 m_new->m_data = m_new->m_pktdat; 829 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 830 } 831 832 m_adj(m_new, ETHER_ALIGN); 833 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 834 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 835 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 836 r->ti_type = TI_BDTYPE_RECV_BD; 837 r->ti_flags = TI_BDFLAG_MINI_RING; 838#ifdef TI_CSUM_OFFLOAD 839 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 840#endif 841 r->ti_len = m_new->m_len; 842 r->ti_idx = i; 843 844 return(0); 845} 846 847/* 848 * Initialize a jumbo receive ring descriptor. This allocates 849 * a jumbo buffer from the pool managed internally by the driver. 850 */ 851static int ti_newbuf_jumbo(sc, i, m) 852 struct ti_softc *sc; 853 int i; 854 struct mbuf *m; 855{ 856 struct mbuf *m_new = NULL; 857 struct ti_rx_desc *r; 858 859 if (m == NULL) { 860 caddr_t *buf = NULL; 861 862 /* Allocate the mbuf. */ 863 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 864 if (m_new == NULL) { 865 printf("ti%d: mbuf allocation failed " 866 "-- packet dropped!\n", sc->ti_unit); 867 return(ENOBUFS); 868 } 869 870 /* Allocate the jumbo buffer */ 871 buf = ti_jalloc(sc); 872 if (buf == NULL) { 873 m_freem(m_new); 874 printf("ti%d: jumbo allocation failed " 875 "-- packet dropped!\n", sc->ti_unit); 876 return(ENOBUFS); 877 } 878 879 /* Attach the buffer to the mbuf. */ 880 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 881 m_new->m_flags |= M_EXT; 882 m_new->m_len = m_new->m_pkthdr.len = 883 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 884 m_new->m_ext.ext_free = ti_jfree; 885 m_new->m_ext.ext_ref = ti_jref; 886 } else { 887 m_new = m; 888 m_new->m_data = m_new->m_ext.ext_buf; 889 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 890 } 891 892 m_adj(m_new, ETHER_ALIGN); 893 /* Set up the descriptor. */ 894 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 895 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 896 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 897 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 898 r->ti_flags = TI_BDFLAG_JUMBO_RING; 899#ifdef TI_CSUM_OFFLOAD 900 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 901#endif 902 r->ti_len = m_new->m_len; 903 r->ti_idx = i; 904 905 return(0); 906} 907 908/* 909 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 910 * that's 1MB or memory, which is a lot. For now, we fill only the first 911 * 256 ring entries and hope that our CPU is fast enough to keep up with 912 * the NIC. 913 */ 914static int ti_init_rx_ring_std(sc) 915 struct ti_softc *sc; 916{ 917 register int i; 918 struct ti_cmd_desc cmd; 919 920 for (i = 0; i < TI_SSLOTS; i++) { 921 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 922 return(ENOBUFS); 923 }; 924 925 TI_UPDATE_STDPROD(sc, i - 1); 926 sc->ti_std = i - 1; 927 928 return(0); 929} 930 931static void ti_free_rx_ring_std(sc) 932 struct ti_softc *sc; 933{ 934 register int i; 935 936 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 937 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 938 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 939 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 940 } 941 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 942 sizeof(struct ti_rx_desc)); 943 } 944 945 return; 946} 947 948static int ti_init_rx_ring_jumbo(sc) 949 struct ti_softc *sc; 950{ 951 register int i; 952 struct ti_cmd_desc cmd; 953 954 for (i = 0; i < (TI_JSLOTS - 20); i++) { 955 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 956 return(ENOBUFS); 957 }; 958 959 TI_UPDATE_JUMBOPROD(sc, i - 1); 960 sc->ti_jumbo = i - 1; 961 962 return(0); 963} 964 965static void ti_free_rx_ring_jumbo(sc) 966 struct ti_softc *sc; 967{ 968 register int i; 969 970 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 971 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 972 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 973 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 974 } 975 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 976 sizeof(struct ti_rx_desc)); 977 } 978 979 return; 980} 981 982static int ti_init_rx_ring_mini(sc) 983 struct ti_softc *sc; 984{ 985 register int i; 986 987 for (i = 0; i < TI_MSLOTS; i++) { 988 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 989 return(ENOBUFS); 990 }; 991 992 TI_UPDATE_MINIPROD(sc, i - 1); 993 sc->ti_mini = i - 1; 994 995 return(0); 996} 997 998static void ti_free_rx_ring_mini(sc) 999 struct ti_softc *sc; 1000{ 1001 register int i; 1002 1003 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1004 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1005 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1006 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1007 } 1008 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1009 sizeof(struct ti_rx_desc)); 1010 } 1011 1012 return; 1013} 1014 1015static void ti_free_tx_ring(sc) 1016 struct ti_softc *sc; 1017{ 1018 register int i; 1019 1020 if (sc->ti_rdata->ti_tx_ring == NULL) 1021 return; 1022 1023 for (i = 0; i < TI_TX_RING_CNT; i++) { 1024 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1025 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1026 sc->ti_cdata.ti_tx_chain[i] = NULL; 1027 } 1028 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1029 sizeof(struct ti_tx_desc)); 1030 } 1031 1032 return; 1033} 1034 1035static int ti_init_tx_ring(sc) 1036 struct ti_softc *sc; 1037{ 1038 sc->ti_txcnt = 0; 1039 sc->ti_tx_saved_considx = 0; 1040 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1041 return(0); 1042} 1043 1044/* 1045 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1046 * but we have to support the old way too so that Tigon 1 cards will 1047 * work. 1048 */ 1049void ti_add_mcast(sc, addr) 1050 struct ti_softc *sc; 1051 struct ether_addr *addr; 1052{ 1053 struct ti_cmd_desc cmd; 1054 u_int16_t *m; 1055 u_int32_t ext[2] = {0, 0}; 1056 1057 m = (u_int16_t *)&addr->octet[0]; 1058 1059 switch(sc->ti_hwrev) { 1060 case TI_HWREV_TIGON: 1061 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1062 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1063 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1064 break; 1065 case TI_HWREV_TIGON_II: 1066 ext[0] = htons(m[0]); 1067 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1068 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1069 break; 1070 default: 1071 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1072 break; 1073 } 1074 1075 return; 1076} 1077 1078void ti_del_mcast(sc, addr) 1079 struct ti_softc *sc; 1080 struct ether_addr *addr; 1081{ 1082 struct ti_cmd_desc cmd; 1083 u_int16_t *m; 1084 u_int32_t ext[2] = {0, 0}; 1085 1086 m = (u_int16_t *)&addr->octet[0]; 1087 1088 switch(sc->ti_hwrev) { 1089 case TI_HWREV_TIGON: 1090 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1091 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1092 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1093 break; 1094 case TI_HWREV_TIGON_II: 1095 ext[0] = htons(m[0]); 1096 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1097 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1098 break; 1099 default: 1100 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1101 break; 1102 } 1103 1104 return; 1105} 1106 1107/* 1108 * Configure the Tigon's multicast address filter. 1109 * 1110 * The actual multicast table management is a bit of a pain, thanks to 1111 * slight brain damage on the part of both Alteon and us. With our 1112 * multicast code, we are only alerted when the multicast address table 1113 * changes and at that point we only have the current list of addresses: 1114 * we only know the current state, not the previous state, so we don't 1115 * actually know what addresses were removed or added. The firmware has 1116 * state, but we can't get our grubby mits on it, and there is no 'delete 1117 * all multicast addresses' command. Hence, we have to maintain our own 1118 * state so we know what addresses have been programmed into the NIC at 1119 * any given time. 1120 */ 1121static void ti_setmulti(sc) 1122 struct ti_softc *sc; 1123{ 1124 struct ifnet *ifp; 1125 struct ifmultiaddr *ifma; 1126 struct ti_cmd_desc cmd; 1127 struct ti_mc_entry *mc; 1128 u_int32_t intrs; 1129 1130 ifp = &sc->arpcom.ac_if; 1131 1132 if (ifp->if_flags & IFF_ALLMULTI) { 1133 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1134 return; 1135 } else { 1136 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1137 } 1138 1139 /* Disable interrupts. */ 1140 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1141 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1142 1143 /* First, zot all the existing filters. */ 1144 while (sc->ti_mc_listhead.slh_first != NULL) { 1145 mc = sc->ti_mc_listhead.slh_first; 1146 ti_del_mcast(sc, &mc->mc_addr); 1147 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1148 free(mc, M_DEVBUF); 1149 } 1150 1151 /* Now program new ones. */ 1152 for (ifma = ifp->if_multiaddrs.lh_first; 1153 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1154 if (ifma->ifma_addr->sa_family != AF_LINK) 1155 continue; 1156 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1157 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1158 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1159 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1160 ti_add_mcast(sc, &mc->mc_addr); 1161 } 1162 1163 /* Re-enable interrupts. */ 1164 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1165 1166 return; 1167} 1168 1169/* 1170 * Check to see if the BIOS has configured us for a 64 bit slot when 1171 * we aren't actually in one. If we detect this condition, we can work 1172 * around it on the Tigon 2 by setting a bit in the PCI state register, 1173 * but for the Tigon 1 we must give up and abort the interface attach. 1174 */ 1175static int ti_64bitslot_war(sc) 1176 struct ti_softc *sc; 1177{ 1178 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1179 CSR_WRITE_4(sc, 0x600, 0); 1180 CSR_WRITE_4(sc, 0x604, 0); 1181 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1182 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1183 if (sc->ti_hwrev == TI_HWREV_TIGON) 1184 return(EINVAL); 1185 else { 1186 TI_SETBIT(sc, TI_PCI_STATE, 1187 TI_PCISTATE_32BIT_BUS); 1188 return(0); 1189 } 1190 } 1191 } 1192 1193 return(0); 1194} 1195 1196/* 1197 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1198 * self-test results. 1199 */ 1200static int ti_chipinit(sc) 1201 struct ti_softc *sc; 1202{ 1203 u_int32_t cacheline; 1204 u_int32_t pci_writemax = 0; 1205 1206 /* Initialize link to down state. */ 1207 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1208 1209 /* Set endianness before we access any non-PCI registers. */ 1210#if BYTE_ORDER == BIG_ENDIAN 1211 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1212 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1213#else 1214 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1215 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1216#endif 1217 1218 /* Check the ROM failed bit to see if self-tests passed. */ 1219 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1220 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1221 return(ENODEV); 1222 } 1223 1224 /* Halt the CPU. */ 1225 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1226 1227 /* Figure out the hardware revision. */ 1228 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1229 case TI_REV_TIGON_I: 1230 sc->ti_hwrev = TI_HWREV_TIGON; 1231 break; 1232 case TI_REV_TIGON_II: 1233 sc->ti_hwrev = TI_HWREV_TIGON_II; 1234 break; 1235 default: 1236 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1237 return(ENODEV); 1238 } 1239 1240 /* Do special setup for Tigon 2. */ 1241 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1242 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1243 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1244 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1245 } 1246 1247 /* Set up the PCI state register. */ 1248 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1249 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1250 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1251 } 1252 1253 /* Clear the read/write max DMA parameters. */ 1254 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1255 TI_PCISTATE_READ_MAXDMA)); 1256 1257 /* Get cache line size. */ 1258 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1259 1260 /* 1261 * If the system has set enabled the PCI memory write 1262 * and invalidate command in the command register, set 1263 * the write max parameter accordingly. This is necessary 1264 * to use MWI with the Tigon 2. 1265 */ 1266 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1267 switch(cacheline) { 1268 case 1: 1269 case 4: 1270 case 8: 1271 case 16: 1272 case 32: 1273 case 64: 1274 break; 1275 default: 1276 /* Disable PCI memory write and invalidate. */ 1277 if (bootverbose) 1278 printf("ti%d: cache line size %d not " 1279 "supported; disabling PCI MWI\n", 1280 sc->ti_unit, cacheline); 1281 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1282 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1283 break; 1284 } 1285 } 1286 1287#ifdef __brokenalpha__ 1288 /* 1289 * From the Alteon sample driver: 1290 * Must insure that we do not cross an 8K (bytes) boundary 1291 * for DMA reads. Our highest limit is 1K bytes. This is a 1292 * restriction on some ALPHA platforms with early revision 1293 * 21174 PCI chipsets, such as the AlphaPC 164lx 1294 */ 1295 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1296#else 1297 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1298#endif 1299 1300 /* This sets the min dma param all the way up (0xff). */ 1301 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1302 1303 /* Configure DMA variables. */ 1304#if BYTE_ORDER == BIG_ENDIAN 1305 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1306 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1307 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1308 TI_OPMODE_DONT_FRAG_JUMBO); 1309#else 1310 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1311 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1312 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1313#endif 1314 1315 /* 1316 * Only allow 1 DMA channel to be active at a time. 1317 * I don't think this is a good idea, but without it 1318 * the firmware racks up lots of nicDmaReadRingFull 1319 * errors. 1320 */ 1321#ifndef TI_CSUM_OFFLOAD 1322 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1323#endif 1324 1325 /* Recommended settings from Tigon manual. */ 1326 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1327 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1328 1329 if (ti_64bitslot_war(sc)) { 1330 printf("ti%d: bios thinks we're in a 64 bit slot, " 1331 "but we aren't", sc->ti_unit); 1332 return(EINVAL); 1333 } 1334 1335 return(0); 1336} 1337 1338/* 1339 * Initialize the general information block and firmware, and 1340 * start the CPU(s) running. 1341 */ 1342static int ti_gibinit(sc) 1343 struct ti_softc *sc; 1344{ 1345 struct ti_rcb *rcb; 1346 int i; 1347 struct ifnet *ifp; 1348 1349 ifp = &sc->arpcom.ac_if; 1350 1351 /* Disable interrupts for now. */ 1352 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1353 1354 /* Tell the chip where to find the general information block. */ 1355 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1357 1358 /* Load the firmware into SRAM. */ 1359 ti_loadfw(sc); 1360 1361 /* Set up the contents of the general info and ring control blocks. */ 1362 1363 /* Set up the event ring and producer pointer. */ 1364 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1365 1366 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1367 rcb->ti_flags = 0; 1368 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1369 vtophys(&sc->ti_ev_prodidx); 1370 sc->ti_ev_prodidx.ti_idx = 0; 1371 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1372 sc->ti_ev_saved_considx = 0; 1373 1374 /* Set up the command ring and producer mailbox. */ 1375 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1376 1377 sc->ti_rdata->ti_cmd_ring = 1378 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1379 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1380 rcb->ti_flags = 0; 1381 rcb->ti_max_len = 0; 1382 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1383 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1384 } 1385 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1386 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1387 sc->ti_cmd_saved_prodidx = 0; 1388 1389 /* 1390 * Assign the address of the stats refresh buffer. 1391 * We re-use the current stats buffer for this to 1392 * conserve memory. 1393 */ 1394 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1395 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1396 1397 /* Set up the standard receive ring. */ 1398 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1399 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1400 rcb->ti_max_len = TI_FRAMELEN; 1401 rcb->ti_flags = 0; 1402#ifdef TI_CSUM_OFFLOAD 1403 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1404#endif 1405#if NVLAN > 0 1406 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1407#endif 1408 1409 /* Set up the jumbo receive ring. */ 1410 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1411 TI_HOSTADDR(rcb->ti_hostaddr) = 1412 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1413 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1414 rcb->ti_flags = 0; 1415#ifdef TI_CSUM_OFFLOAD 1416 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1417#endif 1418#if NVLAN > 0 1419 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1420#endif 1421 1422 /* 1423 * Set up the mini ring. Only activated on the 1424 * Tigon 2 but the slot in the config block is 1425 * still there on the Tigon 1. 1426 */ 1427 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1428 TI_HOSTADDR(rcb->ti_hostaddr) = 1429 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1430 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1431 if (sc->ti_hwrev == TI_HWREV_TIGON) 1432 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1433 else 1434 rcb->ti_flags = 0; 1435#ifdef TI_CSUM_OFFLOAD 1436 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1437#endif 1438#if NVLAN > 0 1439 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1440#endif 1441 1442 /* 1443 * Set up the receive return ring. 1444 */ 1445 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1446 TI_HOSTADDR(rcb->ti_hostaddr) = 1447 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1448 rcb->ti_flags = 0; 1449 rcb->ti_max_len = TI_RETURN_RING_CNT; 1450 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1451 vtophys(&sc->ti_return_prodidx); 1452 1453 /* 1454 * Set up the tx ring. Note: for the Tigon 2, we have the option 1455 * of putting the transmit ring in the host's address space and 1456 * letting the chip DMA it instead of leaving the ring in the NIC's 1457 * memory and accessing it through the shared memory region. We 1458 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1459 * so we have to revert to the shared memory scheme if we detect 1460 * a Tigon 1 chip. 1461 */ 1462 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1463 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1464 sc->ti_rdata->ti_tx_ring_nic = 1465 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1466 } 1467 bzero((char *)sc->ti_rdata->ti_tx_ring, 1468 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1469 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1470 if (sc->ti_hwrev == TI_HWREV_TIGON) 1471 rcb->ti_flags = 0; 1472 else 1473 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1474#if NVLAN > 0 1475 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1476#endif 1477 rcb->ti_max_len = TI_TX_RING_CNT; 1478 if (sc->ti_hwrev == TI_HWREV_TIGON) 1479 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1480 else 1481 TI_HOSTADDR(rcb->ti_hostaddr) = 1482 vtophys(&sc->ti_rdata->ti_tx_ring); 1483 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1484 vtophys(&sc->ti_tx_considx); 1485 1486 /* Set up tuneables */ 1487 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1488 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1489 (sc->ti_rx_coal_ticks / 10)); 1490 else 1491 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1492 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1493 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1494 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1495 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1496 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1497 1498 /* Turn interrupts on. */ 1499 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1500 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1501 1502 /* Start CPU. */ 1503 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1504 1505 return(0); 1506} 1507 1508/* 1509 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1510 * against our list and return its name if we find a match. 1511 */ 1512static int ti_probe(dev) 1513 device_t dev; 1514{ 1515 struct ti_type *t; 1516 1517 t = ti_devs; 1518 1519 while(t->ti_name != NULL) { 1520 if ((pci_get_vendor(dev) == t->ti_vid) && 1521 (pci_get_device(dev) == t->ti_did)) { 1522 device_set_desc(dev, t->ti_name); 1523 return(0); 1524 } 1525 t++; 1526 } 1527 1528 return(ENXIO); 1529} 1530 1531static int ti_attach(dev) 1532 device_t dev; 1533{ 1534 int s; 1535 u_int32_t command; 1536 struct ifnet *ifp; 1537 struct ti_softc *sc; 1538 int unit, error = 0, rid; 1539 1540 s = splimp(); 1541 1542 sc = device_get_softc(dev); 1543 unit = device_get_unit(dev); 1544 bzero(sc, sizeof(struct ti_softc)); 1545 1546 /* 1547 * Map control/status registers. 1548 */ 1549 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1550 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1551 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1552 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1553 1554 if (!(command & PCIM_CMD_MEMEN)) { 1555 printf("ti%d: failed to enable memory mapping!\n", unit); 1556 error = ENXIO; 1557 goto fail; 1558 } 1559 1560 rid = TI_PCI_LOMEM; 1561 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1562 0, ~0, 1, RF_ACTIVE); 1563 1564 if (sc->ti_res == NULL) { 1565 printf ("ti%d: couldn't map memory\n", unit); 1566 error = ENXIO; 1567 goto fail; 1568 } 1569 1570 sc->ti_btag = rman_get_bustag(sc->ti_res); 1571 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1572 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1573 1574 /* 1575 * XXX FIXME: rman_get_virtual() on the alpha is currently 1576 * broken and returns a physical address instead of a kernel 1577 * virtual address. Consequently, we need to do a little 1578 * extra mangling of the vhandle on the alpha. This should 1579 * eventually be fixed! The whole idea here is to get rid 1580 * of platform dependencies. 1581 */ 1582#ifdef __alpha__ 1583 if (pci_cvt_to_bwx(sc->ti_vhandle)) 1584 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 1585 else 1586 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 1587 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 1588#endif 1589 1590 /* Allocate interrupt */ 1591 rid = 0; 1592 1593 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1594 RF_SHAREABLE | RF_ACTIVE); 1595 1596 if (sc->ti_irq == NULL) { 1597 printf("ti%d: couldn't map interrupt\n", unit); 1598 error = ENXIO; 1599 goto fail; 1600 } 1601 1602 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1603 ti_intr, sc, &sc->ti_intrhand); 1604 1605 if (error) { 1606 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1607 bus_release_resource(dev, SYS_RES_MEMORY, 1608 TI_PCI_LOMEM, sc->ti_res); 1609 printf("ti%d: couldn't set up irq\n", unit); 1610 goto fail; 1611 } 1612 1613 sc->ti_unit = unit; 1614 1615 if (ti_chipinit(sc)) { 1616 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1617 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1618 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1619 bus_release_resource(dev, SYS_RES_MEMORY, 1620 TI_PCI_LOMEM, sc->ti_res); 1621 error = ENXIO; 1622 goto fail; 1623 } 1624 1625 /* Zero out the NIC's on-board SRAM. */ 1626 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1627 1628 /* Init again -- zeroing memory may have clobbered some registers. */ 1629 if (ti_chipinit(sc)) { 1630 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1631 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1632 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1633 bus_release_resource(dev, SYS_RES_MEMORY, 1634 TI_PCI_LOMEM, sc->ti_res); 1635 error = ENXIO; 1636 goto fail; 1637 } 1638 1639 /* 1640 * Get station address from the EEPROM. Note: the manual states 1641 * that the MAC address is at offset 0x8c, however the data is 1642 * stored as two longwords (since that's how it's loaded into 1643 * the NIC). This means the MAC address is actually preceeded 1644 * by two zero bytes. We need to skip over those. 1645 */ 1646 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1647 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1648 printf("ti%d: failed to read station address\n", unit); 1649 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1650 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1651 bus_release_resource(dev, SYS_RES_MEMORY, 1652 TI_PCI_LOMEM, sc->ti_res); 1653 error = ENXIO; 1654 goto fail; 1655 } 1656 1657 /* 1658 * A Tigon chip was detected. Inform the world. 1659 */ 1660 printf("ti%d: Ethernet address: %6D\n", unit, 1661 sc->arpcom.ac_enaddr, ":"); 1662 1663 /* Allocate the general information block and ring buffers. */ 1664 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1665 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1666 1667 if (sc->ti_rdata == NULL) { 1668 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1669 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1670 bus_release_resource(dev, SYS_RES_MEMORY, 1671 TI_PCI_LOMEM, sc->ti_res); 1672 error = ENXIO; 1673 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1674 goto fail; 1675 } 1676 1677 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1678 1679 /* Try to allocate memory for jumbo buffers. */ 1680 if (ti_alloc_jumbo_mem(sc)) { 1681 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1682 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1683 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1684 bus_release_resource(dev, SYS_RES_MEMORY, 1685 TI_PCI_LOMEM, sc->ti_res); 1686 free(sc->ti_rdata, M_DEVBUF); 1687 error = ENXIO; 1688 goto fail; 1689 } 1690 1691 /* Set default tuneable values. */ 1692 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1693 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1694 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1695 sc->ti_rx_max_coal_bds = 64; 1696 sc->ti_tx_max_coal_bds = 128; 1697 sc->ti_tx_buf_ratio = 21; 1698 1699 /* Set up ifnet structure */ 1700 ifp = &sc->arpcom.ac_if; 1701 ifp->if_softc = sc; 1702 ifp->if_unit = sc->ti_unit; 1703 ifp->if_name = "ti"; 1704 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1705 ifp->if_ioctl = ti_ioctl; 1706 ifp->if_output = ether_output; 1707 ifp->if_start = ti_start; 1708 ifp->if_watchdog = ti_watchdog; 1709 ifp->if_init = ti_init; 1710 ifp->if_mtu = ETHERMTU; 1711 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1712 1713 /* Set up ifmedia support. */ 1714 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1715 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1716 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1717 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1718 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1719 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1720 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1721 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1722 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1723 1724 /* 1725 * Call MI attach routines. 1726 */ 1727 if_attach(ifp); 1728 ether_ifattach(ifp); 1729 1730 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1731 1732fail: 1733 splx(s); 1734 1735 return(error); 1736} 1737 1738static int ti_detach(dev) 1739 device_t dev; 1740{ 1741 struct ti_softc *sc; 1742 struct ifnet *ifp; 1743 int s; 1744 1745 s = splimp(); 1746 1747 sc = device_get_softc(dev); 1748 ifp = &sc->arpcom.ac_if; 1749 1750 if_detach(ifp); 1751 ti_stop(sc); 1752 1753 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1754 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1755 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1756 1757 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 1758 free(sc->ti_rdata, M_DEVBUF); 1759 ifmedia_removeall(&sc->ifmedia); 1760 1761 splx(s); 1762 1763 return(0); 1764} 1765 1766/* 1767 * Frame reception handling. This is called if there's a frame 1768 * on the receive return list. 1769 * 1770 * Note: we have to be able to handle three possibilities here: 1771 * 1) the frame is from the mini receive ring (can only happen) 1772 * on Tigon 2 boards) 1773 * 2) the frame is from the jumbo recieve ring 1774 * 3) the frame is from the standard receive ring 1775 */ 1776 1777static void ti_rxeof(sc) 1778 struct ti_softc *sc; 1779{ 1780 struct ifnet *ifp; 1781 struct ti_cmd_desc cmd; 1782 1783 ifp = &sc->arpcom.ac_if; 1784 1785 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1786 struct ti_rx_desc *cur_rx; 1787 u_int32_t rxidx; 1788 struct ether_header *eh; 1789 struct mbuf *m = NULL; 1790#if NVLAN > 0 1791 u_int16_t vlan_tag = 0; 1792 int have_tag = 0; 1793#endif 1794#ifdef TI_CSUM_OFFLOAD 1795 struct ip *ip; 1796#endif 1797 1798 cur_rx = 1799 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1800 rxidx = cur_rx->ti_idx; 1801 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1802 1803#if NVLAN > 0 1804 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1805 have_tag = 1; 1806 vlan_tag = cur_rx->ti_vlan_tag; 1807 } 1808#endif 1809 1810 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1811 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1812 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1813 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1814 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1815 ifp->if_ierrors++; 1816 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1817 continue; 1818 } 1819 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1820 ifp->if_ierrors++; 1821 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1822 continue; 1823 } 1824 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1825 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1826 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1827 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1828 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1829 ifp->if_ierrors++; 1830 ti_newbuf_mini(sc, sc->ti_mini, m); 1831 continue; 1832 } 1833 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1834 ifp->if_ierrors++; 1835 ti_newbuf_mini(sc, sc->ti_mini, m); 1836 continue; 1837 } 1838 } else { 1839 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1840 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1841 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1842 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1843 ifp->if_ierrors++; 1844 ti_newbuf_std(sc, sc->ti_std, m); 1845 continue; 1846 } 1847 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1848 ifp->if_ierrors++; 1849 ti_newbuf_std(sc, sc->ti_std, m); 1850 continue; 1851 } 1852 } 1853 1854 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1855 ifp->if_ipackets++; 1856 eh = mtod(m, struct ether_header *); 1857 m->m_pkthdr.rcvif = ifp; 1858 1859 /* 1860 * Handle BPF listeners. Let the BPF user see the packet, but 1861 * don't pass it up to the ether_input() layer unless it's 1862 * a broadcast packet, multicast packet, matches our ethernet 1863 * address or the interface is in promiscuous mode. 1864 */ 1865 if (ifp->if_bpf) { 1866 bpf_mtap(ifp, m); 1867 if (ifp->if_flags & IFF_PROMISC && 1868 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1869 ETHER_ADDR_LEN) && 1870 (eh->ether_dhost[0] & 1) == 0)) { 1871 m_freem(m); 1872 continue; 1873 } 1874 } 1875 1876 /* Remove header from mbuf and pass it on. */ 1877 m_adj(m, sizeof(struct ether_header)); 1878 1879#ifdef TI_CSUM_OFFLOAD 1880 ip = mtod(m, struct ip *); 1881 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 1882 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 1883 m->m_flags |= M_HWCKSUM; 1884#endif 1885 1886#if NVLAN > 0 1887 /* 1888 * If we received a packet with a vlan tag, pass it 1889 * to vlan_input() instead of ether_input(). 1890 */ 1891 if (have_tag) { 1892 vlan_input_tag(eh, m, vlan_tag); 1893 have_tag = vlan_tag = 0; 1894 continue; 1895 } 1896#endif 1897 ether_input(ifp, eh, m); 1898 } 1899 1900 /* Only necessary on the Tigon 1. */ 1901 if (sc->ti_hwrev == TI_HWREV_TIGON) 1902 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1903 sc->ti_rx_saved_considx); 1904 1905 TI_UPDATE_STDPROD(sc, sc->ti_std); 1906 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1907 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1908 1909 return; 1910} 1911 1912static void ti_txeof(sc) 1913 struct ti_softc *sc; 1914{ 1915 struct ti_tx_desc *cur_tx = NULL; 1916 struct ifnet *ifp; 1917 1918 ifp = &sc->arpcom.ac_if; 1919 1920 /* 1921 * Go through our tx ring and free mbufs for those 1922 * frames that have been sent. 1923 */ 1924 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1925 u_int32_t idx = 0; 1926 1927 idx = sc->ti_tx_saved_considx; 1928 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1929 if (idx > 383) 1930 CSR_WRITE_4(sc, TI_WINBASE, 1931 TI_TX_RING_BASE + 6144); 1932 else if (idx > 255) 1933 CSR_WRITE_4(sc, TI_WINBASE, 1934 TI_TX_RING_BASE + 4096); 1935 else if (idx > 127) 1936 CSR_WRITE_4(sc, TI_WINBASE, 1937 TI_TX_RING_BASE + 2048); 1938 else 1939 CSR_WRITE_4(sc, TI_WINBASE, 1940 TI_TX_RING_BASE); 1941 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1942 } else 1943 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1944 if (cur_tx->ti_flags & TI_BDFLAG_END) 1945 ifp->if_opackets++; 1946 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1947 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1948 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1949 } 1950 sc->ti_txcnt--; 1951 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1952 ifp->if_timer = 0; 1953 } 1954 1955 if (cur_tx != NULL) 1956 ifp->if_flags &= ~IFF_OACTIVE; 1957 1958 return; 1959} 1960 1961static void ti_intr(xsc) 1962 void *xsc; 1963{ 1964 struct ti_softc *sc; 1965 struct ifnet *ifp; 1966 1967 sc = xsc; 1968 ifp = &sc->arpcom.ac_if; 1969 1970#ifdef notdef 1971 /* Avoid this for now -- checking this register is expensive. */ 1972 /* Make sure this is really our interrupt. */ 1973 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1974 return; 1975#endif 1976 1977 /* Ack interrupt and stop others from occuring. */ 1978 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1979 1980 if (ifp->if_flags & IFF_RUNNING) { 1981 /* Check RX return ring producer/consumer */ 1982 ti_rxeof(sc); 1983 1984 /* Check TX ring producer/consumer */ 1985 ti_txeof(sc); 1986 } 1987 1988 ti_handle_events(sc); 1989 1990 /* Re-enable interrupts. */ 1991 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1992 1993 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1994 ti_start(ifp); 1995 1996 return; 1997} 1998 1999static void ti_stats_update(sc) 2000 struct ti_softc *sc; 2001{ 2002 struct ifnet *ifp; 2003 2004 ifp = &sc->arpcom.ac_if; 2005 2006 ifp->if_collisions += 2007 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2008 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2009 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2010 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2011 ifp->if_collisions; 2012 2013 return; 2014} 2015 2016/* 2017 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2018 * pointers to descriptors. 2019 */ 2020static int ti_encap(sc, m_head, txidx) 2021 struct ti_softc *sc; 2022 struct mbuf *m_head; 2023 u_int32_t *txidx; 2024{ 2025 struct ti_tx_desc *f = NULL; 2026 struct mbuf *m; 2027 u_int32_t frag, cur, cnt = 0; 2028#if NVLAN > 0 2029 struct ifvlan *ifv = NULL; 2030 2031 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2032 m_head->m_pkthdr.rcvif != NULL && 2033 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2034 ifv = m_head->m_pkthdr.rcvif->if_softc; 2035#endif 2036 2037 m = m_head; 2038 cur = frag = *txidx; 2039 2040 /* 2041 * Start packing the mbufs in this chain into 2042 * the fragment pointers. Stop when we run out 2043 * of fragments or hit the end of the mbuf chain. 2044 */ 2045 for (m = m_head; m != NULL; m = m->m_next) { 2046 if (m->m_len != 0) { 2047 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2048 if (frag > 383) 2049 CSR_WRITE_4(sc, TI_WINBASE, 2050 TI_TX_RING_BASE + 6144); 2051 else if (frag > 255) 2052 CSR_WRITE_4(sc, TI_WINBASE, 2053 TI_TX_RING_BASE + 4096); 2054 else if (frag > 127) 2055 CSR_WRITE_4(sc, TI_WINBASE, 2056 TI_TX_RING_BASE + 2048); 2057 else 2058 CSR_WRITE_4(sc, TI_WINBASE, 2059 TI_TX_RING_BASE); 2060 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2061 } else 2062 f = &sc->ti_rdata->ti_tx_ring[frag]; 2063 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2064 break; 2065 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2066 f->ti_len = m->m_len; 2067 f->ti_flags = 0; 2068#if NVLAN > 0 2069 if (ifv != NULL) { 2070 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2071 f->ti_vlan_tag = ifv->ifv_tag; 2072 } else { 2073 f->ti_vlan_tag = 0; 2074 } 2075#endif 2076 /* 2077 * Sanity check: avoid coming within 16 descriptors 2078 * of the end of the ring. 2079 */ 2080 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2081 return(ENOBUFS); 2082 cur = frag; 2083 TI_INC(frag, TI_TX_RING_CNT); 2084 cnt++; 2085 } 2086 } 2087 2088 if (m != NULL) 2089 return(ENOBUFS); 2090 2091 if (frag == sc->ti_tx_saved_considx) 2092 return(ENOBUFS); 2093 2094 if (sc->ti_hwrev == TI_HWREV_TIGON) 2095 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2096 TI_BDFLAG_END; 2097 else 2098 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2099 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2100 sc->ti_txcnt += cnt; 2101 2102 *txidx = frag; 2103 2104 return(0); 2105} 2106 2107/* 2108 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2109 * to the mbuf data regions directly in the transmit descriptors. 2110 */ 2111static void ti_start(ifp) 2112 struct ifnet *ifp; 2113{ 2114 struct ti_softc *sc; 2115 struct mbuf *m_head = NULL; 2116 u_int32_t prodidx = 0; 2117 2118 sc = ifp->if_softc; 2119 2120 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2121 2122 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2123 IF_DEQUEUE(&ifp->if_snd, m_head); 2124 if (m_head == NULL) 2125 break; 2126 2127 /* 2128 * Pack the data into the transmit ring. If we 2129 * don't have room, set the OACTIVE flag and wait 2130 * for the NIC to drain the ring. 2131 */ 2132 if (ti_encap(sc, m_head, &prodidx)) { 2133 IF_PREPEND(&ifp->if_snd, m_head); 2134 ifp->if_flags |= IFF_OACTIVE; 2135 break; 2136 } 2137 2138 /* 2139 * If there's a BPF listener, bounce a copy of this frame 2140 * to him. 2141 */ 2142 if (ifp->if_bpf) 2143 bpf_mtap(ifp, m_head); 2144 } 2145 2146 /* Transmit */ 2147 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2148 2149 /* 2150 * Set a timeout in case the chip goes out to lunch. 2151 */ 2152 ifp->if_timer = 5; 2153 2154 return; 2155} 2156 2157static void ti_init(xsc) 2158 void *xsc; 2159{ 2160 struct ti_softc *sc = xsc; 2161 int s; 2162 2163 s = splimp(); 2164 2165 /* Cancel pending I/O and flush buffers. */ 2166 ti_stop(sc); 2167 2168 /* Init the gen info block, ring control blocks and firmware. */ 2169 if (ti_gibinit(sc)) { 2170 printf("ti%d: initialization failure\n", sc->ti_unit); 2171 splx(s); 2172 return; 2173 } 2174 2175 splx(s); 2176 2177 return; 2178} 2179 2180static void ti_init2(sc) 2181 struct ti_softc *sc; 2182{ 2183 struct ti_cmd_desc cmd; 2184 struct ifnet *ifp; 2185 u_int16_t *m; 2186 struct ifmedia *ifm; 2187 int tmp; 2188 2189 ifp = &sc->arpcom.ac_if; 2190 2191 /* Specify MTU and interface index. */ 2192 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2193 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2194 ETHER_HDR_LEN + ETHER_CRC_LEN); 2195 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2196 2197 /* Load our MAC address. */ 2198 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2199 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2200 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2201 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2202 2203 /* Enable or disable promiscuous mode as needed. */ 2204 if (ifp->if_flags & IFF_PROMISC) { 2205 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2206 } else { 2207 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2208 } 2209 2210 /* Program multicast filter. */ 2211 ti_setmulti(sc); 2212 2213 /* 2214 * If this is a Tigon 1, we should tell the 2215 * firmware to use software packet filtering. 2216 */ 2217 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2218 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2219 } 2220 2221 /* Init RX ring. */ 2222 ti_init_rx_ring_std(sc); 2223 2224 /* Init jumbo RX ring. */ 2225 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2226 ti_init_rx_ring_jumbo(sc); 2227 2228 /* 2229 * If this is a Tigon 2, we can also configure the 2230 * mini ring. 2231 */ 2232 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2233 ti_init_rx_ring_mini(sc); 2234 2235 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2236 sc->ti_rx_saved_considx = 0; 2237 2238 /* Init TX ring. */ 2239 ti_init_tx_ring(sc); 2240 2241 /* Tell firmware we're alive. */ 2242 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2243 2244 /* Enable host interrupts. */ 2245 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2246 2247 ifp->if_flags |= IFF_RUNNING; 2248 ifp->if_flags &= ~IFF_OACTIVE; 2249 2250 /* 2251 * Make sure to set media properly. We have to do this 2252 * here since we have to issue commands in order to set 2253 * the link negotiation and we can't issue commands until 2254 * the firmware is running. 2255 */ 2256 ifm = &sc->ifmedia; 2257 tmp = ifm->ifm_media; 2258 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2259 ti_ifmedia_upd(ifp); 2260 ifm->ifm_media = tmp; 2261 2262 return; 2263} 2264 2265/* 2266 * Set media options. 2267 */ 2268static int ti_ifmedia_upd(ifp) 2269 struct ifnet *ifp; 2270{ 2271 struct ti_softc *sc; 2272 struct ifmedia *ifm; 2273 struct ti_cmd_desc cmd; 2274 2275 sc = ifp->if_softc; 2276 ifm = &sc->ifmedia; 2277 2278 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2279 return(EINVAL); 2280 2281 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2282 case IFM_AUTO: 2283 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2284 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2285 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2286 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2287 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2288 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2289 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2290 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2291 break; 2292 case IFM_1000_SX: 2293 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2294 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2295 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2296 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2297 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2298 break; 2299 case IFM_100_FX: 2300 case IFM_10_FL: 2301 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2302 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2303 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2304 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2305 } else { 2306 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2307 } 2308 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2309 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2310 } else { 2311 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2312 } 2313 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2314 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2315 break; 2316 } 2317 2318 return(0); 2319} 2320 2321/* 2322 * Report current media status. 2323 */ 2324static void ti_ifmedia_sts(ifp, ifmr) 2325 struct ifnet *ifp; 2326 struct ifmediareq *ifmr; 2327{ 2328 struct ti_softc *sc; 2329 2330 sc = ifp->if_softc; 2331 2332 ifmr->ifm_status = IFM_AVALID; 2333 ifmr->ifm_active = IFM_ETHER; 2334 2335 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2336 return; 2337 2338 ifmr->ifm_status |= IFM_ACTIVE; 2339 2340 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2341 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2342 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2343 u_int32_t media; 2344 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2345 if (media & TI_LNK_100MB) 2346 ifmr->ifm_active |= IFM_100_FX; 2347 if (media & TI_LNK_10MB) 2348 ifmr->ifm_active |= IFM_10_FL; 2349 if (media & TI_LNK_FULL_DUPLEX) 2350 ifmr->ifm_active |= IFM_FDX; 2351 if (media & TI_LNK_HALF_DUPLEX) 2352 ifmr->ifm_active |= IFM_HDX; 2353 } 2354 2355 return; 2356} 2357 2358static int ti_ioctl(ifp, command, data) 2359 struct ifnet *ifp; 2360 u_long command; 2361 caddr_t data; 2362{ 2363 struct ti_softc *sc = ifp->if_softc; 2364 struct ifreq *ifr = (struct ifreq *) data; 2365 int s, error = 0; 2366 struct ti_cmd_desc cmd; 2367 2368 s = splimp(); 2369 2370 switch(command) { 2371 case SIOCSIFADDR: 2372 case SIOCGIFADDR: 2373 error = ether_ioctl(ifp, command, data); 2374 break; 2375 case SIOCSIFMTU: 2376 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2377 error = EINVAL; 2378 else { 2379 ifp->if_mtu = ifr->ifr_mtu; 2380 ti_init(sc); 2381 } 2382 break; 2383 case SIOCSIFFLAGS: 2384 if (ifp->if_flags & IFF_UP) { 2385 /* 2386 * If only the state of the PROMISC flag changed, 2387 * then just use the 'set promisc mode' command 2388 * instead of reinitializing the entire NIC. Doing 2389 * a full re-init means reloading the firmware and 2390 * waiting for it to start up, which may take a 2391 * second or two. 2392 */ 2393 if (ifp->if_flags & IFF_RUNNING && 2394 ifp->if_flags & IFF_PROMISC && 2395 !(sc->ti_if_flags & IFF_PROMISC)) { 2396 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2397 TI_CMD_CODE_PROMISC_ENB, 0); 2398 } else if (ifp->if_flags & IFF_RUNNING && 2399 !(ifp->if_flags & IFF_PROMISC) && 2400 sc->ti_if_flags & IFF_PROMISC) { 2401 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2402 TI_CMD_CODE_PROMISC_DIS, 0); 2403 } else 2404 ti_init(sc); 2405 } else { 2406 if (ifp->if_flags & IFF_RUNNING) { 2407 ti_stop(sc); 2408 } 2409 } 2410 sc->ti_if_flags = ifp->if_flags; 2411 error = 0; 2412 break; 2413 case SIOCADDMULTI: 2414 case SIOCDELMULTI: 2415 if (ifp->if_flags & IFF_RUNNING) { 2416 ti_setmulti(sc); 2417 error = 0; 2418 } 2419 break; 2420 case SIOCSIFMEDIA: 2421 case SIOCGIFMEDIA: 2422 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2423 break; 2424 default: 2425 error = EINVAL; 2426 break; 2427 } 2428 2429 (void)splx(s); 2430 2431 return(error); 2432} 2433 2434static void ti_watchdog(ifp) 2435 struct ifnet *ifp; 2436{ 2437 struct ti_softc *sc; 2438 2439 sc = ifp->if_softc; 2440 2441 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2442 ti_stop(sc); 2443 ti_init(sc); 2444 2445 ifp->if_oerrors++; 2446 2447 return; 2448} 2449 2450/* 2451 * Stop the adapter and free any mbufs allocated to the 2452 * RX and TX lists. 2453 */ 2454static void ti_stop(sc) 2455 struct ti_softc *sc; 2456{ 2457 struct ifnet *ifp; 2458 struct ti_cmd_desc cmd; 2459 2460 ifp = &sc->arpcom.ac_if; 2461 2462 /* Disable host interrupts. */ 2463 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2464 /* 2465 * Tell firmware we're shutting down. 2466 */ 2467 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2468 2469 /* Halt and reinitialize. */ 2470 ti_chipinit(sc); 2471 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2472 ti_chipinit(sc); 2473 2474 /* Free the RX lists. */ 2475 ti_free_rx_ring_std(sc); 2476 2477 /* Free jumbo RX list. */ 2478 ti_free_rx_ring_jumbo(sc); 2479 2480 /* Free mini RX list. */ 2481 ti_free_rx_ring_mini(sc); 2482 2483 /* Free TX buffers. */ 2484 ti_free_tx_ring(sc); 2485 2486 sc->ti_ev_prodidx.ti_idx = 0; 2487 sc->ti_return_prodidx.ti_idx = 0; 2488 sc->ti_tx_considx.ti_idx = 0; 2489 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2490 2491 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2492 2493 return; 2494} 2495 2496/* 2497 * Stop all chip I/O so that the kernel's probe routines don't 2498 * get confused by errant DMAs when rebooting. 2499 */ 2500static void ti_shutdown(dev) 2501 device_t dev; 2502{ 2503 struct ti_softc *sc; 2504 2505 sc = device_get_softc(dev); 2506 2507 ti_chipinit(sc); 2508 2509 return; 2510} 2511