if_ti.c revision 48597
118316Swollman/* 218316Swollman * Copyright (c) 1997, 1998, 1999 318316Swollman * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 418316Swollman * 518316Swollman * Redistribution and use in source and binary forms, with or without 618316Swollman * modification, are permitted provided that the following conditions 718316Swollman * are met: 818316Swollman * 1. Redistributions of source code must retain the above copyright 918316Swollman * notice, this list of conditions and the following disclaimer. 1018316Swollman * 2. Redistributions in binary form must reproduce the above copyright 1118316Swollman * notice, this list of conditions and the following disclaimer in the 1218316Swollman * documentation and/or other materials provided with the distribution. 1318316Swollman * 3. All advertising materials mentioning features or use of this software 1418316Swollman * must display the following acknowledgement: 1518316Swollman * This product includes software developed by Bill Paul. 1618316Swollman * 4. Neither the name of the author nor the names of any co-contributors 1718316Swollman * may be used to endorse or promote products derived from this software 1818316Swollman * without specific prior written permission. 1918316Swollman * 2018316Swollman * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2118316Swollman * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2218316Swollman * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2318316Swollman * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2418316Swollman * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2518316Swollman * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2618316Swollman * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2718316Swollman * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2818316Swollman * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2918316Swollman * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3018316Swollman * THE POSSIBILITY OF SUCH DAMAGE. 3118316Swollman * 3218316Swollman * $Id: if_ti.c,v 1.114 1999/07/05 19:20:31 wpaul Exp $ 3318316Swollman */ 3418316Swollman 3518316Swollman/* 3618316Swollman * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 3718316Swollman * Manuals, sample driver and firmware source kits are available 3818316Swollman * from http://www.alteon.com/support/openkits. 3918316Swollman * 4018316Swollman * Written by Bill Paul <wpaul@ctr.columbia.edu> 4118316Swollman * Electrical Engineering Department 4218316Swollman * Columbia University, New York City 4318316Swollman */ 4418316Swollman 4518316Swollman/* 4618316Swollman * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 4718316Swollman * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 4818316Swollman * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 4918316Swollman * Tigon supports hardware IP, TCP and UCP checksumming, multicast 5018316Swollman * filtering and jumbo (9014 byte) frames. The hardware is largely 5118316Swollman * controlled by firmware, which must be loaded into the NIC during 5218316Swollman * initialization. 5318316Swollman * 5418316Swollman * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 5518316Swollman * revision, which supports new features such as extended commands, 5618316Swollman * extended jumbo receive ring desciptors and a mini receive ring. 5718316Swollman * 5818316Swollman * Alteon Networks is to be commended for releasing such a vast amount 5918316Swollman * of development material for the Tigon NIC without requiring an NDA 6018316Swollman * (although they really should have done it a long time ago). With 6118316Swollman * any luck, the other vendors will finally wise up and follow Alteon's 6218316Swollman * stellar example. 6318316Swollman * 6418316Swollman * The firmware for the Tigon 1 and 2 NICs is compiled directly into 6518316Swollman * this driver by #including it as a C header file. This bloats the 6618316Swollman * driver somewhat, but it's the easiest method considering that the 6718316Swollman * driver code and firmware code need to be kept in sync. The source 6818316Swollman * for the firmware is not provided with the FreeBSD distribution since 6918316Swollman * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 7018316Swollman * 7118316Swollman * The following people deserve special thanks: 7218316Swollman * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 7318316Swollman * for testing 7418316Swollman * - Raymond Lee of Netgear, for providing a pair of Netgear 7518316Swollman * GA620 Tigon 2 boards for testing 7618316Swollman * - Ulf Zimmermann, for bringing the GA260 to my attention and 7718316Swollman * convincing me to write this driver. 7818316Swollman * - Andrew Gallatin for providing FreeBSD/Alpha support. 7918316Swollman */ 8018316Swollman 8118316Swollman#include "bpfilter.h" 8218316Swollman#include "vlan.h" 8318316Swollman 8418316Swollman#include <sys/param.h> 8518316Swollman#include <sys/systm.h> 8618316Swollman#include <sys/sockio.h> 8718316Swollman#include <sys/mbuf.h> 8818316Swollman#include <sys/malloc.h> 8918316Swollman#include <sys/kernel.h> 9018316Swollman#include <sys/socket.h> 9118316Swollman#include <sys/queue.h> 9218316Swollman 9318316Swollman#include <net/if.h> 9418316Swollman#include <net/if_arp.h> 9518316Swollman#include <net/ethernet.h> 9618316Swollman#include <net/if_dl.h> 9718316Swollman#include <net/if_media.h> 9818316Swollman 9918316Swollman#if NBPFILTER > 0 10018316Swollman#include <net/bpf.h> 10118316Swollman#endif 10218316Swollman 10318316Swollman#if NVLAN > 0 10418316Swollman#include <net/if_types.h> 10518316Swollman#include <net/if_vlan_var.h> 10618316Swollman#endif 10718316Swollman 10818316Swollman#include <netinet/in_systm.h> 10918316Swollman#include <netinet/in.h> 11018316Swollman#include <netinet/ip.h> 11118316Swollman 11218316Swollman#include <vm/vm.h> /* for vtophys */ 11318316Swollman#include <vm/pmap.h> /* for vtophys */ 11418316Swollman#include <machine/clock.h> /* for DELAY */ 11518316Swollman#include <machine/bus_memio.h> 11618316Swollman#include <machine/bus.h> 11718316Swollman 11818316Swollman#include <pci/pcireg.h> 11918316Swollman#include <pci/pcivar.h> 12018316Swollman 12118316Swollman#include <pci/if_tireg.h> 12218316Swollman#include <pci/ti_fw.h> 12318316Swollman#include <pci/ti_fw2.h> 12418316Swollman 12518316Swollman#ifdef M_HWCKSUM 12618316Swollman/*#define TI_CSUM_OFFLOAD*/ 12718316Swollman#endif 12818316Swollman 12918316Swollman#if !defined(lint) 13018316Swollmanstatic const char rcsid[] = 13118316Swollman "$Id: if_ti.c,v 1.114 1999/07/05 19:20:31 wpaul Exp $"; 13218316Swollman#endif 13318316Swollman 13418316Swollman/* 13518316Swollman * Various supported device vendors/types and their names. 13618316Swollman */ 13718316Swollman 13818316Swollmanstatic struct ti_type ti_devs[] = { 13918316Swollman { ALT_VENDORID, ALT_DEVICEID_ACENIC, 14018316Swollman "Alteon AceNIC Gigabit Ethernet" }, 14118316Swollman { TC_VENDORID, TC_DEVICEID_3C985, 14218316Swollman "3Com 3c985-SX Gigabit Ethernet" }, 14318316Swollman { NG_VENDORID, NG_DEVICEID_GA620, 14418316Swollman "Netgear GA620 Gigabit Ethernet" }, 14518316Swollman { SGI_VENDORID, SGI_DEVICEID_TIGON, 14618316Swollman "Silicon Graphics Gigabit Ethernet" }, 14718316Swollman { 0, 0, NULL } 14818316Swollman}; 14918316Swollman 15018316Swollmanstatic unsigned long ti_count; 15118316Swollman 15218316Swollmanstatic const char *ti_probe __P((pcici_t, pcidi_t)); 15318316Swollmanstatic void ti_attach __P((pcici_t, int)); 15418316Swollmanstatic void ti_txeof __P((struct ti_softc *)); 15518316Swollmanstatic void ti_rxeof __P((struct ti_softc *)); 15618316Swollman 15718316Swollmanstatic void ti_stats_update __P((struct ti_softc *)); 15818316Swollmanstatic int ti_encap __P((struct ti_softc *, struct mbuf *, 15918316Swollman u_int32_t *)); 16018316Swollman 16118316Swollmanstatic void ti_intr __P((void *)); 16218316Swollmanstatic void ti_start __P((struct ifnet *)); 16318316Swollmanstatic int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 16418316Swollmanstatic void ti_init __P((void *)); 16518316Swollmanstatic void ti_init2 __P((struct ti_softc *)); 16618316Swollmanstatic void ti_stop __P((struct ti_softc *)); 16718316Swollmanstatic void ti_watchdog __P((struct ifnet *)); 16818316Swollmanstatic void ti_shutdown __P((int, void *)); 16918316Swollmanstatic int ti_ifmedia_upd __P((struct ifnet *)); 17018316Swollmanstatic void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17118316Swollman 17218316Swollmanstatic u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 17318316Swollmanstatic u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 17418316Swollman int, u_int8_t *)); 17518316Swollmanstatic int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 17618316Swollman 17718316Swollmanstatic void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 17818316Swollmanstatic void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 17918316Swollmanstatic void ti_setmulti __P((struct ti_softc *)); 18018316Swollman 18118316Swollmanstatic void ti_mem __P((struct ti_softc *, u_int32_t, 18218316Swollman u_int32_t, caddr_t)); 18318316Swollmanstatic void ti_loadfw __P((struct ti_softc *)); 18418316Swollmanstatic void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 18518316Swollmanstatic void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 18618316Swollman caddr_t, int)); 18718316Swollmanstatic void ti_handle_events __P((struct ti_softc *)); 18818316Swollmanstatic int ti_alloc_jumbo_mem __P((struct ti_softc *)); 18918316Swollmanstatic void *ti_jalloc __P((struct ti_softc *)); 19018316Swollmanstatic void ti_jfree __P((caddr_t, u_int)); 19118316Swollmanstatic void ti_jref __P((caddr_t, u_int)); 19218316Swollmanstatic int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 19318316Swollmanstatic int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 19418316Swollmanstatic int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 19518316Swollmanstatic int ti_init_rx_ring_std __P((struct ti_softc *)); 19618316Swollmanstatic void ti_free_rx_ring_std __P((struct ti_softc *)); 19718316Swollmanstatic int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 19818316Swollmanstatic void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 19918316Swollmanstatic int ti_init_rx_ring_mini __P((struct ti_softc *)); 20018316Swollmanstatic void ti_free_rx_ring_mini __P((struct ti_softc *)); 20118316Swollmanstatic void ti_free_tx_ring __P((struct ti_softc *)); 20218316Swollmanstatic int ti_init_tx_ring __P((struct ti_softc *)); 20318316Swollman 20418316Swollmanstatic int ti_64bitslot_war __P((struct ti_softc *)); 20518316Swollmanstatic int ti_chipinit __P((struct ti_softc *)); 20618316Swollmanstatic int ti_gibinit __P((struct ti_softc *)); 20718316Swollman 20818316Swollman/* 20918316Swollman * Send an instruction or address to the EEPROM, check for ACK. 21018316Swollman */ 21118316Swollmanstatic u_int32_t ti_eeprom_putbyte(sc, byte) 21218316Swollman struct ti_softc *sc; 21318316Swollman int byte; 21418316Swollman{ 21518316Swollman register int i, ack = 0; 21618316Swollman 21718316Swollman /* 21818316Swollman * Make sure we're in TX mode. 21918316Swollman */ 22018316Swollman TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 22118316Swollman 22218316Swollman /* 22318316Swollman * Feed in each bit and stobe the clock. 22418316Swollman */ 22518316Swollman for (i = 0x80; i; i >>= 1) { 22618316Swollman if (byte & i) { 22718316Swollman TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 22818316Swollman } else { 22918316Swollman TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 23018316Swollman } 23118316Swollman DELAY(1); 23218316Swollman TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 23318316Swollman DELAY(1); 23418316Swollman TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 23518316Swollman } 23618316Swollman 23718316Swollman /* 23818316Swollman * Turn off TX mode. 23918316Swollman */ 24018316Swollman TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 24118316Swollman 24218316Swollman /* 24318316Swollman * Check for ack. 24418316Swollman */ 24518316Swollman TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 24618316Swollman ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 24718316Swollman TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 24818316Swollman 24918316Swollman return(ack); 25018316Swollman} 25118316Swollman 25218316Swollman/* 25318316Swollman * Read a byte of data stored in the EEPROM at address 'addr.' 25418316Swollman * We have to send two address bytes since the EEPROM can hold 25518316Swollman * more than 256 bytes of data. 25618316Swollman */ 25718316Swollmanstatic u_int8_t ti_eeprom_getbyte(sc, addr, dest) 25818316Swollman struct ti_softc *sc; 25918316Swollman int addr; 26018316Swollman u_int8_t *dest; 26118316Swollman{ 26218316Swollman register int i; 26318316Swollman u_int8_t byte = 0; 26418316Swollman 26518316Swollman EEPROM_START; 26618316Swollman 26718316Swollman /* 26818316Swollman * Send write control code to EEPROM. 26918316Swollman */ 27018316Swollman if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 27118316Swollman printf("ti%d: failed to send write command, status: %x\n", 27218316Swollman sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 27318316Swollman return(1); 27418316Swollman } 27518316Swollman 27618316Swollman /* 27718316Swollman * Send first byte of address of byte we want to read. 27818316Swollman */ 27918316Swollman if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 28018316Swollman printf("ti%d: failed to send address, status: %x\n", 28118316Swollman sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 28218316Swollman return(1); 28318316Swollman } 28418316Swollman /* 28518316Swollman * Send second byte address of byte we want to read. 28618316Swollman */ 28718316Swollman if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 28818316Swollman printf("ti%d: failed to send address, status: %x\n", 28918316Swollman sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 29018316Swollman return(1); 29118316Swollman } 29218316Swollman 29318316Swollman EEPROM_STOP; 29418316Swollman EEPROM_START; 29518316Swollman /* 29618316Swollman * Send read control code to EEPROM. 29718316Swollman */ 29818316Swollman if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 29918316Swollman printf("ti%d: failed to send read command, status: %x\n", 30018316Swollman sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 30118316Swollman return(1); 30218316Swollman } 30318316Swollman 30418316Swollman /* 30518316Swollman * Start reading bits from EEPROM. 30618316Swollman */ 30718316Swollman TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 30818316Swollman for (i = 0x80; i; i >>= 1) { 30918316Swollman TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 31018316Swollman DELAY(1); 31118316Swollman if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 31218316Swollman byte |= i; 31318316Swollman TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 31418316Swollman DELAY(1); 31518316Swollman } 31618316Swollman 31718316Swollman EEPROM_STOP; 31818316Swollman 31918316Swollman /* 32018316Swollman * No ACK generated for read, so just return byte. 32118316Swollman */ 32218316Swollman 32318316Swollman *dest = byte; 32418316Swollman 32518316Swollman return(0); 32618316Swollman} 32718316Swollman 32818316Swollman/* 32918316Swollman * Read a sequence of bytes from the EEPROM. 33018316Swollman */ 33118316Swollmanstatic int ti_read_eeprom(sc, dest, off, cnt) 33218316Swollman struct ti_softc *sc; 33318316Swollman caddr_t dest; 33418316Swollman int off; 33518316Swollman int cnt; 33618316Swollman{ 33718316Swollman int err = 0, i; 33818316Swollman u_int8_t byte = 0; 33918316Swollman 34018316Swollman for (i = 0; i < cnt; i++) { 34118316Swollman err = ti_eeprom_getbyte(sc, off + i, &byte); 34218316Swollman if (err) 34318316Swollman break; 34418316Swollman *(dest + i) = byte; 34518316Swollman } 34618316Swollman 34718316Swollman return(err ? 1 : 0); 34818316Swollman} 34918316Swollman 35018316Swollman/* 35118316Swollman * NIC memory access function. Can be used to either clear a section 35218316Swollman * of NIC local memory or (if buf is non-NULL) copy data into it. 35318316Swollman */ 35418316Swollmanstatic void ti_mem(sc, addr, len, buf) 35518316Swollman struct ti_softc *sc; 35618316Swollman u_int32_t addr, len; 35718316Swollman caddr_t buf; 35818316Swollman{ 35918316Swollman int segptr, segsize, cnt; 36018316Swollman caddr_t ti_winbase, ptr; 36118316Swollman 36218316Swollman segptr = addr; 36318316Swollman cnt = len; 36418316Swollman#ifdef __i386__ 36518316Swollman ti_winbase = (caddr_t)(sc->ti_bhandle + TI_WINDOW); 36618316Swollman#endif 36718316Swollman#ifdef __alpha__ 36818316Swollman ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 36918316Swollman#endif 37018316Swollman ptr = buf; 37118316Swollman 37218316Swollman while(cnt) { 37318316Swollman if (cnt < TI_WINLEN) 37418316Swollman segsize = cnt; 37518316Swollman else 37618316Swollman segsize = TI_WINLEN - (segptr % TI_WINLEN); 37718316Swollman CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 37818316Swollman if (buf == NULL) 37918316Swollman bzero((char *)ti_winbase + (segptr & 38018316Swollman (TI_WINLEN - 1)), segsize); 38118316Swollman else { 38218316Swollman bcopy((char *)ptr, (char *)ti_winbase + 38318316Swollman (segptr & (TI_WINLEN - 1)), segsize); 38418316Swollman ptr += segsize; 38518316Swollman } 38618316Swollman segptr += segsize; 38718316Swollman cnt -= segsize; 38818316Swollman } 38918316Swollman 39018316Swollman return; 39118316Swollman} 39218316Swollman 39318316Swollman/* 39418316Swollman * Load firmware image into the NIC. Check that the firmware revision 39518316Swollman * is acceptable and see if we want the firmware for the Tigon 1 or 39618316Swollman * Tigon 2. 39718316Swollman */ 39818316Swollmanstatic void ti_loadfw(sc) 39918316Swollman struct ti_softc *sc; 40018316Swollman{ 40118316Swollman switch(sc->ti_hwrev) { 40218316Swollman case TI_HWREV_TIGON: 40318316Swollman if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 40418316Swollman tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 40518316Swollman tigonFwReleaseFix != TI_FIRMWARE_FIX) { 40618316Swollman printf("ti%d: firmware revision mismatch; want " 40718316Swollman "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 40818316Swollman TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 40918316Swollman TI_FIRMWARE_FIX, tigonFwReleaseMajor, 41018316Swollman tigonFwReleaseMinor, tigonFwReleaseFix); 41118316Swollman return; 41218316Swollman } 41318316Swollman ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 41418316Swollman (caddr_t)tigonFwText); 41518316Swollman ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 41618316Swollman (caddr_t)tigonFwData); 41718316Swollman ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 41818316Swollman (caddr_t)tigonFwRodata); 41918316Swollman ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 42018316Swollman ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 42118316Swollman CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 42218316Swollman break; 42318316Swollman case TI_HWREV_TIGON_II: 42418316Swollman if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 42518316Swollman tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 42618316Swollman tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 42718316Swollman printf("ti%d: firmware revision mismatch; want " 42818316Swollman "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 42918316Swollman TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 43018316Swollman TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 43118316Swollman tigon2FwReleaseMinor, tigon2FwReleaseFix); 43218316Swollman return; 43318316Swollman } 43418316Swollman ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 43518316Swollman (caddr_t)tigon2FwText); 43618316Swollman ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 43718316Swollman (caddr_t)tigon2FwData); 43818316Swollman ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 43918316Swollman (caddr_t)tigon2FwRodata); 44018316Swollman ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 44118316Swollman ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 44218316Swollman CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 44318316Swollman break; 44418316Swollman default: 44518316Swollman printf("ti%d: can't load firmware: unknown hardware rev\n", 44618316Swollman sc->ti_unit); 44718316Swollman break; 44818316Swollman } 44918316Swollman 45018316Swollman return; 45118316Swollman} 45218316Swollman 45318316Swollman/* 45418316Swollman * Send the NIC a command via the command ring. 45518316Swollman */ 45618316Swollmanstatic void ti_cmd(sc, cmd) 45718316Swollman struct ti_softc *sc; 45818316Swollman struct ti_cmd_desc *cmd; 45918316Swollman{ 46018316Swollman u_int32_t index; 46118316Swollman 46218316Swollman if (sc->ti_rdata->ti_cmd_ring == NULL) 46318316Swollman return; 46418316Swollman 46518316Swollman index = sc->ti_cmd_saved_prodidx; 46618316Swollman CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 46718316Swollman TI_INC(index, TI_CMD_RING_CNT); 46818316Swollman CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 46918316Swollman sc->ti_cmd_saved_prodidx = index; 47018316Swollman 47118316Swollman return; 47218316Swollman} 47318316Swollman 47418316Swollman/* 47518316Swollman * Send the NIC an extended command. The 'len' parameter specifies the 47618316Swollman * number of command slots to include after the initial command. 47718316Swollman */ 47818316Swollmanstatic void ti_cmd_ext(sc, cmd, arg, len) 47918316Swollman struct ti_softc *sc; 48018316Swollman struct ti_cmd_desc *cmd; 48118316Swollman caddr_t arg; 48218316Swollman int len; 48318316Swollman{ 48418316Swollman u_int32_t index; 48518316Swollman register int i; 48618316Swollman 48718316Swollman if (sc->ti_rdata->ti_cmd_ring == NULL) 48818316Swollman return; 48918316Swollman 49018316Swollman index = sc->ti_cmd_saved_prodidx; 49118316Swollman CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 49218316Swollman TI_INC(index, TI_CMD_RING_CNT); 49318316Swollman for (i = 0; i < len; i++) { 49418316Swollman CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 49518316Swollman *(u_int32_t *)(&arg[i * 4])); 49618316Swollman TI_INC(index, TI_CMD_RING_CNT); 49718316Swollman } 49818316Swollman CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 49918316Swollman sc->ti_cmd_saved_prodidx = index; 50018316Swollman 50118316Swollman return; 50218316Swollman} 50318316Swollman 50418316Swollman/* 50518316Swollman * Handle events that have triggered interrupts. 50618316Swollman */ 50718316Swollmanstatic void ti_handle_events(sc) 50818316Swollman struct ti_softc *sc; 50918316Swollman{ 51018316Swollman struct ti_event_desc *e; 51118316Swollman 51218316Swollman if (sc->ti_rdata->ti_event_ring == NULL) 51318316Swollman return; 51418316Swollman 51518316Swollman while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 51618316Swollman e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 51718316Swollman switch(e->ti_event) { 51818316Swollman case TI_EV_LINKSTAT_CHANGED: 51918316Swollman sc->ti_linkstat = e->ti_code; 52018316Swollman if (e->ti_code == TI_EV_CODE_LINK_UP) 52118316Swollman printf("ti%d: 10/100 link up\n", sc->ti_unit); 52218316Swollman else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 52318316Swollman printf("ti%d: gigabit link up\n", sc->ti_unit); 52418316Swollman else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 52518316Swollman printf("ti%d: link down\n", sc->ti_unit); 52618316Swollman break; 52718316Swollman case TI_EV_ERROR: 52818316Swollman if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 52918316Swollman printf("ti%d: invalid command\n", sc->ti_unit); 53018316Swollman else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 53118316Swollman printf("ti%d: unknown command\n", sc->ti_unit); 53218316Swollman else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 53318316Swollman printf("ti%d: bad config data\n", sc->ti_unit); 53418316Swollman break; 53518316Swollman case TI_EV_FIRMWARE_UP: 53618316Swollman ti_init2(sc); 53718316Swollman break; 53818316Swollman case TI_EV_STATS_UPDATED: 53918316Swollman ti_stats_update(sc); 54018316Swollman break; 54118316Swollman case TI_EV_RESET_JUMBO_RING: 54218316Swollman case TI_EV_MCAST_UPDATED: 54318316Swollman /* Who cares. */ 54418316Swollman break; 54518316Swollman default: 54618316Swollman printf("ti%d: unknown event: %d\n", 54718316Swollman sc->ti_unit, e->ti_event); 54818316Swollman break; 54918316Swollman } 55018316Swollman /* Advance the consumer index. */ 55118316Swollman TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 55218316Swollman CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 55318316Swollman } 55418316Swollman 55518316Swollman return; 55618316Swollman} 55718316Swollman 55818316Swollman/* 55918316Swollman * Memory management for the jumbo receive ring is a pain in the 56018316Swollman * butt. We need to allocate at least 9018 bytes of space per frame, 56118316Swollman * _and_ it has to be contiguous (unless you use the extended 56218316Swollman * jumbo descriptor format). Using malloc() all the time won't 56318316Swollman * work: malloc() allocates memory in powers of two, which means we 56418316Swollman * would end up wasting a considerable amount of space by allocating 56518316Swollman * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 56618316Swollman * to do our own memory management. 567 * 568 * The driver needs to allocate a contiguous chunk of memory at boot 569 * time. We then chop this up ourselves into 9K pieces and use them 570 * as external mbuf storage. 571 * 572 * One issue here is how much memory to allocate. The jumbo ring has 573 * 256 slots in it, but at 9K per slot than can consume over 2MB of 574 * RAM. This is a bit much, especially considering we also need 575 * RAM for the standard ring and mini ring (on the Tigon 2). To 576 * save space, we only actually allocate enough memory for 64 slots 577 * by default, which works out to between 500 and 600K. This can 578 * be tuned by changing a #define in if_tireg.h. 579 */ 580 581static int ti_alloc_jumbo_mem(sc) 582 struct ti_softc *sc; 583{ 584 caddr_t ptr; 585 register int i; 586 struct ti_jpool_entry *entry; 587 588 /* Grab a big chunk o' storage. */ 589 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 590 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 591 592 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 593 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 594 return(ENOBUFS); 595 } 596 597 SLIST_INIT(&sc->ti_jfree_listhead); 598 SLIST_INIT(&sc->ti_jinuse_listhead); 599 600 /* 601 * Now divide it up into 9K pieces and save the addresses 602 * in an array. Note that we play an evil trick here by using 603 * the first few bytes in the buffer to hold the the address 604 * of the softc structure for this interface. This is because 605 * ti_jfree() needs it, but it is called by the mbuf management 606 * code which will not pass it to us explicitly. 607 */ 608 ptr = sc->ti_cdata.ti_jumbo_buf; 609 for (i = 0; i < TI_JSLOTS; i++) { 610 u_int64_t **aptr; 611 aptr = (u_int64_t **)ptr; 612 aptr[0] = (u_int64_t *)sc; 613 ptr += sizeof(u_int64_t); 614 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 615 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 616 ptr += (TI_JLEN - sizeof(u_int64_t)); 617 entry = malloc(sizeof(struct ti_jpool_entry), 618 M_DEVBUF, M_NOWAIT); 619 if (entry == NULL) { 620 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 621 sc->ti_cdata.ti_jumbo_buf = NULL; 622 printf("ti%d: no memory for jumbo " 623 "buffer queue!\n", sc->ti_unit); 624 return(ENOBUFS); 625 } 626 entry->slot = i; 627 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 628 } 629 630 return(0); 631} 632 633/* 634 * Allocate a jumbo buffer. 635 */ 636static void *ti_jalloc(sc) 637 struct ti_softc *sc; 638{ 639 struct ti_jpool_entry *entry; 640 641 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 642 643 if (entry == NULL) { 644 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 645 return(NULL); 646 } 647 648 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 649 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 650 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 651 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 652} 653 654/* 655 * Adjust usage count on a jumbo buffer. In general this doesn't 656 * get used much because our jumbo buffers don't get passed around 657 * too much, but it's implemented for correctness. 658 */ 659static void ti_jref(buf, size) 660 caddr_t buf; 661 u_int size; 662{ 663 struct ti_softc *sc; 664 u_int64_t **aptr; 665 register int i; 666 667 /* Extract the softc struct pointer. */ 668 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 669 sc = (struct ti_softc *)(aptr[0]); 670 671 if (sc == NULL) 672 panic("ti_jref: can't find softc pointer!"); 673 674 if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN) 675 panic("ti_jref: adjusting refcount of buf of wrong size!"); 676 677 /* calculate the slot this buffer belongs to */ 678 679 i = ((vm_offset_t)aptr 680 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 681 682 if ((i < 0) || (i >= TI_JSLOTS)) 683 panic("ti_jref: asked to reference buffer " 684 "that we don't manage!"); 685 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 686 panic("ti_jref: buffer already free!"); 687 else 688 sc->ti_cdata.ti_jslots[i].ti_inuse++; 689 690 return; 691} 692 693/* 694 * Release a jumbo buffer. 695 */ 696static void ti_jfree(buf, size) 697 caddr_t buf; 698 u_int size; 699{ 700 struct ti_softc *sc; 701 u_int64_t **aptr; 702 int i; 703 struct ti_jpool_entry *entry; 704 705 /* Extract the softc struct pointer. */ 706 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 707 sc = (struct ti_softc *)(aptr[0]); 708 709 if (sc == NULL) 710 panic("ti_jfree: can't find softc pointer!"); 711 712 if (size != TI_JUMBO_FRAMELEN - ETHER_ALIGN) 713 panic("ti_jfree: freeing buffer of wrong size!"); 714 715 /* calculate the slot this buffer belongs to */ 716 717 i = ((vm_offset_t)aptr 718 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 719 720 if ((i < 0) || (i >= TI_JSLOTS)) 721 panic("ti_jfree: asked to free buffer that we don't manage!"); 722 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 723 panic("ti_jfree: buffer already free!"); 724 else { 725 sc->ti_cdata.ti_jslots[i].ti_inuse--; 726 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 727 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 728 if (entry == NULL) 729 panic("ti_jfree: buffer not in use!"); 730 entry->slot = i; 731 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 732 jpool_entries); 733 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 734 entry, jpool_entries); 735 } 736 } 737 738 return; 739} 740 741 742/* 743 * Intialize a standard receive ring descriptor. 744 */ 745static int ti_newbuf_std(sc, i, m) 746 struct ti_softc *sc; 747 int i; 748 struct mbuf *m; 749{ 750 struct mbuf *m_new = NULL; 751 struct ti_rx_desc *r; 752 753 if (m != NULL) { 754 m_new = m; 755 } else { 756 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 757 if (m_new == NULL) { 758 printf("ti%d: mbuf allocation failed " 759 "-- packet dropped!\n", sc->ti_unit); 760 return(ENOBUFS); 761 } 762 763 MCLGET(m_new, M_DONTWAIT); 764 if (!(m_new->m_flags & M_EXT)) { 765 printf("ti%d: cluster allocation failed " 766 "-- packet dropped!\n", sc->ti_unit); 767 m_freem(m_new); 768 return(ENOBUFS); 769 } 770 } 771 772 m_adj(m_new, ETHER_ALIGN); 773 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 774 r = &sc->ti_rdata->ti_rx_std_ring[i]; 775 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 776 r->ti_type = TI_BDTYPE_RECV_BD; 777#ifdef TI_CSUM_OFFLOAD 778 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 779#else 780 r->ti_flags = 0; 781#endif 782 r->ti_len = MCLBYTES - ETHER_ALIGN; 783 r->ti_idx = i; 784 785 return(0); 786} 787 788/* 789 * Intialize a mini receive ring descriptor. This only applies to 790 * the Tigon 2. 791 */ 792static int ti_newbuf_mini(sc, i, m) 793 struct ti_softc *sc; 794 int i; 795 struct mbuf *m; 796{ 797 struct mbuf *m_new = NULL; 798 struct ti_rx_desc *r; 799 800 if (m != NULL) { 801 m_new = m; 802 } else { 803 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 804 if (m_new == NULL) { 805 printf("ti%d: mbuf allocation failed " 806 "-- packet dropped!\n", sc->ti_unit); 807 return(ENOBUFS); 808 } 809 } 810 m_adj(m_new, ETHER_ALIGN); 811 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 812 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 813 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 814 r->ti_type = TI_BDTYPE_RECV_BD; 815 r->ti_flags = TI_BDFLAG_MINI_RING; 816#ifdef TI_CSUM_OFFLOAD 817 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 818#endif 819 r->ti_len = MHLEN - ETHER_ALIGN; 820 r->ti_idx = i; 821 822 return(0); 823} 824 825/* 826 * Initialize a jumbo receive ring descriptor. This allocates 827 * a jumbo buffer from the pool managed internally by the driver. 828 */ 829static int ti_newbuf_jumbo(sc, i, m) 830 struct ti_softc *sc; 831 int i; 832 struct mbuf *m; 833{ 834 struct mbuf *m_new = NULL; 835 struct ti_rx_desc *r; 836 837 if (m != NULL) { 838 m_new = m; 839 } else { 840 caddr_t *buf = NULL; 841 842 /* Allocate the mbuf. */ 843 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 844 if (m_new == NULL) { 845 printf("ti%d: mbuf allocation failed " 846 "-- packet dropped!\n", sc->ti_unit); 847 return(ENOBUFS); 848 } 849 850 /* Allocate the jumbo buffer */ 851 buf = ti_jalloc(sc); 852 if (buf == NULL) { 853 m_freem(m_new); 854 printf("ti%d: jumbo allocation failed " 855 "-- packet dropped!\n", sc->ti_unit); 856 return(ENOBUFS); 857 } 858 859 /* Attach the buffer to the mbuf. */ 860 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 861 m_new->m_data += ETHER_ALIGN; 862 m_new->m_flags |= M_EXT; 863 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 864 m_new->m_ext.ext_free = ti_jfree; 865 m_new->m_ext.ext_ref = ti_jref; 866 } 867 868 /* Set up the descriptor. */ 869 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 870 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 871 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 872 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 873 r->ti_flags = TI_BDFLAG_JUMBO_RING; 874#ifdef TI_CSUM_OFFLOAD 875 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 876#endif 877 r->ti_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 878 r->ti_idx = i; 879 880 return(0); 881} 882 883/* 884 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 885 * that's 1MB or memory, which is a lot. For now, we fill only the first 886 * 256 ring entries and hope that our CPU is fast enough to keep up with 887 * the NIC. 888 */ 889static int ti_init_rx_ring_std(sc) 890 struct ti_softc *sc; 891{ 892 register int i; 893 struct ti_cmd_desc cmd; 894 895 for (i = 0; i < TI_SSLOTS; i++) { 896 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 897 return(ENOBUFS); 898 }; 899 900 TI_UPDATE_STDPROD(sc, i - 1); 901 sc->ti_std = i - 1; 902 903 return(0); 904} 905 906static void ti_free_rx_ring_std(sc) 907 struct ti_softc *sc; 908{ 909 register int i; 910 911 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 912 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 913 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 914 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 915 } 916 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 917 sizeof(struct ti_rx_desc)); 918 } 919 920 return; 921} 922 923static int ti_init_rx_ring_jumbo(sc) 924 struct ti_softc *sc; 925{ 926 register int i; 927 struct ti_cmd_desc cmd; 928 929 for (i = 0; i < (TI_JSLOTS - 20); i++) { 930 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 931 return(ENOBUFS); 932 }; 933 934 TI_UPDATE_JUMBOPROD(sc, i - 1); 935 sc->ti_jumbo = i - 1; 936 937 return(0); 938} 939 940static void ti_free_rx_ring_jumbo(sc) 941 struct ti_softc *sc; 942{ 943 register int i; 944 945 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 946 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 947 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 948 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 949 } 950 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 951 sizeof(struct ti_rx_desc)); 952 } 953 954 return; 955} 956 957static int ti_init_rx_ring_mini(sc) 958 struct ti_softc *sc; 959{ 960 register int i; 961 962 for (i = 0; i < TI_MSLOTS; i++) { 963 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 964 return(ENOBUFS); 965 }; 966 967 TI_UPDATE_MINIPROD(sc, i - 1); 968 sc->ti_mini = i - 1; 969 970 return(0); 971} 972 973static void ti_free_rx_ring_mini(sc) 974 struct ti_softc *sc; 975{ 976 register int i; 977 978 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 979 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 980 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 981 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 982 } 983 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 984 sizeof(struct ti_rx_desc)); 985 } 986 987 return; 988} 989 990static void ti_free_tx_ring(sc) 991 struct ti_softc *sc; 992{ 993 register int i; 994 995 if (sc->ti_rdata->ti_tx_ring == NULL) 996 return; 997 998 for (i = 0; i < TI_TX_RING_CNT; i++) { 999 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1000 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1001 sc->ti_cdata.ti_tx_chain[i] = NULL; 1002 } 1003 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1004 sizeof(struct ti_tx_desc)); 1005 } 1006 1007 return; 1008} 1009 1010static int ti_init_tx_ring(sc) 1011 struct ti_softc *sc; 1012{ 1013 sc->ti_txcnt = 0; 1014 sc->ti_tx_saved_considx = 0; 1015 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1016 return(0); 1017} 1018 1019/* 1020 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1021 * but we have to support the old way too so that Tigon 1 cards will 1022 * work. 1023 */ 1024void ti_add_mcast(sc, addr) 1025 struct ti_softc *sc; 1026 struct ether_addr *addr; 1027{ 1028 struct ti_cmd_desc cmd; 1029 u_int16_t *m; 1030 u_int32_t ext[2] = {0, 0}; 1031 1032 m = (u_int16_t *)&addr->octet[0]; 1033 1034 switch(sc->ti_hwrev) { 1035 case TI_HWREV_TIGON: 1036 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1037 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1038 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1039 break; 1040 case TI_HWREV_TIGON_II: 1041 ext[0] = htons(m[0]); 1042 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1043 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1044 break; 1045 default: 1046 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1047 break; 1048 } 1049 1050 return; 1051} 1052 1053void ti_del_mcast(sc, addr) 1054 struct ti_softc *sc; 1055 struct ether_addr *addr; 1056{ 1057 struct ti_cmd_desc cmd; 1058 u_int16_t *m; 1059 u_int32_t ext[2] = {0, 0}; 1060 1061 m = (u_int16_t *)&addr->octet[0]; 1062 1063 switch(sc->ti_hwrev) { 1064 case TI_HWREV_TIGON: 1065 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1066 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1067 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1068 break; 1069 case TI_HWREV_TIGON_II: 1070 ext[0] = htons(m[0]); 1071 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1072 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1073 break; 1074 default: 1075 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1076 break; 1077 } 1078 1079 return; 1080} 1081 1082/* 1083 * Configure the Tigon's multicast address filter. 1084 * 1085 * The actual multicast table management is a bit of a pain, thanks to 1086 * slight brain damage on the part of both Alteon and us. With our 1087 * multicast code, we are only alerted when the multicast address table 1088 * changes and at that point we only have the current list of addresses: 1089 * we only know the current state, not the previous state, so we don't 1090 * actually know what addresses were removed or added. The firmware has 1091 * state, but we can't get our grubby mits on it, and there is no 'delete 1092 * all multicast addresses' command. Hence, we have to maintain our own 1093 * state so we know what addresses have been programmed into the NIC at 1094 * any given time. 1095 */ 1096static void ti_setmulti(sc) 1097 struct ti_softc *sc; 1098{ 1099 struct ifnet *ifp; 1100 struct ifmultiaddr *ifma; 1101 struct ti_cmd_desc cmd; 1102 struct ti_mc_entry *mc; 1103 u_int32_t intrs; 1104 1105 ifp = &sc->arpcom.ac_if; 1106 1107 if (ifp->if_flags & IFF_ALLMULTI) { 1108 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1109 return; 1110 } else { 1111 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1112 } 1113 1114 /* Disable interrupts. */ 1115 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1116 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1117 1118 /* First, zot all the existing filters. */ 1119 while (sc->ti_mc_listhead.slh_first != NULL) { 1120 mc = sc->ti_mc_listhead.slh_first; 1121 ti_del_mcast(sc, &mc->mc_addr); 1122 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1123 free(mc, M_DEVBUF); 1124 } 1125 1126 /* Now program new ones. */ 1127 for (ifma = ifp->if_multiaddrs.lh_first; 1128 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1129 if (ifma->ifma_addr->sa_family != AF_LINK) 1130 continue; 1131 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1132 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1133 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1134 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1135 ti_add_mcast(sc, &mc->mc_addr); 1136 } 1137 1138 /* Re-enable interrupts. */ 1139 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1140 1141 return; 1142} 1143 1144/* 1145 * Check to see if the BIOS has configured us for a 64 bit slot when 1146 * we aren't actually in one. If we detect this condition, we can work 1147 * around it on the Tigon 2 by setting a bit in the PCI state register, 1148 * but for the Tigon 1 we must give up and abort the interface attach. 1149 */ 1150static int ti_64bitslot_war(sc) 1151 struct ti_softc *sc; 1152{ 1153 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1154 CSR_WRITE_4(sc, 0x600, 0); 1155 CSR_WRITE_4(sc, 0x604, 0); 1156 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1157 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1158 if (sc->ti_hwrev == TI_HWREV_TIGON) 1159 return(EINVAL); 1160 else { 1161 TI_SETBIT(sc, TI_PCI_STATE, 1162 TI_PCISTATE_32BIT_BUS); 1163 return(0); 1164 } 1165 } 1166 } 1167 1168 return(0); 1169} 1170 1171/* 1172 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1173 * self-test results. 1174 */ 1175static int ti_chipinit(sc) 1176 struct ti_softc *sc; 1177{ 1178 u_int32_t cacheline; 1179 u_int32_t pci_writemax = 0; 1180 1181 /* Initialize link to down state. */ 1182 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1183 1184 /* Set endianness before we access any non-PCI registers. */ 1185#if BYTE_ORDER == BIG_ENDIAN 1186 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1187 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1188#else 1189 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1190 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1191#endif 1192 1193 /* Check the ROM failed bit to see if self-tests passed. */ 1194 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1195 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1196 return(ENODEV); 1197 } 1198 1199 /* Halt the CPU. */ 1200 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1201 1202 /* Figure out the hardware revision. */ 1203 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1204 case TI_REV_TIGON_I: 1205 sc->ti_hwrev = TI_HWREV_TIGON; 1206 break; 1207 case TI_REV_TIGON_II: 1208 sc->ti_hwrev = TI_HWREV_TIGON_II; 1209 break; 1210 default: 1211 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1212 return(ENODEV); 1213 } 1214 1215 /* Do special setup for Tigon 2. */ 1216 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1217 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1218 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1219 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1220 } 1221 1222 /* Set up the PCI state register. */ 1223 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1224 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1225 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1226 } 1227 1228 /* Clear the read/write max DMA parameters. */ 1229 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1230 TI_PCISTATE_READ_MAXDMA)); 1231 1232 /* Get cache line size. */ 1233 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1234 1235 /* 1236 * If the system has set enabled the PCI memory write 1237 * and invalidate command in the command register, set 1238 * the write max parameter accordingly. This is necessary 1239 * to use MWI with the Tigon 2. 1240 */ 1241 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1242 switch(cacheline) { 1243 case 1: 1244 case 4: 1245 case 8: 1246 case 16: 1247 case 32: 1248 case 64: 1249 break; 1250 default: 1251 /* Disable PCI memory write and invalidate. */ 1252 if (bootverbose) 1253 printf("ti%d: cache line size %d not " 1254 "supported; disabling PCI MWI\n", 1255 sc->ti_unit, cacheline); 1256 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1257 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1258 break; 1259 } 1260 } 1261 1262#ifdef __brokenalpha__ 1263 /* 1264 * From the Alteon sample driver: 1265 * Must insure that we do not cross an 8K (bytes) boundary 1266 * for DMA reads. Our highest limit is 1K bytes. This is a 1267 * restriction on some ALPHA platforms with early revision 1268 * 21174 PCI chipsets, such as the AlphaPC 164lx 1269 */ 1270 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1271#else 1272 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1273#endif 1274 1275 /* This sets the min dma param all the way up (0xff). */ 1276 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1277 1278 /* Configure DMA variables. */ 1279#if BYTE_ORDER == BIG_ENDIAN 1280 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1281 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1282 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1283 TI_OPMODE_DONT_FRAG_JUMBO); 1284#else 1285 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1286 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1287 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1288#endif 1289 1290 /* 1291 * Only allow 1 DMA channel to be active at a time. 1292 * I don't think this is a good idea, but without it 1293 * the firmware racks up lots of nicDmaReadRingFull 1294 * errors. 1295 */ 1296#ifndef TI_CSUM_OFFLOAD 1297 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1298#endif 1299 1300 /* Recommended settings from Tigon manual. */ 1301 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1302 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1303 1304 if (ti_64bitslot_war(sc)) { 1305 printf("ti%d: bios thinks we're in a 64 bit slot, " 1306 "but we aren't", sc->ti_unit); 1307 return(EINVAL); 1308 } 1309 1310 return(0); 1311} 1312 1313/* 1314 * Initialize the general information block and firmware, and 1315 * start the CPU(s) running. 1316 */ 1317static int ti_gibinit(sc) 1318 struct ti_softc *sc; 1319{ 1320 struct ti_rcb *rcb; 1321 int i; 1322 struct ifnet *ifp; 1323 1324 ifp = &sc->arpcom.ac_if; 1325 1326 /* Disable interrupts for now. */ 1327 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1328 1329 /* Tell the chip where to find the general information block. */ 1330 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1331 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1332 1333 /* Load the firmware into SRAM. */ 1334 ti_loadfw(sc); 1335 1336 /* Set up the contents of the general info and ring control blocks. */ 1337 1338 /* Set up the event ring and producer pointer. */ 1339 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1340 1341 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1342 rcb->ti_flags = 0; 1343 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1344 vtophys(&sc->ti_ev_prodidx); 1345 sc->ti_ev_prodidx.ti_idx = 0; 1346 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1347 sc->ti_ev_saved_considx = 0; 1348 1349 /* Set up the command ring and producer mailbox. */ 1350 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1351 1352#ifdef __i386__ 1353 sc->ti_rdata->ti_cmd_ring = 1354 (struct ti_cmd_desc *)(sc->ti_bhandle + TI_GCR_CMDRING); 1355#endif 1356#ifdef __alpha__ 1357 sc->ti_rdata->ti_cmd_ring = 1358 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1359#endif 1360 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1361 rcb->ti_flags = 0; 1362 rcb->ti_max_len = 0; 1363 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1364 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1365 } 1366 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1367 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1368 sc->ti_cmd_saved_prodidx = 0; 1369 1370 /* 1371 * Assign the address of the stats refresh buffer. 1372 * We re-use the current stats buffer for this to 1373 * conserve memory. 1374 */ 1375 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1376 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1377 1378 /* Set up the standard receive ring. */ 1379 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1380 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1381 rcb->ti_max_len = TI_FRAMELEN; 1382 rcb->ti_flags = 0; 1383#ifdef TI_CSUM_OFFLOAD 1384 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1385#endif 1386#if NVLAN > 0 1387 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1388#endif 1389 1390 /* Set up the jumbo receive ring. */ 1391 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1392 TI_HOSTADDR(rcb->ti_hostaddr) = 1393 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1394 rcb->ti_max_len = TI_JUMBO_FRAMELEN - ETHER_ALIGN; 1395 rcb->ti_flags = 0; 1396#ifdef TI_CSUM_OFFLOAD 1397 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1398#endif 1399#if NVLAN > 0 1400 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1401#endif 1402 1403 /* 1404 * Set up the mini ring. Only activated on the 1405 * Tigon 2 but the slot in the config block is 1406 * still there on the Tigon 1. 1407 */ 1408 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1409 TI_HOSTADDR(rcb->ti_hostaddr) = 1410 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1411 rcb->ti_max_len = MHLEN; 1412 if (sc->ti_hwrev == TI_HWREV_TIGON) 1413 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1414 else 1415 rcb->ti_flags = 0; 1416#ifdef TI_CSUM_OFFLOAD 1417 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1418#endif 1419#if NVLAN > 0 1420 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1421#endif 1422 1423 /* 1424 * Set up the receive return ring. 1425 */ 1426 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1427 TI_HOSTADDR(rcb->ti_hostaddr) = 1428 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1429 rcb->ti_flags = 0; 1430 rcb->ti_max_len = TI_RETURN_RING_CNT; 1431 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1432 vtophys(&sc->ti_return_prodidx); 1433 1434 /* 1435 * Set up the tx ring. Note: for the Tigon 2, we have the option 1436 * of putting the transmit ring in the host's address space and 1437 * letting the chip DMA it instead of leaving the ring in the NIC's 1438 * memory and accessing it through the shared memory region. We 1439 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1440 * so we have to revert to the shared memory scheme if we detect 1441 * a Tigon 1 chip. 1442 */ 1443 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1444 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1445#ifdef __i386__ 1446 sc->ti_rdata->ti_tx_ring_nic = 1447 (struct ti_tx_desc *)(sc->ti_bhandle + TI_WINDOW); 1448#endif 1449#ifdef __alpha__ 1450 sc->ti_rdata->ti_tx_ring_nic = 1451 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1452#endif 1453 } 1454 bzero((char *)sc->ti_rdata->ti_tx_ring, 1455 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1456 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1457 if (sc->ti_hwrev == TI_HWREV_TIGON) 1458 rcb->ti_flags = 0; 1459 else 1460 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1461#if NVLAN > 0 1462 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1463#endif 1464 rcb->ti_max_len = TI_TX_RING_CNT; 1465 if (sc->ti_hwrev == TI_HWREV_TIGON) 1466 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1467 else 1468 TI_HOSTADDR(rcb->ti_hostaddr) = 1469 vtophys(&sc->ti_rdata->ti_tx_ring); 1470 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1471 vtophys(&sc->ti_tx_considx); 1472 1473 /* Set up tuneables */ 1474 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1475 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1476 (sc->ti_rx_coal_ticks / 10)); 1477 else 1478 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1479 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1480 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1481 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1482 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1483 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1484 1485 /* Turn interrupts on. */ 1486 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1487 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1488 1489 /* Start CPU. */ 1490 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1491 1492 return(0); 1493} 1494 1495/* 1496 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1497 * against our list and return its name if we find a match. 1498 */ 1499static const char * 1500ti_probe(config_id, device_id) 1501 pcici_t config_id; 1502 pcidi_t device_id; 1503{ 1504 struct ti_type *t; 1505 1506 t = ti_devs; 1507 1508 while(t->ti_name != NULL) { 1509 if ((device_id & 0xFFFF) == t->ti_vid && 1510 ((device_id >> 16) & 0xFFFF) == t->ti_did) 1511 return(t->ti_name); 1512 t++; 1513 } 1514 1515 return(NULL); 1516} 1517 1518 1519static void 1520ti_attach(config_id, unit) 1521 pcici_t config_id; 1522 int unit; 1523{ 1524 vm_offset_t pbase, vbase; 1525 int s; 1526 u_int32_t command; 1527 struct ifnet *ifp; 1528 struct ti_softc *sc; 1529 1530 s = splimp(); 1531 1532 /* First, allocate memory for the softc struct. */ 1533 sc = malloc(sizeof(struct ti_softc), M_DEVBUF, M_NOWAIT); 1534 if (sc == NULL) { 1535 printf("ti%d: no memory for softc struct!\n", unit); 1536 goto fail; 1537 } 1538 1539 bzero(sc, sizeof(struct ti_softc)); 1540 1541 /* 1542 * Map control/status registers. 1543 */ 1544 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1545 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1546 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1547 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1548 1549 if (!(command & PCIM_CMD_MEMEN)) { 1550 printf("ti%d: failed to enable memory mapping!\n", unit); 1551 free(sc, M_DEVBUF); 1552 goto fail; 1553 } 1554 1555#ifdef __i386__ 1556 if (!pci_map_mem(config_id, TI_PCI_LOMEM, &vbase, &pbase)) { 1557 printf ("ti%d: couldn't map memory\n", unit); 1558 free(sc, M_DEVBUF); 1559 goto fail; 1560 } 1561 1562 sc->ti_bhandle = vbase; 1563 sc->ti_btag = I386_BUS_SPACE_MEM; 1564#endif 1565 1566#ifdef __alpha__ 1567 if (!(pci_map_bwx(config_id, TI_PCI_LOMEM, &vbase, &pbase) || 1568 pci_map_dense(config_id, TI_PCI_LOMEM, &vbase, &pbase))){ 1569 printf ("ti%d: couldn't map memory\n", unit); 1570 free(sc, M_DEVBUF); 1571 goto fail; 1572 } 1573 1574 sc->ti_bhandle = pbase; 1575 sc->ti_vhandle = vbase; 1576 sc->ti_btag = ALPHA_BUS_SPACE_MEM; 1577#endif 1578 /* Allocate interrupt */ 1579 if (!pci_map_int(config_id, ti_intr, sc, &net_imask)) { 1580 printf("ti%d: couldn't map interrupt\n", unit); 1581 free(sc, M_DEVBUF); 1582 goto fail; 1583 } 1584 1585 sc->ti_unit = unit; 1586 1587 if (ti_chipinit(sc)) { 1588 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1589 free(sc, M_DEVBUF); 1590 goto fail; 1591 } 1592 1593 /* Zero out the NIC's on-board SRAM. */ 1594 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1595 1596 /* Init again -- zeroing memory may have clobbered some registers. */ 1597 if (ti_chipinit(sc)) { 1598 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1599 free(sc, M_DEVBUF); 1600 goto fail; 1601 } 1602 1603 /* 1604 * Get station address from the EEPROM. Note: the manual states 1605 * that the MAC address is at offset 0x8c, however the data is 1606 * stored as two longwords (since that's how it's loaded into 1607 * the NIC). This means the MAC address is actually preceeded 1608 * by two zero bytes. We need to skip over those. 1609 */ 1610 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1611 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1612 printf("ti%d: failed to read station address\n", unit); 1613 free(sc, M_DEVBUF); 1614 goto fail; 1615 } 1616 1617 /* 1618 * A Tigon chip was detected. Inform the world. 1619 */ 1620 printf("ti%d: Ethernet address: %6D\n", unit, 1621 sc->arpcom.ac_enaddr, ":"); 1622 1623 /* Allocate the general information block and ring buffers. */ 1624 sc->ti_rdata_ptr = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1625 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1626 1627 if (sc->ti_rdata_ptr == NULL) { 1628 free(sc, M_DEVBUF); 1629 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1630 goto fail; 1631 } 1632 1633 sc->ti_rdata = (struct ti_ring_data *)sc->ti_rdata_ptr; 1634 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1635 1636 /* Try to allocate memory for jumbo buffers. */ 1637 if (ti_alloc_jumbo_mem(sc)) { 1638 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1639 free(sc->ti_rdata_ptr, M_DEVBUF); 1640 free(sc, M_DEVBUF); 1641 goto fail; 1642 } 1643 1644 /* Set default tuneable values. */ 1645 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1646 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1647 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1648 sc->ti_rx_max_coal_bds = 64; 1649 sc->ti_tx_max_coal_bds = 128; 1650 sc->ti_tx_buf_ratio = 21; 1651 1652 /* Set up ifnet structure */ 1653 ifp = &sc->arpcom.ac_if; 1654 ifp->if_softc = sc; 1655 ifp->if_unit = sc->ti_unit; 1656 ifp->if_name = "ti"; 1657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1658 ifp->if_ioctl = ti_ioctl; 1659 ifp->if_output = ether_output; 1660 ifp->if_start = ti_start; 1661 ifp->if_watchdog = ti_watchdog; 1662 ifp->if_init = ti_init; 1663 ifp->if_mtu = ETHERMTU; 1664 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1665 1666 /* Set up ifmedia support. */ 1667 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1668 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1669 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1670 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1671 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1672 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1673 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1674 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1675 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1676 1677 /* 1678 * Call MI attach routines. 1679 */ 1680 if_attach(ifp); 1681 ether_ifattach(ifp); 1682 1683#if NBPFILTER > 0 1684 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1685#endif 1686 1687 at_shutdown(ti_shutdown, sc, SHUTDOWN_POST_SYNC); 1688 1689fail: 1690 splx(s); 1691 1692 return; 1693} 1694 1695/* 1696 * Frame reception handling. This is called if there's a frame 1697 * on the receive return list. 1698 * 1699 * Note: we have to be able to handle three possibilities here: 1700 * 1) the frame is from the mini receive ring (can only happen) 1701 * on Tigon 2 boards) 1702 * 2) the frame is from the jumbo recieve ring 1703 * 3) the frame is from the standard receive ring 1704 */ 1705 1706static void ti_rxeof(sc) 1707 struct ti_softc *sc; 1708{ 1709 struct ifnet *ifp; 1710 struct ti_cmd_desc cmd; 1711 1712 ifp = &sc->arpcom.ac_if; 1713 1714 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1715 struct ti_rx_desc *cur_rx; 1716 u_int32_t rxidx; 1717 struct ether_header *eh; 1718 struct mbuf *m = NULL; 1719#if NVLAN > 0 1720 u_int16_t vlan_tag = 0; 1721 int have_tag = 0; 1722#endif 1723#ifdef TI_CSUM_OFFLOAD 1724 struct ip *ip; 1725#endif 1726 1727 cur_rx = 1728 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1729 rxidx = cur_rx->ti_idx; 1730 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1731 1732#if NVLAN > 0 1733 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1734 have_tag = 1; 1735 vlan_tag = cur_rx->ti_vlan_tag; 1736 } 1737#endif 1738 1739 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1740 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1741 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1742 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1743 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1744 ifp->if_ierrors++; 1745 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1746 continue; 1747 } 1748 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1749 ifp->if_ierrors++; 1750 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1751 continue; 1752 } 1753 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1754 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1755 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1756 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1757 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1758 ifp->if_ierrors++; 1759 ti_newbuf_mini(sc, sc->ti_mini, m); 1760 continue; 1761 } 1762 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1763 ifp->if_ierrors++; 1764 ti_newbuf_mini(sc, sc->ti_mini, m); 1765 continue; 1766 } 1767 } else { 1768 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1769 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1770 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1771 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1772 ifp->if_ierrors++; 1773 ti_newbuf_std(sc, sc->ti_std, m); 1774 continue; 1775 } 1776 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1777 ifp->if_ierrors++; 1778 ti_newbuf_std(sc, sc->ti_std, m); 1779 continue; 1780 } 1781 } 1782 1783 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1784 ifp->if_ipackets++; 1785 eh = mtod(m, struct ether_header *); 1786 m->m_pkthdr.rcvif = ifp; 1787 1788#if NBPFILTER > 0 1789 /* 1790 * Handle BPF listeners. Let the BPF user see the packet, but 1791 * don't pass it up to the ether_input() layer unless it's 1792 * a broadcast packet, multicast packet, matches our ethernet 1793 * address or the interface is in promiscuous mode. 1794 */ 1795 if (ifp->if_bpf) { 1796 bpf_mtap(ifp, m); 1797 if (ifp->if_flags & IFF_PROMISC && 1798 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1799 ETHER_ADDR_LEN) && 1800 (eh->ether_dhost[0] & 1) == 0)) { 1801 m_freem(m); 1802 continue; 1803 } 1804 } 1805#endif 1806 1807 /* Remove header from mbuf and pass it on. */ 1808 m_adj(m, sizeof(struct ether_header)); 1809 1810#ifdef TI_CSUM_OFFLOAD 1811 ip = mtod(m, struct ip *); 1812 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 1813 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 1814 m->m_flags |= M_HWCKSUM; 1815#endif 1816 1817#if NVLAN > 0 1818 /* 1819 * If we received a packet with a vlan tag, pass it 1820 * to vlan_input() instead of ether_input(). 1821 */ 1822 if (have_tag) { 1823 vlan_input_tag(eh, m, vlan_tag); 1824 have_tag = vlan_tag = 0; 1825 continue; 1826 } 1827#endif 1828 ether_input(ifp, eh, m); 1829 } 1830 1831 /* Only necessary on the Tigon 1. */ 1832 if (sc->ti_hwrev == TI_HWREV_TIGON) 1833 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1834 sc->ti_rx_saved_considx); 1835 1836 TI_UPDATE_STDPROD(sc, sc->ti_std); 1837 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1838 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1839 1840 return; 1841} 1842 1843static void ti_txeof(sc) 1844 struct ti_softc *sc; 1845{ 1846 struct ti_tx_desc *cur_tx = NULL; 1847 struct ifnet *ifp; 1848 1849 ifp = &sc->arpcom.ac_if; 1850 1851 /* 1852 * Go through our tx ring and free mbufs for those 1853 * frames that have been sent. 1854 */ 1855 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1856 u_int32_t idx = 0; 1857 1858 idx = sc->ti_tx_saved_considx; 1859 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1860 if (idx > 383) 1861 CSR_WRITE_4(sc, TI_WINBASE, 1862 TI_TX_RING_BASE + 6144); 1863 else if (idx > 255) 1864 CSR_WRITE_4(sc, TI_WINBASE, 1865 TI_TX_RING_BASE + 4096); 1866 else if (idx > 127) 1867 CSR_WRITE_4(sc, TI_WINBASE, 1868 TI_TX_RING_BASE + 2048); 1869 else 1870 CSR_WRITE_4(sc, TI_WINBASE, 1871 TI_TX_RING_BASE); 1872 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1873 } else 1874 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1875 if (cur_tx->ti_flags & TI_BDFLAG_END) 1876 ifp->if_opackets++; 1877 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1878 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1879 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1880 } 1881 sc->ti_txcnt--; 1882 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1883 ifp->if_timer = 0; 1884 } 1885 1886 if (cur_tx != NULL) 1887 ifp->if_flags &= ~IFF_OACTIVE; 1888 1889 return; 1890} 1891 1892static void ti_intr(xsc) 1893 void *xsc; 1894{ 1895 struct ti_softc *sc; 1896 struct ifnet *ifp; 1897 1898 sc = xsc; 1899 ifp = &sc->arpcom.ac_if; 1900 1901#ifdef notdef 1902 /* Avoid this for now -- checking this register is expensive. */ 1903 /* Make sure this is really our interrupt. */ 1904 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1905 return; 1906#endif 1907 1908 /* Ack interrupt and stop others from occuring. */ 1909 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1910 1911 if (ifp->if_flags & IFF_RUNNING) { 1912 /* Check RX return ring producer/consumer */ 1913 ti_rxeof(sc); 1914 1915 /* Check TX ring producer/consumer */ 1916 ti_txeof(sc); 1917 } 1918 1919 ti_handle_events(sc); 1920 1921 /* Re-enable interrupts. */ 1922 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1923 1924 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1925 ti_start(ifp); 1926 1927 return; 1928} 1929 1930static void ti_stats_update(sc) 1931 struct ti_softc *sc; 1932{ 1933 struct ifnet *ifp; 1934 1935 ifp = &sc->arpcom.ac_if; 1936 1937 ifp->if_collisions += 1938 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1939 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1940 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1941 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1942 ifp->if_collisions; 1943 1944 return; 1945} 1946 1947/* 1948 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1949 * pointers to descriptors. 1950 */ 1951static int ti_encap(sc, m_head, txidx) 1952 struct ti_softc *sc; 1953 struct mbuf *m_head; 1954 u_int32_t *txidx; 1955{ 1956 struct ti_tx_desc *f = NULL; 1957 struct mbuf *m; 1958 u_int32_t frag, cur, cnt = 0; 1959#if NVLAN > 0 1960 struct ifvlan *ifv = NULL; 1961 1962 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1963 m_head->m_pkthdr.rcvif != NULL && 1964 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1965 ifv = m_head->m_pkthdr.rcvif->if_softc; 1966#endif 1967 1968 m = m_head; 1969 cur = frag = *txidx; 1970 1971 /* 1972 * Start packing the mbufs in this chain into 1973 * the fragment pointers. Stop when we run out 1974 * of fragments or hit the end of the mbuf chain. 1975 */ 1976 for (m = m_head; m != NULL; m = m->m_next) { 1977 if (m->m_len != 0) { 1978 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1979 if (frag > 383) 1980 CSR_WRITE_4(sc, TI_WINBASE, 1981 TI_TX_RING_BASE + 6144); 1982 else if (frag > 255) 1983 CSR_WRITE_4(sc, TI_WINBASE, 1984 TI_TX_RING_BASE + 4096); 1985 else if (frag > 127) 1986 CSR_WRITE_4(sc, TI_WINBASE, 1987 TI_TX_RING_BASE + 2048); 1988 else 1989 CSR_WRITE_4(sc, TI_WINBASE, 1990 TI_TX_RING_BASE); 1991 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 1992 } else 1993 f = &sc->ti_rdata->ti_tx_ring[frag]; 1994 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1995 break; 1996 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 1997 f->ti_len = m->m_len; 1998 f->ti_flags = 0; 1999#if NVLAN > 0 2000 if (ifv != NULL) { 2001 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2002 f->ti_vlan_tag = ifv->ifv_tag; 2003 } else { 2004 f->ti_vlan_tag = 0; 2005 } 2006#endif 2007 /* 2008 * Sanity check: avoid coming within 16 descriptors 2009 * of the end of the ring. 2010 */ 2011 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2012 return(ENOBUFS); 2013 cur = frag; 2014 TI_INC(frag, TI_TX_RING_CNT); 2015 cnt++; 2016 } 2017 } 2018 2019 if (m != NULL) 2020 return(ENOBUFS); 2021 2022 if (frag == sc->ti_tx_saved_considx) 2023 return(ENOBUFS); 2024 2025 if (sc->ti_hwrev == TI_HWREV_TIGON) 2026 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2027 TI_BDFLAG_END; 2028 else 2029 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2030 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2031 sc->ti_txcnt += cnt; 2032 2033 *txidx = frag; 2034 2035 return(0); 2036} 2037 2038/* 2039 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2040 * to the mbuf data regions directly in the transmit descriptors. 2041 */ 2042static void ti_start(ifp) 2043 struct ifnet *ifp; 2044{ 2045 struct ti_softc *sc; 2046 struct mbuf *m_head = NULL; 2047 u_int32_t prodidx = 0; 2048 2049 sc = ifp->if_softc; 2050 2051 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2052 2053 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2054 IF_DEQUEUE(&ifp->if_snd, m_head); 2055 if (m_head == NULL) 2056 break; 2057 2058 /* 2059 * Pack the data into the transmit ring. If we 2060 * don't have room, set the OACTIVE flag and wait 2061 * for the NIC to drain the ring. 2062 */ 2063 if (ti_encap(sc, m_head, &prodidx)) { 2064 IF_PREPEND(&ifp->if_snd, m_head); 2065 ifp->if_flags |= IFF_OACTIVE; 2066 break; 2067 } 2068 2069 /* 2070 * If there's a BPF listener, bounce a copy of this frame 2071 * to him. 2072 */ 2073#if NBPFILTER > 0 2074 if (ifp->if_bpf) 2075 bpf_mtap(ifp, m_head); 2076#endif 2077 } 2078 2079 /* Transmit */ 2080 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2081 2082 /* 2083 * Set a timeout in case the chip goes out to lunch. 2084 */ 2085 ifp->if_timer = 5; 2086 2087 return; 2088} 2089 2090static void ti_init(xsc) 2091 void *xsc; 2092{ 2093 struct ti_softc *sc = xsc; 2094 int s; 2095 2096 s = splimp(); 2097 2098 /* Cancel pending I/O and flush buffers. */ 2099 ti_stop(sc); 2100 2101 /* Init the gen info block, ring control blocks and firmware. */ 2102 if (ti_gibinit(sc)) { 2103 printf("ti%d: initialization failure\n", sc->ti_unit); 2104 splx(s); 2105 return; 2106 } 2107 2108 splx(s); 2109 2110 return; 2111} 2112 2113static void ti_init2(sc) 2114 struct ti_softc *sc; 2115{ 2116 struct ti_cmd_desc cmd; 2117 struct ifnet *ifp; 2118 u_int16_t *m; 2119 struct ifmedia *ifm; 2120 int tmp; 2121 2122 ifp = &sc->arpcom.ac_if; 2123 2124 /* Specify MTU and interface index. */ 2125 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2126 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2127 ETHER_HDR_LEN + ETHER_CRC_LEN); 2128 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2129 2130 /* Load our MAC address. */ 2131 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2132 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2133 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2134 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2135 2136 /* Enable or disable promiscuous mode as needed. */ 2137 if (ifp->if_flags & IFF_PROMISC) { 2138 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2139 } else { 2140 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2141 } 2142 2143 /* Program multicast filter. */ 2144 ti_setmulti(sc); 2145 2146 /* 2147 * If this is a Tigon 1, we should tell the 2148 * firmware to use software packet filtering. 2149 */ 2150 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2151 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2152 } 2153 2154 /* Init RX ring. */ 2155 ti_init_rx_ring_std(sc); 2156 2157 /* Init jumbo RX ring. */ 2158 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2159 ti_init_rx_ring_jumbo(sc); 2160 2161 /* 2162 * If this is a Tigon 2, we can also configure the 2163 * mini ring. 2164 */ 2165 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2166 ti_init_rx_ring_mini(sc); 2167 2168 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2169 sc->ti_rx_saved_considx = 0; 2170 2171 /* Init TX ring. */ 2172 ti_init_tx_ring(sc); 2173 2174 /* Tell firmware we're alive. */ 2175 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2176 2177 /* Enable host interrupts. */ 2178 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2179 2180 ifp->if_flags |= IFF_RUNNING; 2181 ifp->if_flags &= ~IFF_OACTIVE; 2182 2183 /* 2184 * Make sure to set media properly. We have to do this 2185 * here since we have to issue commands in order to set 2186 * the link negotiation and we can't issue commands until 2187 * the firmware is running. 2188 */ 2189 ifm = &sc->ifmedia; 2190 tmp = ifm->ifm_media; 2191 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2192 ti_ifmedia_upd(ifp); 2193 ifm->ifm_media = tmp; 2194 2195 return; 2196} 2197 2198/* 2199 * Set media options. 2200 */ 2201static int ti_ifmedia_upd(ifp) 2202 struct ifnet *ifp; 2203{ 2204 struct ti_softc *sc; 2205 struct ifmedia *ifm; 2206 struct ti_cmd_desc cmd; 2207 2208 sc = ifp->if_softc; 2209 ifm = &sc->ifmedia; 2210 2211 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2212 return(EINVAL); 2213 2214 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2215 case IFM_AUTO: 2216 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2217 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2218 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2219 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2220 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2221 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2222 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2223 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2224 break; 2225 case IFM_1000_SX: 2226 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2227 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2228 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2229 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2230 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2231 break; 2232 case IFM_100_FX: 2233 case IFM_10_FL: 2234 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2235 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2236 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2237 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2238 } else { 2239 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2240 } 2241 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2242 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2243 } else { 2244 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2245 } 2246 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2247 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2248 break; 2249 } 2250 2251 return(0); 2252} 2253 2254/* 2255 * Report current media status. 2256 */ 2257static void ti_ifmedia_sts(ifp, ifmr) 2258 struct ifnet *ifp; 2259 struct ifmediareq *ifmr; 2260{ 2261 struct ti_softc *sc; 2262 2263 sc = ifp->if_softc; 2264 2265 ifmr->ifm_status = IFM_AVALID; 2266 ifmr->ifm_active = IFM_ETHER; 2267 2268 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2269 return; 2270 2271 ifmr->ifm_status |= IFM_ACTIVE; 2272 2273 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2274 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2275 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2276 u_int32_t media; 2277 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2278 if (media & TI_LNK_100MB) 2279 ifmr->ifm_active |= IFM_100_FX; 2280 if (media & TI_LNK_10MB) 2281 ifmr->ifm_active |= IFM_10_FL; 2282 if (media & TI_LNK_FULL_DUPLEX) 2283 ifmr->ifm_active |= IFM_FDX; 2284 if (media & TI_LNK_HALF_DUPLEX) 2285 ifmr->ifm_active |= IFM_HDX; 2286 } 2287 2288 return; 2289} 2290 2291static int ti_ioctl(ifp, command, data) 2292 struct ifnet *ifp; 2293 u_long command; 2294 caddr_t data; 2295{ 2296 struct ti_softc *sc = ifp->if_softc; 2297 struct ifreq *ifr = (struct ifreq *) data; 2298 int s, error = 0; 2299 struct ti_cmd_desc cmd; 2300 2301 s = splimp(); 2302 2303 switch(command) { 2304 case SIOCSIFADDR: 2305 case SIOCGIFADDR: 2306 error = ether_ioctl(ifp, command, data); 2307 break; 2308 case SIOCSIFMTU: 2309 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2310 error = EINVAL; 2311 else { 2312 ifp->if_mtu = ifr->ifr_mtu; 2313 ti_init(sc); 2314 } 2315 break; 2316 case SIOCSIFFLAGS: 2317 if (ifp->if_flags & IFF_UP) { 2318 /* 2319 * If only the state of the PROMISC flag changed, 2320 * then just use the 'set promisc mode' command 2321 * instead of reinitializing the entire NIC. Doing 2322 * a full re-init means reloading the firmware and 2323 * waiting for it to start up, which may take a 2324 * second or two. 2325 */ 2326 if (ifp->if_flags & IFF_RUNNING && 2327 ifp->if_flags & IFF_PROMISC && 2328 !(sc->ti_if_flags & IFF_PROMISC)) { 2329 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2330 TI_CMD_CODE_PROMISC_ENB, 0); 2331 } else if (ifp->if_flags & IFF_RUNNING && 2332 !(ifp->if_flags & IFF_PROMISC) && 2333 sc->ti_if_flags & IFF_PROMISC) { 2334 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2335 TI_CMD_CODE_PROMISC_DIS, 0); 2336 } else 2337 ti_init(sc); 2338 } else { 2339 if (ifp->if_flags & IFF_RUNNING) { 2340 ti_stop(sc); 2341 } 2342 } 2343 sc->ti_if_flags = ifp->if_flags; 2344 error = 0; 2345 break; 2346 case SIOCADDMULTI: 2347 case SIOCDELMULTI: 2348 if (ifp->if_flags & IFF_RUNNING) { 2349 ti_setmulti(sc); 2350 error = 0; 2351 } 2352 break; 2353 case SIOCSIFMEDIA: 2354 case SIOCGIFMEDIA: 2355 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2356 break; 2357 default: 2358 error = EINVAL; 2359 break; 2360 } 2361 2362 (void)splx(s); 2363 2364 return(error); 2365} 2366 2367static void ti_watchdog(ifp) 2368 struct ifnet *ifp; 2369{ 2370 struct ti_softc *sc; 2371 2372 sc = ifp->if_softc; 2373 2374 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2375 ti_stop(sc); 2376 ti_init(sc); 2377 2378 ifp->if_oerrors++; 2379 2380 return; 2381} 2382 2383/* 2384 * Stop the adapter and free any mbufs allocated to the 2385 * RX and TX lists. 2386 */ 2387static void ti_stop(sc) 2388 struct ti_softc *sc; 2389{ 2390 struct ifnet *ifp; 2391 struct ti_cmd_desc cmd; 2392 2393 ifp = &sc->arpcom.ac_if; 2394 2395 /* Disable host interrupts. */ 2396 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2397 /* 2398 * Tell firmware we're shutting down. 2399 */ 2400 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2401 2402 /* Halt and reinitialize. */ 2403 ti_chipinit(sc); 2404 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2405 ti_chipinit(sc); 2406 2407 /* Free the RX lists. */ 2408 ti_free_rx_ring_std(sc); 2409 2410 /* Free jumbo RX list. */ 2411 ti_free_rx_ring_jumbo(sc); 2412 2413 /* Free mini RX list. */ 2414 ti_free_rx_ring_mini(sc); 2415 2416 /* Free TX buffers. */ 2417 ti_free_tx_ring(sc); 2418 2419 sc->ti_ev_prodidx.ti_idx = 0; 2420 sc->ti_return_prodidx.ti_idx = 0; 2421 sc->ti_tx_considx.ti_idx = 0; 2422 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2423 2424 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2425 2426 return; 2427} 2428 2429/* 2430 * Stop all chip I/O so that the kernel's probe routines don't 2431 * get confused by errant DMAs when rebooting. 2432 */ 2433static void ti_shutdown(howto, xsc) 2434 int howto; 2435 void *xsc; 2436{ 2437 struct ti_softc *sc; 2438 2439 sc = xsc; 2440 2441 ti_chipinit(sc); 2442 2443 return; 2444} 2445 2446static struct pci_device ti_device = { 2447 "ti", 2448 ti_probe, 2449 ti_attach, 2450 &ti_count, 2451 NULL 2452}; 2453COMPAT_PCI_DRIVER(ti, ti_device); 2454