if_ti.c revision 227324
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 227324 2011-11-07 22:58:49Z yongari $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103 104#include <net/bpf.h> 105 106#include <netinet/in_systm.h> 107#include <netinet/in.h> 108#include <netinet/ip.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115/* #define TI_PRIVATE_JUMBOS */ 116#ifndef TI_PRIVATE_JUMBOS 117#include <vm/vm.h> 118#include <vm/vm_page.h> 119#endif 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123 124#include <sys/tiio.h> 125#include <dev/ti/if_tireg.h> 126#include <dev/ti/ti_fw.h> 127#include <dev/ti/ti_fw2.h> 128 129#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 130/* 131 * We can only turn on header splitting if we're using extended receive 132 * BDs. 133 */ 134#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 135#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 136#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 137 138typedef enum { 139 TI_SWAP_HTON, 140 TI_SWAP_NTOH 141} ti_swap_type; 142 143/* 144 * Various supported device vendors/types and their names. 145 */ 146 147static const struct ti_type const ti_devs[] = { 148 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 149 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 150 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 151 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 152 { TC_VENDORID, TC_DEVICEID_3C985, 153 "3Com 3c985-SX Gigabit Ethernet" }, 154 { NG_VENDORID, NG_DEVICEID_GA620, 155 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 156 { NG_VENDORID, NG_DEVICEID_GA620T, 157 "Netgear GA620 1000baseT Gigabit Ethernet" }, 158 { SGI_VENDORID, SGI_DEVICEID_TIGON, 159 "Silicon Graphics Gigabit Ethernet" }, 160 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 161 "Farallon PN9000SX Gigabit Ethernet" }, 162 { 0, 0, NULL } 163}; 164 165 166static d_open_t ti_open; 167static d_close_t ti_close; 168static d_ioctl_t ti_ioctl2; 169 170static struct cdevsw ti_cdevsw = { 171 .d_version = D_VERSION, 172 .d_flags = 0, 173 .d_open = ti_open, 174 .d_close = ti_close, 175 .d_ioctl = ti_ioctl2, 176 .d_name = "ti", 177}; 178 179static int ti_probe(device_t); 180static int ti_attach(device_t); 181static int ti_detach(device_t); 182static void ti_txeof(struct ti_softc *); 183static void ti_rxeof(struct ti_softc *); 184 185static void ti_stats_update(struct ti_softc *); 186static int ti_encap(struct ti_softc *, struct mbuf **); 187 188static void ti_intr(void *); 189static void ti_start(struct ifnet *); 190static void ti_start_locked(struct ifnet *); 191static int ti_ioctl(struct ifnet *, u_long, caddr_t); 192static void ti_init(void *); 193static void ti_init_locked(void *); 194static void ti_init2(struct ti_softc *); 195static void ti_stop(struct ti_softc *); 196static void ti_watchdog(void *); 197static int ti_shutdown(device_t); 198static int ti_ifmedia_upd(struct ifnet *); 199static int ti_ifmedia_upd_locked(struct ti_softc *); 200static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 201 202static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 203static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 204static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 205 206static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 207static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 208static void ti_setmulti(struct ti_softc *); 209 210static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 211static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 212static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 213static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 214 int); 215static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 216 int, int, int); 217static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 218static void ti_loadfw(struct ti_softc *); 219static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 220static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 221static void ti_handle_events(struct ti_softc *); 222static int ti_alloc_dmamaps(struct ti_softc *); 223static void ti_free_dmamaps(struct ti_softc *); 224static int ti_alloc_jumbo_mem(struct ti_softc *); 225#ifdef TI_PRIVATE_JUMBOS 226static void *ti_jalloc(struct ti_softc *); 227static void ti_jfree(void *, void *); 228#endif /* TI_PRIVATE_JUMBOS */ 229static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 230static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 231static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 232static int ti_init_rx_ring_std(struct ti_softc *); 233static void ti_free_rx_ring_std(struct ti_softc *); 234static int ti_init_rx_ring_jumbo(struct ti_softc *); 235static void ti_free_rx_ring_jumbo(struct ti_softc *); 236static int ti_init_rx_ring_mini(struct ti_softc *); 237static void ti_free_rx_ring_mini(struct ti_softc *); 238static void ti_free_tx_ring(struct ti_softc *); 239static int ti_init_tx_ring(struct ti_softc *); 240 241static int ti_64bitslot_war(struct ti_softc *); 242static int ti_chipinit(struct ti_softc *); 243static int ti_gibinit(struct ti_softc *); 244 245#ifdef TI_JUMBO_HDRSPLIT 246static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 247 int idx); 248#endif /* TI_JUMBO_HDRSPLIT */ 249 250static device_method_t ti_methods[] = { 251 /* Device interface */ 252 DEVMETHOD(device_probe, ti_probe), 253 DEVMETHOD(device_attach, ti_attach), 254 DEVMETHOD(device_detach, ti_detach), 255 DEVMETHOD(device_shutdown, ti_shutdown), 256 { 0, 0 } 257}; 258 259static driver_t ti_driver = { 260 "ti", 261 ti_methods, 262 sizeof(struct ti_softc) 263}; 264 265static devclass_t ti_devclass; 266 267DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 268MODULE_DEPEND(ti, pci, 1, 1, 1); 269MODULE_DEPEND(ti, ether, 1, 1, 1); 270 271/* 272 * Send an instruction or address to the EEPROM, check for ACK. 273 */ 274static uint32_t 275ti_eeprom_putbyte(struct ti_softc *sc, int byte) 276{ 277 int i, ack = 0; 278 279 /* 280 * Make sure we're in TX mode. 281 */ 282 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 283 284 /* 285 * Feed in each bit and stobe the clock. 286 */ 287 for (i = 0x80; i; i >>= 1) { 288 if (byte & i) { 289 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 290 } else { 291 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 292 } 293 DELAY(1); 294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 295 DELAY(1); 296 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 297 } 298 299 /* 300 * Turn off TX mode. 301 */ 302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 303 304 /* 305 * Check for ack. 306 */ 307 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 311 return (ack); 312} 313 314/* 315 * Read a byte of data stored in the EEPROM at address 'addr.' 316 * We have to send two address bytes since the EEPROM can hold 317 * more than 256 bytes of data. 318 */ 319static uint8_t 320ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 321{ 322 int i; 323 uint8_t byte = 0; 324 325 EEPROM_START; 326 327 /* 328 * Send write control code to EEPROM. 329 */ 330 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 331 device_printf(sc->ti_dev, 332 "failed to send write command, status: %x\n", 333 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 334 return (1); 335 } 336 337 /* 338 * Send first byte of address of byte we want to read. 339 */ 340 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 341 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 342 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 343 return (1); 344 } 345 /* 346 * Send second byte address of byte we want to read. 347 */ 348 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 349 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 350 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 351 return (1); 352 } 353 354 EEPROM_STOP; 355 EEPROM_START; 356 /* 357 * Send read control code to EEPROM. 358 */ 359 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 360 device_printf(sc->ti_dev, 361 "failed to send read command, status: %x\n", 362 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 363 return (1); 364 } 365 366 /* 367 * Start reading bits from EEPROM. 368 */ 369 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 370 for (i = 0x80; i; i >>= 1) { 371 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 372 DELAY(1); 373 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 374 byte |= i; 375 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 376 DELAY(1); 377 } 378 379 EEPROM_STOP; 380 381 /* 382 * No ACK generated for read, so just return byte. 383 */ 384 385 *dest = byte; 386 387 return (0); 388} 389 390/* 391 * Read a sequence of bytes from the EEPROM. 392 */ 393static int 394ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 395{ 396 int err = 0, i; 397 uint8_t byte = 0; 398 399 for (i = 0; i < cnt; i++) { 400 err = ti_eeprom_getbyte(sc, off + i, &byte); 401 if (err) 402 break; 403 *(dest + i) = byte; 404 } 405 406 return (err ? 1 : 0); 407} 408 409/* 410 * NIC memory read function. 411 * Can be used to copy data from NIC local memory. 412 */ 413static void 414ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 415{ 416 int segptr, segsize, cnt; 417 char *ptr; 418 419 segptr = addr; 420 cnt = len; 421 ptr = buf; 422 423 while (cnt) { 424 if (cnt < TI_WINLEN) 425 segsize = cnt; 426 else 427 segsize = TI_WINLEN - (segptr % TI_WINLEN); 428 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 429 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 430 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 431 segsize / 4); 432 ptr += segsize; 433 segptr += segsize; 434 cnt -= segsize; 435 } 436} 437 438 439/* 440 * NIC memory write function. 441 * Can be used to copy data into NIC local memory. 442 */ 443static void 444ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 445{ 446 int segptr, segsize, cnt; 447 char *ptr; 448 449 segptr = addr; 450 cnt = len; 451 ptr = buf; 452 453 while (cnt) { 454 if (cnt < TI_WINLEN) 455 segsize = cnt; 456 else 457 segsize = TI_WINLEN - (segptr % TI_WINLEN); 458 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 459 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 460 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 461 segsize / 4); 462 ptr += segsize; 463 segptr += segsize; 464 cnt -= segsize; 465 } 466} 467 468/* 469 * NIC memory read function. 470 * Can be used to clear a section of NIC local memory. 471 */ 472static void 473ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 474{ 475 int segptr, segsize, cnt; 476 477 segptr = addr; 478 cnt = len; 479 480 while (cnt) { 481 if (cnt < TI_WINLEN) 482 segsize = cnt; 483 else 484 segsize = TI_WINLEN - (segptr % TI_WINLEN); 485 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 486 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 487 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 488 segptr += segsize; 489 cnt -= segsize; 490 } 491} 492 493static int 494ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 495 caddr_t buf, int useraddr, int readdata) 496{ 497 int segptr, segsize, cnt; 498 caddr_t ptr; 499 uint32_t origwin; 500 uint8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 501 int resid, segresid; 502 int first_pass; 503 504 TI_LOCK_ASSERT(sc); 505 506 /* 507 * At the moment, we don't handle non-aligned cases, we just bail. 508 * If this proves to be a problem, it will be fixed. 509 */ 510 if ((readdata == 0) 511 && (tigon_addr & 0x3)) { 512 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 513 "word-aligned\n", __func__, tigon_addr); 514 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 515 "yet supported\n", __func__); 516 return (EINVAL); 517 } 518 519 segptr = tigon_addr & ~0x3; 520 segresid = tigon_addr - segptr; 521 522 /* 523 * This is the non-aligned amount left over that we'll need to 524 * copy. 525 */ 526 resid = len & 0x3; 527 528 /* Add in the left over amount at the front of the buffer */ 529 resid += segresid; 530 531 cnt = len & ~0x3; 532 /* 533 * If resid + segresid is >= 4, add multiples of 4 to the count and 534 * decrease the residual by that much. 535 */ 536 cnt += resid & ~0x3; 537 resid -= resid & ~0x3; 538 539 ptr = buf; 540 541 first_pass = 1; 542 543 /* 544 * Save the old window base value. 545 */ 546 origwin = CSR_READ_4(sc, TI_WINBASE); 547 548 while (cnt) { 549 bus_size_t ti_offset; 550 551 if (cnt < TI_WINLEN) 552 segsize = cnt; 553 else 554 segsize = TI_WINLEN - (segptr % TI_WINLEN); 555 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 556 557 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 558 559 if (readdata) { 560 561 bus_space_read_region_4(sc->ti_btag, 562 sc->ti_bhandle, ti_offset, 563 (uint32_t *)tmparray, 564 segsize >> 2); 565 if (useraddr) { 566 /* 567 * Yeah, this is a little on the kludgy 568 * side, but at least this code is only 569 * used for debugging. 570 */ 571 ti_bcopy_swap(tmparray, tmparray2, segsize, 572 TI_SWAP_NTOH); 573 574 TI_UNLOCK(sc); 575 if (first_pass) { 576 copyout(&tmparray2[segresid], ptr, 577 segsize - segresid); 578 first_pass = 0; 579 } else 580 copyout(tmparray2, ptr, segsize); 581 TI_LOCK(sc); 582 } else { 583 if (first_pass) { 584 585 ti_bcopy_swap(tmparray, tmparray2, 586 segsize, TI_SWAP_NTOH); 587 TI_UNLOCK(sc); 588 bcopy(&tmparray2[segresid], ptr, 589 segsize - segresid); 590 TI_LOCK(sc); 591 first_pass = 0; 592 } else 593 ti_bcopy_swap(tmparray, ptr, segsize, 594 TI_SWAP_NTOH); 595 } 596 597 } else { 598 if (useraddr) { 599 TI_UNLOCK(sc); 600 copyin(ptr, tmparray2, segsize); 601 TI_LOCK(sc); 602 ti_bcopy_swap(tmparray2, tmparray, segsize, 603 TI_SWAP_HTON); 604 } else 605 ti_bcopy_swap(ptr, tmparray, segsize, 606 TI_SWAP_HTON); 607 608 bus_space_write_region_4(sc->ti_btag, 609 sc->ti_bhandle, ti_offset, 610 (uint32_t *)tmparray, 611 segsize >> 2); 612 } 613 segptr += segsize; 614 ptr += segsize; 615 cnt -= segsize; 616 } 617 618 /* 619 * Handle leftover, non-word-aligned bytes. 620 */ 621 if (resid != 0) { 622 uint32_t tmpval, tmpval2; 623 bus_size_t ti_offset; 624 625 /* 626 * Set the segment pointer. 627 */ 628 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 629 630 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 631 632 /* 633 * First, grab whatever is in our source/destination. 634 * We'll obviously need this for reads, but also for 635 * writes, since we'll be doing read/modify/write. 636 */ 637 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 638 ti_offset, &tmpval, 1); 639 640 /* 641 * Next, translate this from little-endian to big-endian 642 * (at least on i386 boxes). 643 */ 644 tmpval2 = ntohl(tmpval); 645 646 if (readdata) { 647 /* 648 * If we're reading, just copy the leftover number 649 * of bytes from the host byte order buffer to 650 * the user's buffer. 651 */ 652 if (useraddr) { 653 TI_UNLOCK(sc); 654 copyout(&tmpval2, ptr, resid); 655 TI_LOCK(sc); 656 } else 657 bcopy(&tmpval2, ptr, resid); 658 } else { 659 /* 660 * If we're writing, first copy the bytes to be 661 * written into the network byte order buffer, 662 * leaving the rest of the buffer with whatever was 663 * originally in there. Then, swap the bytes 664 * around into host order and write them out. 665 * 666 * XXX KDM the read side of this has been verified 667 * to work, but the write side of it has not been 668 * verified. So user beware. 669 */ 670 if (useraddr) { 671 TI_UNLOCK(sc); 672 copyin(ptr, &tmpval2, resid); 673 TI_LOCK(sc); 674 } else 675 bcopy(ptr, &tmpval2, resid); 676 677 tmpval = htonl(tmpval2); 678 679 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 680 ti_offset, &tmpval, 1); 681 } 682 } 683 684 CSR_WRITE_4(sc, TI_WINBASE, origwin); 685 686 return (0); 687} 688 689static int 690ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 691 caddr_t buf, int useraddr, int readdata, int cpu) 692{ 693 uint32_t segptr; 694 int cnt; 695 uint32_t tmpval, tmpval2; 696 caddr_t ptr; 697 698 TI_LOCK_ASSERT(sc); 699 700 /* 701 * At the moment, we don't handle non-aligned cases, we just bail. 702 * If this proves to be a problem, it will be fixed. 703 */ 704 if (tigon_addr & 0x3) { 705 device_printf(sc->ti_dev, "%s: tigon address %#x " 706 "isn't word-aligned\n", __func__, tigon_addr); 707 return (EINVAL); 708 } 709 710 if (len & 0x3) { 711 device_printf(sc->ti_dev, "%s: transfer length %d " 712 "isn't word-aligned\n", __func__, len); 713 return (EINVAL); 714 } 715 716 segptr = tigon_addr; 717 cnt = len; 718 ptr = buf; 719 720 while (cnt) { 721 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 722 723 if (readdata) { 724 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 725 726 tmpval = ntohl(tmpval2); 727 728 /* 729 * Note: I've used this debugging interface 730 * extensively with Alteon's 12.3.15 firmware, 731 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 732 * 733 * When you compile the firmware without 734 * optimization, which is necessary sometimes in 735 * order to properly step through it, you sometimes 736 * read out a bogus value of 0xc0017c instead of 737 * whatever was supposed to be in that scratchpad 738 * location. That value is on the stack somewhere, 739 * but I've never been able to figure out what was 740 * causing the problem. 741 * 742 * The address seems to pop up in random places, 743 * often not in the same place on two subsequent 744 * reads. 745 * 746 * In any case, the underlying data doesn't seem 747 * to be affected, just the value read out. 748 * 749 * KDM, 3/7/2000 750 */ 751 752 if (tmpval2 == 0xc0017c) 753 device_printf(sc->ti_dev, "found 0xc0017c at " 754 "%#x (tmpval2)\n", segptr); 755 756 if (tmpval == 0xc0017c) 757 device_printf(sc->ti_dev, "found 0xc0017c at " 758 "%#x (tmpval)\n", segptr); 759 760 if (useraddr) 761 copyout(&tmpval, ptr, 4); 762 else 763 bcopy(&tmpval, ptr, 4); 764 } else { 765 if (useraddr) 766 copyin(ptr, &tmpval2, 4); 767 else 768 bcopy(ptr, &tmpval2, 4); 769 770 tmpval = htonl(tmpval2); 771 772 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 773 } 774 775 cnt -= 4; 776 segptr += 4; 777 ptr += 4; 778 } 779 780 return (0); 781} 782 783static int 784ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 785{ 786 const uint8_t *tmpsrc; 787 uint8_t *tmpdst; 788 size_t tmplen; 789 790 if (len & 0x3) { 791 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 792 len); 793 return (-1); 794 } 795 796 tmpsrc = src; 797 tmpdst = dst; 798 tmplen = len; 799 800 while (tmplen) { 801 if (swap_type == TI_SWAP_NTOH) 802 *(uint32_t *)tmpdst = 803 ntohl(*(const uint32_t *)tmpsrc); 804 else 805 *(uint32_t *)tmpdst = 806 htonl(*(const uint32_t *)tmpsrc); 807 808 tmpsrc += 4; 809 tmpdst += 4; 810 tmplen -= 4; 811 } 812 813 return (0); 814} 815 816/* 817 * Load firmware image into the NIC. Check that the firmware revision 818 * is acceptable and see if we want the firmware for the Tigon 1 or 819 * Tigon 2. 820 */ 821static void 822ti_loadfw(struct ti_softc *sc) 823{ 824 825 TI_LOCK_ASSERT(sc); 826 827 switch (sc->ti_hwrev) { 828 case TI_HWREV_TIGON: 829 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 830 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 831 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 832 device_printf(sc->ti_dev, "firmware revision mismatch; " 833 "want %d.%d.%d, got %d.%d.%d\n", 834 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 835 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 836 tigonFwReleaseMinor, tigonFwReleaseFix); 837 return; 838 } 839 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 840 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 841 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 842 tigonFwRodata); 843 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 844 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 845 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 846 break; 847 case TI_HWREV_TIGON_II: 848 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 849 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 850 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 851 device_printf(sc->ti_dev, "firmware revision mismatch; " 852 "want %d.%d.%d, got %d.%d.%d\n", 853 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 854 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 855 tigon2FwReleaseMinor, tigon2FwReleaseFix); 856 return; 857 } 858 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 859 tigon2FwText); 860 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 861 tigon2FwData); 862 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 863 tigon2FwRodata); 864 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 865 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 866 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 867 break; 868 default: 869 device_printf(sc->ti_dev, 870 "can't load firmware: unknown hardware rev\n"); 871 break; 872 } 873} 874 875/* 876 * Send the NIC a command via the command ring. 877 */ 878static void 879ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 880{ 881 int index; 882 883 index = sc->ti_cmd_saved_prodidx; 884 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 885 TI_INC(index, TI_CMD_RING_CNT); 886 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 887 sc->ti_cmd_saved_prodidx = index; 888} 889 890/* 891 * Send the NIC an extended command. The 'len' parameter specifies the 892 * number of command slots to include after the initial command. 893 */ 894static void 895ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 896{ 897 int index; 898 int i; 899 900 index = sc->ti_cmd_saved_prodidx; 901 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 902 TI_INC(index, TI_CMD_RING_CNT); 903 for (i = 0; i < len; i++) { 904 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 905 *(uint32_t *)(&arg[i * 4])); 906 TI_INC(index, TI_CMD_RING_CNT); 907 } 908 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 909 sc->ti_cmd_saved_prodidx = index; 910} 911 912/* 913 * Handle events that have triggered interrupts. 914 */ 915static void 916ti_handle_events(struct ti_softc *sc) 917{ 918 struct ti_event_desc *e; 919 920 if (sc->ti_rdata->ti_event_ring == NULL) 921 return; 922 923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 924 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 925 switch (TI_EVENT_EVENT(e)) { 926 case TI_EV_LINKSTAT_CHANGED: 927 sc->ti_linkstat = TI_EVENT_CODE(e); 928 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 930 sc->ti_ifp->if_baudrate = IF_Mbps(100); 931 if (bootverbose) 932 device_printf(sc->ti_dev, 933 "10/100 link up\n"); 934 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 936 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 937 if (bootverbose) 938 device_printf(sc->ti_dev, 939 "gigabit link up\n"); 940 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 941 if_link_state_change(sc->ti_ifp, 942 LINK_STATE_DOWN); 943 sc->ti_ifp->if_baudrate = 0; 944 if (bootverbose) 945 device_printf(sc->ti_dev, 946 "link down\n"); 947 } 948 break; 949 case TI_EV_ERROR: 950 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 951 device_printf(sc->ti_dev, "invalid command\n"); 952 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 953 device_printf(sc->ti_dev, "unknown command\n"); 954 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 955 device_printf(sc->ti_dev, "bad config data\n"); 956 break; 957 case TI_EV_FIRMWARE_UP: 958 ti_init2(sc); 959 break; 960 case TI_EV_STATS_UPDATED: 961 ti_stats_update(sc); 962 break; 963 case TI_EV_RESET_JUMBO_RING: 964 case TI_EV_MCAST_UPDATED: 965 /* Who cares. */ 966 break; 967 default: 968 device_printf(sc->ti_dev, "unknown event: %d\n", 969 TI_EVENT_EVENT(e)); 970 break; 971 } 972 /* Advance the consumer index. */ 973 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 974 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 975 } 976} 977 978static int 979ti_alloc_dmamaps(struct ti_softc *sc) 980{ 981 int i; 982 983 for (i = 0; i < TI_TX_RING_CNT; i++) { 984 sc->ti_cdata.ti_txdesc[i].tx_m = NULL; 985 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 986 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 987 &sc->ti_cdata.ti_txdesc[i].tx_dmamap)) 988 return (ENOBUFS); 989 } 990 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 991 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 992 &sc->ti_cdata.ti_rx_std_maps[i])) 993 return (ENOBUFS); 994 } 995 996 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 997 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 998 &sc->ti_cdata.ti_rx_jumbo_maps[i])) 999 return (ENOBUFS); 1000 } 1001 1002 /* Mini ring is not available on Tigon 1. */ 1003 if (sc->ti_hwrev == TI_HWREV_TIGON) 1004 return (0); 1005 1006 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1007 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1008 &sc->ti_cdata.ti_rx_mini_maps[i])) 1009 return (ENOBUFS); 1010 } 1011 1012 return (0); 1013} 1014 1015static void 1016ti_free_dmamaps(struct ti_softc *sc) 1017{ 1018 int i; 1019 1020 if (sc->ti_mbuftx_dmat) 1021 for (i = 0; i < TI_TX_RING_CNT; i++) 1022 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1023 bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1024 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1025 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1026 } 1027 1028 if (sc->ti_mbufrx_dmat) 1029 for (i = 0; i < TI_STD_RX_RING_CNT; i++) 1030 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1031 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1032 sc->ti_cdata.ti_rx_std_maps[i]); 1033 sc->ti_cdata.ti_rx_std_maps[i] = 0; 1034 } 1035 1036 if (sc->ti_jumbo_dmat) 1037 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1038 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1039 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1040 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1041 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0; 1042 } 1043 if (sc->ti_mbufrx_dmat) 1044 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1045 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1046 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1047 sc->ti_cdata.ti_rx_mini_maps[i]); 1048 sc->ti_cdata.ti_rx_mini_maps[i] = 0; 1049 } 1050} 1051 1052#ifdef TI_PRIVATE_JUMBOS 1053 1054/* 1055 * Memory management for the jumbo receive ring is a pain in the 1056 * butt. We need to allocate at least 9018 bytes of space per frame, 1057 * _and_ it has to be contiguous (unless you use the extended 1058 * jumbo descriptor format). Using malloc() all the time won't 1059 * work: malloc() allocates memory in powers of two, which means we 1060 * would end up wasting a considerable amount of space by allocating 1061 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 1062 * to do our own memory management. 1063 * 1064 * The driver needs to allocate a contiguous chunk of memory at boot 1065 * time. We then chop this up ourselves into 9K pieces and use them 1066 * as external mbuf storage. 1067 * 1068 * One issue here is how much memory to allocate. The jumbo ring has 1069 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1070 * RAM. This is a bit much, especially considering we also need 1071 * RAM for the standard ring and mini ring (on the Tigon 2). To 1072 * save space, we only actually allocate enough memory for 64 slots 1073 * by default, which works out to between 500 and 600K. This can 1074 * be tuned by changing a #define in if_tireg.h. 1075 */ 1076 1077static int 1078ti_alloc_jumbo_mem(struct ti_softc *sc) 1079{ 1080 struct ti_jpool_entry *entry; 1081 caddr_t ptr; 1082 int i; 1083 1084 /* 1085 * Grab a big chunk o' storage. Since we are chopping this pool up 1086 * into ~9k chunks, there doesn't appear to be a need to use page 1087 * alignment. 1088 */ 1089 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1090 1, 0, /* algnmnt, boundary */ 1091 BUS_SPACE_MAXADDR, /* lowaddr */ 1092 BUS_SPACE_MAXADDR, /* highaddr */ 1093 NULL, NULL, /* filter, filterarg */ 1094 TI_JMEM, /* maxsize */ 1095 1, /* nsegments */ 1096 TI_JMEM, /* maxsegsize */ 1097 0, /* flags */ 1098 NULL, NULL, /* lockfunc, lockarg */ 1099 &sc->ti_jumbo_dmat) != 0) { 1100 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1101 return (ENOBUFS); 1102 } 1103 1104 if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1105 (void**)&sc->ti_cdata.ti_jumbo_buf, 1106 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 1107 &sc->ti_jumbo_dmamap) != 0) { 1108 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1109 return (ENOBUFS); 1110 } 1111 1112 SLIST_INIT(&sc->ti_jfree_listhead); 1113 SLIST_INIT(&sc->ti_jinuse_listhead); 1114 1115 /* 1116 * Now divide it up into 9K pieces and save the addresses 1117 * in an array. 1118 */ 1119 ptr = sc->ti_cdata.ti_jumbo_buf; 1120 for (i = 0; i < TI_JSLOTS; i++) { 1121 sc->ti_cdata.ti_jslots[i] = ptr; 1122 ptr += TI_JLEN; 1123 entry = malloc(sizeof(struct ti_jpool_entry), 1124 M_DEVBUF, M_NOWAIT); 1125 if (entry == NULL) { 1126 device_printf(sc->ti_dev, "no memory for jumbo " 1127 "buffer queue!\n"); 1128 return (ENOBUFS); 1129 } 1130 entry->slot = i; 1131 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1132 } 1133 1134 return (0); 1135} 1136 1137/* 1138 * Allocate a jumbo buffer. 1139 */ 1140static void *ti_jalloc(struct ti_softc *sc) 1141{ 1142 struct ti_jpool_entry *entry; 1143 1144 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1145 1146 if (entry == NULL) { 1147 device_printf(sc->ti_dev, "no free jumbo buffers\n"); 1148 return (NULL); 1149 } 1150 1151 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1152 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1153 return (sc->ti_cdata.ti_jslots[entry->slot]); 1154} 1155 1156/* 1157 * Release a jumbo buffer. 1158 */ 1159static void 1160ti_jfree(void *buf, void *args) 1161{ 1162 struct ti_softc *sc; 1163 int i; 1164 struct ti_jpool_entry *entry; 1165 1166 /* Extract the softc struct pointer. */ 1167 sc = (struct ti_softc *)args; 1168 1169 if (sc == NULL) 1170 panic("ti_jfree: didn't get softc pointer!"); 1171 1172 /* calculate the slot this buffer belongs to */ 1173 i = ((vm_offset_t)buf 1174 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1175 1176 if ((i < 0) || (i >= TI_JSLOTS)) 1177 panic("ti_jfree: asked to free buffer that we don't manage!"); 1178 1179 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1180 if (entry == NULL) 1181 panic("ti_jfree: buffer not in use!"); 1182 entry->slot = i; 1183 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1184 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1185} 1186 1187#else 1188 1189static int 1190ti_alloc_jumbo_mem(struct ti_softc *sc) 1191{ 1192 1193 /* 1194 * The VM system will take care of providing aligned pages. Alignment 1195 * is set to 1 here so that busdma resources won't be wasted. 1196 */ 1197 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1198 1, 0, /* algnmnt, boundary */ 1199 BUS_SPACE_MAXADDR, /* lowaddr */ 1200 BUS_SPACE_MAXADDR, /* highaddr */ 1201 NULL, NULL, /* filter, filterarg */ 1202 PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1203 4, /* nsegments */ 1204 PAGE_SIZE, /* maxsegsize */ 1205 0, /* flags */ 1206 NULL, NULL, /* lockfunc, lockarg */ 1207 &sc->ti_jumbo_dmat) != 0) { 1208 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1209 return (ENOBUFS); 1210 } 1211 1212 return (0); 1213} 1214 1215#endif /* TI_PRIVATE_JUMBOS */ 1216 1217/* 1218 * Intialize a standard receive ring descriptor. 1219 */ 1220static int 1221ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m) 1222{ 1223 bus_dmamap_t map; 1224 bus_dma_segment_t segs; 1225 struct mbuf *m_new = NULL; 1226 struct ti_rx_desc *r; 1227 int nsegs; 1228 1229 nsegs = 0; 1230 if (m == NULL) { 1231 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1232 if (m_new == NULL) 1233 return (ENOBUFS); 1234 1235 MCLGET(m_new, M_DONTWAIT); 1236 if (!(m_new->m_flags & M_EXT)) { 1237 m_freem(m_new); 1238 return (ENOBUFS); 1239 } 1240 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1241 } else { 1242 m_new = m; 1243 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1244 m_new->m_data = m_new->m_ext.ext_buf; 1245 } 1246 1247 m_adj(m_new, ETHER_ALIGN); 1248 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1249 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1250 map = sc->ti_cdata.ti_rx_std_maps[i]; 1251 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1252 &nsegs, 0)) 1253 return (ENOBUFS); 1254 if (nsegs != 1) 1255 return (ENOBUFS); 1256 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1257 r->ti_len = segs.ds_len; 1258 r->ti_type = TI_BDTYPE_RECV_BD; 1259 r->ti_flags = 0; 1260 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1261 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1262 r->ti_idx = i; 1263 1264 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1265 return (0); 1266} 1267 1268/* 1269 * Intialize a mini receive ring descriptor. This only applies to 1270 * the Tigon 2. 1271 */ 1272static int 1273ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m) 1274{ 1275 bus_dma_segment_t segs; 1276 bus_dmamap_t map; 1277 struct mbuf *m_new = NULL; 1278 struct ti_rx_desc *r; 1279 int nsegs; 1280 1281 nsegs = 0; 1282 if (m == NULL) { 1283 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1284 if (m_new == NULL) { 1285 return (ENOBUFS); 1286 } 1287 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1288 } else { 1289 m_new = m; 1290 m_new->m_data = m_new->m_pktdat; 1291 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1292 } 1293 1294 m_adj(m_new, ETHER_ALIGN); 1295 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1296 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1297 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1298 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1299 &nsegs, 0)) 1300 return (ENOBUFS); 1301 if (nsegs != 1) 1302 return (ENOBUFS); 1303 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1304 r->ti_len = segs.ds_len; 1305 r->ti_type = TI_BDTYPE_RECV_BD; 1306 r->ti_flags = TI_BDFLAG_MINI_RING; 1307 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1308 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1309 r->ti_idx = i; 1310 1311 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1312 return (0); 1313} 1314 1315#ifdef TI_PRIVATE_JUMBOS 1316 1317/* 1318 * Initialize a jumbo receive ring descriptor. This allocates 1319 * a jumbo buffer from the pool managed internally by the driver. 1320 */ 1321static int 1322ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 1323{ 1324 bus_dmamap_t map; 1325 struct mbuf *m_new = NULL; 1326 struct ti_rx_desc *r; 1327 int nsegs; 1328 bus_dma_segment_t segs; 1329 1330 if (m == NULL) { 1331 caddr_t *buf = NULL; 1332 1333 /* Allocate the mbuf. */ 1334 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1335 if (m_new == NULL) { 1336 return (ENOBUFS); 1337 } 1338 1339 /* Allocate the jumbo buffer */ 1340 buf = ti_jalloc(sc); 1341 if (buf == NULL) { 1342 m_freem(m_new); 1343 device_printf(sc->ti_dev, "jumbo allocation failed " 1344 "-- packet dropped!\n"); 1345 return (ENOBUFS); 1346 } 1347 1348 /* Attach the buffer to the mbuf. */ 1349 m_new->m_data = (void *) buf; 1350 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1351 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, buf, 1352 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1353 } else { 1354 m_new = m; 1355 m_new->m_data = m_new->m_ext.ext_buf; 1356 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1357 } 1358 1359 m_adj(m_new, ETHER_ALIGN); 1360 /* Set up the descriptor. */ 1361 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1362 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1363 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1364 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1365 &nsegs, 0)) 1366 return (ENOBUFS); 1367 if (nsegs != 1) 1368 return (ENOBUFS); 1369 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1370 r->ti_len = segs.ds_len; 1371 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1372 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1373 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1374 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1375 r->ti_idx = i; 1376 1377 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1378 return (0); 1379} 1380 1381#else 1382 1383#if (PAGE_SIZE == 4096) 1384#define NPAYLOAD 2 1385#else 1386#define NPAYLOAD 1 1387#endif 1388 1389#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1390#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1391#define NFS_HDR_LEN (UDP_HDR_LEN) 1392static int HDR_LEN = TCP_HDR_LEN; 1393 1394/* 1395 * Initialize a jumbo receive ring descriptor. This allocates 1396 * a jumbo buffer from the pool managed internally by the driver. 1397 */ 1398static int 1399ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1400{ 1401 bus_dmamap_t map; 1402 struct mbuf *cur, *m_new = NULL; 1403 struct mbuf *m[3] = {NULL, NULL, NULL}; 1404 struct ti_rx_desc_ext *r; 1405 vm_page_t frame; 1406 static int color; 1407 /* 1 extra buf to make nobufs easy*/ 1408 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1409 int i; 1410 bus_dma_segment_t segs[4]; 1411 int nsegs; 1412 1413 if (m_old != NULL) { 1414 m_new = m_old; 1415 cur = m_old->m_next; 1416 for (i = 0; i <= NPAYLOAD; i++){ 1417 m[i] = cur; 1418 cur = cur->m_next; 1419 } 1420 } else { 1421 /* Allocate the mbufs. */ 1422 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1423 if (m_new == NULL) { 1424 device_printf(sc->ti_dev, "mbuf allocation failed " 1425 "-- packet dropped!\n"); 1426 goto nobufs; 1427 } 1428 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1429 if (m[NPAYLOAD] == NULL) { 1430 device_printf(sc->ti_dev, "cluster mbuf allocation " 1431 "failed -- packet dropped!\n"); 1432 goto nobufs; 1433 } 1434 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1435 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1436 device_printf(sc->ti_dev, "mbuf allocation failed " 1437 "-- packet dropped!\n"); 1438 goto nobufs; 1439 } 1440 m[NPAYLOAD]->m_len = MCLBYTES; 1441 1442 for (i = 0; i < NPAYLOAD; i++){ 1443 MGET(m[i], M_DONTWAIT, MT_DATA); 1444 if (m[i] == NULL) { 1445 device_printf(sc->ti_dev, "mbuf allocation " 1446 "failed -- packet dropped!\n"); 1447 goto nobufs; 1448 } 1449 frame = vm_page_alloc(NULL, color++, 1450 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1451 VM_ALLOC_WIRED); 1452 if (frame == NULL) { 1453 device_printf(sc->ti_dev, "buffer allocation " 1454 "failed -- packet dropped!\n"); 1455 printf(" index %d page %d\n", idx, i); 1456 goto nobufs; 1457 } 1458 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1459 if (sf[i] == NULL) { 1460 vm_page_unwire(frame, 0); 1461 vm_page_free(frame); 1462 device_printf(sc->ti_dev, "buffer allocation " 1463 "failed -- packet dropped!\n"); 1464 printf(" index %d page %d\n", idx, i); 1465 goto nobufs; 1466 } 1467 } 1468 for (i = 0; i < NPAYLOAD; i++){ 1469 /* Attach the buffer to the mbuf. */ 1470 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1471 m[i]->m_len = PAGE_SIZE; 1472 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1473 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1474 0, EXT_DISPOSABLE); 1475 m[i]->m_next = m[i+1]; 1476 } 1477 /* link the buffers to the header */ 1478 m_new->m_next = m[0]; 1479 m_new->m_data += ETHER_ALIGN; 1480 if (sc->ti_hdrsplit) 1481 m_new->m_len = MHLEN - ETHER_ALIGN; 1482 else 1483 m_new->m_len = HDR_LEN; 1484 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1485 } 1486 1487 /* Set up the descriptor. */ 1488 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1489 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1490 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1491 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1492 &nsegs, 0)) 1493 return (ENOBUFS); 1494 if ((nsegs < 1) || (nsegs > 4)) 1495 return (ENOBUFS); 1496 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1497 r->ti_len0 = m_new->m_len; 1498 1499 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1500 r->ti_len1 = PAGE_SIZE; 1501 1502 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1503 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1504 1505 if (PAGE_SIZE == 4096) { 1506 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1507 r->ti_len3 = MCLBYTES; 1508 } else { 1509 r->ti_len3 = 0; 1510 } 1511 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1512 1513 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1514 1515 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1516 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1517 1518 r->ti_idx = idx; 1519 1520 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1521 return (0); 1522 1523nobufs: 1524 1525 /* 1526 * Warning! : 1527 * This can only be called before the mbufs are strung together. 1528 * If the mbufs are strung together, m_freem() will free the chain, 1529 * so that the later mbufs will be freed multiple times. 1530 */ 1531 if (m_new) 1532 m_freem(m_new); 1533 1534 for (i = 0; i < 3; i++) { 1535 if (m[i]) 1536 m_freem(m[i]); 1537 if (sf[i]) 1538 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1539 } 1540 return (ENOBUFS); 1541} 1542#endif 1543 1544/* 1545 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1546 * that's 1MB or memory, which is a lot. For now, we fill only the first 1547 * 256 ring entries and hope that our CPU is fast enough to keep up with 1548 * the NIC. 1549 */ 1550static int 1551ti_init_rx_ring_std(struct ti_softc *sc) 1552{ 1553 int i; 1554 struct ti_cmd_desc cmd; 1555 1556 for (i = 0; i < TI_SSLOTS; i++) { 1557 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1558 return (ENOBUFS); 1559 }; 1560 1561 TI_UPDATE_STDPROD(sc, i - 1); 1562 sc->ti_std = i - 1; 1563 1564 return (0); 1565} 1566 1567static void 1568ti_free_rx_ring_std(struct ti_softc *sc) 1569{ 1570 bus_dmamap_t map; 1571 int i; 1572 1573 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1574 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1575 map = sc->ti_cdata.ti_rx_std_maps[i]; 1576 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1577 BUS_DMASYNC_POSTREAD); 1578 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1579 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1580 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1581 } 1582 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1583 sizeof(struct ti_rx_desc)); 1584 } 1585} 1586 1587static int 1588ti_init_rx_ring_jumbo(struct ti_softc *sc) 1589{ 1590 struct ti_cmd_desc cmd; 1591 int i; 1592 1593 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1594 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1595 return (ENOBUFS); 1596 }; 1597 1598 TI_UPDATE_JUMBOPROD(sc, i - 1); 1599 sc->ti_jumbo = i - 1; 1600 1601 return (0); 1602} 1603 1604static void 1605ti_free_rx_ring_jumbo(struct ti_softc *sc) 1606{ 1607 bus_dmamap_t map; 1608 int i; 1609 1610 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1611 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1612 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1613 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1614 BUS_DMASYNC_POSTREAD); 1615 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 1616 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1617 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1618 } 1619 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1620 sizeof(struct ti_rx_desc)); 1621 } 1622} 1623 1624static int 1625ti_init_rx_ring_mini(struct ti_softc *sc) 1626{ 1627 int i; 1628 1629 for (i = 0; i < TI_MSLOTS; i++) { 1630 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1631 return (ENOBUFS); 1632 }; 1633 1634 TI_UPDATE_MINIPROD(sc, i - 1); 1635 sc->ti_mini = i - 1; 1636 1637 return (0); 1638} 1639 1640static void 1641ti_free_rx_ring_mini(struct ti_softc *sc) 1642{ 1643 bus_dmamap_t map; 1644 int i; 1645 1646 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1647 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1648 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1649 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1650 BUS_DMASYNC_POSTREAD); 1651 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1652 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1653 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1654 } 1655 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1656 sizeof(struct ti_rx_desc)); 1657 } 1658} 1659 1660static void 1661ti_free_tx_ring(struct ti_softc *sc) 1662{ 1663 struct ti_txdesc *txd; 1664 int i; 1665 1666 if (sc->ti_rdata->ti_tx_ring == NULL) 1667 return; 1668 1669 for (i = 0; i < TI_TX_RING_CNT; i++) { 1670 txd = &sc->ti_cdata.ti_txdesc[i]; 1671 if (txd->tx_m != NULL) { 1672 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 1673 BUS_DMASYNC_POSTWRITE); 1674 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 1675 m_freem(txd->tx_m); 1676 txd->tx_m = NULL; 1677 } 1678 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1679 sizeof(struct ti_tx_desc)); 1680 } 1681} 1682 1683static int 1684ti_init_tx_ring(struct ti_softc *sc) 1685{ 1686 struct ti_txdesc *txd; 1687 int i; 1688 1689 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1690 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1691 for (i = 0; i < TI_TX_RING_CNT; i++) { 1692 txd = &sc->ti_cdata.ti_txdesc[i]; 1693 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1694 } 1695 sc->ti_txcnt = 0; 1696 sc->ti_tx_saved_considx = 0; 1697 sc->ti_tx_saved_prodidx = 0; 1698 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1699 return (0); 1700} 1701 1702/* 1703 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1704 * but we have to support the old way too so that Tigon 1 cards will 1705 * work. 1706 */ 1707static void 1708ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1709{ 1710 struct ti_cmd_desc cmd; 1711 uint16_t *m; 1712 uint32_t ext[2] = {0, 0}; 1713 1714 m = (uint16_t *)&addr->octet[0]; 1715 1716 switch (sc->ti_hwrev) { 1717 case TI_HWREV_TIGON: 1718 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1719 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1720 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1721 break; 1722 case TI_HWREV_TIGON_II: 1723 ext[0] = htons(m[0]); 1724 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1725 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1726 break; 1727 default: 1728 device_printf(sc->ti_dev, "unknown hwrev\n"); 1729 break; 1730 } 1731} 1732 1733static void 1734ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1735{ 1736 struct ti_cmd_desc cmd; 1737 uint16_t *m; 1738 uint32_t ext[2] = {0, 0}; 1739 1740 m = (uint16_t *)&addr->octet[0]; 1741 1742 switch (sc->ti_hwrev) { 1743 case TI_HWREV_TIGON: 1744 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1745 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1746 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1747 break; 1748 case TI_HWREV_TIGON_II: 1749 ext[0] = htons(m[0]); 1750 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1751 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1752 break; 1753 default: 1754 device_printf(sc->ti_dev, "unknown hwrev\n"); 1755 break; 1756 } 1757} 1758 1759/* 1760 * Configure the Tigon's multicast address filter. 1761 * 1762 * The actual multicast table management is a bit of a pain, thanks to 1763 * slight brain damage on the part of both Alteon and us. With our 1764 * multicast code, we are only alerted when the multicast address table 1765 * changes and at that point we only have the current list of addresses: 1766 * we only know the current state, not the previous state, so we don't 1767 * actually know what addresses were removed or added. The firmware has 1768 * state, but we can't get our grubby mits on it, and there is no 'delete 1769 * all multicast addresses' command. Hence, we have to maintain our own 1770 * state so we know what addresses have been programmed into the NIC at 1771 * any given time. 1772 */ 1773static void 1774ti_setmulti(struct ti_softc *sc) 1775{ 1776 struct ifnet *ifp; 1777 struct ifmultiaddr *ifma; 1778 struct ti_cmd_desc cmd; 1779 struct ti_mc_entry *mc; 1780 uint32_t intrs; 1781 1782 TI_LOCK_ASSERT(sc); 1783 1784 ifp = sc->ti_ifp; 1785 1786 if (ifp->if_flags & IFF_ALLMULTI) { 1787 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1788 return; 1789 } else { 1790 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1791 } 1792 1793 /* Disable interrupts. */ 1794 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1795 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1796 1797 /* First, zot all the existing filters. */ 1798 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1799 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1800 ti_del_mcast(sc, &mc->mc_addr); 1801 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1802 free(mc, M_DEVBUF); 1803 } 1804 1805 /* Now program new ones. */ 1806 if_maddr_rlock(ifp); 1807 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1808 if (ifma->ifma_addr->sa_family != AF_LINK) 1809 continue; 1810 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1811 if (mc == NULL) { 1812 device_printf(sc->ti_dev, 1813 "no memory for mcast filter entry\n"); 1814 continue; 1815 } 1816 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1817 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1818 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1819 ti_add_mcast(sc, &mc->mc_addr); 1820 } 1821 if_maddr_runlock(ifp); 1822 1823 /* Re-enable interrupts. */ 1824 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1825} 1826 1827/* 1828 * Check to see if the BIOS has configured us for a 64 bit slot when 1829 * we aren't actually in one. If we detect this condition, we can work 1830 * around it on the Tigon 2 by setting a bit in the PCI state register, 1831 * but for the Tigon 1 we must give up and abort the interface attach. 1832 */ 1833static int ti_64bitslot_war(struct ti_softc *sc) 1834{ 1835 1836 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1837 CSR_WRITE_4(sc, 0x600, 0); 1838 CSR_WRITE_4(sc, 0x604, 0); 1839 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1840 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1841 if (sc->ti_hwrev == TI_HWREV_TIGON) 1842 return (EINVAL); 1843 else { 1844 TI_SETBIT(sc, TI_PCI_STATE, 1845 TI_PCISTATE_32BIT_BUS); 1846 return (0); 1847 } 1848 } 1849 } 1850 1851 return (0); 1852} 1853 1854/* 1855 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1856 * self-test results. 1857 */ 1858static int 1859ti_chipinit(struct ti_softc *sc) 1860{ 1861 uint32_t cacheline; 1862 uint32_t pci_writemax = 0; 1863 uint32_t hdrsplit; 1864 1865 /* Initialize link to down state. */ 1866 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1867 1868 /* Set endianness before we access any non-PCI registers. */ 1869#if 0 && BYTE_ORDER == BIG_ENDIAN 1870 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1871 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1872#else 1873 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1874 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1875#endif 1876 1877 /* Check the ROM failed bit to see if self-tests passed. */ 1878 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1879 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 1880 return (ENODEV); 1881 } 1882 1883 /* Halt the CPU. */ 1884 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1885 1886 /* Figure out the hardware revision. */ 1887 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1888 case TI_REV_TIGON_I: 1889 sc->ti_hwrev = TI_HWREV_TIGON; 1890 break; 1891 case TI_REV_TIGON_II: 1892 sc->ti_hwrev = TI_HWREV_TIGON_II; 1893 break; 1894 default: 1895 device_printf(sc->ti_dev, "unsupported chip revision\n"); 1896 return (ENODEV); 1897 } 1898 1899 /* Do special setup for Tigon 2. */ 1900 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1901 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1902 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1903 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1904 } 1905 1906 /* 1907 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1908 * can't do header splitting. 1909 */ 1910#ifdef TI_JUMBO_HDRSPLIT 1911 if (sc->ti_hwrev != TI_HWREV_TIGON) 1912 sc->ti_hdrsplit = 1; 1913 else 1914 device_printf(sc->ti_dev, 1915 "can't do header splitting on a Tigon I board\n"); 1916#endif /* TI_JUMBO_HDRSPLIT */ 1917 1918 /* Set up the PCI state register. */ 1919 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1920 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1921 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1922 } 1923 1924 /* Clear the read/write max DMA parameters. */ 1925 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1926 TI_PCISTATE_READ_MAXDMA)); 1927 1928 /* Get cache line size. */ 1929 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1930 1931 /* 1932 * If the system has set enabled the PCI memory write 1933 * and invalidate command in the command register, set 1934 * the write max parameter accordingly. This is necessary 1935 * to use MWI with the Tigon 2. 1936 */ 1937 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1938 switch (cacheline) { 1939 case 1: 1940 case 4: 1941 case 8: 1942 case 16: 1943 case 32: 1944 case 64: 1945 break; 1946 default: 1947 /* Disable PCI memory write and invalidate. */ 1948 if (bootverbose) 1949 device_printf(sc->ti_dev, "cache line size %d" 1950 " not supported; disabling PCI MWI\n", 1951 cacheline); 1952 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1953 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1954 break; 1955 } 1956 } 1957 1958 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1959 1960 /* This sets the min dma param all the way up (0xff). */ 1961 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1962 1963 if (sc->ti_hdrsplit) 1964 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1965 else 1966 hdrsplit = 0; 1967 1968 /* Configure DMA variables. */ 1969#if BYTE_ORDER == BIG_ENDIAN 1970 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1971 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1972 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1973 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1974#else /* BYTE_ORDER */ 1975 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1976 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1977 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1978#endif /* BYTE_ORDER */ 1979 1980 /* 1981 * Only allow 1 DMA channel to be active at a time. 1982 * I don't think this is a good idea, but without it 1983 * the firmware racks up lots of nicDmaReadRingFull 1984 * errors. This is not compatible with hardware checksums. 1985 */ 1986 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 1987 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1988 1989 /* Recommended settings from Tigon manual. */ 1990 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1991 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1992 1993 if (ti_64bitslot_war(sc)) { 1994 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 1995 "but we aren't"); 1996 return (EINVAL); 1997 } 1998 1999 return (0); 2000} 2001 2002/* 2003 * Initialize the general information block and firmware, and 2004 * start the CPU(s) running. 2005 */ 2006static int 2007ti_gibinit(struct ti_softc *sc) 2008{ 2009 struct ifnet *ifp; 2010 struct ti_rcb *rcb; 2011 uint32_t rdphys; 2012 int i; 2013 2014 TI_LOCK_ASSERT(sc); 2015 2016 ifp = sc->ti_ifp; 2017 rdphys = sc->ti_rdata_phys; 2018 2019 /* Disable interrupts for now. */ 2020 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2021 2022 /* 2023 * Tell the chip where to find the general information block. 2024 * While this struct could go into >4GB memory, we allocate it in a 2025 * single slab with the other descriptors, and those don't seem to 2026 * support being located in a 64-bit region. 2027 */ 2028 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2029 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 2030 2031 /* Load the firmware into SRAM. */ 2032 ti_loadfw(sc); 2033 2034 /* Set up the contents of the general info and ring control blocks. */ 2035 2036 /* Set up the event ring and producer pointer. */ 2037 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 2038 2039 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 2040 rcb->ti_flags = 0; 2041 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2042 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 2043 sc->ti_ev_prodidx.ti_idx = 0; 2044 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2045 sc->ti_ev_saved_considx = 0; 2046 2047 /* Set up the command ring and producer mailbox. */ 2048 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 2049 2050 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 2051 rcb->ti_flags = 0; 2052 rcb->ti_max_len = 0; 2053 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2054 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2055 } 2056 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2057 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2058 sc->ti_cmd_saved_prodidx = 0; 2059 2060 /* 2061 * Assign the address of the stats refresh buffer. 2062 * We re-use the current stats buffer for this to 2063 * conserve memory. 2064 */ 2065 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2066 rdphys + TI_RD_OFF(ti_info.ti_stats); 2067 2068 /* Set up the standard receive ring. */ 2069 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2070 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 2071 rcb->ti_max_len = TI_FRAMELEN; 2072 rcb->ti_flags = 0; 2073 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2074 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2075 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2076 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2077 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2078 2079 /* Set up the jumbo receive ring. */ 2080 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2081 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 2082 2083#ifdef TI_PRIVATE_JUMBOS 2084 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 2085 rcb->ti_flags = 0; 2086#else 2087 rcb->ti_max_len = PAGE_SIZE; 2088 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2089#endif 2090 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2091 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2092 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2093 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2094 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2095 2096 /* 2097 * Set up the mini ring. Only activated on the 2098 * Tigon 2 but the slot in the config block is 2099 * still there on the Tigon 1. 2100 */ 2101 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2102 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 2103 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2104 if (sc->ti_hwrev == TI_HWREV_TIGON) 2105 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2106 else 2107 rcb->ti_flags = 0; 2108 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2109 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2110 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2111 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2112 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2113 2114 /* 2115 * Set up the receive return ring. 2116 */ 2117 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2118 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 2119 rcb->ti_flags = 0; 2120 rcb->ti_max_len = TI_RETURN_RING_CNT; 2121 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2122 rdphys + TI_RD_OFF(ti_return_prodidx_r); 2123 2124 /* 2125 * Set up the tx ring. Note: for the Tigon 2, we have the option 2126 * of putting the transmit ring in the host's address space and 2127 * letting the chip DMA it instead of leaving the ring in the NIC's 2128 * memory and accessing it through the shared memory region. We 2129 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2130 * so we have to revert to the shared memory scheme if we detect 2131 * a Tigon 1 chip. 2132 */ 2133 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2134 bzero((char *)sc->ti_rdata->ti_tx_ring, 2135 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2136 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2137 if (sc->ti_hwrev == TI_HWREV_TIGON) 2138 rcb->ti_flags = 0; 2139 else 2140 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2141 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2142 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2143 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM) 2144 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2145 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2146 rcb->ti_max_len = TI_TX_RING_CNT; 2147 if (sc->ti_hwrev == TI_HWREV_TIGON) 2148 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2149 else 2150 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 2151 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2152 rdphys + TI_RD_OFF(ti_tx_considx_r); 2153 2154 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2155 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2156 2157 /* Set up tuneables */ 2158#if 0 2159 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2160 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2161 (sc->ti_rx_coal_ticks / 10)); 2162 else 2163#endif 2164 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2165 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2166 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2167 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2168 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2169 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2170 2171 /* Turn interrupts on. */ 2172 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2173 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2174 2175 /* Start CPU. */ 2176 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2177 2178 return (0); 2179} 2180 2181static void 2182ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2183{ 2184 struct ti_softc *sc; 2185 2186 sc = arg; 2187 if (error || nseg != 1) 2188 return; 2189 2190 /* 2191 * All of the Tigon data structures need to live at <4GB. This 2192 * cast is fine since busdma was told about this constraint. 2193 */ 2194 sc->ti_rdata_phys = segs[0].ds_addr; 2195 return; 2196} 2197 2198/* 2199 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2200 * against our list and return its name if we find a match. 2201 */ 2202static int 2203ti_probe(device_t dev) 2204{ 2205 const struct ti_type *t; 2206 2207 t = ti_devs; 2208 2209 while (t->ti_name != NULL) { 2210 if ((pci_get_vendor(dev) == t->ti_vid) && 2211 (pci_get_device(dev) == t->ti_did)) { 2212 device_set_desc(dev, t->ti_name); 2213 return (BUS_PROBE_DEFAULT); 2214 } 2215 t++; 2216 } 2217 2218 return (ENXIO); 2219} 2220 2221static int 2222ti_attach(device_t dev) 2223{ 2224 struct ifnet *ifp; 2225 struct ti_softc *sc; 2226 int error = 0, rid; 2227 u_char eaddr[6]; 2228 2229 sc = device_get_softc(dev); 2230 sc->ti_dev = dev; 2231 2232 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2233 MTX_DEF); 2234 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2235 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2236 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2237 if (ifp == NULL) { 2238 device_printf(dev, "can not if_alloc()\n"); 2239 error = ENOSPC; 2240 goto fail; 2241 } 2242 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2243 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2244 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2245 2246 /* 2247 * Map control/status registers. 2248 */ 2249 pci_enable_busmaster(dev); 2250 2251 rid = PCIR_BAR(0); 2252 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2253 RF_ACTIVE); 2254 2255 if (sc->ti_res == NULL) { 2256 device_printf(dev, "couldn't map memory\n"); 2257 error = ENXIO; 2258 goto fail; 2259 } 2260 2261 sc->ti_btag = rman_get_bustag(sc->ti_res); 2262 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2263 2264 /* Allocate interrupt */ 2265 rid = 0; 2266 2267 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2268 RF_SHAREABLE | RF_ACTIVE); 2269 2270 if (sc->ti_irq == NULL) { 2271 device_printf(dev, "couldn't map interrupt\n"); 2272 error = ENXIO; 2273 goto fail; 2274 } 2275 2276 if (ti_chipinit(sc)) { 2277 device_printf(dev, "chip initialization failed\n"); 2278 error = ENXIO; 2279 goto fail; 2280 } 2281 2282 /* Zero out the NIC's on-board SRAM. */ 2283 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2284 2285 /* Init again -- zeroing memory may have clobbered some registers. */ 2286 if (ti_chipinit(sc)) { 2287 device_printf(dev, "chip initialization failed\n"); 2288 error = ENXIO; 2289 goto fail; 2290 } 2291 2292 /* 2293 * Get station address from the EEPROM. Note: the manual states 2294 * that the MAC address is at offset 0x8c, however the data is 2295 * stored as two longwords (since that's how it's loaded into 2296 * the NIC). This means the MAC address is actually preceded 2297 * by two zero bytes. We need to skip over those. 2298 */ 2299 if (ti_read_eeprom(sc, eaddr, 2300 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2301 device_printf(dev, "failed to read station address\n"); 2302 error = ENXIO; 2303 goto fail; 2304 } 2305 2306 /* Allocate the general information block and ring buffers. */ 2307 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 2308 1, 0, /* algnmnt, boundary */ 2309 BUS_SPACE_MAXADDR, /* lowaddr */ 2310 BUS_SPACE_MAXADDR, /* highaddr */ 2311 NULL, NULL, /* filter, filterarg */ 2312 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2313 0, /* nsegments */ 2314 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2315 0, /* flags */ 2316 NULL, NULL, /* lockfunc, lockarg */ 2317 &sc->ti_parent_dmat) != 0) { 2318 device_printf(dev, "Failed to allocate parent dmat\n"); 2319 error = ENOMEM; 2320 goto fail; 2321 } 2322 2323 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2324 PAGE_SIZE, 0, /* algnmnt, boundary */ 2325 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2326 BUS_SPACE_MAXADDR, /* highaddr */ 2327 NULL, NULL, /* filter, filterarg */ 2328 sizeof(struct ti_ring_data), /* maxsize */ 2329 1, /* nsegments */ 2330 sizeof(struct ti_ring_data), /* maxsegsize */ 2331 0, /* flags */ 2332 NULL, NULL, /* lockfunc, lockarg */ 2333 &sc->ti_rdata_dmat) != 0) { 2334 device_printf(dev, "Failed to allocate rdata dmat\n"); 2335 error = ENOMEM; 2336 goto fail; 2337 } 2338 2339 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2340 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2341 &sc->ti_rdata_dmamap) != 0) { 2342 device_printf(dev, "Failed to allocate rdata memory\n"); 2343 error = ENOMEM; 2344 goto fail; 2345 } 2346 2347 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2348 sc->ti_rdata, sizeof(struct ti_ring_data), 2349 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2350 device_printf(dev, "Failed to load rdata segments\n"); 2351 error = ENOMEM; 2352 goto fail; 2353 } 2354 2355 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2356 2357 /* Try to allocate memory for jumbo buffers. */ 2358 if (ti_alloc_jumbo_mem(sc)) { 2359 device_printf(dev, "jumbo buffer allocation failed\n"); 2360 error = ENXIO; 2361 goto fail; 2362 } 2363 2364 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2365 1, 0, /* algnmnt, boundary */ 2366 BUS_SPACE_MAXADDR, /* lowaddr */ 2367 BUS_SPACE_MAXADDR, /* highaddr */ 2368 NULL, NULL, /* filter, filterarg */ 2369 MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2370 TI_MAXTXSEGS, /* nsegments */ 2371 MCLBYTES, /* maxsegsize */ 2372 0, /* flags */ 2373 NULL, NULL, /* lockfunc, lockarg */ 2374 &sc->ti_mbuftx_dmat) != 0) { 2375 device_printf(dev, "Failed to allocate rdata dmat\n"); 2376 error = ENOMEM; 2377 goto fail; 2378 } 2379 2380 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2381 1, 0, /* algnmnt, boundary */ 2382 BUS_SPACE_MAXADDR, /* lowaddr */ 2383 BUS_SPACE_MAXADDR, /* highaddr */ 2384 NULL, NULL, /* filter, filterarg */ 2385 MCLBYTES, /* maxsize */ 2386 1, /* nsegments */ 2387 MCLBYTES, /* maxsegsize */ 2388 0, /* flags */ 2389 NULL, NULL, /* lockfunc, lockarg */ 2390 &sc->ti_mbufrx_dmat) != 0) { 2391 device_printf(dev, "Failed to allocate rdata dmat\n"); 2392 error = ENOMEM; 2393 goto fail; 2394 } 2395 2396 if (ti_alloc_dmamaps(sc)) { 2397 device_printf(dev, "dma map creation failed\n"); 2398 error = ENXIO; 2399 goto fail; 2400 } 2401 2402 /* 2403 * We really need a better way to tell a 1000baseTX card 2404 * from a 1000baseSX one, since in theory there could be 2405 * OEMed 1000baseTX cards from lame vendors who aren't 2406 * clever enough to change the PCI ID. For the moment 2407 * though, the AceNIC is the only copper card available. 2408 */ 2409 if (pci_get_vendor(dev) == ALT_VENDORID && 2410 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2411 sc->ti_copper = 1; 2412 /* Ok, it's not the only copper card available. */ 2413 if (pci_get_vendor(dev) == NG_VENDORID && 2414 pci_get_device(dev) == NG_DEVICEID_GA620T) 2415 sc->ti_copper = 1; 2416 2417 /* Set default tuneable values. */ 2418 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2419#if 0 2420 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2421#endif 2422 sc->ti_rx_coal_ticks = 170; 2423 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2424 sc->ti_rx_max_coal_bds = 64; 2425#if 0 2426 sc->ti_tx_max_coal_bds = 128; 2427#endif 2428 sc->ti_tx_max_coal_bds = 32; 2429 sc->ti_tx_buf_ratio = 21; 2430 2431 /* Set up ifnet structure */ 2432 ifp->if_softc = sc; 2433 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2434 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2435 ifp->if_ioctl = ti_ioctl; 2436 ifp->if_start = ti_start; 2437 ifp->if_init = ti_init; 2438 ifp->if_baudrate = IF_Gbps(1UL); 2439 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2440 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2441 IFQ_SET_READY(&ifp->if_snd); 2442 2443 /* Set up ifmedia support. */ 2444 if (sc->ti_copper) { 2445 /* 2446 * Copper cards allow manual 10/100 mode selection, 2447 * but not manual 1000baseTX mode selection. Why? 2448 * Becuase currently there's no way to specify the 2449 * master/slave setting through the firmware interface, 2450 * so Alteon decided to just bag it and handle it 2451 * via autonegotiation. 2452 */ 2453 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2454 ifmedia_add(&sc->ifmedia, 2455 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2456 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2457 ifmedia_add(&sc->ifmedia, 2458 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2459 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2460 ifmedia_add(&sc->ifmedia, 2461 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2462 } else { 2463 /* Fiber cards don't support 10/100 modes. */ 2464 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2465 ifmedia_add(&sc->ifmedia, 2466 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2467 } 2468 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2469 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2470 2471 /* 2472 * We're assuming here that card initialization is a sequential 2473 * thing. If it isn't, multiple cards probing at the same time 2474 * could stomp on the list of softcs here. 2475 */ 2476 2477 /* Register the device */ 2478 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2479 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2480 sc->dev->si_drv1 = sc; 2481 2482 /* 2483 * Call MI attach routine. 2484 */ 2485 ether_ifattach(ifp, eaddr); 2486 2487 /* VLAN capability setup. */ 2488 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2489 IFCAP_VLAN_HWTAGGING; 2490 ifp->if_capenable = ifp->if_capabilities; 2491 /* Tell the upper layer we support VLAN over-sized frames. */ 2492 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2493 2494 /* Driver supports link state tracking. */ 2495 ifp->if_capabilities |= IFCAP_LINKSTATE; 2496 ifp->if_capenable |= IFCAP_LINKSTATE; 2497 2498 /* Hook interrupt last to avoid having to lock softc */ 2499 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2500 NULL, ti_intr, sc, &sc->ti_intrhand); 2501 2502 if (error) { 2503 device_printf(dev, "couldn't set up irq\n"); 2504 goto fail; 2505 } 2506 2507fail: 2508 if (error) 2509 ti_detach(dev); 2510 2511 return (error); 2512} 2513 2514/* 2515 * Shutdown hardware and free up resources. This can be called any 2516 * time after the mutex has been initialized. It is called in both 2517 * the error case in attach and the normal detach case so it needs 2518 * to be careful about only freeing resources that have actually been 2519 * allocated. 2520 */ 2521static int 2522ti_detach(device_t dev) 2523{ 2524 struct ti_softc *sc; 2525 struct ifnet *ifp; 2526 2527 sc = device_get_softc(dev); 2528 if (sc->dev) 2529 destroy_dev(sc->dev); 2530 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2531 ifp = sc->ti_ifp; 2532 if (device_is_attached(dev)) { 2533 ether_ifdetach(ifp); 2534 TI_LOCK(sc); 2535 ti_stop(sc); 2536 TI_UNLOCK(sc); 2537 } 2538 2539 /* These should only be active if attach succeeded */ 2540 callout_drain(&sc->ti_watchdog); 2541 bus_generic_detach(dev); 2542 ti_free_dmamaps(sc); 2543 ifmedia_removeall(&sc->ifmedia); 2544 2545#ifdef TI_PRIVATE_JUMBOS 2546 if (sc->ti_cdata.ti_jumbo_buf) 2547 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2548 sc->ti_jumbo_dmamap); 2549#endif 2550 if (sc->ti_jumbo_dmat) 2551 bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2552 if (sc->ti_mbuftx_dmat) 2553 bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2554 if (sc->ti_mbufrx_dmat) 2555 bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2556 if (sc->ti_rdata && sc->ti_rdata_dmamap) 2557 bus_dmamap_unload(sc->ti_rdata_dmat, sc->ti_rdata_dmamap); 2558 if (sc->ti_rdata) 2559 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2560 sc->ti_rdata_dmamap); 2561 if (sc->ti_rdata_dmat) 2562 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2563 if (sc->ti_parent_dmat) 2564 bus_dma_tag_destroy(sc->ti_parent_dmat); 2565 if (sc->ti_intrhand) 2566 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2567 if (sc->ti_irq) 2568 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2569 if (sc->ti_res) { 2570 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2571 sc->ti_res); 2572 } 2573 if (ifp) 2574 if_free(ifp); 2575 2576 mtx_destroy(&sc->ti_mtx); 2577 2578 return (0); 2579} 2580 2581#ifdef TI_JUMBO_HDRSPLIT 2582/* 2583 * If hdr_len is 0, that means that header splitting wasn't done on 2584 * this packet for some reason. The two most likely reasons are that 2585 * the protocol isn't a supported protocol for splitting, or this 2586 * packet had a fragment offset that wasn't 0. 2587 * 2588 * The header length, if it is non-zero, will always be the length of 2589 * the headers on the packet, but that length could be longer than the 2590 * first mbuf. So we take the minimum of the two as the actual 2591 * length. 2592 */ 2593static __inline void 2594ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2595{ 2596 int i = 0; 2597 int lengths[4] = {0, 0, 0, 0}; 2598 struct mbuf *m, *mp; 2599 2600 if (hdr_len != 0) 2601 top->m_len = min(hdr_len, top->m_len); 2602 pkt_len -= top->m_len; 2603 lengths[i++] = top->m_len; 2604 2605 mp = top; 2606 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2607 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2608 pkt_len -= m->m_len; 2609 lengths[i++] = m->m_len; 2610 mp = m; 2611 } 2612 2613#if 0 2614 if (hdr_len != 0) 2615 printf("got split packet: "); 2616 else 2617 printf("got non-split packet: "); 2618 2619 printf("%d,%d,%d,%d = %d\n", lengths[0], 2620 lengths[1], lengths[2], lengths[3], 2621 lengths[0] + lengths[1] + lengths[2] + 2622 lengths[3]); 2623#endif 2624 2625 if (pkt_len) 2626 panic("header splitting didn't"); 2627 2628 if (m) { 2629 m_freem(m); 2630 mp->m_next = NULL; 2631 2632 } 2633 if (mp->m_next != NULL) 2634 panic("ti_hdr_split: last mbuf in chain should be null"); 2635} 2636#endif /* TI_JUMBO_HDRSPLIT */ 2637 2638/* 2639 * Frame reception handling. This is called if there's a frame 2640 * on the receive return list. 2641 * 2642 * Note: we have to be able to handle three possibilities here: 2643 * 1) the frame is from the mini receive ring (can only happen) 2644 * on Tigon 2 boards) 2645 * 2) the frame is from the jumbo recieve ring 2646 * 3) the frame is from the standard receive ring 2647 */ 2648 2649static void 2650ti_rxeof(struct ti_softc *sc) 2651{ 2652 struct ifnet *ifp; 2653 bus_dmamap_t map; 2654 struct ti_cmd_desc cmd; 2655 int jumbocnt, minicnt, stdcnt; 2656 2657 TI_LOCK_ASSERT(sc); 2658 2659 ifp = sc->ti_ifp; 2660 2661 jumbocnt = minicnt = stdcnt = 0; 2662 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2663 struct ti_rx_desc *cur_rx; 2664 uint32_t rxidx; 2665 struct mbuf *m = NULL; 2666 uint16_t vlan_tag = 0; 2667 int have_tag = 0; 2668 2669 cur_rx = 2670 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2671 rxidx = cur_rx->ti_idx; 2672 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2673 2674 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2675 have_tag = 1; 2676 vlan_tag = cur_rx->ti_vlan_tag; 2677 } 2678 2679 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2680 jumbocnt++; 2681 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2682 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2683 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2684 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2685 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2686 BUS_DMASYNC_POSTREAD); 2687 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 2688 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2689 ifp->if_ierrors++; 2690 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2691 continue; 2692 } 2693 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2694 ifp->if_ierrors++; 2695 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2696 continue; 2697 } 2698#ifdef TI_PRIVATE_JUMBOS 2699 m->m_len = cur_rx->ti_len; 2700#else /* TI_PRIVATE_JUMBOS */ 2701#ifdef TI_JUMBO_HDRSPLIT 2702 if (sc->ti_hdrsplit) 2703 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2704 cur_rx->ti_len, rxidx); 2705 else 2706#endif /* TI_JUMBO_HDRSPLIT */ 2707 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2708#endif /* TI_PRIVATE_JUMBOS */ 2709 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2710 minicnt++; 2711 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2712 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2713 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2714 map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2715 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2716 BUS_DMASYNC_POSTREAD); 2717 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2718 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2719 ifp->if_ierrors++; 2720 ti_newbuf_mini(sc, sc->ti_mini, m); 2721 continue; 2722 } 2723 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2724 ifp->if_ierrors++; 2725 ti_newbuf_mini(sc, sc->ti_mini, m); 2726 continue; 2727 } 2728 m->m_len = cur_rx->ti_len; 2729 } else { 2730 stdcnt++; 2731 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2732 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2733 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2734 map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2735 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2736 BUS_DMASYNC_POSTREAD); 2737 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2738 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2739 ifp->if_ierrors++; 2740 ti_newbuf_std(sc, sc->ti_std, m); 2741 continue; 2742 } 2743 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2744 ifp->if_ierrors++; 2745 ti_newbuf_std(sc, sc->ti_std, m); 2746 continue; 2747 } 2748 m->m_len = cur_rx->ti_len; 2749 } 2750 2751 m->m_pkthdr.len = cur_rx->ti_len; 2752 ifp->if_ipackets++; 2753 m->m_pkthdr.rcvif = ifp; 2754 2755 if (ifp->if_capenable & IFCAP_RXCSUM) { 2756 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2757 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2758 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2759 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2760 } 2761 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2762 m->m_pkthdr.csum_data = 2763 cur_rx->ti_tcp_udp_cksum; 2764 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2765 } 2766 } 2767 2768 /* 2769 * If we received a packet with a vlan tag, 2770 * tag it before passing the packet upward. 2771 */ 2772 if (have_tag) { 2773 m->m_pkthdr.ether_vtag = vlan_tag; 2774 m->m_flags |= M_VLANTAG; 2775 } 2776 TI_UNLOCK(sc); 2777 (*ifp->if_input)(ifp, m); 2778 TI_LOCK(sc); 2779 } 2780 2781 /* Only necessary on the Tigon 1. */ 2782 if (sc->ti_hwrev == TI_HWREV_TIGON) 2783 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2784 sc->ti_rx_saved_considx); 2785 2786 if (stdcnt > 0) 2787 TI_UPDATE_STDPROD(sc, sc->ti_std); 2788 if (minicnt > 0) 2789 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2790 if (jumbocnt > 0) 2791 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2792} 2793 2794static void 2795ti_txeof(struct ti_softc *sc) 2796{ 2797 struct ti_txdesc *txd; 2798 struct ti_tx_desc txdesc; 2799 struct ti_tx_desc *cur_tx = NULL; 2800 struct ifnet *ifp; 2801 int idx; 2802 2803 ifp = sc->ti_ifp; 2804 2805 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2806 if (txd == NULL) 2807 return; 2808 /* 2809 * Go through our tx ring and free mbufs for those 2810 * frames that have been sent. 2811 */ 2812 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2813 TI_INC(idx, TI_TX_RING_CNT)) { 2814 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2815 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2816 sizeof(txdesc), &txdesc); 2817 cur_tx = &txdesc; 2818 } else 2819 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2820 sc->ti_txcnt--; 2821 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2822 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2823 continue; 2824 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2825 BUS_DMASYNC_POSTWRITE); 2826 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2827 2828 ifp->if_opackets++; 2829 m_freem(txd->tx_m); 2830 txd->tx_m = NULL; 2831 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2832 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2833 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2834 } 2835 sc->ti_tx_saved_considx = idx; 2836 2837 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0; 2838} 2839 2840static void 2841ti_intr(void *xsc) 2842{ 2843 struct ti_softc *sc; 2844 struct ifnet *ifp; 2845 2846 sc = xsc; 2847 TI_LOCK(sc); 2848 ifp = sc->ti_ifp; 2849 2850/*#ifdef notdef*/ 2851 /* Avoid this for now -- checking this register is expensive. */ 2852 /* Make sure this is really our interrupt. */ 2853 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2854 TI_UNLOCK(sc); 2855 return; 2856 } 2857/*#endif*/ 2858 2859 /* Ack interrupt and stop others from occuring. */ 2860 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2861 2862 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2863 /* Check RX return ring producer/consumer */ 2864 ti_rxeof(sc); 2865 2866 /* Check TX ring producer/consumer */ 2867 ti_txeof(sc); 2868 } 2869 2870 ti_handle_events(sc); 2871 2872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2873 /* Re-enable interrupts. */ 2874 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2875 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2876 ti_start_locked(ifp); 2877 } 2878 2879 TI_UNLOCK(sc); 2880} 2881 2882static void 2883ti_stats_update(struct ti_softc *sc) 2884{ 2885 struct ifnet *ifp; 2886 2887 ifp = sc->ti_ifp; 2888 2889 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2890 BUS_DMASYNC_POSTREAD); 2891 2892 ifp->if_collisions += 2893 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2894 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2895 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2896 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2897 ifp->if_collisions; 2898 2899 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2900 BUS_DMASYNC_PREREAD); 2901} 2902 2903/* 2904 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2905 * pointers to descriptors. 2906 */ 2907static int 2908ti_encap(struct ti_softc *sc, struct mbuf **m_head) 2909{ 2910 struct ti_txdesc *txd; 2911 struct ti_tx_desc *f; 2912 struct ti_tx_desc txdesc; 2913 struct mbuf *m; 2914 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 2915 uint16_t csum_flags; 2916 int error, frag, i, nseg; 2917 2918 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 2919 return (ENOBUFS); 2920 2921 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2922 *m_head, txsegs, &nseg, 0); 2923 if (error == EFBIG) { 2924 m = m_defrag(*m_head, M_DONTWAIT); 2925 if (m == NULL) { 2926 m_freem(*m_head); 2927 *m_head = NULL; 2928 return (ENOMEM); 2929 } 2930 *m_head = m; 2931 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, 2932 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2933 if (error) { 2934 m_freem(*m_head); 2935 *m_head = NULL; 2936 return (error); 2937 } 2938 } else if (error != 0) 2939 return (error); 2940 if (nseg == 0) { 2941 m_freem(*m_head); 2942 *m_head = NULL; 2943 return (EIO); 2944 } 2945 2946 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 2947 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2948 return (ENOBUFS); 2949 } 2950 2951 m = *m_head; 2952 csum_flags = 0; 2953 if (m->m_pkthdr.csum_flags) { 2954 if (m->m_pkthdr.csum_flags & CSUM_IP) 2955 csum_flags |= TI_BDFLAG_IP_CKSUM; 2956 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2957 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2958 if (m->m_flags & M_LASTFRAG) 2959 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2960 else if (m->m_flags & M_FRAG) 2961 csum_flags |= TI_BDFLAG_IP_FRAG; 2962 } 2963 2964 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2965 BUS_DMASYNC_PREWRITE); 2966 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2967 BUS_DMASYNC_PREWRITE); 2968 2969 frag = sc->ti_tx_saved_prodidx; 2970 for (i = 0; i < nseg; i++) { 2971 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2972 bzero(&txdesc, sizeof(txdesc)); 2973 f = &txdesc; 2974 } else 2975 f = &sc->ti_rdata->ti_tx_ring[frag]; 2976 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 2977 f->ti_len = txsegs[i].ds_len; 2978 f->ti_flags = csum_flags; 2979 if (m->m_flags & M_VLANTAG) { 2980 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2981 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 2982 } else { 2983 f->ti_vlan_tag = 0; 2984 } 2985 2986 if (sc->ti_hwrev == TI_HWREV_TIGON) 2987 ti_mem_write(sc, TI_TX_RING_BASE + frag * 2988 sizeof(txdesc), sizeof(txdesc), &txdesc); 2989 TI_INC(frag, TI_TX_RING_CNT); 2990 } 2991 2992 sc->ti_tx_saved_prodidx = frag; 2993 /* set TI_BDFLAG_END on the last descriptor */ 2994 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 2995 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2996 txdesc.ti_flags |= TI_BDFLAG_END; 2997 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 2998 sizeof(txdesc), &txdesc); 2999 } else 3000 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3001 3002 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3003 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3004 txd->tx_m = m; 3005 sc->ti_txcnt += nseg; 3006 3007 return (0); 3008} 3009 3010static void 3011ti_start(struct ifnet *ifp) 3012{ 3013 struct ti_softc *sc; 3014 3015 sc = ifp->if_softc; 3016 TI_LOCK(sc); 3017 ti_start_locked(ifp); 3018 TI_UNLOCK(sc); 3019} 3020 3021/* 3022 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3023 * to the mbuf data regions directly in the transmit descriptors. 3024 */ 3025static void 3026ti_start_locked(struct ifnet *ifp) 3027{ 3028 struct ti_softc *sc; 3029 struct mbuf *m_head = NULL; 3030 int enq = 0; 3031 3032 sc = ifp->if_softc; 3033 3034 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3035 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3036 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3037 if (m_head == NULL) 3038 break; 3039 3040 /* 3041 * XXX 3042 * safety overkill. If this is a fragmented packet chain 3043 * with delayed TCP/UDP checksums, then only encapsulate 3044 * it if we have enough descriptors to handle the entire 3045 * chain at once. 3046 * (paranoia -- may not actually be needed) 3047 */ 3048 if (m_head->m_flags & M_FIRSTFRAG && 3049 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3050 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3051 m_head->m_pkthdr.csum_data + 16) { 3052 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3053 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3054 break; 3055 } 3056 } 3057 3058 /* 3059 * Pack the data into the transmit ring. If we 3060 * don't have room, set the OACTIVE flag and wait 3061 * for the NIC to drain the ring. 3062 */ 3063 if (ti_encap(sc, &m_head)) { 3064 if (m_head == NULL) 3065 break; 3066 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3067 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3068 break; 3069 } 3070 3071 enq++; 3072 /* 3073 * If there's a BPF listener, bounce a copy of this frame 3074 * to him. 3075 */ 3076 ETHER_BPF_MTAP(ifp, m_head); 3077 } 3078 3079 if (enq > 0) { 3080 /* Transmit */ 3081 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3082 3083 /* 3084 * Set a timeout in case the chip goes out to lunch. 3085 */ 3086 sc->ti_timer = 5; 3087 } 3088} 3089 3090static void 3091ti_init(void *xsc) 3092{ 3093 struct ti_softc *sc; 3094 3095 sc = xsc; 3096 TI_LOCK(sc); 3097 ti_init_locked(sc); 3098 TI_UNLOCK(sc); 3099} 3100 3101static void 3102ti_init_locked(void *xsc) 3103{ 3104 struct ti_softc *sc = xsc; 3105 3106 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3107 return; 3108 3109 /* Cancel pending I/O and flush buffers. */ 3110 ti_stop(sc); 3111 3112 /* Init the gen info block, ring control blocks and firmware. */ 3113 if (ti_gibinit(sc)) { 3114 device_printf(sc->ti_dev, "initialization failure\n"); 3115 return; 3116 } 3117} 3118 3119static void ti_init2(struct ti_softc *sc) 3120{ 3121 struct ti_cmd_desc cmd; 3122 struct ifnet *ifp; 3123 uint8_t *ea; 3124 struct ifmedia *ifm; 3125 int tmp; 3126 3127 TI_LOCK_ASSERT(sc); 3128 3129 ifp = sc->ti_ifp; 3130 3131 /* Specify MTU and interface index. */ 3132 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3133 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3134 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3135 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3136 3137 /* Load our MAC address. */ 3138 ea = IF_LLADDR(sc->ti_ifp); 3139 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3140 CSR_WRITE_4(sc, TI_GCR_PAR1, 3141 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3142 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3143 3144 /* Enable or disable promiscuous mode as needed. */ 3145 if (ifp->if_flags & IFF_PROMISC) { 3146 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3147 } else { 3148 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3149 } 3150 3151 /* Program multicast filter. */ 3152 ti_setmulti(sc); 3153 3154 /* 3155 * If this is a Tigon 1, we should tell the 3156 * firmware to use software packet filtering. 3157 */ 3158 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3159 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3160 } 3161 3162 /* Init RX ring. */ 3163 if (ti_init_rx_ring_std(sc) != 0) { 3164 /* XXX */ 3165 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3166 return; 3167 } 3168 3169 /* Init jumbo RX ring. */ 3170 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) { 3171 if (ti_init_rx_ring_jumbo(sc) != 0) { 3172 /* XXX */ 3173 device_printf(sc->ti_dev, 3174 "no memory for jumbo Rx buffers.\n"); 3175 return; 3176 } 3177 } 3178 3179 /* 3180 * If this is a Tigon 2, we can also configure the 3181 * mini ring. 3182 */ 3183 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3184 if (ti_init_rx_ring_mini(sc) != 0) { 3185 /* XXX */ 3186 device_printf(sc->ti_dev, 3187 "no memory for mini Rx buffers.\n"); 3188 return; 3189 } 3190 } 3191 3192 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3193 sc->ti_rx_saved_considx = 0; 3194 3195 /* Init TX ring. */ 3196 ti_init_tx_ring(sc); 3197 3198 /* Tell firmware we're alive. */ 3199 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3200 3201 /* Enable host interrupts. */ 3202 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3203 3204 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3205 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3206 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3207 3208 /* 3209 * Make sure to set media properly. We have to do this 3210 * here since we have to issue commands in order to set 3211 * the link negotiation and we can't issue commands until 3212 * the firmware is running. 3213 */ 3214 ifm = &sc->ifmedia; 3215 tmp = ifm->ifm_media; 3216 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3217 ti_ifmedia_upd_locked(sc); 3218 ifm->ifm_media = tmp; 3219} 3220 3221/* 3222 * Set media options. 3223 */ 3224static int 3225ti_ifmedia_upd(struct ifnet *ifp) 3226{ 3227 struct ti_softc *sc; 3228 int error; 3229 3230 sc = ifp->if_softc; 3231 TI_LOCK(sc); 3232 error = ti_ifmedia_upd(ifp); 3233 TI_UNLOCK(sc); 3234 3235 return (error); 3236} 3237 3238static int 3239ti_ifmedia_upd_locked(struct ti_softc *sc) 3240{ 3241 struct ifmedia *ifm; 3242 struct ti_cmd_desc cmd; 3243 uint32_t flowctl; 3244 3245 ifm = &sc->ifmedia; 3246 3247 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3248 return (EINVAL); 3249 3250 flowctl = 0; 3251 3252 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3253 case IFM_AUTO: 3254 /* 3255 * Transmit flow control doesn't work on the Tigon 1. 3256 */ 3257 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3258 3259 /* 3260 * Transmit flow control can also cause problems on the 3261 * Tigon 2, apparantly with both the copper and fiber 3262 * boards. The symptom is that the interface will just 3263 * hang. This was reproduced with Alteon 180 switches. 3264 */ 3265#if 0 3266 if (sc->ti_hwrev != TI_HWREV_TIGON) 3267 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3268#endif 3269 3270 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3271 TI_GLNK_FULL_DUPLEX| flowctl | 3272 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3273 3274 flowctl = TI_LNK_RX_FLOWCTL_Y; 3275#if 0 3276 if (sc->ti_hwrev != TI_HWREV_TIGON) 3277 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3278#endif 3279 3280 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3281 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3282 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3283 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3284 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3285 break; 3286 case IFM_1000_SX: 3287 case IFM_1000_T: 3288 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3289#if 0 3290 if (sc->ti_hwrev != TI_HWREV_TIGON) 3291 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3292#endif 3293 3294 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3295 flowctl |TI_GLNK_ENB); 3296 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3297 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3298 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3299 } 3300 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3301 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3302 break; 3303 case IFM_100_FX: 3304 case IFM_10_FL: 3305 case IFM_100_TX: 3306 case IFM_10_T: 3307 flowctl = TI_LNK_RX_FLOWCTL_Y; 3308#if 0 3309 if (sc->ti_hwrev != TI_HWREV_TIGON) 3310 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3311#endif 3312 3313 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3314 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3315 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3316 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3317 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3318 } else { 3319 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3320 } 3321 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3322 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3323 } else { 3324 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3325 } 3326 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3327 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3328 break; 3329 } 3330 3331 return (0); 3332} 3333 3334/* 3335 * Report current media status. 3336 */ 3337static void 3338ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3339{ 3340 struct ti_softc *sc; 3341 uint32_t media = 0; 3342 3343 sc = ifp->if_softc; 3344 3345 TI_LOCK(sc); 3346 3347 ifmr->ifm_status = IFM_AVALID; 3348 ifmr->ifm_active = IFM_ETHER; 3349 3350 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3351 TI_UNLOCK(sc); 3352 return; 3353 } 3354 3355 ifmr->ifm_status |= IFM_ACTIVE; 3356 3357 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3358 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3359 if (sc->ti_copper) 3360 ifmr->ifm_active |= IFM_1000_T; 3361 else 3362 ifmr->ifm_active |= IFM_1000_SX; 3363 if (media & TI_GLNK_FULL_DUPLEX) 3364 ifmr->ifm_active |= IFM_FDX; 3365 else 3366 ifmr->ifm_active |= IFM_HDX; 3367 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3368 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3369 if (sc->ti_copper) { 3370 if (media & TI_LNK_100MB) 3371 ifmr->ifm_active |= IFM_100_TX; 3372 if (media & TI_LNK_10MB) 3373 ifmr->ifm_active |= IFM_10_T; 3374 } else { 3375 if (media & TI_LNK_100MB) 3376 ifmr->ifm_active |= IFM_100_FX; 3377 if (media & TI_LNK_10MB) 3378 ifmr->ifm_active |= IFM_10_FL; 3379 } 3380 if (media & TI_LNK_FULL_DUPLEX) 3381 ifmr->ifm_active |= IFM_FDX; 3382 if (media & TI_LNK_HALF_DUPLEX) 3383 ifmr->ifm_active |= IFM_HDX; 3384 } 3385 TI_UNLOCK(sc); 3386} 3387 3388static int 3389ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3390{ 3391 struct ti_softc *sc = ifp->if_softc; 3392 struct ifreq *ifr = (struct ifreq *) data; 3393 struct ti_cmd_desc cmd; 3394 int mask, error = 0; 3395 3396 switch (command) { 3397 case SIOCSIFMTU: 3398 TI_LOCK(sc); 3399 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3400 error = EINVAL; 3401 else { 3402 ifp->if_mtu = ifr->ifr_mtu; 3403 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3404 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3405 ti_init_locked(sc); 3406 } 3407 } 3408 TI_UNLOCK(sc); 3409 break; 3410 case SIOCSIFFLAGS: 3411 TI_LOCK(sc); 3412 if (ifp->if_flags & IFF_UP) { 3413 /* 3414 * If only the state of the PROMISC flag changed, 3415 * then just use the 'set promisc mode' command 3416 * instead of reinitializing the entire NIC. Doing 3417 * a full re-init means reloading the firmware and 3418 * waiting for it to start up, which may take a 3419 * second or two. 3420 */ 3421 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3422 ifp->if_flags & IFF_PROMISC && 3423 !(sc->ti_if_flags & IFF_PROMISC)) { 3424 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3425 TI_CMD_CODE_PROMISC_ENB, 0); 3426 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3427 !(ifp->if_flags & IFF_PROMISC) && 3428 sc->ti_if_flags & IFF_PROMISC) { 3429 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3430 TI_CMD_CODE_PROMISC_DIS, 0); 3431 } else 3432 ti_init_locked(sc); 3433 } else { 3434 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3435 ti_stop(sc); 3436 } 3437 } 3438 sc->ti_if_flags = ifp->if_flags; 3439 TI_UNLOCK(sc); 3440 break; 3441 case SIOCADDMULTI: 3442 case SIOCDELMULTI: 3443 TI_LOCK(sc); 3444 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3445 ti_setmulti(sc); 3446 TI_UNLOCK(sc); 3447 break; 3448 case SIOCSIFMEDIA: 3449 case SIOCGIFMEDIA: 3450 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3451 break; 3452 case SIOCSIFCAP: 3453 TI_LOCK(sc); 3454 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3455 if ((mask & IFCAP_TXCSUM) != 0 && 3456 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3457 ifp->if_capenable ^= IFCAP_TXCSUM; 3458 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3459 ifp->if_hwassist |= TI_CSUM_FEATURES; 3460 else 3461 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3462 } 3463 if ((mask & IFCAP_RXCSUM) != 0 && 3464 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3465 ifp->if_capenable ^= IFCAP_RXCSUM; 3466 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3467 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3468 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3469 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3470 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3471 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3472 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3473 IFCAP_VLAN_HWTAGGING)) != 0) { 3474 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3475 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3476 ti_init_locked(sc); 3477 } 3478 } 3479 TI_UNLOCK(sc); 3480 VLAN_CAPABILITIES(ifp); 3481 break; 3482 default: 3483 error = ether_ioctl(ifp, command, data); 3484 break; 3485 } 3486 3487 return (error); 3488} 3489 3490static int 3491ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3492{ 3493 struct ti_softc *sc; 3494 3495 sc = dev->si_drv1; 3496 if (sc == NULL) 3497 return (ENODEV); 3498 3499 TI_LOCK(sc); 3500 sc->ti_flags |= TI_FLAG_DEBUGING; 3501 TI_UNLOCK(sc); 3502 3503 return (0); 3504} 3505 3506static int 3507ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3508{ 3509 struct ti_softc *sc; 3510 3511 sc = dev->si_drv1; 3512 if (sc == NULL) 3513 return (ENODEV); 3514 3515 TI_LOCK(sc); 3516 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3517 TI_UNLOCK(sc); 3518 3519 return (0); 3520} 3521 3522/* 3523 * This ioctl routine goes along with the Tigon character device. 3524 */ 3525static int 3526ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3527 struct thread *td) 3528{ 3529 struct ti_softc *sc; 3530 int error; 3531 3532 sc = dev->si_drv1; 3533 if (sc == NULL) 3534 return (ENODEV); 3535 3536 error = 0; 3537 3538 switch (cmd) { 3539 case TIIOCGETSTATS: 3540 { 3541 struct ti_stats *outstats; 3542 3543 outstats = (struct ti_stats *)addr; 3544 3545 TI_LOCK(sc); 3546 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3547 sizeof(struct ti_stats)); 3548 TI_UNLOCK(sc); 3549 break; 3550 } 3551 case TIIOCGETPARAMS: 3552 { 3553 struct ti_params *params; 3554 3555 params = (struct ti_params *)addr; 3556 3557 TI_LOCK(sc); 3558 params->ti_stat_ticks = sc->ti_stat_ticks; 3559 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3560 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3561 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3562 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3563 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3564 params->param_mask = TI_PARAM_ALL; 3565 TI_UNLOCK(sc); 3566 3567 error = 0; 3568 3569 break; 3570 } 3571 case TIIOCSETPARAMS: 3572 { 3573 struct ti_params *params; 3574 3575 params = (struct ti_params *)addr; 3576 3577 TI_LOCK(sc); 3578 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3579 sc->ti_stat_ticks = params->ti_stat_ticks; 3580 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3581 } 3582 3583 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3584 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3585 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3586 sc->ti_rx_coal_ticks); 3587 } 3588 3589 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3590 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3591 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3592 sc->ti_tx_coal_ticks); 3593 } 3594 3595 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3596 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3597 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3598 sc->ti_rx_max_coal_bds); 3599 } 3600 3601 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3602 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3603 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3604 sc->ti_tx_max_coal_bds); 3605 } 3606 3607 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3608 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3609 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3610 sc->ti_tx_buf_ratio); 3611 } 3612 TI_UNLOCK(sc); 3613 3614 error = 0; 3615 3616 break; 3617 } 3618 case TIIOCSETTRACE: { 3619 ti_trace_type trace_type; 3620 3621 trace_type = *(ti_trace_type *)addr; 3622 3623 /* 3624 * Set tracing to whatever the user asked for. Setting 3625 * this register to 0 should have the effect of disabling 3626 * tracing. 3627 */ 3628 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3629 3630 error = 0; 3631 3632 break; 3633 } 3634 case TIIOCGETTRACE: { 3635 struct ti_trace_buf *trace_buf; 3636 uint32_t trace_start, cur_trace_ptr, trace_len; 3637 3638 trace_buf = (struct ti_trace_buf *)addr; 3639 3640 TI_LOCK(sc); 3641 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3642 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3643 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3644 3645#if 0 3646 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3647 "trace_len = %d\n", trace_start, 3648 cur_trace_ptr, trace_len); 3649 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3650 trace_buf->buf_len); 3651#endif 3652 3653 error = ti_copy_mem(sc, trace_start, min(trace_len, 3654 trace_buf->buf_len), 3655 (caddr_t)trace_buf->buf, 1, 1); 3656 3657 if (error == 0) { 3658 trace_buf->fill_len = min(trace_len, 3659 trace_buf->buf_len); 3660 if (cur_trace_ptr < trace_start) 3661 trace_buf->cur_trace_ptr = 3662 trace_start - cur_trace_ptr; 3663 else 3664 trace_buf->cur_trace_ptr = 3665 cur_trace_ptr - trace_start; 3666 } else 3667 trace_buf->fill_len = 0; 3668 TI_UNLOCK(sc); 3669 3670 break; 3671 } 3672 3673 /* 3674 * For debugging, five ioctls are needed: 3675 * ALT_ATTACH 3676 * ALT_READ_TG_REG 3677 * ALT_WRITE_TG_REG 3678 * ALT_READ_TG_MEM 3679 * ALT_WRITE_TG_MEM 3680 */ 3681 case ALT_ATTACH: 3682 /* 3683 * From what I can tell, Alteon's Solaris Tigon driver 3684 * only has one character device, so you have to attach 3685 * to the Tigon board you're interested in. This seems 3686 * like a not-so-good way to do things, since unless you 3687 * subsequently specify the unit number of the device 3688 * you're interested in every ioctl, you'll only be 3689 * able to debug one board at a time. 3690 */ 3691 error = 0; 3692 break; 3693 case ALT_READ_TG_MEM: 3694 case ALT_WRITE_TG_MEM: 3695 { 3696 struct tg_mem *mem_param; 3697 uint32_t sram_end, scratch_end; 3698 3699 mem_param = (struct tg_mem *)addr; 3700 3701 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3702 sram_end = TI_END_SRAM_I; 3703 scratch_end = TI_END_SCRATCH_I; 3704 } else { 3705 sram_end = TI_END_SRAM_II; 3706 scratch_end = TI_END_SCRATCH_II; 3707 } 3708 3709 /* 3710 * For now, we'll only handle accessing regular SRAM, 3711 * nothing else. 3712 */ 3713 TI_LOCK(sc); 3714 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3715 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3716 /* 3717 * In this instance, we always copy to/from user 3718 * space, so the user space argument is set to 1. 3719 */ 3720 error = ti_copy_mem(sc, mem_param->tgAddr, 3721 mem_param->len, 3722 mem_param->userAddr, 1, 3723 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3724 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3725 && (mem_param->tgAddr <= scratch_end)) { 3726 error = ti_copy_scratch(sc, mem_param->tgAddr, 3727 mem_param->len, 3728 mem_param->userAddr, 1, 3729 (cmd == ALT_READ_TG_MEM) ? 3730 1 : 0, TI_PROCESSOR_A); 3731 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3732 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3733 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3734 if_printf(sc->ti_ifp, 3735 "invalid memory range for Tigon I\n"); 3736 error = EINVAL; 3737 break; 3738 } 3739 error = ti_copy_scratch(sc, mem_param->tgAddr - 3740 TI_SCRATCH_DEBUG_OFF, 3741 mem_param->len, 3742 mem_param->userAddr, 1, 3743 (cmd == ALT_READ_TG_MEM) ? 3744 1 : 0, TI_PROCESSOR_B); 3745 } else { 3746 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3747 "out of supported range\n", 3748 mem_param->tgAddr, mem_param->len); 3749 error = EINVAL; 3750 } 3751 TI_UNLOCK(sc); 3752 3753 break; 3754 } 3755 case ALT_READ_TG_REG: 3756 case ALT_WRITE_TG_REG: 3757 { 3758 struct tg_reg *regs; 3759 uint32_t tmpval; 3760 3761 regs = (struct tg_reg *)addr; 3762 3763 /* 3764 * Make sure the address in question isn't out of range. 3765 */ 3766 if (regs->addr > TI_REG_MAX) { 3767 error = EINVAL; 3768 break; 3769 } 3770 TI_LOCK(sc); 3771 if (cmd == ALT_READ_TG_REG) { 3772 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3773 regs->addr, &tmpval, 1); 3774 regs->data = ntohl(tmpval); 3775#if 0 3776 if ((regs->addr == TI_CPU_STATE) 3777 || (regs->addr == TI_CPU_CTL_B)) { 3778 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3779 regs->addr, tmpval); 3780 } 3781#endif 3782 } else { 3783 tmpval = htonl(regs->data); 3784 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3785 regs->addr, &tmpval, 1); 3786 } 3787 TI_UNLOCK(sc); 3788 3789 break; 3790 } 3791 default: 3792 error = ENOTTY; 3793 break; 3794 } 3795 return (error); 3796} 3797 3798static void 3799ti_watchdog(void *arg) 3800{ 3801 struct ti_softc *sc; 3802 struct ifnet *ifp; 3803 3804 sc = arg; 3805 TI_LOCK_ASSERT(sc); 3806 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3807 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3808 return; 3809 3810 /* 3811 * When we're debugging, the chip is often stopped for long periods 3812 * of time, and that would normally cause the watchdog timer to fire. 3813 * Since that impedes debugging, we don't want to do that. 3814 */ 3815 if (sc->ti_flags & TI_FLAG_DEBUGING) 3816 return; 3817 3818 ifp = sc->ti_ifp; 3819 if_printf(ifp, "watchdog timeout -- resetting\n"); 3820 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3821 ti_init_locked(sc); 3822 3823 ifp->if_oerrors++; 3824} 3825 3826/* 3827 * Stop the adapter and free any mbufs allocated to the 3828 * RX and TX lists. 3829 */ 3830static void 3831ti_stop(struct ti_softc *sc) 3832{ 3833 struct ifnet *ifp; 3834 struct ti_cmd_desc cmd; 3835 3836 TI_LOCK_ASSERT(sc); 3837 3838 ifp = sc->ti_ifp; 3839 3840 /* Disable host interrupts. */ 3841 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3842 /* 3843 * Tell firmware we're shutting down. 3844 */ 3845 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3846 3847 /* Halt and reinitialize. */ 3848 if (ti_chipinit(sc) == 0) { 3849 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3850 /* XXX ignore init errors. */ 3851 ti_chipinit(sc); 3852 } 3853 3854 /* Free the RX lists. */ 3855 ti_free_rx_ring_std(sc); 3856 3857 /* Free jumbo RX list. */ 3858 ti_free_rx_ring_jumbo(sc); 3859 3860 /* Free mini RX list. */ 3861 ti_free_rx_ring_mini(sc); 3862 3863 /* Free TX buffers. */ 3864 ti_free_tx_ring(sc); 3865 3866 sc->ti_ev_prodidx.ti_idx = 0; 3867 sc->ti_return_prodidx.ti_idx = 0; 3868 sc->ti_tx_considx.ti_idx = 0; 3869 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3870 3871 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3872 callout_stop(&sc->ti_watchdog); 3873} 3874 3875/* 3876 * Stop all chip I/O so that the kernel's probe routines don't 3877 * get confused by errant DMAs when rebooting. 3878 */ 3879static int 3880ti_shutdown(device_t dev) 3881{ 3882 struct ti_softc *sc; 3883 3884 sc = device_get_softc(dev); 3885 TI_LOCK(sc); 3886 ti_chipinit(sc); 3887 TI_UNLOCK(sc); 3888 3889 return (0); 3890} 3891