if_ti.c revision 153396
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 153396 2005-12-14 00:03:41Z scottl $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94 95#include <net/if.h> 96#include <net/if_arp.h> 97#include <net/ethernet.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100#include <net/if_types.h> 101#include <net/if_vlan_var.h> 102 103#include <net/bpf.h> 104 105#include <netinet/in_systm.h> 106#include <netinet/in.h> 107#include <netinet/ip.h> 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/bus.h> 112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> 115 116/* #define TI_PRIVATE_JUMBOS */ 117 118#if !defined(TI_PRIVATE_JUMBOS) 119#include <sys/sockio.h> 120#include <sys/uio.h> 121#include <sys/lock.h> 122#include <sys/sf_buf.h> 123#include <vm/vm_extern.h> 124#include <vm/pmap.h> 125#include <vm/vm_map.h> 126#include <vm/vm_map.h> 127#include <vm/vm_param.h> 128#include <vm/vm_pageout.h> 129#include <sys/vmmeter.h> 130#include <vm/vm_page.h> 131#include <vm/vm_object.h> 132#include <vm/vm_kern.h> 133#include <sys/proc.h> 134#endif /* !TI_PRIVATE_JUMBOS */ 135 136#include <dev/pci/pcireg.h> 137#include <dev/pci/pcivar.h> 138 139#include <sys/tiio.h> 140#include <dev/ti/if_tireg.h> 141#include <dev/ti/ti_fw.h> 142#include <dev/ti/ti_fw2.h> 143 144#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 145/* 146 * We can only turn on header splitting if we're using extended receive 147 * BDs. 148 */ 149#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 150#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 151#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 152 153struct ti_softc *tis[8]; 154 155typedef enum { 156 TI_SWAP_HTON, 157 TI_SWAP_NTOH 158} ti_swap_type; 159 160 161/* 162 * Various supported device vendors/types and their names. 163 */ 164 165static struct ti_type ti_devs[] = { 166 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 167 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 168 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 169 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 170 { TC_VENDORID, TC_DEVICEID_3C985, 171 "3Com 3c985-SX Gigabit Ethernet" }, 172 { NG_VENDORID, NG_DEVICEID_GA620, 173 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 174 { NG_VENDORID, NG_DEVICEID_GA620T, 175 "Netgear GA620 1000baseT Gigabit Ethernet" }, 176 { SGI_VENDORID, SGI_DEVICEID_TIGON, 177 "Silicon Graphics Gigabit Ethernet" }, 178 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 179 "Farallon PN9000SX Gigabit Ethernet" }, 180 { 0, 0, NULL } 181}; 182 183 184static d_open_t ti_open; 185static d_close_t ti_close; 186static d_ioctl_t ti_ioctl2; 187 188static struct cdevsw ti_cdevsw = { 189 .d_version = D_VERSION, 190 .d_flags = 0, 191 .d_open = ti_open, 192 .d_close = ti_close, 193 .d_ioctl = ti_ioctl2, 194 .d_name = "ti", 195}; 196 197static int ti_probe(device_t); 198static int ti_attach(device_t); 199static int ti_detach(device_t); 200static void ti_txeof(struct ti_softc *); 201static void ti_rxeof(struct ti_softc *); 202 203static void ti_stats_update(struct ti_softc *); 204static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *); 205static void ti_encap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 206 bus_size_t mapsize, int error); 207 208static void ti_intr(void *); 209static void ti_start(struct ifnet *); 210static int ti_ioctl(struct ifnet *, u_long, caddr_t); 211static void ti_init(void *); 212static void ti_init2(struct ti_softc *); 213static void ti_stop(struct ti_softc *); 214static void ti_watchdog(struct ifnet *); 215static void ti_shutdown(device_t); 216static int ti_ifmedia_upd(struct ifnet *); 217static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 219static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 220static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 221static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 222 223static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 224static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 225static void ti_setmulti(struct ti_softc *); 226 227static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t); 228static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 229static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 230 int, int, int); 231static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 232static void ti_loadfw(struct ti_softc *); 233static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 234static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 235static void ti_handle_events(struct ti_softc *); 236static int ti_alloc_dmamaps(struct ti_softc *); 237static void ti_free_dmamaps(struct ti_softc *); 238static int ti_alloc_jumbo_mem(struct ti_softc *); 239#ifdef TI_PRIVATE_JUMBOS 240static void *ti_jalloc(struct ti_softc *); 241static void ti_jfree(void *, void *); 242#endif /* TI_PRIVATE_JUMBOS */ 243static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 244static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 245static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 246static int ti_init_rx_ring_std(struct ti_softc *); 247static void ti_free_rx_ring_std(struct ti_softc *); 248static int ti_init_rx_ring_jumbo(struct ti_softc *); 249static void ti_free_rx_ring_jumbo(struct ti_softc *); 250static int ti_init_rx_ring_mini(struct ti_softc *); 251static void ti_free_rx_ring_mini(struct ti_softc *); 252static void ti_free_tx_ring(struct ti_softc *); 253static int ti_init_tx_ring(struct ti_softc *); 254 255static int ti_64bitslot_war(struct ti_softc *); 256static int ti_chipinit(struct ti_softc *); 257static int ti_gibinit(struct ti_softc *); 258 259#ifdef TI_JUMBO_HDRSPLIT 260static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 261 int pkt_len, int idx); 262#endif /* TI_JUMBO_HDRSPLIT */ 263 264static device_method_t ti_methods[] = { 265 /* Device interface */ 266 DEVMETHOD(device_probe, ti_probe), 267 DEVMETHOD(device_attach, ti_attach), 268 DEVMETHOD(device_detach, ti_detach), 269 DEVMETHOD(device_shutdown, ti_shutdown), 270 { 0, 0 } 271}; 272 273static driver_t ti_driver = { 274 "ti", 275 ti_methods, 276 sizeof(struct ti_softc) 277}; 278 279static devclass_t ti_devclass; 280 281DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 282MODULE_DEPEND(ti, pci, 1, 1, 1); 283MODULE_DEPEND(ti, ether, 1, 1, 1); 284 285/* 286 * Send an instruction or address to the EEPROM, check for ACK. 287 */ 288static u_int32_t ti_eeprom_putbyte(sc, byte) 289 struct ti_softc *sc; 290 int byte; 291{ 292 register int i, ack = 0; 293 294 /* 295 * Make sure we're in TX mode. 296 */ 297 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 298 299 /* 300 * Feed in each bit and stobe the clock. 301 */ 302 for (i = 0x80; i; i >>= 1) { 303 if (byte & i) { 304 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 305 } else { 306 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 307 } 308 DELAY(1); 309 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 DELAY(1); 311 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 312 } 313 314 /* 315 * Turn off TX mode. 316 */ 317 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 318 319 /* 320 * Check for ack. 321 */ 322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 323 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 324 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 325 326 return (ack); 327} 328 329/* 330 * Read a byte of data stored in the EEPROM at address 'addr.' 331 * We have to send two address bytes since the EEPROM can hold 332 * more than 256 bytes of data. 333 */ 334static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 335 struct ti_softc *sc; 336 int addr; 337 u_int8_t *dest; 338{ 339 register int i; 340 u_int8_t byte = 0; 341 342 EEPROM_START; 343 344 /* 345 * Send write control code to EEPROM. 346 */ 347 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 348 if_printf(sc->ti_ifp, 349 "failed to send write command, status: %x\n", 350 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 351 return (1); 352 } 353 354 /* 355 * Send first byte of address of byte we want to read. 356 */ 357 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 358 if_printf(sc->ti_ifp, "failed to send address, status: %x\n", 359 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 360 return (1); 361 } 362 /* 363 * Send second byte address of byte we want to read. 364 */ 365 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 366 if_printf(sc->ti_ifp, "failed to send address, status: %x\n", 367 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 368 return (1); 369 } 370 371 EEPROM_STOP; 372 EEPROM_START; 373 /* 374 * Send read control code to EEPROM. 375 */ 376 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 377 if_printf(sc->ti_ifp, 378 "failed to send read command, status: %x\n", 379 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 380 return (1); 381 } 382 383 /* 384 * Start reading bits from EEPROM. 385 */ 386 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 387 for (i = 0x80; i; i >>= 1) { 388 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 389 DELAY(1); 390 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 391 byte |= i; 392 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 393 DELAY(1); 394 } 395 396 EEPROM_STOP; 397 398 /* 399 * No ACK generated for read, so just return byte. 400 */ 401 402 *dest = byte; 403 404 return (0); 405} 406 407/* 408 * Read a sequence of bytes from the EEPROM. 409 */ 410static int 411ti_read_eeprom(sc, dest, off, cnt) 412 struct ti_softc *sc; 413 caddr_t dest; 414 int off; 415 int cnt; 416{ 417 int err = 0, i; 418 u_int8_t byte = 0; 419 420 for (i = 0; i < cnt; i++) { 421 err = ti_eeprom_getbyte(sc, off + i, &byte); 422 if (err) 423 break; 424 *(dest + i) = byte; 425 } 426 427 return (err ? 1 : 0); 428} 429 430/* 431 * NIC memory access function. Can be used to either clear a section 432 * of NIC local memory or (if buf is non-NULL) copy data into it. 433 */ 434static void 435ti_mem(sc, addr, len, buf) 436 struct ti_softc *sc; 437 u_int32_t addr, len; 438 caddr_t buf; 439{ 440 int segptr, segsize, cnt; 441 caddr_t ti_winbase, ptr; 442 443 segptr = addr; 444 cnt = len; 445 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 446 ptr = buf; 447 448 while (cnt) { 449 if (cnt < TI_WINLEN) 450 segsize = cnt; 451 else 452 segsize = TI_WINLEN - (segptr % TI_WINLEN); 453 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 454 if (buf == NULL) 455 bzero((char *)ti_winbase + (segptr & 456 (TI_WINLEN - 1)), segsize); 457 else { 458 bcopy((char *)ptr, (char *)ti_winbase + 459 (segptr & (TI_WINLEN - 1)), segsize); 460 ptr += segsize; 461 } 462 segptr += segsize; 463 cnt -= segsize; 464 } 465} 466 467static int 468ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 469 struct ti_softc *sc; 470 u_int32_t tigon_addr, len; 471 caddr_t buf; 472 int useraddr, readdata; 473{ 474 int segptr, segsize, cnt; 475 caddr_t ptr; 476 u_int32_t origwin; 477 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 478 int resid, segresid; 479 int first_pass; 480 481 /* 482 * At the moment, we don't handle non-aligned cases, we just bail. 483 * If this proves to be a problem, it will be fixed. 484 */ 485 if ((readdata == 0) 486 && (tigon_addr & 0x3)) { 487 if_printf(sc->ti_ifp, "ti_copy_mem: tigon address %#x isn't " 488 "word-aligned\n", tigon_addr); 489 if_printf(sc->ti_ifp, "ti_copy_mem: unaligned writes aren't " 490 "yet supported\n"); 491 return (EINVAL); 492 } 493 494 segptr = tigon_addr & ~0x3; 495 segresid = tigon_addr - segptr; 496 497 /* 498 * This is the non-aligned amount left over that we'll need to 499 * copy. 500 */ 501 resid = len & 0x3; 502 503 /* Add in the left over amount at the front of the buffer */ 504 resid += segresid; 505 506 cnt = len & ~0x3; 507 /* 508 * If resid + segresid is >= 4, add multiples of 4 to the count and 509 * decrease the residual by that much. 510 */ 511 cnt += resid & ~0x3; 512 resid -= resid & ~0x3; 513 514 ptr = buf; 515 516 first_pass = 1; 517 518 /* 519 * Save the old window base value. 520 */ 521 origwin = CSR_READ_4(sc, TI_WINBASE); 522 523 while (cnt) { 524 bus_size_t ti_offset; 525 526 if (cnt < TI_WINLEN) 527 segsize = cnt; 528 else 529 segsize = TI_WINLEN - (segptr % TI_WINLEN); 530 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 531 532 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 533 534 if (readdata) { 535 536 bus_space_read_region_4(sc->ti_btag, 537 sc->ti_bhandle, ti_offset, 538 (u_int32_t *)tmparray, 539 segsize >> 2); 540 if (useraddr) { 541 /* 542 * Yeah, this is a little on the kludgy 543 * side, but at least this code is only 544 * used for debugging. 545 */ 546 ti_bcopy_swap(tmparray, tmparray2, segsize, 547 TI_SWAP_NTOH); 548 549 TI_UNLOCK(sc); 550 if (first_pass) { 551 copyout(&tmparray2[segresid], ptr, 552 segsize - segresid); 553 first_pass = 0; 554 } else 555 copyout(tmparray2, ptr, segsize); 556 TI_LOCK(sc); 557 } else { 558 if (first_pass) { 559 560 ti_bcopy_swap(tmparray, tmparray2, 561 segsize, TI_SWAP_NTOH); 562 TI_UNLOCK(sc); 563 bcopy(&tmparray2[segresid], ptr, 564 segsize - segresid); 565 TI_LOCK(sc); 566 first_pass = 0; 567 } else 568 ti_bcopy_swap(tmparray, ptr, segsize, 569 TI_SWAP_NTOH); 570 } 571 572 } else { 573 if (useraddr) { 574 TI_UNLOCK(sc); 575 copyin(ptr, tmparray2, segsize); 576 TI_LOCK(sc); 577 ti_bcopy_swap(tmparray2, tmparray, segsize, 578 TI_SWAP_HTON); 579 } else 580 ti_bcopy_swap(ptr, tmparray, segsize, 581 TI_SWAP_HTON); 582 583 bus_space_write_region_4(sc->ti_btag, 584 sc->ti_bhandle, ti_offset, 585 (u_int32_t *)tmparray, 586 segsize >> 2); 587 } 588 segptr += segsize; 589 ptr += segsize; 590 cnt -= segsize; 591 } 592 593 /* 594 * Handle leftover, non-word-aligned bytes. 595 */ 596 if (resid != 0) { 597 u_int32_t tmpval, tmpval2; 598 bus_size_t ti_offset; 599 600 /* 601 * Set the segment pointer. 602 */ 603 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 604 605 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 606 607 /* 608 * First, grab whatever is in our source/destination. 609 * We'll obviously need this for reads, but also for 610 * writes, since we'll be doing read/modify/write. 611 */ 612 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 613 ti_offset, &tmpval, 1); 614 615 /* 616 * Next, translate this from little-endian to big-endian 617 * (at least on i386 boxes). 618 */ 619 tmpval2 = ntohl(tmpval); 620 621 if (readdata) { 622 /* 623 * If we're reading, just copy the leftover number 624 * of bytes from the host byte order buffer to 625 * the user's buffer. 626 */ 627 if (useraddr) { 628 TI_UNLOCK(sc); 629 copyout(&tmpval2, ptr, resid); 630 TI_LOCK(sc); 631 } else 632 bcopy(&tmpval2, ptr, resid); 633 } else { 634 /* 635 * If we're writing, first copy the bytes to be 636 * written into the network byte order buffer, 637 * leaving the rest of the buffer with whatever was 638 * originally in there. Then, swap the bytes 639 * around into host order and write them out. 640 * 641 * XXX KDM the read side of this has been verified 642 * to work, but the write side of it has not been 643 * verified. So user beware. 644 */ 645 if (useraddr) { 646 TI_UNLOCK(sc); 647 copyin(ptr, &tmpval2, resid); 648 TI_LOCK(sc); 649 } else 650 bcopy(ptr, &tmpval2, resid); 651 652 tmpval = htonl(tmpval2); 653 654 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 655 ti_offset, &tmpval, 1); 656 } 657 } 658 659 CSR_WRITE_4(sc, TI_WINBASE, origwin); 660 661 return (0); 662} 663 664static int 665ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 666 struct ti_softc *sc; 667 u_int32_t tigon_addr, len; 668 caddr_t buf; 669 int useraddr, readdata; 670 int cpu; 671{ 672 u_int32_t segptr; 673 int cnt; 674 u_int32_t tmpval, tmpval2; 675 caddr_t ptr; 676 677 /* 678 * At the moment, we don't handle non-aligned cases, we just bail. 679 * If this proves to be a problem, it will be fixed. 680 */ 681 if (tigon_addr & 0x3) { 682 if_printf(sc->ti_ifp, "ti_copy_scratch: tigon address %#x " 683 "isn't word-aligned\n", tigon_addr); 684 return (EINVAL); 685 } 686 687 if (len & 0x3) { 688 if_printf(sc->ti_ifp, "ti_copy_scratch: transfer length %d " 689 "isn't word-aligned\n", len); 690 return (EINVAL); 691 } 692 693 segptr = tigon_addr; 694 cnt = len; 695 ptr = buf; 696 697 while (cnt) { 698 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 699 700 if (readdata) { 701 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 702 703 tmpval = ntohl(tmpval2); 704 705 /* 706 * Note: I've used this debugging interface 707 * extensively with Alteon's 12.3.15 firmware, 708 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 709 * 710 * When you compile the firmware without 711 * optimization, which is necessary sometimes in 712 * order to properly step through it, you sometimes 713 * read out a bogus value of 0xc0017c instead of 714 * whatever was supposed to be in that scratchpad 715 * location. That value is on the stack somewhere, 716 * but I've never been able to figure out what was 717 * causing the problem. 718 * 719 * The address seems to pop up in random places, 720 * often not in the same place on two subsequent 721 * reads. 722 * 723 * In any case, the underlying data doesn't seem 724 * to be affected, just the value read out. 725 * 726 * KDM, 3/7/2000 727 */ 728 729 if (tmpval2 == 0xc0017c) 730 if_printf(sc->ti_ifp, "found 0xc0017c at %#x " 731 "(tmpval2)\n", segptr); 732 733 if (tmpval == 0xc0017c) 734 if_printf(sc->ti_ifp, "found 0xc0017c at %#x " 735 "(tmpval)\n", segptr); 736 737 if (useraddr) 738 copyout(&tmpval, ptr, 4); 739 else 740 bcopy(&tmpval, ptr, 4); 741 } else { 742 if (useraddr) 743 copyin(ptr, &tmpval2, 4); 744 else 745 bcopy(ptr, &tmpval2, 4); 746 747 tmpval = htonl(tmpval2); 748 749 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 750 } 751 752 cnt -= 4; 753 segptr += 4; 754 ptr += 4; 755 } 756 757 return (0); 758} 759 760static int 761ti_bcopy_swap(src, dst, len, swap_type) 762 const void *src; 763 void *dst; 764 size_t len; 765 ti_swap_type swap_type; 766{ 767 const u_int8_t *tmpsrc; 768 u_int8_t *tmpdst; 769 size_t tmplen; 770 771 if (len & 0x3) { 772 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 773 len); 774 return (-1); 775 } 776 777 tmpsrc = src; 778 tmpdst = dst; 779 tmplen = len; 780 781 while (tmplen) { 782 if (swap_type == TI_SWAP_NTOH) 783 *(u_int32_t *)tmpdst = 784 ntohl(*(const u_int32_t *)tmpsrc); 785 else 786 *(u_int32_t *)tmpdst = 787 htonl(*(const u_int32_t *)tmpsrc); 788 789 tmpsrc += 4; 790 tmpdst += 4; 791 tmplen -= 4; 792 } 793 794 return (0); 795} 796 797/* 798 * Load firmware image into the NIC. Check that the firmware revision 799 * is acceptable and see if we want the firmware for the Tigon 1 or 800 * Tigon 2. 801 */ 802static void 803ti_loadfw(sc) 804 struct ti_softc *sc; 805{ 806 switch (sc->ti_hwrev) { 807 case TI_HWREV_TIGON: 808 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 809 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 810 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 811 if_printf(sc->ti_ifp, "firmware revision mismatch; " 812 "want %d.%d.%d, got %d.%d.%d\n", 813 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 814 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 815 tigonFwReleaseMinor, tigonFwReleaseFix); 816 return; 817 } 818 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 819 (caddr_t)tigonFwText); 820 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 821 (caddr_t)tigonFwData); 822 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 823 (caddr_t)tigonFwRodata); 824 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 825 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 826 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 827 break; 828 case TI_HWREV_TIGON_II: 829 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 830 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 831 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 832 if_printf(sc->ti_ifp, "firmware revision mismatch; " 833 "want %d.%d.%d, got %d.%d.%d\n", 834 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 835 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 836 tigon2FwReleaseMinor, tigon2FwReleaseFix); 837 return; 838 } 839 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 840 (caddr_t)tigon2FwText); 841 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 842 (caddr_t)tigon2FwData); 843 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 844 (caddr_t)tigon2FwRodata); 845 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 846 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 847 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 848 break; 849 default: 850 if_printf(sc->ti_ifp, 851 "can't load firmware: unknown hardware rev\n"); 852 break; 853 } 854} 855 856/* 857 * Send the NIC a command via the command ring. 858 */ 859static void 860ti_cmd(sc, cmd) 861 struct ti_softc *sc; 862 struct ti_cmd_desc *cmd; 863{ 864 u_int32_t index; 865 866 if (sc->ti_rdata->ti_cmd_ring == NULL) 867 return; 868 869 index = sc->ti_cmd_saved_prodidx; 870 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 871 TI_INC(index, TI_CMD_RING_CNT); 872 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 873 sc->ti_cmd_saved_prodidx = index; 874} 875 876/* 877 * Send the NIC an extended command. The 'len' parameter specifies the 878 * number of command slots to include after the initial command. 879 */ 880static void 881ti_cmd_ext(sc, cmd, arg, len) 882 struct ti_softc *sc; 883 struct ti_cmd_desc *cmd; 884 caddr_t arg; 885 int len; 886{ 887 u_int32_t index; 888 register int i; 889 890 if (sc->ti_rdata->ti_cmd_ring == NULL) 891 return; 892 893 index = sc->ti_cmd_saved_prodidx; 894 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 895 TI_INC(index, TI_CMD_RING_CNT); 896 for (i = 0; i < len; i++) { 897 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 898 *(u_int32_t *)(&arg[i * 4])); 899 TI_INC(index, TI_CMD_RING_CNT); 900 } 901 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 902 sc->ti_cmd_saved_prodidx = index; 903} 904 905/* 906 * Handle events that have triggered interrupts. 907 */ 908static void 909ti_handle_events(sc) 910 struct ti_softc *sc; 911{ 912 struct ti_event_desc *e; 913 914 if (sc->ti_rdata->ti_event_ring == NULL) 915 return; 916 917 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 918 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 919 switch (e->ti_event) { 920 case TI_EV_LINKSTAT_CHANGED: 921 sc->ti_linkstat = e->ti_code; 922 if (e->ti_code == TI_EV_CODE_LINK_UP) 923 if_printf(sc->ti_ifp, "10/100 link up\n"); 924 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 925 if_printf(sc->ti_ifp, "gigabit link up\n"); 926 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 927 if_printf(sc->ti_ifp, "link down\n"); 928 break; 929 case TI_EV_ERROR: 930 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 931 if_printf(sc->ti_ifp, "invalid command\n"); 932 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 933 if_printf(sc->ti_ifp, "unknown command\n"); 934 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 935 if_printf(sc->ti_ifp, "bad config data\n"); 936 break; 937 case TI_EV_FIRMWARE_UP: 938 ti_init2(sc); 939 break; 940 case TI_EV_STATS_UPDATED: 941 ti_stats_update(sc); 942 break; 943 case TI_EV_RESET_JUMBO_RING: 944 case TI_EV_MCAST_UPDATED: 945 /* Who cares. */ 946 break; 947 default: 948 if_printf(sc->ti_ifp, "unknown event: %d\n", 949 e->ti_event); 950 break; 951 } 952 /* Advance the consumer index. */ 953 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 954 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 955 } 956} 957 958static int 959ti_alloc_dmamaps(struct ti_softc *sc) 960{ 961 int i; 962 963 for (i = 0; i < TI_TX_RING_CNT; i++) { 964 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 965 &sc->ti_cdata.ti_tx_maps[i])) 966 return (ENOBUFS); 967 } 968 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 969 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 970 &sc->ti_cdata.ti_rx_std_maps[i])) 971 return (ENOBUFS); 972 } 973 974 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 975 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 976 &sc->ti_cdata.ti_rx_jumbo_maps[i])) 977 return (ENOBUFS); 978 } 979 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 980 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 981 &sc->ti_cdata.ti_rx_mini_maps[i])) 982 return (ENOBUFS); 983 } 984 985 return (0); 986} 987 988static void 989ti_free_dmamaps(struct ti_softc *sc) 990{ 991 int i; 992 993 for (i = 0; i < TI_TX_RING_CNT; i++) 994 bus_dmamap_destroy(sc->ti_mbuftx_dmat, 995 sc->ti_cdata.ti_tx_maps[i]); 996 997 for (i = 0; i < TI_STD_RX_RING_CNT; i++) 998 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 999 sc->ti_cdata.ti_rx_std_maps[i]); 1000 1001 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1002 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1003 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1004 1005 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1006 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1007 sc->ti_cdata.ti_rx_mini_maps[i]); 1008} 1009 1010#ifdef TI_PRIVATE_JUMBOS 1011 1012/* 1013 * Memory management for the jumbo receive ring is a pain in the 1014 * butt. We need to allocate at least 9018 bytes of space per frame, 1015 * _and_ it has to be contiguous (unless you use the extended 1016 * jumbo descriptor format). Using malloc() all the time won't 1017 * work: malloc() allocates memory in powers of two, which means we 1018 * would end up wasting a considerable amount of space by allocating 1019 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 1020 * to do our own memory management. 1021 * 1022 * The driver needs to allocate a contiguous chunk of memory at boot 1023 * time. We then chop this up ourselves into 9K pieces and use them 1024 * as external mbuf storage. 1025 * 1026 * One issue here is how much memory to allocate. The jumbo ring has 1027 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1028 * RAM. This is a bit much, especially considering we also need 1029 * RAM for the standard ring and mini ring (on the Tigon 2). To 1030 * save space, we only actually allocate enough memory for 64 slots 1031 * by default, which works out to between 500 and 600K. This can 1032 * be tuned by changing a #define in if_tireg.h. 1033 */ 1034 1035static int 1036ti_alloc_jumbo_mem(sc) 1037 struct ti_softc *sc; 1038{ 1039 caddr_t ptr; 1040 register int i; 1041 struct ti_jpool_entry *entry; 1042 1043 /* 1044 * Grab a big chunk o' storage. Since we are chopping this pool up 1045 * into ~9k chunks, there doesn't appear to be a need to use page 1046 * alignment. 1047 */ 1048 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1049 1, 0, /* algnmnt, boundary */ 1050 BUS_SPACE_MAXADDR, /* lowaddr */ 1051 BUS_SPACE_MAXADDR, /* highaddr */ 1052 NULL, NULL, /* filter, filterarg */ 1053 TI_JMEM, /* maxsize */ 1054 1, /* nsegments */ 1055 TI_JMEM, /* maxsegsize */ 1056 0, /* flags */ 1057 NULL, NULL, /* lockfunc, lockarg */ 1058 &sc->ti_jumbo_dmat) != 0) { 1059 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1060 return (ENOBUFS); 1061 } 1062 1063 if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1064 (void**)&sc->ti_cdata.ti_jumbo_buf, 1065 BUS_DMA_NOWAIT, &sc->ti_jumbo_dmamap) != 0) { 1066 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1067 return (ENOBUFS); 1068 } 1069 1070 SLIST_INIT(&sc->ti_jfree_listhead); 1071 SLIST_INIT(&sc->ti_jinuse_listhead); 1072 1073 /* 1074 * Now divide it up into 9K pieces and save the addresses 1075 * in an array. 1076 */ 1077 ptr = sc->ti_cdata.ti_jumbo_buf; 1078 for (i = 0; i < TI_JSLOTS; i++) { 1079 sc->ti_cdata.ti_jslots[i] = ptr; 1080 ptr += TI_JLEN; 1081 entry = malloc(sizeof(struct ti_jpool_entry), 1082 M_DEVBUF, M_NOWAIT); 1083 if (entry == NULL) { 1084 device_printf(sc->ti_dev, "no memory for jumbo " 1085 "buffer queue!\n"); 1086 return (ENOBUFS); 1087 } 1088 entry->slot = i; 1089 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1090 } 1091 1092 return (0); 1093} 1094 1095/* 1096 * Allocate a jumbo buffer. 1097 */ 1098static void *ti_jalloc(sc) 1099 struct ti_softc *sc; 1100{ 1101 struct ti_jpool_entry *entry; 1102 1103 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1104 1105 if (entry == NULL) { 1106 if_printf(sc->ti_ifp, "no free jumbo buffers\n"); 1107 return (NULL); 1108 } 1109 1110 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1111 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1112 return (sc->ti_cdata.ti_jslots[entry->slot]); 1113} 1114 1115/* 1116 * Release a jumbo buffer. 1117 */ 1118static void 1119ti_jfree(buf, args) 1120 void *buf; 1121 void *args; 1122{ 1123 struct ti_softc *sc; 1124 int i; 1125 struct ti_jpool_entry *entry; 1126 1127 /* Extract the softc struct pointer. */ 1128 sc = (struct ti_softc *)args; 1129 1130 if (sc == NULL) 1131 panic("ti_jfree: didn't get softc pointer!"); 1132 1133 /* calculate the slot this buffer belongs to */ 1134 i = ((vm_offset_t)buf 1135 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1136 1137 if ((i < 0) || (i >= TI_JSLOTS)) 1138 panic("ti_jfree: asked to free buffer that we don't manage!"); 1139 1140 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1141 if (entry == NULL) 1142 panic("ti_jfree: buffer not in use!"); 1143 entry->slot = i; 1144 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1145 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1146} 1147 1148#else 1149 1150static int 1151ti_alloc_jumbo_mem(sc) 1152 struct ti_softc *sc; 1153{ 1154 1155 /* 1156 * The VM system will take care of providing aligned pages. Alignment 1157 * is set to 1 here so that busdma resources won't be wasted. 1158 */ 1159 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1160 1, 0, /* algnmnt, boundary */ 1161 BUS_SPACE_MAXADDR, /* lowaddr */ 1162 BUS_SPACE_MAXADDR, /* highaddr */ 1163 NULL, NULL, /* filter, filterarg */ 1164 PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1165 4, /* nsegments */ 1166 PAGE_SIZE, /* maxsegsize */ 1167 0, /* flags */ 1168 NULL, NULL, /* lockfunc, lockarg */ 1169 &sc->ti_jumbo_dmat) != 0) { 1170 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1171 return (ENOBUFS); 1172 } 1173 1174 return (0); 1175} 1176 1177#endif /* TI_PRIVATE_JUMBOS */ 1178 1179/* 1180 * Intialize a standard receive ring descriptor. 1181 */ 1182static int 1183ti_newbuf_std(sc, i, m) 1184 struct ti_softc *sc; 1185 int i; 1186 struct mbuf *m; 1187{ 1188 bus_dmamap_t map; 1189 bus_dma_segment_t segs; 1190 struct mbuf *m_new = NULL; 1191 struct ti_rx_desc *r; 1192 int nsegs; 1193 1194 nsegs = 0; 1195 if (m == NULL) { 1196 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1197 if (m_new == NULL) 1198 return (ENOBUFS); 1199 1200 MCLGET(m_new, M_DONTWAIT); 1201 if (!(m_new->m_flags & M_EXT)) { 1202 m_freem(m_new); 1203 return (ENOBUFS); 1204 } 1205 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1206 } else { 1207 m_new = m; 1208 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1209 m_new->m_data = m_new->m_ext.ext_buf; 1210 } 1211 1212 m_adj(m_new, ETHER_ALIGN); 1213 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1214 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1215 map = sc->ti_cdata.ti_rx_std_maps[i]; 1216 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1217 &nsegs, 0)) 1218 return (ENOBUFS); 1219 if (nsegs != 1) 1220 return (ENOBUFS); 1221 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1222 r->ti_len = segs.ds_len; 1223 r->ti_type = TI_BDTYPE_RECV_BD; 1224 r->ti_flags = 0; 1225 if (sc->ti_ifp->if_hwassist) 1226 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1227 r->ti_idx = i; 1228 1229 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1230 return (0); 1231} 1232 1233/* 1234 * Intialize a mini receive ring descriptor. This only applies to 1235 * the Tigon 2. 1236 */ 1237static int 1238ti_newbuf_mini(sc, i, m) 1239 struct ti_softc *sc; 1240 int i; 1241 struct mbuf *m; 1242{ 1243 bus_dma_segment_t segs; 1244 bus_dmamap_t map; 1245 struct mbuf *m_new = NULL; 1246 struct ti_rx_desc *r; 1247 int nsegs; 1248 1249 nsegs = 0; 1250 if (m == NULL) { 1251 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1252 if (m_new == NULL) { 1253 return (ENOBUFS); 1254 } 1255 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1256 } else { 1257 m_new = m; 1258 m_new->m_data = m_new->m_pktdat; 1259 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1260 } 1261 1262 m_adj(m_new, ETHER_ALIGN); 1263 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1264 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1265 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1266 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1267 &nsegs, 0)) 1268 return (ENOBUFS); 1269 if (nsegs != 1) 1270 return (ENOBUFS); 1271 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1272 r->ti_len = segs.ds_len; 1273 r->ti_type = TI_BDTYPE_RECV_BD; 1274 r->ti_flags = TI_BDFLAG_MINI_RING; 1275 if (sc->ti_ifp->if_hwassist) 1276 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1277 r->ti_idx = i; 1278 1279 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1280 return (0); 1281} 1282 1283#ifdef TI_PRIVATE_JUMBOS 1284 1285/* 1286 * Initialize a jumbo receive ring descriptor. This allocates 1287 * a jumbo buffer from the pool managed internally by the driver. 1288 */ 1289static int 1290ti_newbuf_jumbo(sc, i, m) 1291 struct ti_softc *sc; 1292 int i; 1293 struct mbuf *m; 1294{ 1295 bus_dmamap_t map; 1296 struct mbuf *m_new = NULL; 1297 struct ti_rx_desc *r; 1298 int nsegs; 1299 bus_dma_segment_t segs; 1300 1301 if (m == NULL) { 1302 caddr_t *buf = NULL; 1303 1304 /* Allocate the mbuf. */ 1305 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1306 if (m_new == NULL) { 1307 return (ENOBUFS); 1308 } 1309 1310 /* Allocate the jumbo buffer */ 1311 buf = ti_jalloc(sc); 1312 if (buf == NULL) { 1313 m_freem(m_new); 1314 if_printf(sc->ti_ifp, "jumbo allocation failed " 1315 "-- packet dropped!\n"); 1316 return (ENOBUFS); 1317 } 1318 1319 /* Attach the buffer to the mbuf. */ 1320 m_new->m_data = (void *) buf; 1321 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1322 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1323 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1324 } else { 1325 m_new = m; 1326 m_new->m_data = m_new->m_ext.ext_buf; 1327 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1328 } 1329 1330 m_adj(m_new, ETHER_ALIGN); 1331 /* Set up the descriptor. */ 1332 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1333 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1334 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1335 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1336 &nsegs, 0)) 1337 return (ENOBUFS); 1338 if (nsegs != 1) 1339 return (ENOBUFS); 1340 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1341 r->ti_len = segs.ds_len; 1342 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1343 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1344 if (sc->ti_ifp->if_hwassist) 1345 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1346 r->ti_idx = i; 1347 1348 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1349 return (0); 1350} 1351 1352#else 1353#include <vm/vm_page.h> 1354 1355#if (PAGE_SIZE == 4096) 1356#define NPAYLOAD 2 1357#else 1358#define NPAYLOAD 1 1359#endif 1360 1361#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1362#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1363#define NFS_HDR_LEN (UDP_HDR_LEN) 1364static int HDR_LEN = TCP_HDR_LEN; 1365 1366 1367/* 1368 * Initialize a jumbo receive ring descriptor. This allocates 1369 * a jumbo buffer from the pool managed internally by the driver. 1370 */ 1371static int 1372ti_newbuf_jumbo(sc, idx, m_old) 1373 struct ti_softc *sc; 1374 int idx; 1375 struct mbuf *m_old; 1376{ 1377 bus_dmamap_t map; 1378 struct mbuf *cur, *m_new = NULL; 1379 struct mbuf *m[3] = {NULL, NULL, NULL}; 1380 struct ti_rx_desc_ext *r; 1381 vm_page_t frame; 1382 static int color; 1383 /* 1 extra buf to make nobufs easy*/ 1384 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1385 int i; 1386 bus_dma_segment_t segs[4]; 1387 int nsegs; 1388 1389 if (m_old != NULL) { 1390 m_new = m_old; 1391 cur = m_old->m_next; 1392 for (i = 0; i <= NPAYLOAD; i++){ 1393 m[i] = cur; 1394 cur = cur->m_next; 1395 } 1396 } else { 1397 /* Allocate the mbufs. */ 1398 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1399 if (m_new == NULL) { 1400 if_printf(sc->ti_ifp, "mbuf allocation failed " 1401 "-- packet dropped!\n"); 1402 goto nobufs; 1403 } 1404 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1405 if (m[NPAYLOAD] == NULL) { 1406 if_printf(sc->ti_ifp, "cluster mbuf allocation failed " 1407 "-- packet dropped!\n"); 1408 goto nobufs; 1409 } 1410 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1411 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1412 if_printf(sc->ti_ifp, "mbuf allocation failed " 1413 "-- packet dropped!\n"); 1414 goto nobufs; 1415 } 1416 m[NPAYLOAD]->m_len = MCLBYTES; 1417 1418 for (i = 0; i < NPAYLOAD; i++){ 1419 MGET(m[i], M_DONTWAIT, MT_DATA); 1420 if (m[i] == NULL) { 1421 if_printf(sc->ti_ifp, "mbuf allocation failed " 1422 "-- packet dropped!\n"); 1423 goto nobufs; 1424 } 1425 frame = vm_page_alloc(NULL, color++, 1426 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1427 VM_ALLOC_WIRED); 1428 if (frame == NULL) { 1429 if_printf(sc->ti_ifp, "buffer allocation " 1430 "failed -- packet dropped!\n"); 1431 printf(" index %d page %d\n", idx, i); 1432 goto nobufs; 1433 } 1434 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1435 if (sf[i] == NULL) { 1436 vm_page_lock_queues(); 1437 vm_page_unwire(frame, 0); 1438 vm_page_free(frame); 1439 vm_page_unlock_queues(); 1440 if_printf(sc->ti_ifp, "buffer allocation " 1441 "failed -- packet dropped!\n"); 1442 printf(" index %d page %d\n", idx, i); 1443 goto nobufs; 1444 } 1445 } 1446 for (i = 0; i < NPAYLOAD; i++){ 1447 /* Attach the buffer to the mbuf. */ 1448 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1449 m[i]->m_len = PAGE_SIZE; 1450 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1451 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE); 1452 m[i]->m_next = m[i+1]; 1453 } 1454 /* link the buffers to the header */ 1455 m_new->m_next = m[0]; 1456 m_new->m_data += ETHER_ALIGN; 1457 if (sc->ti_hdrsplit) 1458 m_new->m_len = MHLEN - ETHER_ALIGN; 1459 else 1460 m_new->m_len = HDR_LEN; 1461 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1462 } 1463 1464 /* Set up the descriptor. */ 1465 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1466 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1467 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1468 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1469 &nsegs, 0)) 1470 return (ENOBUFS); 1471 if ((nsegs < 1) || (nsegs > 4)) 1472 return (ENOBUFS); 1473 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1474 r->ti_len0 = m_new->m_len; 1475 1476 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1477 r->ti_len1 = PAGE_SIZE; 1478 1479 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1480 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1481 1482 if (PAGE_SIZE == 4096) { 1483 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1484 r->ti_len3 = MCLBYTES; 1485 } else { 1486 r->ti_len3 = 0; 1487 } 1488 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1489 1490 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1491 1492 if (sc->ti_ifp->if_hwassist) 1493 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1494 1495 r->ti_idx = idx; 1496 1497 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1498 return (0); 1499 1500nobufs: 1501 1502 /* 1503 * Warning! : 1504 * This can only be called before the mbufs are strung together. 1505 * If the mbufs are strung together, m_freem() will free the chain, 1506 * so that the later mbufs will be freed multiple times. 1507 */ 1508 if (m_new) 1509 m_freem(m_new); 1510 1511 for (i = 0; i < 3; i++) { 1512 if (m[i]) 1513 m_freem(m[i]); 1514 if (sf[i]) 1515 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1516 } 1517 return (ENOBUFS); 1518} 1519#endif 1520 1521 1522 1523/* 1524 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1525 * that's 1MB or memory, which is a lot. For now, we fill only the first 1526 * 256 ring entries and hope that our CPU is fast enough to keep up with 1527 * the NIC. 1528 */ 1529static int 1530ti_init_rx_ring_std(sc) 1531 struct ti_softc *sc; 1532{ 1533 register int i; 1534 struct ti_cmd_desc cmd; 1535 1536 for (i = 0; i < TI_SSLOTS; i++) { 1537 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1538 return (ENOBUFS); 1539 }; 1540 1541 TI_UPDATE_STDPROD(sc, i - 1); 1542 sc->ti_std = i - 1; 1543 1544 return (0); 1545} 1546 1547static void 1548ti_free_rx_ring_std(sc) 1549 struct ti_softc *sc; 1550{ 1551 register int i; 1552 1553 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1554 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1555 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1556 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1557 } 1558 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1559 sizeof(struct ti_rx_desc)); 1560 } 1561} 1562 1563static int 1564ti_init_rx_ring_jumbo(sc) 1565 struct ti_softc *sc; 1566{ 1567 register int i; 1568 struct ti_cmd_desc cmd; 1569 1570 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1571 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1572 return (ENOBUFS); 1573 }; 1574 1575 TI_UPDATE_JUMBOPROD(sc, i - 1); 1576 sc->ti_jumbo = i - 1; 1577 1578 return (0); 1579} 1580 1581static void 1582ti_free_rx_ring_jumbo(sc) 1583 struct ti_softc *sc; 1584{ 1585 register int i; 1586 1587 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1588 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1589 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1590 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1591 } 1592 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1593 sizeof(struct ti_rx_desc)); 1594 } 1595} 1596 1597static int 1598ti_init_rx_ring_mini(sc) 1599 struct ti_softc *sc; 1600{ 1601 register int i; 1602 1603 for (i = 0; i < TI_MSLOTS; i++) { 1604 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1605 return (ENOBUFS); 1606 }; 1607 1608 TI_UPDATE_MINIPROD(sc, i - 1); 1609 sc->ti_mini = i - 1; 1610 1611 return (0); 1612} 1613 1614static void 1615ti_free_rx_ring_mini(sc) 1616 struct ti_softc *sc; 1617{ 1618 register int i; 1619 1620 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1621 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1622 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1623 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1624 } 1625 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1626 sizeof(struct ti_rx_desc)); 1627 } 1628} 1629 1630static void 1631ti_free_tx_ring(sc) 1632 struct ti_softc *sc; 1633{ 1634 register int i; 1635 1636 if (sc->ti_rdata->ti_tx_ring == NULL) 1637 return; 1638 1639 for (i = 0; i < TI_TX_RING_CNT; i++) { 1640 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1641 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1642 sc->ti_cdata.ti_tx_chain[i] = NULL; 1643 } 1644 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1645 sizeof(struct ti_tx_desc)); 1646 } 1647} 1648 1649static int 1650ti_init_tx_ring(sc) 1651 struct ti_softc *sc; 1652{ 1653 sc->ti_txcnt = 0; 1654 sc->ti_tx_saved_considx = 0; 1655 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1656 return (0); 1657} 1658 1659/* 1660 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1661 * but we have to support the old way too so that Tigon 1 cards will 1662 * work. 1663 */ 1664static void 1665ti_add_mcast(sc, addr) 1666 struct ti_softc *sc; 1667 struct ether_addr *addr; 1668{ 1669 struct ti_cmd_desc cmd; 1670 u_int16_t *m; 1671 u_int32_t ext[2] = {0, 0}; 1672 1673 m = (u_int16_t *)&addr->octet[0]; 1674 1675 switch (sc->ti_hwrev) { 1676 case TI_HWREV_TIGON: 1677 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1678 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1679 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1680 break; 1681 case TI_HWREV_TIGON_II: 1682 ext[0] = htons(m[0]); 1683 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1684 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1685 break; 1686 default: 1687 if_printf(sc->ti_ifp, "unknown hwrev\n"); 1688 break; 1689 } 1690} 1691 1692static void 1693ti_del_mcast(sc, addr) 1694 struct ti_softc *sc; 1695 struct ether_addr *addr; 1696{ 1697 struct ti_cmd_desc cmd; 1698 u_int16_t *m; 1699 u_int32_t ext[2] = {0, 0}; 1700 1701 m = (u_int16_t *)&addr->octet[0]; 1702 1703 switch (sc->ti_hwrev) { 1704 case TI_HWREV_TIGON: 1705 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1706 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1707 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1708 break; 1709 case TI_HWREV_TIGON_II: 1710 ext[0] = htons(m[0]); 1711 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1712 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1713 break; 1714 default: 1715 if_printf(sc->ti_ifp, "unknown hwrev\n"); 1716 break; 1717 } 1718} 1719 1720/* 1721 * Configure the Tigon's multicast address filter. 1722 * 1723 * The actual multicast table management is a bit of a pain, thanks to 1724 * slight brain damage on the part of both Alteon and us. With our 1725 * multicast code, we are only alerted when the multicast address table 1726 * changes and at that point we only have the current list of addresses: 1727 * we only know the current state, not the previous state, so we don't 1728 * actually know what addresses were removed or added. The firmware has 1729 * state, but we can't get our grubby mits on it, and there is no 'delete 1730 * all multicast addresses' command. Hence, we have to maintain our own 1731 * state so we know what addresses have been programmed into the NIC at 1732 * any given time. 1733 */ 1734static void 1735ti_setmulti(sc) 1736 struct ti_softc *sc; 1737{ 1738 struct ifnet *ifp; 1739 struct ifmultiaddr *ifma; 1740 struct ti_cmd_desc cmd; 1741 struct ti_mc_entry *mc; 1742 u_int32_t intrs; 1743 1744 ifp = sc->ti_ifp; 1745 1746 if (ifp->if_flags & IFF_ALLMULTI) { 1747 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1748 return; 1749 } else { 1750 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1751 } 1752 1753 /* Disable interrupts. */ 1754 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1755 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1756 1757 /* First, zot all the existing filters. */ 1758 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1759 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1760 ti_del_mcast(sc, &mc->mc_addr); 1761 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1762 free(mc, M_DEVBUF); 1763 } 1764 1765 /* Now program new ones. */ 1766 IF_ADDR_LOCK(ifp); 1767 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1768 if (ifma->ifma_addr->sa_family != AF_LINK) 1769 continue; 1770 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1771 if (mc == NULL) { 1772 if_printf(ifp, "no memory for mcast filter entry\n"); 1773 continue; 1774 } 1775 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1776 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1777 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1778 ti_add_mcast(sc, &mc->mc_addr); 1779 } 1780 IF_ADDR_UNLOCK(ifp); 1781 1782 /* Re-enable interrupts. */ 1783 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1784} 1785 1786/* 1787 * Check to see if the BIOS has configured us for a 64 bit slot when 1788 * we aren't actually in one. If we detect this condition, we can work 1789 * around it on the Tigon 2 by setting a bit in the PCI state register, 1790 * but for the Tigon 1 we must give up and abort the interface attach. 1791 */ 1792static int ti_64bitslot_war(sc) 1793 struct ti_softc *sc; 1794{ 1795 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1796 CSR_WRITE_4(sc, 0x600, 0); 1797 CSR_WRITE_4(sc, 0x604, 0); 1798 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1799 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1800 if (sc->ti_hwrev == TI_HWREV_TIGON) 1801 return (EINVAL); 1802 else { 1803 TI_SETBIT(sc, TI_PCI_STATE, 1804 TI_PCISTATE_32BIT_BUS); 1805 return (0); 1806 } 1807 } 1808 } 1809 1810 return (0); 1811} 1812 1813/* 1814 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1815 * self-test results. 1816 */ 1817static int 1818ti_chipinit(sc) 1819 struct ti_softc *sc; 1820{ 1821 u_int32_t cacheline; 1822 u_int32_t pci_writemax = 0; 1823 u_int32_t hdrsplit; 1824 1825 /* Initialize link to down state. */ 1826 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1827 1828 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1829 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 1830 else 1831 sc->ti_ifp->if_hwassist = 0; 1832 1833 /* Set endianness before we access any non-PCI registers. */ 1834#if BYTE_ORDER == BIG_ENDIAN 1835 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1836 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1837#else 1838 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1839 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1840#endif 1841 1842 /* Check the ROM failed bit to see if self-tests passed. */ 1843 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1844 if_printf(sc->ti_ifp, "board self-diagnostics failed!\n"); 1845 return (ENODEV); 1846 } 1847 1848 /* Halt the CPU. */ 1849 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1850 1851 /* Figure out the hardware revision. */ 1852 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1853 case TI_REV_TIGON_I: 1854 sc->ti_hwrev = TI_HWREV_TIGON; 1855 break; 1856 case TI_REV_TIGON_II: 1857 sc->ti_hwrev = TI_HWREV_TIGON_II; 1858 break; 1859 default: 1860 if_printf(sc->ti_ifp, "unsupported chip revision\n"); 1861 return (ENODEV); 1862 } 1863 1864 /* Do special setup for Tigon 2. */ 1865 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1866 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1867 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1868 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1869 } 1870 1871 /* 1872 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1873 * can't do header splitting. 1874 */ 1875#ifdef TI_JUMBO_HDRSPLIT 1876 if (sc->ti_hwrev != TI_HWREV_TIGON) 1877 sc->ti_hdrsplit = 1; 1878 else 1879 if_printf(sc->ti_ifp, 1880 "can't do header splitting on a Tigon I board\n"); 1881#endif /* TI_JUMBO_HDRSPLIT */ 1882 1883 /* Set up the PCI state register. */ 1884 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1885 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1886 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1887 } 1888 1889 /* Clear the read/write max DMA parameters. */ 1890 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1891 TI_PCISTATE_READ_MAXDMA)); 1892 1893 /* Get cache line size. */ 1894 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1895 1896 /* 1897 * If the system has set enabled the PCI memory write 1898 * and invalidate command in the command register, set 1899 * the write max parameter accordingly. This is necessary 1900 * to use MWI with the Tigon 2. 1901 */ 1902 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1903 switch (cacheline) { 1904 case 1: 1905 case 4: 1906 case 8: 1907 case 16: 1908 case 32: 1909 case 64: 1910 break; 1911 default: 1912 /* Disable PCI memory write and invalidate. */ 1913 if (bootverbose) 1914 if_printf(sc->ti_ifp, "cache line size %d not " 1915 "supported; disabling PCI MWI\n", 1916 cacheline); 1917 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1918 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1919 break; 1920 } 1921 } 1922 1923#ifdef __brokenalpha__ 1924 /* 1925 * From the Alteon sample driver: 1926 * Must insure that we do not cross an 8K (bytes) boundary 1927 * for DMA reads. Our highest limit is 1K bytes. This is a 1928 * restriction on some ALPHA platforms with early revision 1929 * 21174 PCI chipsets, such as the AlphaPC 164lx 1930 */ 1931 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1932#else 1933 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1934#endif 1935 1936 /* This sets the min dma param all the way up (0xff). */ 1937 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1938 1939 if (sc->ti_hdrsplit) 1940 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1941 else 1942 hdrsplit = 0; 1943 1944 /* Configure DMA variables. */ 1945#if BYTE_ORDER == BIG_ENDIAN 1946 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1947 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1948 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1949 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1950#else /* BYTE_ORDER */ 1951 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1952 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1953 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1954#endif /* BYTE_ORDER */ 1955 1956 /* 1957 * Only allow 1 DMA channel to be active at a time. 1958 * I don't think this is a good idea, but without it 1959 * the firmware racks up lots of nicDmaReadRingFull 1960 * errors. This is not compatible with hardware checksums. 1961 */ 1962 if (sc->ti_ifp->if_hwassist == 0) 1963 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1964 1965 /* Recommended settings from Tigon manual. */ 1966 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1967 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1968 1969 if (ti_64bitslot_war(sc)) { 1970 if_printf(sc->ti_ifp, "bios thinks we're in a 64 bit slot, " 1971 "but we aren't"); 1972 return (EINVAL); 1973 } 1974 1975 return (0); 1976} 1977 1978#define TI_RD_OFF(x) offsetof(struct ti_ring_data, x) 1979 1980/* 1981 * Initialize the general information block and firmware, and 1982 * start the CPU(s) running. 1983 */ 1984static int 1985ti_gibinit(sc) 1986 struct ti_softc *sc; 1987{ 1988 struct ti_rcb *rcb; 1989 int i; 1990 struct ifnet *ifp; 1991 uint32_t rdphys; 1992 1993 ifp = sc->ti_ifp; 1994 rdphys = sc->ti_rdata_phys; 1995 1996 /* Disable interrupts for now. */ 1997 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1998 1999 /* 2000 * Tell the chip where to find the general information block. 2001 * While this struct could go into >4GB memory, we allocate it in a 2002 * single slab with the other descriptors, and those don't seem to 2003 * support being located in a 64-bit region. 2004 */ 2005 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2006 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 2007 2008 /* Load the firmware into SRAM. */ 2009 ti_loadfw(sc); 2010 2011 /* Set up the contents of the general info and ring control blocks. */ 2012 2013 /* Set up the event ring and producer pointer. */ 2014 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 2015 2016 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 2017 rcb->ti_flags = 0; 2018 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2019 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 2020 sc->ti_ev_prodidx.ti_idx = 0; 2021 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2022 sc->ti_ev_saved_considx = 0; 2023 2024 /* Set up the command ring and producer mailbox. */ 2025 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 2026 2027 sc->ti_rdata->ti_cmd_ring = 2028 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 2029 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 2030 rcb->ti_flags = 0; 2031 rcb->ti_max_len = 0; 2032 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2033 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2034 } 2035 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2036 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2037 sc->ti_cmd_saved_prodidx = 0; 2038 2039 /* 2040 * Assign the address of the stats refresh buffer. 2041 * We re-use the current stats buffer for this to 2042 * conserve memory. 2043 */ 2044 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2045 rdphys + TI_RD_OFF(ti_info.ti_stats); 2046 2047 /* Set up the standard receive ring. */ 2048 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2049 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 2050 rcb->ti_max_len = TI_FRAMELEN; 2051 rcb->ti_flags = 0; 2052 if (sc->ti_ifp->if_hwassist) 2053 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2054 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2055 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2056 2057 /* Set up the jumbo receive ring. */ 2058 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2059 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 2060 2061#ifdef TI_PRIVATE_JUMBOS 2062 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 2063 rcb->ti_flags = 0; 2064#else 2065 rcb->ti_max_len = PAGE_SIZE; 2066 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2067#endif 2068 if (sc->ti_ifp->if_hwassist) 2069 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2070 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2071 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2072 2073 /* 2074 * Set up the mini ring. Only activated on the 2075 * Tigon 2 but the slot in the config block is 2076 * still there on the Tigon 1. 2077 */ 2078 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2079 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 2080 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2081 if (sc->ti_hwrev == TI_HWREV_TIGON) 2082 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2083 else 2084 rcb->ti_flags = 0; 2085 if (sc->ti_ifp->if_hwassist) 2086 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2087 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2088 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2089 2090 /* 2091 * Set up the receive return ring. 2092 */ 2093 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2094 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 2095 rcb->ti_flags = 0; 2096 rcb->ti_max_len = TI_RETURN_RING_CNT; 2097 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2098 rdphys + TI_RD_OFF(ti_return_prodidx_r); 2099 2100 /* 2101 * Set up the tx ring. Note: for the Tigon 2, we have the option 2102 * of putting the transmit ring in the host's address space and 2103 * letting the chip DMA it instead of leaving the ring in the NIC's 2104 * memory and accessing it through the shared memory region. We 2105 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2106 * so we have to revert to the shared memory scheme if we detect 2107 * a Tigon 1 chip. 2108 */ 2109 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2110 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2111 sc->ti_rdata->ti_tx_ring_nic = 2112 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 2113 } 2114 bzero((char *)sc->ti_rdata->ti_tx_ring, 2115 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2116 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2117 if (sc->ti_hwrev == TI_HWREV_TIGON) 2118 rcb->ti_flags = 0; 2119 else 2120 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2121 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2122 if (sc->ti_ifp->if_hwassist) 2123 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2124 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2125 rcb->ti_max_len = TI_TX_RING_CNT; 2126 if (sc->ti_hwrev == TI_HWREV_TIGON) 2127 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2128 else 2129 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 2130 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2131 rdphys + TI_RD_OFF(ti_tx_considx_r); 2132 2133 /* Set up tuneables */ 2134#if 0 2135 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2136 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2137 (sc->ti_rx_coal_ticks / 10)); 2138 else 2139#endif 2140 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2141 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2142 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2143 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2144 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2145 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2146 2147 /* Turn interrupts on. */ 2148 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2149 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2150 2151 /* Start CPU. */ 2152 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2153 2154 return (0); 2155} 2156 2157static void 2158ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2159{ 2160 struct ti_softc *sc; 2161 2162 sc = arg; 2163 if (error || nseg != 1) 2164 return; 2165 2166 /* 2167 * All of the Tigon data structures need to live at <4GB. This 2168 * cast is fine since busdma was told about this constraint. 2169 */ 2170 sc->ti_rdata_phys = (uint32_t)segs[0].ds_addr; 2171 return; 2172} 2173 2174/* 2175 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2176 * against our list and return its name if we find a match. 2177 */ 2178static int 2179ti_probe(dev) 2180 device_t dev; 2181{ 2182 struct ti_type *t; 2183 2184 t = ti_devs; 2185 2186 while (t->ti_name != NULL) { 2187 if ((pci_get_vendor(dev) == t->ti_vid) && 2188 (pci_get_device(dev) == t->ti_did)) { 2189 device_set_desc(dev, t->ti_name); 2190 return (BUS_PROBE_DEFAULT); 2191 } 2192 t++; 2193 } 2194 2195 return (ENXIO); 2196} 2197 2198static int 2199ti_attach(dev) 2200 device_t dev; 2201{ 2202 struct ifnet *ifp; 2203 struct ti_softc *sc; 2204 int error = 0, rid; 2205 u_char eaddr[6]; 2206 2207 sc = device_get_softc(dev); 2208 sc->ti_unit = device_get_unit(dev); 2209 sc->ti_dev = dev; 2210 2211 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2212 MTX_DEF | MTX_RECURSE); 2213 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2214 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2215 if (ifp == NULL) { 2216 device_printf(dev, "can not if_alloc()\n"); 2217 error = ENOSPC; 2218 goto fail; 2219 } 2220 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2221 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2222 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2223 2224 /* 2225 * Map control/status registers. 2226 */ 2227 pci_enable_busmaster(dev); 2228 2229 rid = TI_PCI_LOMEM; 2230 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2231 RF_ACTIVE|PCI_RF_DENSE); 2232 2233 if (sc->ti_res == NULL) { 2234 device_printf(dev, "couldn't map memory\n"); 2235 error = ENXIO; 2236 goto fail; 2237 } 2238 2239 sc->ti_btag = rman_get_bustag(sc->ti_res); 2240 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2241 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2242 2243 /* Allocate interrupt */ 2244 rid = 0; 2245 2246 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2247 RF_SHAREABLE | RF_ACTIVE); 2248 2249 if (sc->ti_irq == NULL) { 2250 device_printf(dev, "couldn't map interrupt\n"); 2251 error = ENXIO; 2252 goto fail; 2253 } 2254 2255 if (ti_chipinit(sc)) { 2256 device_printf(dev, "chip initialization failed\n"); 2257 error = ENXIO; 2258 goto fail; 2259 } 2260 2261 /* Zero out the NIC's on-board SRAM. */ 2262 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2263 2264 /* Init again -- zeroing memory may have clobbered some registers. */ 2265 if (ti_chipinit(sc)) { 2266 device_printf(dev, "chip initialization failed\n"); 2267 error = ENXIO; 2268 goto fail; 2269 } 2270 2271 /* 2272 * Get station address from the EEPROM. Note: the manual states 2273 * that the MAC address is at offset 0x8c, however the data is 2274 * stored as two longwords (since that's how it's loaded into 2275 * the NIC). This means the MAC address is actually preceded 2276 * by two zero bytes. We need to skip over those. 2277 */ 2278 if (ti_read_eeprom(sc, eaddr, 2279 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2280 device_printf(dev, "failed to read station address\n"); 2281 error = ENXIO; 2282 goto fail; 2283 } 2284 2285 /* Allocate the general information block and ring buffers. */ 2286 if (bus_dma_tag_create(NULL, /* parent */ 2287 1, 0, /* algnmnt, boundary */ 2288 BUS_SPACE_MAXADDR, /* lowaddr */ 2289 BUS_SPACE_MAXADDR, /* highaddr */ 2290 NULL, NULL, /* filter, filterarg */ 2291 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2292 0, /* nsegments */ 2293 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2294 0, /* flags */ 2295 NULL, NULL, /* lockfunc, lockarg */ 2296 &sc->ti_parent_dmat) != 0) { 2297 device_printf(dev, "Failed to allocate parent dmat\n"); 2298 error = ENOMEM; 2299 goto fail; 2300 } 2301 2302 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2303 PAGE_SIZE, 0, /* algnmnt, boundary */ 2304 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2305 BUS_SPACE_MAXADDR, /* highaddr */ 2306 NULL, NULL, /* filter, filterarg */ 2307 sizeof(struct ti_ring_data), /* maxsize */ 2308 1, /* nsegments */ 2309 sizeof(struct ti_ring_data), /* maxsegsize */ 2310 0, /* flags */ 2311 NULL, NULL, /* lockfunc, lockarg */ 2312 &sc->ti_rdata_dmat) != 0) { 2313 device_printf(dev, "Failed to allocate rdata dmat\n"); 2314 error = ENOMEM; 2315 goto fail; 2316 } 2317 2318 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2319 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) { 2320 device_printf(dev, "Failed to allocate rdata memory\n"); 2321 error = ENOMEM; 2322 goto fail; 2323 } 2324 2325 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2326 sc->ti_rdata, sizeof(struct ti_ring_data), 2327 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2328 device_printf(dev, "Failed to load rdata segments\n"); 2329 error = ENOMEM; 2330 goto fail; 2331 } 2332 2333 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2334 2335 /* Try to allocate memory for jumbo buffers. */ 2336 if (ti_alloc_jumbo_mem(sc)) { 2337 device_printf(dev, "jumbo buffer allocation failed\n"); 2338 error = ENXIO; 2339 goto fail; 2340 } 2341 2342 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2343 1, 0, /* algnmnt, boundary */ 2344 BUS_SPACE_MAXADDR, /* lowaddr */ 2345 BUS_SPACE_MAXADDR, /* highaddr */ 2346 NULL, NULL, /* filter, filterarg */ 2347 MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2348 TI_MAXTXSEGS, /* nsegments */ 2349 MCLBYTES, /* maxsegsize */ 2350 0, /* flags */ 2351 NULL, NULL, /* lockfunc, lockarg */ 2352 &sc->ti_mbuftx_dmat) != 0) { 2353 device_printf(dev, "Failed to allocate rdata dmat\n"); 2354 error = ENOMEM; 2355 goto fail; 2356 } 2357 2358 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2359 1, 0, /* algnmnt, boundary */ 2360 BUS_SPACE_MAXADDR, /* lowaddr */ 2361 BUS_SPACE_MAXADDR, /* highaddr */ 2362 NULL, NULL, /* filter, filterarg */ 2363 MCLBYTES, /* maxsize */ 2364 1, /* nsegments */ 2365 MCLBYTES, /* maxsegsize */ 2366 0, /* flags */ 2367 NULL, NULL, /* lockfunc, lockarg */ 2368 &sc->ti_mbufrx_dmat) != 0) { 2369 device_printf(dev, "Failed to allocate rdata dmat\n"); 2370 error = ENOMEM; 2371 goto fail; 2372 } 2373 2374 if (ti_alloc_dmamaps(sc)) { 2375 device_printf(dev, "dma map creation failed\n"); 2376 error = ENXIO; 2377 goto fail; 2378 } 2379 2380 /* 2381 * We really need a better way to tell a 1000baseTX card 2382 * from a 1000baseSX one, since in theory there could be 2383 * OEMed 1000baseTX cards from lame vendors who aren't 2384 * clever enough to change the PCI ID. For the moment 2385 * though, the AceNIC is the only copper card available. 2386 */ 2387 if (pci_get_vendor(dev) == ALT_VENDORID && 2388 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2389 sc->ti_copper = 1; 2390 /* Ok, it's not the only copper card available. */ 2391 if (pci_get_vendor(dev) == NG_VENDORID && 2392 pci_get_device(dev) == NG_DEVICEID_GA620T) 2393 sc->ti_copper = 1; 2394 2395 /* Set default tuneable values. */ 2396 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2397#if 0 2398 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2399#endif 2400 sc->ti_rx_coal_ticks = 170; 2401 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2402 sc->ti_rx_max_coal_bds = 64; 2403#if 0 2404 sc->ti_tx_max_coal_bds = 128; 2405#endif 2406 sc->ti_tx_max_coal_bds = 32; 2407 sc->ti_tx_buf_ratio = 21; 2408 2409 /* Set up ifnet structure */ 2410 ifp->if_softc = sc; 2411 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2412 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2413 tis[sc->ti_unit] = sc; 2414 ifp->if_ioctl = ti_ioctl; 2415 ifp->if_start = ti_start; 2416 ifp->if_watchdog = ti_watchdog; 2417 ifp->if_init = ti_init; 2418 ifp->if_mtu = ETHERMTU; 2419 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2420 2421 /* Set up ifmedia support. */ 2422 if (sc->ti_copper) { 2423 /* 2424 * Copper cards allow manual 10/100 mode selection, 2425 * but not manual 1000baseTX mode selection. Why? 2426 * Becuase currently there's no way to specify the 2427 * master/slave setting through the firmware interface, 2428 * so Alteon decided to just bag it and handle it 2429 * via autonegotiation. 2430 */ 2431 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2432 ifmedia_add(&sc->ifmedia, 2433 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2434 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2435 ifmedia_add(&sc->ifmedia, 2436 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2437 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2438 ifmedia_add(&sc->ifmedia, 2439 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2440 } else { 2441 /* Fiber cards don't support 10/100 modes. */ 2442 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2443 ifmedia_add(&sc->ifmedia, 2444 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2445 } 2446 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2447 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2448 2449 /* 2450 * We're assuming here that card initialization is a sequential 2451 * thing. If it isn't, multiple cards probing at the same time 2452 * could stomp on the list of softcs here. 2453 */ 2454 2455 /* Register the device */ 2456 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2457 0600, "ti%d", sc->ti_unit); 2458 sc->dev->si_drv1 = sc; 2459 2460 /* 2461 * Call MI attach routine. 2462 */ 2463 ether_ifattach(ifp, eaddr); 2464 2465 /* Hook interrupt last to avoid having to lock softc */ 2466 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2467 ti_intr, sc, &sc->ti_intrhand); 2468 2469 if (error) { 2470 device_printf(dev, "couldn't set up irq\n"); 2471 ether_ifdetach(ifp); 2472 goto fail; 2473 } 2474 2475fail: 2476 if (sc && error) 2477 ti_detach(dev); 2478 2479 return (error); 2480} 2481 2482/* 2483 * Shutdown hardware and free up resources. This can be called any 2484 * time after the mutex has been initialized. It is called in both 2485 * the error case in attach and the normal detach case so it needs 2486 * to be careful about only freeing resources that have actually been 2487 * allocated. 2488 */ 2489static int 2490ti_detach(dev) 2491 device_t dev; 2492{ 2493 struct ti_softc *sc; 2494 struct ifnet *ifp; 2495 2496 sc = device_get_softc(dev); 2497 if (sc->dev) 2498 destroy_dev(sc->dev); 2499 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2500 TI_LOCK(sc); 2501 ifp = sc->ti_ifp; 2502 2503 /* These should only be active if attach succeeded */ 2504 if (device_is_attached(dev)) { 2505 ti_stop(sc); 2506 ether_ifdetach(ifp); 2507 bus_generic_detach(dev); 2508 ti_free_dmamaps(sc); 2509 } 2510 ifmedia_removeall(&sc->ifmedia); 2511 2512#ifdef TI_PRIVATE_JUMBOS 2513 if (sc->ti_cdata.ti_jumbo_buf) 2514 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2515 sc->ti_jumbo_dmamap); 2516#endif 2517 if (sc->ti_jumbo_dmat) 2518 bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2519 if (sc->ti_mbuftx_dmat) 2520 bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2521 if (sc->ti_mbufrx_dmat) 2522 bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2523 if (sc->ti_rdata) 2524 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2525 sc->ti_rdata_dmamap); 2526 if (sc->ti_rdata_dmat) 2527 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2528 if (sc->ti_parent_dmat) 2529 bus_dma_tag_destroy(sc->ti_parent_dmat); 2530 if (sc->ti_intrhand) 2531 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2532 if (sc->ti_irq) 2533 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2534 if (sc->ti_res) { 2535 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2536 sc->ti_res); 2537 } 2538 if (ifp) 2539 if_free(ifp); 2540 2541 TI_UNLOCK(sc); 2542 mtx_destroy(&sc->ti_mtx); 2543 2544 return (0); 2545} 2546 2547#ifdef TI_JUMBO_HDRSPLIT 2548/* 2549 * If hdr_len is 0, that means that header splitting wasn't done on 2550 * this packet for some reason. The two most likely reasons are that 2551 * the protocol isn't a supported protocol for splitting, or this 2552 * packet had a fragment offset that wasn't 0. 2553 * 2554 * The header length, if it is non-zero, will always be the length of 2555 * the headers on the packet, but that length could be longer than the 2556 * first mbuf. So we take the minimum of the two as the actual 2557 * length. 2558 */ 2559static __inline void 2560ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2561{ 2562 int i = 0; 2563 int lengths[4] = {0, 0, 0, 0}; 2564 struct mbuf *m, *mp; 2565 2566 if (hdr_len != 0) 2567 top->m_len = min(hdr_len, top->m_len); 2568 pkt_len -= top->m_len; 2569 lengths[i++] = top->m_len; 2570 2571 mp = top; 2572 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2573 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2574 pkt_len -= m->m_len; 2575 lengths[i++] = m->m_len; 2576 mp = m; 2577 } 2578 2579#if 0 2580 if (hdr_len != 0) 2581 printf("got split packet: "); 2582 else 2583 printf("got non-split packet: "); 2584 2585 printf("%d,%d,%d,%d = %d\n", lengths[0], 2586 lengths[1], lengths[2], lengths[3], 2587 lengths[0] + lengths[1] + lengths[2] + 2588 lengths[3]); 2589#endif 2590 2591 if (pkt_len) 2592 panic("header splitting didn't"); 2593 2594 if (m) { 2595 m_freem(m); 2596 mp->m_next = NULL; 2597 2598 } 2599 if (mp->m_next != NULL) 2600 panic("ti_hdr_split: last mbuf in chain should be null"); 2601} 2602#endif /* TI_JUMBO_HDRSPLIT */ 2603 2604/* 2605 * Frame reception handling. This is called if there's a frame 2606 * on the receive return list. 2607 * 2608 * Note: we have to be able to handle three possibilities here: 2609 * 1) the frame is from the mini receive ring (can only happen) 2610 * on Tigon 2 boards) 2611 * 2) the frame is from the jumbo recieve ring 2612 * 3) the frame is from the standard receive ring 2613 */ 2614 2615static void 2616ti_rxeof(sc) 2617 struct ti_softc *sc; 2618{ 2619 bus_dmamap_t map; 2620 struct ifnet *ifp; 2621 struct ti_cmd_desc cmd; 2622 2623 TI_LOCK_ASSERT(sc); 2624 2625 ifp = sc->ti_ifp; 2626 2627 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2628 struct ti_rx_desc *cur_rx; 2629 u_int32_t rxidx; 2630 struct mbuf *m = NULL; 2631 u_int16_t vlan_tag = 0; 2632 int have_tag = 0; 2633 2634 cur_rx = 2635 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2636 rxidx = cur_rx->ti_idx; 2637 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2638 2639 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2640 have_tag = 1; 2641 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2642 } 2643 2644 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2645 2646 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2647 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2648 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2649 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2650 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2651 BUS_DMASYNC_POSTREAD); 2652 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 2653 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2654 ifp->if_ierrors++; 2655 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2656 continue; 2657 } 2658 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2659 ifp->if_ierrors++; 2660 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2661 continue; 2662 } 2663#ifdef TI_PRIVATE_JUMBOS 2664 m->m_len = cur_rx->ti_len; 2665#else /* TI_PRIVATE_JUMBOS */ 2666#ifdef TI_JUMBO_HDRSPLIT 2667 if (sc->ti_hdrsplit) 2668 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2669 cur_rx->ti_len, rxidx); 2670 else 2671#endif /* TI_JUMBO_HDRSPLIT */ 2672 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2673#endif /* TI_PRIVATE_JUMBOS */ 2674 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2675 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2676 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2677 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2678 map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2679 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2680 BUS_DMASYNC_POSTREAD); 2681 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2682 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2683 ifp->if_ierrors++; 2684 ti_newbuf_mini(sc, sc->ti_mini, m); 2685 continue; 2686 } 2687 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2688 ifp->if_ierrors++; 2689 ti_newbuf_mini(sc, sc->ti_mini, m); 2690 continue; 2691 } 2692 m->m_len = cur_rx->ti_len; 2693 } else { 2694 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2695 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2696 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2697 map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2698 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2699 BUS_DMASYNC_POSTREAD); 2700 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2701 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2702 ifp->if_ierrors++; 2703 ti_newbuf_std(sc, sc->ti_std, m); 2704 continue; 2705 } 2706 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2707 ifp->if_ierrors++; 2708 ti_newbuf_std(sc, sc->ti_std, m); 2709 continue; 2710 } 2711 m->m_len = cur_rx->ti_len; 2712 } 2713 2714 m->m_pkthdr.len = cur_rx->ti_len; 2715 ifp->if_ipackets++; 2716 m->m_pkthdr.rcvif = ifp; 2717 2718 if (ifp->if_hwassist) { 2719 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2720 CSUM_DATA_VALID; 2721 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2722 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2723 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2724 } 2725 2726 /* 2727 * If we received a packet with a vlan tag, 2728 * tag it before passing the packet upward. 2729 */ 2730 if (have_tag) 2731 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2732 TI_UNLOCK(sc); 2733 (*ifp->if_input)(ifp, m); 2734 TI_LOCK(sc); 2735 } 2736 2737 /* Only necessary on the Tigon 1. */ 2738 if (sc->ti_hwrev == TI_HWREV_TIGON) 2739 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2740 sc->ti_rx_saved_considx); 2741 2742 TI_UPDATE_STDPROD(sc, sc->ti_std); 2743 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2744 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2745} 2746 2747static void 2748ti_txeof(sc) 2749 struct ti_softc *sc; 2750{ 2751 struct ti_tx_desc *cur_tx = NULL; 2752 struct ifnet *ifp; 2753 bus_dmamap_t map; 2754 2755 ifp = sc->ti_ifp; 2756 2757 /* 2758 * Go through our tx ring and free mbufs for those 2759 * frames that have been sent. 2760 */ 2761 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2762 u_int32_t idx = 0; 2763 2764 idx = sc->ti_tx_saved_considx; 2765 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2766 if (idx > 383) 2767 CSR_WRITE_4(sc, TI_WINBASE, 2768 TI_TX_RING_BASE + 6144); 2769 else if (idx > 255) 2770 CSR_WRITE_4(sc, TI_WINBASE, 2771 TI_TX_RING_BASE + 4096); 2772 else if (idx > 127) 2773 CSR_WRITE_4(sc, TI_WINBASE, 2774 TI_TX_RING_BASE + 2048); 2775 else 2776 CSR_WRITE_4(sc, TI_WINBASE, 2777 TI_TX_RING_BASE); 2778 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2779 } else 2780 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2781 if (cur_tx->ti_flags & TI_BDFLAG_END) 2782 ifp->if_opackets++; 2783 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2784 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2785 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2786 map = sc->ti_cdata.ti_tx_maps[idx]; 2787 bus_dmamap_sync(sc->ti_mbuftx_dmat, map, 2788 BUS_DMASYNC_POSTWRITE); 2789 bus_dmamap_unload(sc->ti_mbuftx_dmat, map); 2790 } 2791 sc->ti_txcnt--; 2792 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2793 ifp->if_timer = 0; 2794 } 2795 2796 if (cur_tx != NULL) 2797 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2798} 2799 2800static void 2801ti_intr(xsc) 2802 void *xsc; 2803{ 2804 struct ti_softc *sc; 2805 struct ifnet *ifp; 2806 2807 sc = xsc; 2808 TI_LOCK(sc); 2809 ifp = sc->ti_ifp; 2810 2811/*#ifdef notdef*/ 2812 /* Avoid this for now -- checking this register is expensive. */ 2813 /* Make sure this is really our interrupt. */ 2814 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2815 TI_UNLOCK(sc); 2816 return; 2817 } 2818/*#endif*/ 2819 2820 /* Ack interrupt and stop others from occuring. */ 2821 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2822 2823 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2824 /* Check RX return ring producer/consumer */ 2825 ti_rxeof(sc); 2826 2827 /* Check TX ring producer/consumer */ 2828 ti_txeof(sc); 2829 } 2830 2831 ti_handle_events(sc); 2832 2833 /* Re-enable interrupts. */ 2834 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2835 2836 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2837 ifp->if_snd.ifq_head != NULL) 2838 ti_start(ifp); 2839 2840 TI_UNLOCK(sc); 2841} 2842 2843static void 2844ti_stats_update(sc) 2845 struct ti_softc *sc; 2846{ 2847 struct ifnet *ifp; 2848 2849 ifp = sc->ti_ifp; 2850 2851 ifp->if_collisions += 2852 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2853 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2854 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2855 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2856 ifp->if_collisions; 2857} 2858 2859struct ti_dmamap_arg { 2860 struct ti_softc *sc; 2861 struct m_tag *mtag; 2862 struct mbuf *m_head; 2863 u_int16_t csum_flags; 2864 int idx; 2865}; 2866 2867static void 2868ti_encap_cb(arg, segs, nseg, mapsize, error) 2869 void *arg; 2870 bus_dma_segment_t *segs; 2871 int nseg; 2872 bus_size_t mapsize; 2873 int error; 2874{ 2875 struct ti_softc *sc; 2876 struct ti_dmamap_arg *ctx; 2877 struct ti_tx_desc *f = NULL; 2878 struct m_tag *mtag; 2879 u_int32_t frag, cur, cnt = 0; 2880 u_int16_t csum_flags; 2881 2882 if (error) 2883 return; 2884 2885 ctx = (struct ti_dmamap_arg *)arg; 2886 sc = ctx->sc; 2887 cur = frag = ctx->idx; 2888 mtag = ctx->mtag; 2889 csum_flags = ctx->csum_flags; 2890 2891 /* 2892 * Start packing the mbufs in this chain into 2893 * the fragment pointers. Stop when we run out 2894 * of fragments or hit the end of the mbuf chain. 2895 */ 2896 while (nseg-- > 0) { 2897 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2898 if (frag > 383) 2899 CSR_WRITE_4(sc, TI_WINBASE, 2900 TI_TX_RING_BASE + 6144); 2901 else if (frag > 255) 2902 CSR_WRITE_4(sc, TI_WINBASE, 2903 TI_TX_RING_BASE + 4096); 2904 else if (frag > 127) 2905 CSR_WRITE_4(sc, TI_WINBASE, 2906 TI_TX_RING_BASE + 2048); 2907 else 2908 CSR_WRITE_4(sc, TI_WINBASE, 2909 TI_TX_RING_BASE); 2910 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2911 } else 2912 f = &sc->ti_rdata->ti_tx_ring[frag]; 2913 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2914 break; 2915 ti_hostaddr64(&f->ti_addr, segs[cnt].ds_addr); 2916 f->ti_len = segs[cnt].ds_len; 2917 f->ti_flags = csum_flags; 2918 2919 if (mtag != NULL) { 2920 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2921 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2922 } else { 2923 f->ti_vlan_tag = 0; 2924 } 2925 2926 cur = frag; 2927 TI_INC(frag, TI_TX_RING_CNT); 2928 cnt++; 2929 } 2930 2931 if (sc->ti_hwrev == TI_HWREV_TIGON) 2932 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2933 TI_BDFLAG_END; 2934 else 2935 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2936 sc->ti_cdata.ti_tx_chain[cur] = ctx->m_head; 2937 sc->ti_txcnt += cnt; 2938 2939 ctx->idx = frag; 2940 2941} 2942 2943/* 2944 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2945 * pointers to descriptors. 2946 */ 2947static int 2948ti_encap(sc, m_head, txidx) 2949 struct ti_softc *sc; 2950 struct mbuf *m_head; 2951 u_int32_t *txidx; 2952{ 2953 bus_dmamap_t map; 2954 struct ti_dmamap_arg ctx; 2955 u_int32_t frag, cnt;; 2956 u_int16_t csum_flags = 0; 2957 int error; 2958 2959 frag = *txidx; 2960 2961 if (m_head->m_pkthdr.csum_flags) { 2962 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2963 csum_flags |= TI_BDFLAG_IP_CKSUM; 2964 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2965 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2966 if (m_head->m_flags & M_LASTFRAG) 2967 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2968 else if (m_head->m_flags & M_FRAG) 2969 csum_flags |= TI_BDFLAG_IP_FRAG; 2970 } 2971 2972 ctx.sc = sc; 2973 ctx.idx = frag; 2974 ctx.csum_flags = csum_flags; 2975 ctx.mtag = VLAN_OUTPUT_TAG(sc->ti_ifp, m_head); 2976 ctx.m_head = m_head; 2977 2978 map = sc->ti_cdata.ti_tx_maps[frag]; 2979 error = bus_dmamap_load_mbuf(sc->ti_mbuftx_dmat, map, m_head, 2980 ti_encap_cb, &ctx, 0); 2981 if (error) 2982 return (ENOBUFS); 2983 2984 cnt = ctx.idx - frag; 2985 frag = ctx.idx; 2986 2987 /* 2988 * Sanity check: avoid coming within 16 descriptors 2989 * of the end of the ring. 2990 */ 2991 if (((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) || 2992 (frag == sc->ti_tx_saved_considx)) { 2993 bus_dmamap_unload(sc->ti_mbuftx_dmat, map); 2994 return (ENOBUFS); 2995 } 2996 2997 bus_dmamap_sync(sc->ti_mbuftx_dmat, map, BUS_DMASYNC_PREWRITE); 2998 *txidx = frag; 2999 return (0); 3000} 3001 3002/* 3003 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3004 * to the mbuf data regions directly in the transmit descriptors. 3005 */ 3006static void 3007ti_start(ifp) 3008 struct ifnet *ifp; 3009{ 3010 struct ti_softc *sc; 3011 struct mbuf *m_head = NULL; 3012 u_int32_t prodidx = 0; 3013 3014 sc = ifp->if_softc; 3015 TI_LOCK(sc); 3016 3017 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 3018 3019 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 3020 IF_DEQUEUE(&ifp->if_snd, m_head); 3021 if (m_head == NULL) 3022 break; 3023 3024 /* 3025 * XXX 3026 * safety overkill. If this is a fragmented packet chain 3027 * with delayed TCP/UDP checksums, then only encapsulate 3028 * it if we have enough descriptors to handle the entire 3029 * chain at once. 3030 * (paranoia -- may not actually be needed) 3031 */ 3032 if (m_head->m_flags & M_FIRSTFRAG && 3033 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3034 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3035 m_head->m_pkthdr.csum_data + 16) { 3036 IF_PREPEND(&ifp->if_snd, m_head); 3037 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3038 break; 3039 } 3040 } 3041 3042 /* 3043 * Pack the data into the transmit ring. If we 3044 * don't have room, set the OACTIVE flag and wait 3045 * for the NIC to drain the ring. 3046 */ 3047 if (ti_encap(sc, m_head, &prodidx)) { 3048 IF_PREPEND(&ifp->if_snd, m_head); 3049 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3050 break; 3051 } 3052 3053 /* 3054 * If there's a BPF listener, bounce a copy of this frame 3055 * to him. 3056 */ 3057 BPF_MTAP(ifp, m_head); 3058 } 3059 3060 /* Transmit */ 3061 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 3062 3063 /* 3064 * Set a timeout in case the chip goes out to lunch. 3065 */ 3066 ifp->if_timer = 5; 3067 TI_UNLOCK(sc); 3068} 3069 3070static void 3071ti_init(xsc) 3072 void *xsc; 3073{ 3074 struct ti_softc *sc = xsc; 3075 3076 /* Cancel pending I/O and flush buffers. */ 3077 ti_stop(sc); 3078 3079 TI_LOCK(sc); 3080 /* Init the gen info block, ring control blocks and firmware. */ 3081 if (ti_gibinit(sc)) { 3082 if_printf(sc->ti_ifp, "initialization failure\n"); 3083 TI_UNLOCK(sc); 3084 return; 3085 } 3086 3087 TI_UNLOCK(sc); 3088} 3089 3090static void ti_init2(sc) 3091 struct ti_softc *sc; 3092{ 3093 struct ti_cmd_desc cmd; 3094 struct ifnet *ifp; 3095 u_int16_t *m; 3096 struct ifmedia *ifm; 3097 int tmp; 3098 3099 ifp = sc->ti_ifp; 3100 3101 /* Specify MTU and interface index. */ 3102 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 3103 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3104 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3105 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3106 3107 /* Load our MAC address. */ 3108 m = (u_int16_t *)IF_LLADDR(sc->ti_ifp); 3109 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 3110 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 3111 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3112 3113 /* Enable or disable promiscuous mode as needed. */ 3114 if (ifp->if_flags & IFF_PROMISC) { 3115 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3116 } else { 3117 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3118 } 3119 3120 /* Program multicast filter. */ 3121 ti_setmulti(sc); 3122 3123 /* 3124 * If this is a Tigon 1, we should tell the 3125 * firmware to use software packet filtering. 3126 */ 3127 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3128 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3129 } 3130 3131 /* Init RX ring. */ 3132 ti_init_rx_ring_std(sc); 3133 3134 /* Init jumbo RX ring. */ 3135 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3136 ti_init_rx_ring_jumbo(sc); 3137 3138 /* 3139 * If this is a Tigon 2, we can also configure the 3140 * mini ring. 3141 */ 3142 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 3143 ti_init_rx_ring_mini(sc); 3144 3145 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3146 sc->ti_rx_saved_considx = 0; 3147 3148 /* Init TX ring. */ 3149 ti_init_tx_ring(sc); 3150 3151 /* Tell firmware we're alive. */ 3152 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3153 3154 /* Enable host interrupts. */ 3155 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3156 3157 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3158 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3159 3160 /* 3161 * Make sure to set media properly. We have to do this 3162 * here since we have to issue commands in order to set 3163 * the link negotiation and we can't issue commands until 3164 * the firmware is running. 3165 */ 3166 ifm = &sc->ifmedia; 3167 tmp = ifm->ifm_media; 3168 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3169 ti_ifmedia_upd(ifp); 3170 ifm->ifm_media = tmp; 3171} 3172 3173/* 3174 * Set media options. 3175 */ 3176static int 3177ti_ifmedia_upd(ifp) 3178 struct ifnet *ifp; 3179{ 3180 struct ti_softc *sc; 3181 struct ifmedia *ifm; 3182 struct ti_cmd_desc cmd; 3183 u_int32_t flowctl; 3184 3185 sc = ifp->if_softc; 3186 ifm = &sc->ifmedia; 3187 3188 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3189 return (EINVAL); 3190 3191 flowctl = 0; 3192 3193 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3194 case IFM_AUTO: 3195 /* 3196 * Transmit flow control doesn't work on the Tigon 1. 3197 */ 3198 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3199 3200 /* 3201 * Transmit flow control can also cause problems on the 3202 * Tigon 2, apparantly with both the copper and fiber 3203 * boards. The symptom is that the interface will just 3204 * hang. This was reproduced with Alteon 180 switches. 3205 */ 3206#if 0 3207 if (sc->ti_hwrev != TI_HWREV_TIGON) 3208 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3209#endif 3210 3211 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3212 TI_GLNK_FULL_DUPLEX| flowctl | 3213 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3214 3215 flowctl = TI_LNK_RX_FLOWCTL_Y; 3216#if 0 3217 if (sc->ti_hwrev != TI_HWREV_TIGON) 3218 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3219#endif 3220 3221 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3222 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3223 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3224 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3225 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3226 break; 3227 case IFM_1000_SX: 3228 case IFM_1000_T: 3229 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3230#if 0 3231 if (sc->ti_hwrev != TI_HWREV_TIGON) 3232 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3233#endif 3234 3235 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3236 flowctl |TI_GLNK_ENB); 3237 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3238 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3239 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3240 } 3241 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3242 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3243 break; 3244 case IFM_100_FX: 3245 case IFM_10_FL: 3246 case IFM_100_TX: 3247 case IFM_10_T: 3248 flowctl = TI_LNK_RX_FLOWCTL_Y; 3249#if 0 3250 if (sc->ti_hwrev != TI_HWREV_TIGON) 3251 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3252#endif 3253 3254 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3255 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3256 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3257 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3258 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3259 } else { 3260 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3261 } 3262 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3263 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3264 } else { 3265 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3266 } 3267 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3268 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3269 break; 3270 } 3271 3272 return (0); 3273} 3274 3275/* 3276 * Report current media status. 3277 */ 3278static void 3279ti_ifmedia_sts(ifp, ifmr) 3280 struct ifnet *ifp; 3281 struct ifmediareq *ifmr; 3282{ 3283 struct ti_softc *sc; 3284 u_int32_t media = 0; 3285 3286 sc = ifp->if_softc; 3287 3288 ifmr->ifm_status = IFM_AVALID; 3289 ifmr->ifm_active = IFM_ETHER; 3290 3291 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3292 return; 3293 3294 ifmr->ifm_status |= IFM_ACTIVE; 3295 3296 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3297 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3298 if (sc->ti_copper) 3299 ifmr->ifm_active |= IFM_1000_T; 3300 else 3301 ifmr->ifm_active |= IFM_1000_SX; 3302 if (media & TI_GLNK_FULL_DUPLEX) 3303 ifmr->ifm_active |= IFM_FDX; 3304 else 3305 ifmr->ifm_active |= IFM_HDX; 3306 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3307 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3308 if (sc->ti_copper) { 3309 if (media & TI_LNK_100MB) 3310 ifmr->ifm_active |= IFM_100_TX; 3311 if (media & TI_LNK_10MB) 3312 ifmr->ifm_active |= IFM_10_T; 3313 } else { 3314 if (media & TI_LNK_100MB) 3315 ifmr->ifm_active |= IFM_100_FX; 3316 if (media & TI_LNK_10MB) 3317 ifmr->ifm_active |= IFM_10_FL; 3318 } 3319 if (media & TI_LNK_FULL_DUPLEX) 3320 ifmr->ifm_active |= IFM_FDX; 3321 if (media & TI_LNK_HALF_DUPLEX) 3322 ifmr->ifm_active |= IFM_HDX; 3323 } 3324} 3325 3326static int 3327ti_ioctl(ifp, command, data) 3328 struct ifnet *ifp; 3329 u_long command; 3330 caddr_t data; 3331{ 3332 struct ti_softc *sc = ifp->if_softc; 3333 struct ifreq *ifr = (struct ifreq *) data; 3334 int mask, error = 0; 3335 struct ti_cmd_desc cmd; 3336 3337 TI_LOCK(sc); 3338 3339 switch (command) { 3340 case SIOCSIFMTU: 3341 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3342 error = EINVAL; 3343 else { 3344 ifp->if_mtu = ifr->ifr_mtu; 3345 ti_init(sc); 3346 } 3347 break; 3348 case SIOCSIFFLAGS: 3349 if (ifp->if_flags & IFF_UP) { 3350 /* 3351 * If only the state of the PROMISC flag changed, 3352 * then just use the 'set promisc mode' command 3353 * instead of reinitializing the entire NIC. Doing 3354 * a full re-init means reloading the firmware and 3355 * waiting for it to start up, which may take a 3356 * second or two. 3357 */ 3358 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3359 ifp->if_flags & IFF_PROMISC && 3360 !(sc->ti_if_flags & IFF_PROMISC)) { 3361 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3362 TI_CMD_CODE_PROMISC_ENB, 0); 3363 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3364 !(ifp->if_flags & IFF_PROMISC) && 3365 sc->ti_if_flags & IFF_PROMISC) { 3366 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3367 TI_CMD_CODE_PROMISC_DIS, 0); 3368 } else 3369 ti_init(sc); 3370 } else { 3371 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3372 ti_stop(sc); 3373 } 3374 } 3375 sc->ti_if_flags = ifp->if_flags; 3376 error = 0; 3377 break; 3378 case SIOCADDMULTI: 3379 case SIOCDELMULTI: 3380 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3381 ti_setmulti(sc); 3382 error = 0; 3383 } 3384 break; 3385 case SIOCSIFMEDIA: 3386 case SIOCGIFMEDIA: 3387 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3388 break; 3389 case SIOCSIFCAP: 3390 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3391 if (mask & IFCAP_HWCSUM) { 3392 if (IFCAP_HWCSUM & ifp->if_capenable) 3393 ifp->if_capenable &= ~IFCAP_HWCSUM; 3394 else 3395 ifp->if_capenable |= IFCAP_HWCSUM; 3396 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3397 ti_init(sc); 3398 } 3399 error = 0; 3400 break; 3401 default: 3402 error = ether_ioctl(ifp, command, data); 3403 break; 3404 } 3405 3406 TI_UNLOCK(sc); 3407 3408 return (error); 3409} 3410 3411static int 3412ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3413{ 3414 struct ti_softc *sc; 3415 3416 sc = dev->si_drv1; 3417 if (sc == NULL) 3418 return (ENODEV); 3419 3420 TI_LOCK(sc); 3421 sc->ti_flags |= TI_FLAG_DEBUGING; 3422 TI_UNLOCK(sc); 3423 3424 return (0); 3425} 3426 3427static int 3428ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3429{ 3430 struct ti_softc *sc; 3431 3432 sc = dev->si_drv1; 3433 if (sc == NULL) 3434 return (ENODEV); 3435 3436 TI_LOCK(sc); 3437 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3438 TI_UNLOCK(sc); 3439 3440 return (0); 3441} 3442 3443/* 3444 * This ioctl routine goes along with the Tigon character device. 3445 */ 3446static int 3447ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3448 struct thread *td) 3449{ 3450 int error; 3451 struct ti_softc *sc; 3452 3453 sc = dev->si_drv1; 3454 if (sc == NULL) 3455 return (ENODEV); 3456 3457 error = 0; 3458 3459 switch (cmd) { 3460 case TIIOCGETSTATS: 3461 { 3462 struct ti_stats *outstats; 3463 3464 outstats = (struct ti_stats *)addr; 3465 3466 TI_LOCK(sc); 3467 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3468 sizeof(struct ti_stats)); 3469 TI_UNLOCK(sc); 3470 break; 3471 } 3472 case TIIOCGETPARAMS: 3473 { 3474 struct ti_params *params; 3475 3476 params = (struct ti_params *)addr; 3477 3478 TI_LOCK(sc); 3479 params->ti_stat_ticks = sc->ti_stat_ticks; 3480 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3481 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3482 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3483 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3484 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3485 params->param_mask = TI_PARAM_ALL; 3486 TI_UNLOCK(sc); 3487 3488 error = 0; 3489 3490 break; 3491 } 3492 case TIIOCSETPARAMS: 3493 { 3494 struct ti_params *params; 3495 3496 params = (struct ti_params *)addr; 3497 3498 TI_LOCK(sc); 3499 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3500 sc->ti_stat_ticks = params->ti_stat_ticks; 3501 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3502 } 3503 3504 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3505 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3506 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3507 sc->ti_rx_coal_ticks); 3508 } 3509 3510 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3511 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3512 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3513 sc->ti_tx_coal_ticks); 3514 } 3515 3516 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3517 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3518 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3519 sc->ti_rx_max_coal_bds); 3520 } 3521 3522 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3523 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3524 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3525 sc->ti_tx_max_coal_bds); 3526 } 3527 3528 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3529 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3530 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3531 sc->ti_tx_buf_ratio); 3532 } 3533 TI_UNLOCK(sc); 3534 3535 error = 0; 3536 3537 break; 3538 } 3539 case TIIOCSETTRACE: { 3540 ti_trace_type trace_type; 3541 3542 trace_type = *(ti_trace_type *)addr; 3543 3544 /* 3545 * Set tracing to whatever the user asked for. Setting 3546 * this register to 0 should have the effect of disabling 3547 * tracing. 3548 */ 3549 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3550 3551 error = 0; 3552 3553 break; 3554 } 3555 case TIIOCGETTRACE: { 3556 struct ti_trace_buf *trace_buf; 3557 u_int32_t trace_start, cur_trace_ptr, trace_len; 3558 3559 trace_buf = (struct ti_trace_buf *)addr; 3560 3561 TI_LOCK(sc); 3562 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3563 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3564 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3565 3566#if 0 3567 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3568 "trace_len = %d\n", trace_start, 3569 cur_trace_ptr, trace_len); 3570 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3571 trace_buf->buf_len); 3572#endif 3573 3574 error = ti_copy_mem(sc, trace_start, min(trace_len, 3575 trace_buf->buf_len), 3576 (caddr_t)trace_buf->buf, 1, 1); 3577 3578 if (error == 0) { 3579 trace_buf->fill_len = min(trace_len, 3580 trace_buf->buf_len); 3581 if (cur_trace_ptr < trace_start) 3582 trace_buf->cur_trace_ptr = 3583 trace_start - cur_trace_ptr; 3584 else 3585 trace_buf->cur_trace_ptr = 3586 cur_trace_ptr - trace_start; 3587 } else 3588 trace_buf->fill_len = 0; 3589 TI_UNLOCK(sc); 3590 3591 break; 3592 } 3593 3594 /* 3595 * For debugging, five ioctls are needed: 3596 * ALT_ATTACH 3597 * ALT_READ_TG_REG 3598 * ALT_WRITE_TG_REG 3599 * ALT_READ_TG_MEM 3600 * ALT_WRITE_TG_MEM 3601 */ 3602 case ALT_ATTACH: 3603 /* 3604 * From what I can tell, Alteon's Solaris Tigon driver 3605 * only has one character device, so you have to attach 3606 * to the Tigon board you're interested in. This seems 3607 * like a not-so-good way to do things, since unless you 3608 * subsequently specify the unit number of the device 3609 * you're interested in in every ioctl, you'll only be 3610 * able to debug one board at a time. 3611 */ 3612 error = 0; 3613 break; 3614 case ALT_READ_TG_MEM: 3615 case ALT_WRITE_TG_MEM: 3616 { 3617 struct tg_mem *mem_param; 3618 u_int32_t sram_end, scratch_end; 3619 3620 mem_param = (struct tg_mem *)addr; 3621 3622 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3623 sram_end = TI_END_SRAM_I; 3624 scratch_end = TI_END_SCRATCH_I; 3625 } else { 3626 sram_end = TI_END_SRAM_II; 3627 scratch_end = TI_END_SCRATCH_II; 3628 } 3629 3630 /* 3631 * For now, we'll only handle accessing regular SRAM, 3632 * nothing else. 3633 */ 3634 TI_LOCK(sc); 3635 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3636 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3637 /* 3638 * In this instance, we always copy to/from user 3639 * space, so the user space argument is set to 1. 3640 */ 3641 error = ti_copy_mem(sc, mem_param->tgAddr, 3642 mem_param->len, 3643 mem_param->userAddr, 1, 3644 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3645 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3646 && (mem_param->tgAddr <= scratch_end)) { 3647 error = ti_copy_scratch(sc, mem_param->tgAddr, 3648 mem_param->len, 3649 mem_param->userAddr, 1, 3650 (cmd == ALT_READ_TG_MEM) ? 3651 1 : 0, TI_PROCESSOR_A); 3652 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3653 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3654 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3655 if_printf(sc->ti_ifp, 3656 "invalid memory range for Tigon I\n"); 3657 error = EINVAL; 3658 break; 3659 } 3660 error = ti_copy_scratch(sc, mem_param->tgAddr - 3661 TI_SCRATCH_DEBUG_OFF, 3662 mem_param->len, 3663 mem_param->userAddr, 1, 3664 (cmd == ALT_READ_TG_MEM) ? 3665 1 : 0, TI_PROCESSOR_B); 3666 } else { 3667 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3668 "out of supported range\n", 3669 mem_param->tgAddr, mem_param->len); 3670 error = EINVAL; 3671 } 3672 TI_UNLOCK(sc); 3673 3674 break; 3675 } 3676 case ALT_READ_TG_REG: 3677 case ALT_WRITE_TG_REG: 3678 { 3679 struct tg_reg *regs; 3680 u_int32_t tmpval; 3681 3682 regs = (struct tg_reg *)addr; 3683 3684 /* 3685 * Make sure the address in question isn't out of range. 3686 */ 3687 if (regs->addr > TI_REG_MAX) { 3688 error = EINVAL; 3689 break; 3690 } 3691 TI_LOCK(sc); 3692 if (cmd == ALT_READ_TG_REG) { 3693 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3694 regs->addr, &tmpval, 1); 3695 regs->data = ntohl(tmpval); 3696#if 0 3697 if ((regs->addr == TI_CPU_STATE) 3698 || (regs->addr == TI_CPU_CTL_B)) { 3699 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3700 regs->addr, tmpval); 3701 } 3702#endif 3703 } else { 3704 tmpval = htonl(regs->data); 3705 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3706 regs->addr, &tmpval, 1); 3707 } 3708 TI_UNLOCK(sc); 3709 3710 break; 3711 } 3712 default: 3713 error = ENOTTY; 3714 break; 3715 } 3716 return (error); 3717} 3718 3719static void 3720ti_watchdog(ifp) 3721 struct ifnet *ifp; 3722{ 3723 struct ti_softc *sc; 3724 3725 sc = ifp->if_softc; 3726 TI_LOCK(sc); 3727 3728 /* 3729 * When we're debugging, the chip is often stopped for long periods 3730 * of time, and that would normally cause the watchdog timer to fire. 3731 * Since that impedes debugging, we don't want to do that. 3732 */ 3733 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3734 TI_UNLOCK(sc); 3735 return; 3736 } 3737 3738 if_printf(ifp, "watchdog timeout -- resetting\n"); 3739 ti_stop(sc); 3740 ti_init(sc); 3741 3742 ifp->if_oerrors++; 3743 TI_UNLOCK(sc); 3744} 3745 3746/* 3747 * Stop the adapter and free any mbufs allocated to the 3748 * RX and TX lists. 3749 */ 3750static void 3751ti_stop(sc) 3752 struct ti_softc *sc; 3753{ 3754 struct ifnet *ifp; 3755 struct ti_cmd_desc cmd; 3756 3757 TI_LOCK(sc); 3758 3759 ifp = sc->ti_ifp; 3760 3761 /* Disable host interrupts. */ 3762 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3763 /* 3764 * Tell firmware we're shutting down. 3765 */ 3766 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3767 3768 /* Halt and reinitialize. */ 3769 ti_chipinit(sc); 3770 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3771 ti_chipinit(sc); 3772 3773 /* Free the RX lists. */ 3774 ti_free_rx_ring_std(sc); 3775 3776 /* Free jumbo RX list. */ 3777 ti_free_rx_ring_jumbo(sc); 3778 3779 /* Free mini RX list. */ 3780 ti_free_rx_ring_mini(sc); 3781 3782 /* Free TX buffers. */ 3783 ti_free_tx_ring(sc); 3784 3785 sc->ti_ev_prodidx.ti_idx = 0; 3786 sc->ti_return_prodidx.ti_idx = 0; 3787 sc->ti_tx_considx.ti_idx = 0; 3788 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3789 3790 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3791 TI_UNLOCK(sc); 3792} 3793 3794/* 3795 * Stop all chip I/O so that the kernel's probe routines don't 3796 * get confused by errant DMAs when rebooting. 3797 */ 3798static void 3799ti_shutdown(dev) 3800 device_t dev; 3801{ 3802 struct ti_softc *sc; 3803 3804 sc = device_get_softc(dev); 3805 TI_LOCK(sc); 3806 ti_chipinit(sc); 3807 TI_UNLOCK(sc); 3808} 3809