if_ti.c revision 127135
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79#include <sys/cdefs.h> 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 127135 2004-03-17 17:50:55Z njl $"); 81 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/socket.h> 91#include <sys/queue.h> 92#include <sys/conf.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_types.h> 100#include <net/if_vlan_var.h> 101 102#include <net/bpf.h> 103 104#include <netinet/in_systm.h> 105#include <netinet/in.h> 106#include <netinet/ip.h> 107 108#include <vm/vm.h> /* for vtophys */ 109#include <vm/pmap.h> /* for vtophys */ 110#include <machine/bus_memio.h> 111#include <machine/bus.h> 112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> 115 116/* #define TI_PRIVATE_JUMBOS */ 117 118#if !defined(TI_PRIVATE_JUMBOS) 119#include <sys/sockio.h> 120#include <sys/uio.h> 121#include <sys/lock.h> 122#include <vm/vm_extern.h> 123#include <vm/pmap.h> 124#include <vm/vm_map.h> 125#include <vm/vm_map.h> 126#include <vm/vm_param.h> 127#include <vm/vm_pageout.h> 128#include <sys/vmmeter.h> 129#include <vm/vm_page.h> 130#include <vm/vm_object.h> 131#include <vm/vm_kern.h> 132#include <sys/proc.h> 133#include <sys/jumbo.h> 134#endif /* !TI_PRIVATE_JUMBOS */ 135 136#include <dev/pci/pcireg.h> 137#include <dev/pci/pcivar.h> 138 139#include <sys/tiio.h> 140#include <pci/if_tireg.h> 141#include <pci/ti_fw.h> 142#include <pci/ti_fw2.h> 143 144#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 145/* 146 * We can only turn on header splitting if we're using extended receive 147 * BDs. 148 */ 149#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 150#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 151#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 152 153struct ti_softc *tis[8]; 154 155typedef enum { 156 TI_SWAP_HTON, 157 TI_SWAP_NTOH 158} ti_swap_type; 159 160 161/* 162 * Various supported device vendors/types and their names. 163 */ 164 165static struct ti_type ti_devs[] = { 166 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 167 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 168 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 169 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 170 { TC_VENDORID, TC_DEVICEID_3C985, 171 "3Com 3c985-SX Gigabit Ethernet" }, 172 { NG_VENDORID, NG_DEVICEID_GA620, 173 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 174 { NG_VENDORID, NG_DEVICEID_GA620T, 175 "Netgear GA620 1000baseT Gigabit Ethernet" }, 176 { SGI_VENDORID, SGI_DEVICEID_TIGON, 177 "Silicon Graphics Gigabit Ethernet" }, 178 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 179 "Farallon PN9000SX Gigabit Ethernet" }, 180 { 0, 0, NULL } 181}; 182 183 184static d_open_t ti_open; 185static d_close_t ti_close; 186static d_ioctl_t ti_ioctl2; 187 188static struct cdevsw ti_cdevsw = { 189 .d_version = D_VERSION, 190 .d_flags = D_NEEDGIANT, 191 .d_open = ti_open, 192 .d_close = ti_close, 193 .d_ioctl = ti_ioctl2, 194 .d_name = "ti", 195}; 196 197static int ti_probe (device_t); 198static int ti_attach (device_t); 199static int ti_detach (device_t); 200static void ti_txeof (struct ti_softc *); 201static void ti_rxeof (struct ti_softc *); 202 203static void ti_stats_update (struct ti_softc *); 204static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 205 206static void ti_intr (void *); 207static void ti_start (struct ifnet *); 208static int ti_ioctl (struct ifnet *, u_long, caddr_t); 209static void ti_init (void *); 210static void ti_init2 (struct ti_softc *); 211static void ti_stop (struct ti_softc *); 212static void ti_watchdog (struct ifnet *); 213static void ti_shutdown (device_t); 214static int ti_ifmedia_upd (struct ifnet *); 215static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 216 217static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 218static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 219static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 220 221static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 222static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 223static void ti_setmulti (struct ti_softc *); 224 225static void ti_mem (struct ti_softc *, u_int32_t, 226 u_int32_t, caddr_t); 227static int ti_copy_mem (struct ti_softc *, u_int32_t, 228 u_int32_t, caddr_t, int, int); 229static int ti_copy_scratch (struct ti_softc *, u_int32_t, 230 u_int32_t, caddr_t, int, int, int); 231static int ti_bcopy_swap (const void *, void *, size_t, 232 ti_swap_type); 233static void ti_loadfw (struct ti_softc *); 234static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 235static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 236 caddr_t, int); 237static void ti_handle_events (struct ti_softc *); 238#ifdef TI_PRIVATE_JUMBOS 239static int ti_alloc_jumbo_mem (struct ti_softc *); 240static void *ti_jalloc (struct ti_softc *); 241static void ti_jfree (void *, void *); 242#endif /* TI_PRIVATE_JUMBOS */ 243static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 244static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 245static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 246static int ti_init_rx_ring_std (struct ti_softc *); 247static void ti_free_rx_ring_std (struct ti_softc *); 248static int ti_init_rx_ring_jumbo (struct ti_softc *); 249static void ti_free_rx_ring_jumbo (struct ti_softc *); 250static int ti_init_rx_ring_mini (struct ti_softc *); 251static void ti_free_rx_ring_mini (struct ti_softc *); 252static void ti_free_tx_ring (struct ti_softc *); 253static int ti_init_tx_ring (struct ti_softc *); 254 255static int ti_64bitslot_war (struct ti_softc *); 256static int ti_chipinit (struct ti_softc *); 257static int ti_gibinit (struct ti_softc *); 258 259#ifdef TI_JUMBO_HDRSPLIT 260static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 261 int pkt_len, int idx); 262#endif /* TI_JUMBO_HDRSPLIT */ 263 264static device_method_t ti_methods[] = { 265 /* Device interface */ 266 DEVMETHOD(device_probe, ti_probe), 267 DEVMETHOD(device_attach, ti_attach), 268 DEVMETHOD(device_detach, ti_detach), 269 DEVMETHOD(device_shutdown, ti_shutdown), 270 { 0, 0 } 271}; 272 273static driver_t ti_driver = { 274 "ti", 275 ti_methods, 276 sizeof(struct ti_softc) 277}; 278 279static devclass_t ti_devclass; 280 281DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 282MODULE_DEPEND(ti, pci, 1, 1, 1); 283MODULE_DEPEND(ti, ether, 1, 1, 1); 284 285/* 286 * Send an instruction or address to the EEPROM, check for ACK. 287 */ 288static u_int32_t ti_eeprom_putbyte(sc, byte) 289 struct ti_softc *sc; 290 int byte; 291{ 292 register int i, ack = 0; 293 294 /* 295 * Make sure we're in TX mode. 296 */ 297 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 298 299 /* 300 * Feed in each bit and stobe the clock. 301 */ 302 for (i = 0x80; i; i >>= 1) { 303 if (byte & i) { 304 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 305 } else { 306 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 307 } 308 DELAY(1); 309 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 DELAY(1); 311 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 312 } 313 314 /* 315 * Turn off TX mode. 316 */ 317 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 318 319 /* 320 * Check for ack. 321 */ 322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 323 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 324 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 325 326 return(ack); 327} 328 329/* 330 * Read a byte of data stored in the EEPROM at address 'addr.' 331 * We have to send two address bytes since the EEPROM can hold 332 * more than 256 bytes of data. 333 */ 334static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 335 struct ti_softc *sc; 336 int addr; 337 u_int8_t *dest; 338{ 339 register int i; 340 u_int8_t byte = 0; 341 342 EEPROM_START; 343 344 /* 345 * Send write control code to EEPROM. 346 */ 347 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 348 printf("ti%d: failed to send write command, status: %x\n", 349 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 350 return(1); 351 } 352 353 /* 354 * Send first byte of address of byte we want to read. 355 */ 356 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 357 printf("ti%d: failed to send address, status: %x\n", 358 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 359 return(1); 360 } 361 /* 362 * Send second byte address of byte we want to read. 363 */ 364 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 365 printf("ti%d: failed to send address, status: %x\n", 366 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 367 return(1); 368 } 369 370 EEPROM_STOP; 371 EEPROM_START; 372 /* 373 * Send read control code to EEPROM. 374 */ 375 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 376 printf("ti%d: failed to send read command, status: %x\n", 377 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 378 return(1); 379 } 380 381 /* 382 * Start reading bits from EEPROM. 383 */ 384 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 385 for (i = 0x80; i; i >>= 1) { 386 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 387 DELAY(1); 388 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 389 byte |= i; 390 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 391 DELAY(1); 392 } 393 394 EEPROM_STOP; 395 396 /* 397 * No ACK generated for read, so just return byte. 398 */ 399 400 *dest = byte; 401 402 return(0); 403} 404 405/* 406 * Read a sequence of bytes from the EEPROM. 407 */ 408static int 409ti_read_eeprom(sc, dest, off, cnt) 410 struct ti_softc *sc; 411 caddr_t dest; 412 int off; 413 int cnt; 414{ 415 int err = 0, i; 416 u_int8_t byte = 0; 417 418 for (i = 0; i < cnt; i++) { 419 err = ti_eeprom_getbyte(sc, off + i, &byte); 420 if (err) 421 break; 422 *(dest + i) = byte; 423 } 424 425 return(err ? 1 : 0); 426} 427 428/* 429 * NIC memory access function. Can be used to either clear a section 430 * of NIC local memory or (if buf is non-NULL) copy data into it. 431 */ 432static void 433ti_mem(sc, addr, len, buf) 434 struct ti_softc *sc; 435 u_int32_t addr, len; 436 caddr_t buf; 437{ 438 int segptr, segsize, cnt; 439 caddr_t ti_winbase, ptr; 440 441 segptr = addr; 442 cnt = len; 443 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 444 ptr = buf; 445 446 while(cnt) { 447 if (cnt < TI_WINLEN) 448 segsize = cnt; 449 else 450 segsize = TI_WINLEN - (segptr % TI_WINLEN); 451 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 452 if (buf == NULL) 453 bzero((char *)ti_winbase + (segptr & 454 (TI_WINLEN - 1)), segsize); 455 else { 456 bcopy((char *)ptr, (char *)ti_winbase + 457 (segptr & (TI_WINLEN - 1)), segsize); 458 ptr += segsize; 459 } 460 segptr += segsize; 461 cnt -= segsize; 462 } 463 464 return; 465} 466 467static int 468ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 469 struct ti_softc *sc; 470 u_int32_t tigon_addr, len; 471 caddr_t buf; 472 int useraddr, readdata; 473{ 474 int segptr, segsize, cnt; 475 caddr_t ptr; 476 u_int32_t origwin; 477 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 478 int resid, segresid; 479 int first_pass; 480 481 /* 482 * At the moment, we don't handle non-aligned cases, we just bail. 483 * If this proves to be a problem, it will be fixed. 484 */ 485 if ((readdata == 0) 486 && (tigon_addr & 0x3)) { 487 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 488 "word-aligned\n", sc->ti_unit, tigon_addr); 489 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 490 "supported\n", sc->ti_unit); 491 return(EINVAL); 492 } 493 494 segptr = tigon_addr & ~0x3; 495 segresid = tigon_addr - segptr; 496 497 /* 498 * This is the non-aligned amount left over that we'll need to 499 * copy. 500 */ 501 resid = len & 0x3; 502 503 /* Add in the left over amount at the front of the buffer */ 504 resid += segresid; 505 506 cnt = len & ~0x3; 507 /* 508 * If resid + segresid is >= 4, add multiples of 4 to the count and 509 * decrease the residual by that much. 510 */ 511 cnt += resid & ~0x3; 512 resid -= resid & ~0x3; 513 514 ptr = buf; 515 516 first_pass = 1; 517 518 /* 519 * Make sure we aren't interrupted while we're changing the window 520 * pointer. 521 */ 522 TI_LOCK(sc); 523 524 /* 525 * Save the old window base value. 526 */ 527 origwin = CSR_READ_4(sc, TI_WINBASE); 528 529 while(cnt) { 530 bus_size_t ti_offset; 531 532 if (cnt < TI_WINLEN) 533 segsize = cnt; 534 else 535 segsize = TI_WINLEN - (segptr % TI_WINLEN); 536 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 537 538 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 539 540 if (readdata) { 541 542 bus_space_read_region_4(sc->ti_btag, 543 sc->ti_bhandle, ti_offset, 544 (u_int32_t *)tmparray, 545 segsize >> 2); 546 if (useraddr) { 547 /* 548 * Yeah, this is a little on the kludgy 549 * side, but at least this code is only 550 * used for debugging. 551 */ 552 ti_bcopy_swap(tmparray, tmparray2, segsize, 553 TI_SWAP_NTOH); 554 555 if (first_pass) { 556 copyout(&tmparray2[segresid], ptr, 557 segsize - segresid); 558 first_pass = 0; 559 } else 560 copyout(tmparray2, ptr, segsize); 561 } else { 562 if (first_pass) { 563 564 ti_bcopy_swap(tmparray, tmparray2, 565 segsize, TI_SWAP_NTOH); 566 bcopy(&tmparray2[segresid], ptr, 567 segsize - segresid); 568 first_pass = 0; 569 } else 570 ti_bcopy_swap(tmparray, ptr, segsize, 571 TI_SWAP_NTOH); 572 } 573 574 } else { 575 if (useraddr) { 576 copyin(ptr, tmparray2, segsize); 577 ti_bcopy_swap(tmparray2, tmparray, segsize, 578 TI_SWAP_HTON); 579 } else 580 ti_bcopy_swap(ptr, tmparray, segsize, 581 TI_SWAP_HTON); 582 583 bus_space_write_region_4(sc->ti_btag, 584 sc->ti_bhandle, ti_offset, 585 (u_int32_t *)tmparray, 586 segsize >> 2); 587 } 588 segptr += segsize; 589 ptr += segsize; 590 cnt -= segsize; 591 } 592 593 /* 594 * Handle leftover, non-word-aligned bytes. 595 */ 596 if (resid != 0) { 597 u_int32_t tmpval, tmpval2; 598 bus_size_t ti_offset; 599 600 /* 601 * Set the segment pointer. 602 */ 603 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 604 605 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 606 607 /* 608 * First, grab whatever is in our source/destination. 609 * We'll obviously need this for reads, but also for 610 * writes, since we'll be doing read/modify/write. 611 */ 612 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 613 ti_offset, &tmpval, 1); 614 615 /* 616 * Next, translate this from little-endian to big-endian 617 * (at least on i386 boxes). 618 */ 619 tmpval2 = ntohl(tmpval); 620 621 if (readdata) { 622 /* 623 * If we're reading, just copy the leftover number 624 * of bytes from the host byte order buffer to 625 * the user's buffer. 626 */ 627 if (useraddr) 628 copyout(&tmpval2, ptr, resid); 629 else 630 bcopy(&tmpval2, ptr, resid); 631 } else { 632 /* 633 * If we're writing, first copy the bytes to be 634 * written into the network byte order buffer, 635 * leaving the rest of the buffer with whatever was 636 * originally in there. Then, swap the bytes 637 * around into host order and write them out. 638 * 639 * XXX KDM the read side of this has been verified 640 * to work, but the write side of it has not been 641 * verified. So user beware. 642 */ 643 if (useraddr) 644 copyin(ptr, &tmpval2, resid); 645 else 646 bcopy(ptr, &tmpval2, resid); 647 648 tmpval = htonl(tmpval2); 649 650 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 651 ti_offset, &tmpval, 1); 652 } 653 } 654 655 CSR_WRITE_4(sc, TI_WINBASE, origwin); 656 657 TI_UNLOCK(sc); 658 659 return(0); 660} 661 662static int 663ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 664 struct ti_softc *sc; 665 u_int32_t tigon_addr, len; 666 caddr_t buf; 667 int useraddr, readdata; 668 int cpu; 669{ 670 u_int32_t segptr; 671 int cnt; 672 u_int32_t tmpval, tmpval2; 673 caddr_t ptr; 674 675 /* 676 * At the moment, we don't handle non-aligned cases, we just bail. 677 * If this proves to be a problem, it will be fixed. 678 */ 679 if (tigon_addr & 0x3) { 680 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 681 "word-aligned\n", sc->ti_unit, tigon_addr); 682 return(EINVAL); 683 } 684 685 if (len & 0x3) { 686 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 687 "word-aligned\n", sc->ti_unit, len); 688 return(EINVAL); 689 } 690 691 segptr = tigon_addr; 692 cnt = len; 693 ptr = buf; 694 695 TI_LOCK(sc); 696 697 while (cnt) { 698 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 699 700 if (readdata) { 701 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 702 703 tmpval = ntohl(tmpval2); 704 705 /* 706 * Note: I've used this debugging interface 707 * extensively with Alteon's 12.3.15 firmware, 708 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 709 * 710 * When you compile the firmware without 711 * optimization, which is necessary sometimes in 712 * order to properly step through it, you sometimes 713 * read out a bogus value of 0xc0017c instead of 714 * whatever was supposed to be in that scratchpad 715 * location. That value is on the stack somewhere, 716 * but I've never been able to figure out what was 717 * causing the problem. 718 * 719 * The address seems to pop up in random places, 720 * often not in the same place on two subsequent 721 * reads. 722 * 723 * In any case, the underlying data doesn't seem 724 * to be affected, just the value read out. 725 * 726 * KDM, 3/7/2000 727 */ 728 729 if (tmpval2 == 0xc0017c) 730 printf("ti%d: found 0xc0017c at %#x " 731 "(tmpval2)\n", sc->ti_unit, segptr); 732 733 if (tmpval == 0xc0017c) 734 printf("ti%d: found 0xc0017c at %#x " 735 "(tmpval)\n", sc->ti_unit, segptr); 736 737 if (useraddr) 738 copyout(&tmpval, ptr, 4); 739 else 740 bcopy(&tmpval, ptr, 4); 741 } else { 742 if (useraddr) 743 copyin(ptr, &tmpval2, 4); 744 else 745 bcopy(ptr, &tmpval2, 4); 746 747 tmpval = htonl(tmpval2); 748 749 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 750 } 751 752 cnt -= 4; 753 segptr += 4; 754 ptr += 4; 755 } 756 757 TI_UNLOCK(sc); 758 759 return(0); 760} 761 762static int 763ti_bcopy_swap(src, dst, len, swap_type) 764 const void *src; 765 void *dst; 766 size_t len; 767 ti_swap_type swap_type; 768{ 769 const u_int8_t *tmpsrc; 770 u_int8_t *tmpdst; 771 size_t tmplen; 772 773 if (len & 0x3) { 774 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 775 len); 776 return(-1); 777 } 778 779 tmpsrc = src; 780 tmpdst = dst; 781 tmplen = len; 782 783 while (tmplen) { 784 if (swap_type == TI_SWAP_NTOH) 785 *(u_int32_t *)tmpdst = 786 ntohl(*(const u_int32_t *)tmpsrc); 787 else 788 *(u_int32_t *)tmpdst = 789 htonl(*(const u_int32_t *)tmpsrc); 790 791 tmpsrc += 4; 792 tmpdst += 4; 793 tmplen -= 4; 794 } 795 796 return(0); 797} 798 799/* 800 * Load firmware image into the NIC. Check that the firmware revision 801 * is acceptable and see if we want the firmware for the Tigon 1 or 802 * Tigon 2. 803 */ 804static void 805ti_loadfw(sc) 806 struct ti_softc *sc; 807{ 808 switch(sc->ti_hwrev) { 809 case TI_HWREV_TIGON: 810 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 811 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 812 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 813 printf("ti%d: firmware revision mismatch; want " 814 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 815 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 816 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 817 tigonFwReleaseMinor, tigonFwReleaseFix); 818 return; 819 } 820 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 821 (caddr_t)tigonFwText); 822 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 823 (caddr_t)tigonFwData); 824 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 825 (caddr_t)tigonFwRodata); 826 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 827 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 828 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 829 break; 830 case TI_HWREV_TIGON_II: 831 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 832 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 833 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 834 printf("ti%d: firmware revision mismatch; want " 835 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 836 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 837 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 838 tigon2FwReleaseMinor, tigon2FwReleaseFix); 839 return; 840 } 841 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 842 (caddr_t)tigon2FwText); 843 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 844 (caddr_t)tigon2FwData); 845 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 846 (caddr_t)tigon2FwRodata); 847 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 848 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 849 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 850 break; 851 default: 852 printf("ti%d: can't load firmware: unknown hardware rev\n", 853 sc->ti_unit); 854 break; 855 } 856 857 return; 858} 859 860/* 861 * Send the NIC a command via the command ring. 862 */ 863static void 864ti_cmd(sc, cmd) 865 struct ti_softc *sc; 866 struct ti_cmd_desc *cmd; 867{ 868 u_int32_t index; 869 870 if (sc->ti_rdata->ti_cmd_ring == NULL) 871 return; 872 873 index = sc->ti_cmd_saved_prodidx; 874 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 875 TI_INC(index, TI_CMD_RING_CNT); 876 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 877 sc->ti_cmd_saved_prodidx = index; 878 879 return; 880} 881 882/* 883 * Send the NIC an extended command. The 'len' parameter specifies the 884 * number of command slots to include after the initial command. 885 */ 886static void 887ti_cmd_ext(sc, cmd, arg, len) 888 struct ti_softc *sc; 889 struct ti_cmd_desc *cmd; 890 caddr_t arg; 891 int len; 892{ 893 u_int32_t index; 894 register int i; 895 896 if (sc->ti_rdata->ti_cmd_ring == NULL) 897 return; 898 899 index = sc->ti_cmd_saved_prodidx; 900 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 901 TI_INC(index, TI_CMD_RING_CNT); 902 for (i = 0; i < len; i++) { 903 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 904 *(u_int32_t *)(&arg[i * 4])); 905 TI_INC(index, TI_CMD_RING_CNT); 906 } 907 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 908 sc->ti_cmd_saved_prodidx = index; 909 910 return; 911} 912 913/* 914 * Handle events that have triggered interrupts. 915 */ 916static void 917ti_handle_events(sc) 918 struct ti_softc *sc; 919{ 920 struct ti_event_desc *e; 921 922 if (sc->ti_rdata->ti_event_ring == NULL) 923 return; 924 925 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 926 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 927 switch(e->ti_event) { 928 case TI_EV_LINKSTAT_CHANGED: 929 sc->ti_linkstat = e->ti_code; 930 if (e->ti_code == TI_EV_CODE_LINK_UP) 931 printf("ti%d: 10/100 link up\n", sc->ti_unit); 932 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 933 printf("ti%d: gigabit link up\n", sc->ti_unit); 934 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 935 printf("ti%d: link down\n", sc->ti_unit); 936 break; 937 case TI_EV_ERROR: 938 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 939 printf("ti%d: invalid command\n", sc->ti_unit); 940 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 941 printf("ti%d: unknown command\n", sc->ti_unit); 942 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 943 printf("ti%d: bad config data\n", sc->ti_unit); 944 break; 945 case TI_EV_FIRMWARE_UP: 946 ti_init2(sc); 947 break; 948 case TI_EV_STATS_UPDATED: 949 ti_stats_update(sc); 950 break; 951 case TI_EV_RESET_JUMBO_RING: 952 case TI_EV_MCAST_UPDATED: 953 /* Who cares. */ 954 break; 955 default: 956 printf("ti%d: unknown event: %d\n", 957 sc->ti_unit, e->ti_event); 958 break; 959 } 960 /* Advance the consumer index. */ 961 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 962 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 963 } 964 965 return; 966} 967 968#ifdef TI_PRIVATE_JUMBOS 969 970/* 971 * Memory management for the jumbo receive ring is a pain in the 972 * butt. We need to allocate at least 9018 bytes of space per frame, 973 * _and_ it has to be contiguous (unless you use the extended 974 * jumbo descriptor format). Using malloc() all the time won't 975 * work: malloc() allocates memory in powers of two, which means we 976 * would end up wasting a considerable amount of space by allocating 977 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 978 * to do our own memory management. 979 * 980 * The driver needs to allocate a contiguous chunk of memory at boot 981 * time. We then chop this up ourselves into 9K pieces and use them 982 * as external mbuf storage. 983 * 984 * One issue here is how much memory to allocate. The jumbo ring has 985 * 256 slots in it, but at 9K per slot than can consume over 2MB of 986 * RAM. This is a bit much, especially considering we also need 987 * RAM for the standard ring and mini ring (on the Tigon 2). To 988 * save space, we only actually allocate enough memory for 64 slots 989 * by default, which works out to between 500 and 600K. This can 990 * be tuned by changing a #define in if_tireg.h. 991 */ 992 993static int 994ti_alloc_jumbo_mem(sc) 995 struct ti_softc *sc; 996{ 997 caddr_t ptr; 998 register int i; 999 struct ti_jpool_entry *entry; 1000 1001 /* Grab a big chunk o' storage. */ 1002 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 1003 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1004 1005 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 1006 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 1007 return(ENOBUFS); 1008 } 1009 1010 SLIST_INIT(&sc->ti_jfree_listhead); 1011 SLIST_INIT(&sc->ti_jinuse_listhead); 1012 1013 /* 1014 * Now divide it up into 9K pieces and save the addresses 1015 * in an array. 1016 */ 1017 ptr = sc->ti_cdata.ti_jumbo_buf; 1018 for (i = 0; i < TI_JSLOTS; i++) { 1019 sc->ti_cdata.ti_jslots[i] = ptr; 1020 ptr += TI_JLEN; 1021 entry = malloc(sizeof(struct ti_jpool_entry), 1022 M_DEVBUF, M_NOWAIT); 1023 if (entry == NULL) { 1024 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1025 M_DEVBUF); 1026 sc->ti_cdata.ti_jumbo_buf = NULL; 1027 printf("ti%d: no memory for jumbo " 1028 "buffer queue!\n", sc->ti_unit); 1029 return(ENOBUFS); 1030 } 1031 entry->slot = i; 1032 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1033 } 1034 1035 return(0); 1036} 1037 1038/* 1039 * Allocate a jumbo buffer. 1040 */ 1041static void *ti_jalloc(sc) 1042 struct ti_softc *sc; 1043{ 1044 struct ti_jpool_entry *entry; 1045 1046 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1047 1048 if (entry == NULL) { 1049 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1050 return(NULL); 1051 } 1052 1053 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1054 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1055 return(sc->ti_cdata.ti_jslots[entry->slot]); 1056} 1057 1058/* 1059 * Release a jumbo buffer. 1060 */ 1061static void 1062ti_jfree(buf, args) 1063 void *buf; 1064 void *args; 1065{ 1066 struct ti_softc *sc; 1067 int i; 1068 struct ti_jpool_entry *entry; 1069 1070 /* Extract the softc struct pointer. */ 1071 sc = (struct ti_softc *)args; 1072 1073 if (sc == NULL) 1074 panic("ti_jfree: didn't get softc pointer!"); 1075 1076 /* calculate the slot this buffer belongs to */ 1077 i = ((vm_offset_t)buf 1078 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1079 1080 if ((i < 0) || (i >= TI_JSLOTS)) 1081 panic("ti_jfree: asked to free buffer that we don't manage!"); 1082 1083 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1084 if (entry == NULL) 1085 panic("ti_jfree: buffer not in use!"); 1086 entry->slot = i; 1087 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1088 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1089 1090 return; 1091} 1092 1093#endif /* TI_PRIVATE_JUMBOS */ 1094 1095/* 1096 * Intialize a standard receive ring descriptor. 1097 */ 1098static int 1099ti_newbuf_std(sc, i, m) 1100 struct ti_softc *sc; 1101 int i; 1102 struct mbuf *m; 1103{ 1104 struct mbuf *m_new = NULL; 1105 struct ti_rx_desc *r; 1106 1107 if (m == NULL) { 1108 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1109 if (m_new == NULL) 1110 return(ENOBUFS); 1111 1112 MCLGET(m_new, M_DONTWAIT); 1113 if (!(m_new->m_flags & M_EXT)) { 1114 m_freem(m_new); 1115 return(ENOBUFS); 1116 } 1117 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1118 } else { 1119 m_new = m; 1120 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1121 m_new->m_data = m_new->m_ext.ext_buf; 1122 } 1123 1124 m_adj(m_new, ETHER_ALIGN); 1125 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1126 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1127 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1128 r->ti_type = TI_BDTYPE_RECV_BD; 1129 r->ti_flags = 0; 1130 if (sc->arpcom.ac_if.if_hwassist) 1131 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1132 r->ti_len = m_new->m_len; 1133 r->ti_idx = i; 1134 1135 return(0); 1136} 1137 1138/* 1139 * Intialize a mini receive ring descriptor. This only applies to 1140 * the Tigon 2. 1141 */ 1142static int 1143ti_newbuf_mini(sc, i, m) 1144 struct ti_softc *sc; 1145 int i; 1146 struct mbuf *m; 1147{ 1148 struct mbuf *m_new = NULL; 1149 struct ti_rx_desc *r; 1150 1151 if (m == NULL) { 1152 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1153 if (m_new == NULL) { 1154 return(ENOBUFS); 1155 } 1156 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1157 } else { 1158 m_new = m; 1159 m_new->m_data = m_new->m_pktdat; 1160 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1161 } 1162 1163 m_adj(m_new, ETHER_ALIGN); 1164 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1165 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1166 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1167 r->ti_type = TI_BDTYPE_RECV_BD; 1168 r->ti_flags = TI_BDFLAG_MINI_RING; 1169 if (sc->arpcom.ac_if.if_hwassist) 1170 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1171 r->ti_len = m_new->m_len; 1172 r->ti_idx = i; 1173 1174 return(0); 1175} 1176 1177#ifdef TI_PRIVATE_JUMBOS 1178 1179/* 1180 * Initialize a jumbo receive ring descriptor. This allocates 1181 * a jumbo buffer from the pool managed internally by the driver. 1182 */ 1183static int 1184ti_newbuf_jumbo(sc, i, m) 1185 struct ti_softc *sc; 1186 int i; 1187 struct mbuf *m; 1188{ 1189 struct mbuf *m_new = NULL; 1190 struct ti_rx_desc *r; 1191 1192 if (m == NULL) { 1193 caddr_t *buf = NULL; 1194 1195 /* Allocate the mbuf. */ 1196 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1197 if (m_new == NULL) { 1198 return(ENOBUFS); 1199 } 1200 1201 /* Allocate the jumbo buffer */ 1202 buf = ti_jalloc(sc); 1203 if (buf == NULL) { 1204 m_freem(m_new); 1205 printf("ti%d: jumbo allocation failed " 1206 "-- packet dropped!\n", sc->ti_unit); 1207 return(ENOBUFS); 1208 } 1209 1210 /* Attach the buffer to the mbuf. */ 1211 m_new->m_data = (void *) buf; 1212 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1213 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1214 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1215 } else { 1216 m_new = m; 1217 m_new->m_data = m_new->m_ext.ext_buf; 1218 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1219 } 1220 1221 m_adj(m_new, ETHER_ALIGN); 1222 /* Set up the descriptor. */ 1223 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1224 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1225 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1226 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1227 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1228 if (sc->arpcom.ac_if.if_hwassist) 1229 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1230 r->ti_len = m_new->m_len; 1231 r->ti_idx = i; 1232 1233 return(0); 1234} 1235 1236#else 1237#include <vm/vm_page.h> 1238 1239#if (PAGE_SIZE == 4096) 1240#define NPAYLOAD 2 1241#else 1242#define NPAYLOAD 1 1243#endif 1244 1245#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1246#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1247#define NFS_HDR_LEN (UDP_HDR_LEN) 1248static int HDR_LEN = TCP_HDR_LEN; 1249 1250 1251 /* 1252 * Initialize a jumbo receive ring descriptor. This allocates 1253 * a jumbo buffer from the pool managed internally by the driver. 1254 */ 1255static int 1256ti_newbuf_jumbo(sc, idx, m_old) 1257 struct ti_softc *sc; 1258 int idx; 1259 struct mbuf *m_old; 1260{ 1261 struct mbuf *cur, *m_new = NULL; 1262 struct mbuf *m[3] = {NULL, NULL, NULL}; 1263 struct ti_rx_desc_ext *r; 1264 vm_page_t frame; 1265 /* 1 extra buf to make nobufs easy*/ 1266 caddr_t buf[3] = {NULL, NULL, NULL}; 1267 int i; 1268 1269 if (m_old != NULL) { 1270 m_new = m_old; 1271 cur = m_old->m_next; 1272 for (i = 0; i <= NPAYLOAD; i++){ 1273 m[i] = cur; 1274 cur = cur->m_next; 1275 } 1276 } else { 1277 /* Allocate the mbufs. */ 1278 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1279 if (m_new == NULL) { 1280 printf("ti%d: mbuf allocation failed " 1281 "-- packet dropped!\n", sc->ti_unit); 1282 goto nobufs; 1283 } 1284 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1285 if (m[NPAYLOAD] == NULL) { 1286 printf("ti%d: cluster mbuf allocation failed " 1287 "-- packet dropped!\n", sc->ti_unit); 1288 goto nobufs; 1289 } 1290 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1291 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1292 printf("ti%d: mbuf allocation failed " 1293 "-- packet dropped!\n", sc->ti_unit); 1294 goto nobufs; 1295 } 1296 m[NPAYLOAD]->m_len = MCLBYTES; 1297 1298 for (i = 0; i < NPAYLOAD; i++){ 1299 MGET(m[i], M_DONTWAIT, MT_DATA); 1300 if (m[i] == NULL) { 1301 printf("ti%d: mbuf allocation failed " 1302 "-- packet dropped!\n", sc->ti_unit); 1303 goto nobufs; 1304 } 1305 if (!(frame = jumbo_pg_alloc())){ 1306 printf("ti%d: buffer allocation failed " 1307 "-- packet dropped!\n", sc->ti_unit); 1308 printf(" index %d page %d\n", idx, i); 1309 goto nobufs; 1310 } 1311 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame)); 1312 } 1313 for (i = 0; i < NPAYLOAD; i++){ 1314 /* Attach the buffer to the mbuf. */ 1315 m[i]->m_data = (void *)buf[i]; 1316 m[i]->m_len = PAGE_SIZE; 1317 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE, 1318 jumbo_freem, NULL, 0, EXT_DISPOSABLE); 1319 m[i]->m_next = m[i+1]; 1320 } 1321 /* link the buffers to the header */ 1322 m_new->m_next = m[0]; 1323 m_new->m_data += ETHER_ALIGN; 1324 if (sc->ti_hdrsplit) 1325 m_new->m_len = MHLEN - ETHER_ALIGN; 1326 else 1327 m_new->m_len = HDR_LEN; 1328 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1329 } 1330 1331 /* Set up the descriptor. */ 1332 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1333 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1334 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1335 r->ti_len0 = m_new->m_len; 1336 1337 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1338 r->ti_len1 = PAGE_SIZE; 1339 1340 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1341 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1342 1343 if (PAGE_SIZE == 4096) { 1344 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1345 r->ti_len3 = MCLBYTES; 1346 } else { 1347 r->ti_len3 = 0; 1348 } 1349 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1350 1351 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1352 1353 if (sc->arpcom.ac_if.if_hwassist) 1354 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1355 1356 r->ti_idx = idx; 1357 1358 return(0); 1359 1360 nobufs: 1361 1362 /* 1363 * Warning! : 1364 * This can only be called before the mbufs are strung together. 1365 * If the mbufs are strung together, m_freem() will free the chain, 1366 * so that the later mbufs will be freed multiple times. 1367 */ 1368 if (m_new) 1369 m_freem(m_new); 1370 1371 for(i = 0; i < 3; i++){ 1372 if (m[i]) 1373 m_freem(m[i]); 1374 if (buf[i]) 1375 jumbo_pg_free((vm_offset_t)buf[i]); 1376 } 1377 return ENOBUFS; 1378} 1379#endif 1380 1381 1382 1383/* 1384 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1385 * that's 1MB or memory, which is a lot. For now, we fill only the first 1386 * 256 ring entries and hope that our CPU is fast enough to keep up with 1387 * the NIC. 1388 */ 1389static int 1390ti_init_rx_ring_std(sc) 1391 struct ti_softc *sc; 1392{ 1393 register int i; 1394 struct ti_cmd_desc cmd; 1395 1396 for (i = 0; i < TI_SSLOTS; i++) { 1397 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1398 return(ENOBUFS); 1399 }; 1400 1401 TI_UPDATE_STDPROD(sc, i - 1); 1402 sc->ti_std = i - 1; 1403 1404 return(0); 1405} 1406 1407static void 1408ti_free_rx_ring_std(sc) 1409 struct ti_softc *sc; 1410{ 1411 register int i; 1412 1413 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1414 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1415 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1416 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1417 } 1418 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1419 sizeof(struct ti_rx_desc)); 1420 } 1421 1422 return; 1423} 1424 1425static int 1426ti_init_rx_ring_jumbo(sc) 1427 struct ti_softc *sc; 1428{ 1429 register int i; 1430 struct ti_cmd_desc cmd; 1431 1432 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1433 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1434 return(ENOBUFS); 1435 }; 1436 1437 TI_UPDATE_JUMBOPROD(sc, i - 1); 1438 sc->ti_jumbo = i - 1; 1439 1440 return(0); 1441} 1442 1443static void 1444ti_free_rx_ring_jumbo(sc) 1445 struct ti_softc *sc; 1446{ 1447 register int i; 1448 1449 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1450 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1451 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1452 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1453 } 1454 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1455 sizeof(struct ti_rx_desc)); 1456 } 1457 1458 return; 1459} 1460 1461static int 1462ti_init_rx_ring_mini(sc) 1463 struct ti_softc *sc; 1464{ 1465 register int i; 1466 1467 for (i = 0; i < TI_MSLOTS; i++) { 1468 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1469 return(ENOBUFS); 1470 }; 1471 1472 TI_UPDATE_MINIPROD(sc, i - 1); 1473 sc->ti_mini = i - 1; 1474 1475 return(0); 1476} 1477 1478static void 1479ti_free_rx_ring_mini(sc) 1480 struct ti_softc *sc; 1481{ 1482 register int i; 1483 1484 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1485 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1486 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1487 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1488 } 1489 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1490 sizeof(struct ti_rx_desc)); 1491 } 1492 1493 return; 1494} 1495 1496static void 1497ti_free_tx_ring(sc) 1498 struct ti_softc *sc; 1499{ 1500 register int i; 1501 1502 if (sc->ti_rdata->ti_tx_ring == NULL) 1503 return; 1504 1505 for (i = 0; i < TI_TX_RING_CNT; i++) { 1506 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1507 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1508 sc->ti_cdata.ti_tx_chain[i] = NULL; 1509 } 1510 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1511 sizeof(struct ti_tx_desc)); 1512 } 1513 1514 return; 1515} 1516 1517static int 1518ti_init_tx_ring(sc) 1519 struct ti_softc *sc; 1520{ 1521 sc->ti_txcnt = 0; 1522 sc->ti_tx_saved_considx = 0; 1523 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1524 return(0); 1525} 1526 1527/* 1528 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1529 * but we have to support the old way too so that Tigon 1 cards will 1530 * work. 1531 */ 1532static void 1533ti_add_mcast(sc, addr) 1534 struct ti_softc *sc; 1535 struct ether_addr *addr; 1536{ 1537 struct ti_cmd_desc cmd; 1538 u_int16_t *m; 1539 u_int32_t ext[2] = {0, 0}; 1540 1541 m = (u_int16_t *)&addr->octet[0]; 1542 1543 switch(sc->ti_hwrev) { 1544 case TI_HWREV_TIGON: 1545 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1546 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1547 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1548 break; 1549 case TI_HWREV_TIGON_II: 1550 ext[0] = htons(m[0]); 1551 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1552 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1553 break; 1554 default: 1555 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1556 break; 1557 } 1558 1559 return; 1560} 1561 1562static void 1563ti_del_mcast(sc, addr) 1564 struct ti_softc *sc; 1565 struct ether_addr *addr; 1566{ 1567 struct ti_cmd_desc cmd; 1568 u_int16_t *m; 1569 u_int32_t ext[2] = {0, 0}; 1570 1571 m = (u_int16_t *)&addr->octet[0]; 1572 1573 switch(sc->ti_hwrev) { 1574 case TI_HWREV_TIGON: 1575 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1576 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1577 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1578 break; 1579 case TI_HWREV_TIGON_II: 1580 ext[0] = htons(m[0]); 1581 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1582 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1583 break; 1584 default: 1585 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1586 break; 1587 } 1588 1589 return; 1590} 1591 1592/* 1593 * Configure the Tigon's multicast address filter. 1594 * 1595 * The actual multicast table management is a bit of a pain, thanks to 1596 * slight brain damage on the part of both Alteon and us. With our 1597 * multicast code, we are only alerted when the multicast address table 1598 * changes and at that point we only have the current list of addresses: 1599 * we only know the current state, not the previous state, so we don't 1600 * actually know what addresses were removed or added. The firmware has 1601 * state, but we can't get our grubby mits on it, and there is no 'delete 1602 * all multicast addresses' command. Hence, we have to maintain our own 1603 * state so we know what addresses have been programmed into the NIC at 1604 * any given time. 1605 */ 1606static void 1607ti_setmulti(sc) 1608 struct ti_softc *sc; 1609{ 1610 struct ifnet *ifp; 1611 struct ifmultiaddr *ifma; 1612 struct ti_cmd_desc cmd; 1613 struct ti_mc_entry *mc; 1614 u_int32_t intrs; 1615 1616 ifp = &sc->arpcom.ac_if; 1617 1618 if (ifp->if_flags & IFF_ALLMULTI) { 1619 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1620 return; 1621 } else { 1622 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1623 } 1624 1625 /* Disable interrupts. */ 1626 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1627 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1628 1629 /* First, zot all the existing filters. */ 1630 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1631 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1632 ti_del_mcast(sc, &mc->mc_addr); 1633 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1634 free(mc, M_DEVBUF); 1635 } 1636 1637 /* Now program new ones. */ 1638 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1639 if (ifma->ifma_addr->sa_family != AF_LINK) 1640 continue; 1641 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1642 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1643 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1644 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1645 ti_add_mcast(sc, &mc->mc_addr); 1646 } 1647 1648 /* Re-enable interrupts. */ 1649 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1650 1651 return; 1652} 1653 1654/* 1655 * Check to see if the BIOS has configured us for a 64 bit slot when 1656 * we aren't actually in one. If we detect this condition, we can work 1657 * around it on the Tigon 2 by setting a bit in the PCI state register, 1658 * but for the Tigon 1 we must give up and abort the interface attach. 1659 */ 1660static int ti_64bitslot_war(sc) 1661 struct ti_softc *sc; 1662{ 1663 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1664 CSR_WRITE_4(sc, 0x600, 0); 1665 CSR_WRITE_4(sc, 0x604, 0); 1666 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1667 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1668 if (sc->ti_hwrev == TI_HWREV_TIGON) 1669 return(EINVAL); 1670 else { 1671 TI_SETBIT(sc, TI_PCI_STATE, 1672 TI_PCISTATE_32BIT_BUS); 1673 return(0); 1674 } 1675 } 1676 } 1677 1678 return(0); 1679} 1680 1681/* 1682 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1683 * self-test results. 1684 */ 1685static int 1686ti_chipinit(sc) 1687 struct ti_softc *sc; 1688{ 1689 u_int32_t cacheline; 1690 u_int32_t pci_writemax = 0; 1691 u_int32_t hdrsplit; 1692 1693 /* Initialize link to down state. */ 1694 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1695 1696 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1697 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1698 else 1699 sc->arpcom.ac_if.if_hwassist = 0; 1700 1701 /* Set endianness before we access any non-PCI registers. */ 1702#if BYTE_ORDER == BIG_ENDIAN 1703 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1704 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1705#else 1706 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1707 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1708#endif 1709 1710 /* Check the ROM failed bit to see if self-tests passed. */ 1711 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1712 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1713 return(ENODEV); 1714 } 1715 1716 /* Halt the CPU. */ 1717 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1718 1719 /* Figure out the hardware revision. */ 1720 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1721 case TI_REV_TIGON_I: 1722 sc->ti_hwrev = TI_HWREV_TIGON; 1723 break; 1724 case TI_REV_TIGON_II: 1725 sc->ti_hwrev = TI_HWREV_TIGON_II; 1726 break; 1727 default: 1728 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1729 return(ENODEV); 1730 } 1731 1732 /* Do special setup for Tigon 2. */ 1733 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1734 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1735 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1736 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1737 } 1738 1739 /* 1740 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1741 * can't do header splitting. 1742 */ 1743#ifdef TI_JUMBO_HDRSPLIT 1744 if (sc->ti_hwrev != TI_HWREV_TIGON) 1745 sc->ti_hdrsplit = 1; 1746 else 1747 printf("ti%d: can't do header splitting on a Tigon I board\n", 1748 sc->ti_unit); 1749#endif /* TI_JUMBO_HDRSPLIT */ 1750 1751 /* Set up the PCI state register. */ 1752 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1753 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1754 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1755 } 1756 1757 /* Clear the read/write max DMA parameters. */ 1758 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1759 TI_PCISTATE_READ_MAXDMA)); 1760 1761 /* Get cache line size. */ 1762 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1763 1764 /* 1765 * If the system has set enabled the PCI memory write 1766 * and invalidate command in the command register, set 1767 * the write max parameter accordingly. This is necessary 1768 * to use MWI with the Tigon 2. 1769 */ 1770 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1771 switch(cacheline) { 1772 case 1: 1773 case 4: 1774 case 8: 1775 case 16: 1776 case 32: 1777 case 64: 1778 break; 1779 default: 1780 /* Disable PCI memory write and invalidate. */ 1781 if (bootverbose) 1782 printf("ti%d: cache line size %d not " 1783 "supported; disabling PCI MWI\n", 1784 sc->ti_unit, cacheline); 1785 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1786 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1787 break; 1788 } 1789 } 1790 1791#ifdef __brokenalpha__ 1792 /* 1793 * From the Alteon sample driver: 1794 * Must insure that we do not cross an 8K (bytes) boundary 1795 * for DMA reads. Our highest limit is 1K bytes. This is a 1796 * restriction on some ALPHA platforms with early revision 1797 * 21174 PCI chipsets, such as the AlphaPC 164lx 1798 */ 1799 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1800#else 1801 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1802#endif 1803 1804 /* This sets the min dma param all the way up (0xff). */ 1805 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1806 1807 if (sc->ti_hdrsplit) 1808 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1809 else 1810 hdrsplit = 0; 1811 1812 /* Configure DMA variables. */ 1813#if BYTE_ORDER == BIG_ENDIAN 1814 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1815 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1816 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1817 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1818#else /* BYTE_ORDER */ 1819 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1820 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1821 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1822#endif /* BYTE_ORDER */ 1823 1824 /* 1825 * Only allow 1 DMA channel to be active at a time. 1826 * I don't think this is a good idea, but without it 1827 * the firmware racks up lots of nicDmaReadRingFull 1828 * errors. This is not compatible with hardware checksums. 1829 */ 1830 if (sc->arpcom.ac_if.if_hwassist == 0) 1831 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1832 1833 /* Recommended settings from Tigon manual. */ 1834 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1835 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1836 1837 if (ti_64bitslot_war(sc)) { 1838 printf("ti%d: bios thinks we're in a 64 bit slot, " 1839 "but we aren't", sc->ti_unit); 1840 return(EINVAL); 1841 } 1842 1843 return(0); 1844} 1845 1846/* 1847 * Initialize the general information block and firmware, and 1848 * start the CPU(s) running. 1849 */ 1850static int 1851ti_gibinit(sc) 1852 struct ti_softc *sc; 1853{ 1854 struct ti_rcb *rcb; 1855 int i; 1856 struct ifnet *ifp; 1857 1858 ifp = &sc->arpcom.ac_if; 1859 1860 /* Disable interrupts for now. */ 1861 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1862 1863 /* Tell the chip where to find the general information block. */ 1864 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1865 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1866 1867 /* Load the firmware into SRAM. */ 1868 ti_loadfw(sc); 1869 1870 /* Set up the contents of the general info and ring control blocks. */ 1871 1872 /* Set up the event ring and producer pointer. */ 1873 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1874 1875 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1876 rcb->ti_flags = 0; 1877 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1878 vtophys(&sc->ti_ev_prodidx); 1879 sc->ti_ev_prodidx.ti_idx = 0; 1880 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1881 sc->ti_ev_saved_considx = 0; 1882 1883 /* Set up the command ring and producer mailbox. */ 1884 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1885 1886 sc->ti_rdata->ti_cmd_ring = 1887 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1888 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1889 rcb->ti_flags = 0; 1890 rcb->ti_max_len = 0; 1891 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1892 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1893 } 1894 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1895 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1896 sc->ti_cmd_saved_prodidx = 0; 1897 1898 /* 1899 * Assign the address of the stats refresh buffer. 1900 * We re-use the current stats buffer for this to 1901 * conserve memory. 1902 */ 1903 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1904 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1905 1906 /* Set up the standard receive ring. */ 1907 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1908 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1909 rcb->ti_max_len = TI_FRAMELEN; 1910 rcb->ti_flags = 0; 1911 if (sc->arpcom.ac_if.if_hwassist) 1912 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1913 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1914 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1915 1916 /* Set up the jumbo receive ring. */ 1917 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1918 TI_HOSTADDR(rcb->ti_hostaddr) = 1919 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1920 1921#ifdef TI_PRIVATE_JUMBOS 1922 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1923 rcb->ti_flags = 0; 1924#else 1925 rcb->ti_max_len = PAGE_SIZE; 1926 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1927#endif 1928 if (sc->arpcom.ac_if.if_hwassist) 1929 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1930 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1931 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1932 1933 /* 1934 * Set up the mini ring. Only activated on the 1935 * Tigon 2 but the slot in the config block is 1936 * still there on the Tigon 1. 1937 */ 1938 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1939 TI_HOSTADDR(rcb->ti_hostaddr) = 1940 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1941 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1942 if (sc->ti_hwrev == TI_HWREV_TIGON) 1943 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1944 else 1945 rcb->ti_flags = 0; 1946 if (sc->arpcom.ac_if.if_hwassist) 1947 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1948 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1949 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1950 1951 /* 1952 * Set up the receive return ring. 1953 */ 1954 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1955 TI_HOSTADDR(rcb->ti_hostaddr) = 1956 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1957 rcb->ti_flags = 0; 1958 rcb->ti_max_len = TI_RETURN_RING_CNT; 1959 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1960 vtophys(&sc->ti_return_prodidx); 1961 1962 /* 1963 * Set up the tx ring. Note: for the Tigon 2, we have the option 1964 * of putting the transmit ring in the host's address space and 1965 * letting the chip DMA it instead of leaving the ring in the NIC's 1966 * memory and accessing it through the shared memory region. We 1967 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1968 * so we have to revert to the shared memory scheme if we detect 1969 * a Tigon 1 chip. 1970 */ 1971 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1972 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1973 sc->ti_rdata->ti_tx_ring_nic = 1974 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1975 } 1976 bzero((char *)sc->ti_rdata->ti_tx_ring, 1977 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1978 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1979 if (sc->ti_hwrev == TI_HWREV_TIGON) 1980 rcb->ti_flags = 0; 1981 else 1982 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1983 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1984 if (sc->arpcom.ac_if.if_hwassist) 1985 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1986 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1987 rcb->ti_max_len = TI_TX_RING_CNT; 1988 if (sc->ti_hwrev == TI_HWREV_TIGON) 1989 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1990 else 1991 TI_HOSTADDR(rcb->ti_hostaddr) = 1992 vtophys(&sc->ti_rdata->ti_tx_ring); 1993 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1994 vtophys(&sc->ti_tx_considx); 1995 1996 /* Set up tuneables */ 1997#if 0 1998 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1999 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2000 (sc->ti_rx_coal_ticks / 10)); 2001 else 2002#endif 2003 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2004 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2005 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2006 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2007 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2008 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2009 2010 /* Turn interrupts on. */ 2011 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2012 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2013 2014 /* Start CPU. */ 2015 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2016 2017 return(0); 2018} 2019 2020/* 2021 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2022 * against our list and return its name if we find a match. 2023 */ 2024static int 2025ti_probe(dev) 2026 device_t dev; 2027{ 2028 struct ti_type *t; 2029 2030 t = ti_devs; 2031 2032 while(t->ti_name != NULL) { 2033 if ((pci_get_vendor(dev) == t->ti_vid) && 2034 (pci_get_device(dev) == t->ti_did)) { 2035 device_set_desc(dev, t->ti_name); 2036 return(0); 2037 } 2038 t++; 2039 } 2040 2041 return(ENXIO); 2042} 2043 2044static int 2045ti_attach(dev) 2046 device_t dev; 2047{ 2048 struct ifnet *ifp; 2049 struct ti_softc *sc; 2050 int unit, error = 0, rid; 2051 2052 sc = device_get_softc(dev); 2053 unit = device_get_unit(dev); 2054 2055 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2056 MTX_DEF | MTX_RECURSE); 2057 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2058 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM | 2059 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2060 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2061 2062 /* 2063 * Map control/status registers. 2064 */ 2065 pci_enable_busmaster(dev); 2066 2067 rid = TI_PCI_LOMEM; 2068 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2069 RF_ACTIVE|PCI_RF_DENSE); 2070 2071 if (sc->ti_res == NULL) { 2072 printf ("ti%d: couldn't map memory\n", unit); 2073 error = ENXIO; 2074 goto fail; 2075 } 2076 2077 sc->ti_btag = rman_get_bustag(sc->ti_res); 2078 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2079 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2080 2081 /* Allocate interrupt */ 2082 rid = 0; 2083 2084 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2085 RF_SHAREABLE | RF_ACTIVE); 2086 2087 if (sc->ti_irq == NULL) { 2088 printf("ti%d: couldn't map interrupt\n", unit); 2089 error = ENXIO; 2090 goto fail; 2091 } 2092 2093 sc->ti_unit = unit; 2094 2095 if (ti_chipinit(sc)) { 2096 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2097 error = ENXIO; 2098 goto fail; 2099 } 2100 2101 /* Zero out the NIC's on-board SRAM. */ 2102 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2103 2104 /* Init again -- zeroing memory may have clobbered some registers. */ 2105 if (ti_chipinit(sc)) { 2106 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2107 error = ENXIO; 2108 goto fail; 2109 } 2110 2111 /* 2112 * Get station address from the EEPROM. Note: the manual states 2113 * that the MAC address is at offset 0x8c, however the data is 2114 * stored as two longwords (since that's how it's loaded into 2115 * the NIC). This means the MAC address is actually preceded 2116 * by two zero bytes. We need to skip over those. 2117 */ 2118 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2119 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2120 printf("ti%d: failed to read station address\n", unit); 2121 error = ENXIO; 2122 goto fail; 2123 } 2124 2125 /* Allocate the general information block and ring buffers. */ 2126 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2127 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2128 2129 if (sc->ti_rdata == NULL) { 2130 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2131 error = ENXIO; 2132 goto fail; 2133 } 2134 2135 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2136 2137 /* Try to allocate memory for jumbo buffers. */ 2138#ifdef TI_PRIVATE_JUMBOS 2139 if (ti_alloc_jumbo_mem(sc)) { 2140 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2141 error = ENXIO; 2142 goto fail; 2143 } 2144#else 2145 if (!jumbo_vm_init()) { 2146 printf("ti%d: VM initialization failed!\n", sc->ti_unit); 2147 error = ENOMEM; 2148 goto fail; 2149 } 2150#endif 2151 2152 /* 2153 * We really need a better way to tell a 1000baseTX card 2154 * from a 1000baseSX one, since in theory there could be 2155 * OEMed 1000baseTX cards from lame vendors who aren't 2156 * clever enough to change the PCI ID. For the moment 2157 * though, the AceNIC is the only copper card available. 2158 */ 2159 if (pci_get_vendor(dev) == ALT_VENDORID && 2160 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2161 sc->ti_copper = 1; 2162 /* Ok, it's not the only copper card available. */ 2163 if (pci_get_vendor(dev) == NG_VENDORID && 2164 pci_get_device(dev) == NG_DEVICEID_GA620T) 2165 sc->ti_copper = 1; 2166 2167 /* Set default tuneable values. */ 2168 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2169#if 0 2170 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2171#endif 2172 sc->ti_rx_coal_ticks = 170; 2173 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2174 sc->ti_rx_max_coal_bds = 64; 2175#if 0 2176 sc->ti_tx_max_coal_bds = 128; 2177#endif 2178 sc->ti_tx_max_coal_bds = 32; 2179 sc->ti_tx_buf_ratio = 21; 2180 2181 /* Set up ifnet structure */ 2182 ifp = &sc->arpcom.ac_if; 2183 ifp->if_softc = sc; 2184 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2185 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2186 tis[unit] = sc; 2187 ifp->if_ioctl = ti_ioctl; 2188 ifp->if_start = ti_start; 2189 ifp->if_watchdog = ti_watchdog; 2190 ifp->if_init = ti_init; 2191 ifp->if_mtu = ETHERMTU; 2192 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2193 2194 /* Set up ifmedia support. */ 2195 if (sc->ti_copper) { 2196 /* 2197 * Copper cards allow manual 10/100 mode selection, 2198 * but not manual 1000baseTX mode selection. Why? 2199 * Becuase currently there's no way to specify the 2200 * master/slave setting through the firmware interface, 2201 * so Alteon decided to just bag it and handle it 2202 * via autonegotiation. 2203 */ 2204 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2205 ifmedia_add(&sc->ifmedia, 2206 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2207 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2208 ifmedia_add(&sc->ifmedia, 2209 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2210 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2211 ifmedia_add(&sc->ifmedia, 2212 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2213 } else { 2214 /* Fiber cards don't support 10/100 modes. */ 2215 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2216 ifmedia_add(&sc->ifmedia, 2217 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2218 } 2219 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2220 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2221 2222 /* 2223 * We're assuming here that card initialization is a sequential 2224 * thing. If it isn't, multiple cards probing at the same time 2225 * could stomp on the list of softcs here. 2226 */ 2227 2228 /* Register the device */ 2229 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2230 0600, "ti%d", sc->ti_unit); 2231 sc->dev->si_drv1 = sc; 2232 2233 /* 2234 * Call MI attach routine. 2235 */ 2236 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2237 2238 /* Hook interrupt last to avoid having to lock softc */ 2239 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2240 ti_intr, sc, &sc->ti_intrhand); 2241 2242 if (error) { 2243 printf("ti%d: couldn't set up irq\n", unit); 2244 ether_ifdetach(ifp); 2245 goto fail; 2246 } 2247 2248fail: 2249 if (sc && error) 2250 ti_detach(dev); 2251 2252 return(error); 2253} 2254 2255/* 2256 * Shutdown hardware and free up resources. This can be called any 2257 * time after the mutex has been initialized. It is called in both 2258 * the error case in attach and the normal detach case so it needs 2259 * to be careful about only freeing resources that have actually been 2260 * allocated. 2261 */ 2262static int 2263ti_detach(dev) 2264 device_t dev; 2265{ 2266 struct ti_softc *sc; 2267 struct ifnet *ifp; 2268 2269 sc = device_get_softc(dev); 2270 destroy_dev(sc->dev); 2271 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2272 TI_LOCK(sc); 2273 ifp = &sc->arpcom.ac_if; 2274 2275 /* These should only be active if attach succeeded */ 2276 if (device_is_attached(dev)) { 2277 ti_stop(sc); 2278 ether_ifdetach(ifp); 2279 bus_generic_detach(dev); 2280 } 2281 ifmedia_removeall(&sc->ifmedia); 2282 2283 if (sc->ti_intrhand) 2284 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2285 if (sc->ti_irq) 2286 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2287 if (sc->ti_res) { 2288 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2289 sc->ti_res); 2290 } 2291 2292#ifdef TI_PRIVATE_JUMBOS 2293 if (sc->ti_cdata.ti_jumbo_buf) 2294 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2295#endif 2296 if (sc->ti_rdata) 2297 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2298 2299 TI_UNLOCK(sc); 2300 mtx_destroy(&sc->ti_mtx); 2301 2302 return(0); 2303} 2304 2305#ifdef TI_JUMBO_HDRSPLIT 2306/* 2307 * If hdr_len is 0, that means that header splitting wasn't done on 2308 * this packet for some reason. The two most likely reasons are that 2309 * the protocol isn't a supported protocol for splitting, or this 2310 * packet had a fragment offset that wasn't 0. 2311 * 2312 * The header length, if it is non-zero, will always be the length of 2313 * the headers on the packet, but that length could be longer than the 2314 * first mbuf. So we take the minimum of the two as the actual 2315 * length. 2316 */ 2317static __inline void 2318ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2319{ 2320 int i = 0; 2321 int lengths[4] = {0, 0, 0, 0}; 2322 struct mbuf *m, *mp; 2323 2324 if (hdr_len != 0) 2325 top->m_len = min(hdr_len, top->m_len); 2326 pkt_len -= top->m_len; 2327 lengths[i++] = top->m_len; 2328 2329 mp = top; 2330 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2331 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2332 pkt_len -= m->m_len; 2333 lengths[i++] = m->m_len; 2334 mp = m; 2335 } 2336 2337#if 0 2338 if (hdr_len != 0) 2339 printf("got split packet: "); 2340 else 2341 printf("got non-split packet: "); 2342 2343 printf("%d,%d,%d,%d = %d\n", lengths[0], 2344 lengths[1], lengths[2], lengths[3], 2345 lengths[0] + lengths[1] + lengths[2] + 2346 lengths[3]); 2347#endif 2348 2349 if (pkt_len) 2350 panic("header splitting didn't"); 2351 2352 if (m) { 2353 m_freem(m); 2354 mp->m_next = NULL; 2355 2356 } 2357 if (mp->m_next != NULL) 2358 panic("ti_hdr_split: last mbuf in chain should be null"); 2359} 2360#endif /* TI_JUMBO_HDRSPLIT */ 2361 2362/* 2363 * Frame reception handling. This is called if there's a frame 2364 * on the receive return list. 2365 * 2366 * Note: we have to be able to handle three possibilities here: 2367 * 1) the frame is from the mini receive ring (can only happen) 2368 * on Tigon 2 boards) 2369 * 2) the frame is from the jumbo recieve ring 2370 * 3) the frame is from the standard receive ring 2371 */ 2372 2373static void 2374ti_rxeof(sc) 2375 struct ti_softc *sc; 2376{ 2377 struct ifnet *ifp; 2378 struct ti_cmd_desc cmd; 2379 2380 TI_LOCK_ASSERT(sc); 2381 2382 ifp = &sc->arpcom.ac_if; 2383 2384 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2385 struct ti_rx_desc *cur_rx; 2386 u_int32_t rxidx; 2387 struct mbuf *m = NULL; 2388 u_int16_t vlan_tag = 0; 2389 int have_tag = 0; 2390 2391 cur_rx = 2392 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2393 rxidx = cur_rx->ti_idx; 2394 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2395 2396 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2397 have_tag = 1; 2398 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2399 } 2400 2401 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2402 2403 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2404 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2405 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2406 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2407 ifp->if_ierrors++; 2408 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2409 continue; 2410 } 2411 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2412 ifp->if_ierrors++; 2413 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2414 continue; 2415 } 2416#ifdef TI_PRIVATE_JUMBOS 2417 m->m_len = cur_rx->ti_len; 2418#else /* TI_PRIVATE_JUMBOS */ 2419#ifdef TI_JUMBO_HDRSPLIT 2420 if (sc->ti_hdrsplit) 2421 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2422 cur_rx->ti_len, rxidx); 2423 else 2424#endif /* TI_JUMBO_HDRSPLIT */ 2425 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2426#endif /* TI_PRIVATE_JUMBOS */ 2427 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2428 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2429 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2430 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2431 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2432 ifp->if_ierrors++; 2433 ti_newbuf_mini(sc, sc->ti_mini, m); 2434 continue; 2435 } 2436 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2437 ifp->if_ierrors++; 2438 ti_newbuf_mini(sc, sc->ti_mini, m); 2439 continue; 2440 } 2441 m->m_len = cur_rx->ti_len; 2442 } else { 2443 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2444 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2445 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2446 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2447 ifp->if_ierrors++; 2448 ti_newbuf_std(sc, sc->ti_std, m); 2449 continue; 2450 } 2451 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2452 ifp->if_ierrors++; 2453 ti_newbuf_std(sc, sc->ti_std, m); 2454 continue; 2455 } 2456 m->m_len = cur_rx->ti_len; 2457 } 2458 2459 m->m_pkthdr.len = cur_rx->ti_len; 2460 ifp->if_ipackets++; 2461 m->m_pkthdr.rcvif = ifp; 2462 2463 if (ifp->if_hwassist) { 2464 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2465 CSUM_DATA_VALID; 2466 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2467 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2468 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2469 } 2470 2471 /* 2472 * If we received a packet with a vlan tag, 2473 * tag it before passing the packet upward. 2474 */ 2475 if (have_tag) 2476 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2477 TI_UNLOCK(sc); 2478 (*ifp->if_input)(ifp, m); 2479 TI_LOCK(sc); 2480 } 2481 2482 /* Only necessary on the Tigon 1. */ 2483 if (sc->ti_hwrev == TI_HWREV_TIGON) 2484 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2485 sc->ti_rx_saved_considx); 2486 2487 TI_UPDATE_STDPROD(sc, sc->ti_std); 2488 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2489 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2490 2491 return; 2492} 2493 2494static void 2495ti_txeof(sc) 2496 struct ti_softc *sc; 2497{ 2498 struct ti_tx_desc *cur_tx = NULL; 2499 struct ifnet *ifp; 2500 2501 ifp = &sc->arpcom.ac_if; 2502 2503 /* 2504 * Go through our tx ring and free mbufs for those 2505 * frames that have been sent. 2506 */ 2507 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2508 u_int32_t idx = 0; 2509 2510 idx = sc->ti_tx_saved_considx; 2511 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2512 if (idx > 383) 2513 CSR_WRITE_4(sc, TI_WINBASE, 2514 TI_TX_RING_BASE + 6144); 2515 else if (idx > 255) 2516 CSR_WRITE_4(sc, TI_WINBASE, 2517 TI_TX_RING_BASE + 4096); 2518 else if (idx > 127) 2519 CSR_WRITE_4(sc, TI_WINBASE, 2520 TI_TX_RING_BASE + 2048); 2521 else 2522 CSR_WRITE_4(sc, TI_WINBASE, 2523 TI_TX_RING_BASE); 2524 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2525 } else 2526 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2527 if (cur_tx->ti_flags & TI_BDFLAG_END) 2528 ifp->if_opackets++; 2529 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2530 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2531 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2532 } 2533 sc->ti_txcnt--; 2534 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2535 ifp->if_timer = 0; 2536 } 2537 2538 if (cur_tx != NULL) 2539 ifp->if_flags &= ~IFF_OACTIVE; 2540 2541 return; 2542} 2543 2544static void 2545ti_intr(xsc) 2546 void *xsc; 2547{ 2548 struct ti_softc *sc; 2549 struct ifnet *ifp; 2550 2551 sc = xsc; 2552 TI_LOCK(sc); 2553 ifp = &sc->arpcom.ac_if; 2554 2555/*#ifdef notdef*/ 2556 /* Avoid this for now -- checking this register is expensive. */ 2557 /* Make sure this is really our interrupt. */ 2558 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2559 TI_UNLOCK(sc); 2560 return; 2561 } 2562/*#endif*/ 2563 2564 /* Ack interrupt and stop others from occuring. */ 2565 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2566 2567 if (ifp->if_flags & IFF_RUNNING) { 2568 /* Check RX return ring producer/consumer */ 2569 ti_rxeof(sc); 2570 2571 /* Check TX ring producer/consumer */ 2572 ti_txeof(sc); 2573 } 2574 2575 ti_handle_events(sc); 2576 2577 /* Re-enable interrupts. */ 2578 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2579 2580 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2581 ti_start(ifp); 2582 2583 TI_UNLOCK(sc); 2584 2585 return; 2586} 2587 2588static void 2589ti_stats_update(sc) 2590 struct ti_softc *sc; 2591{ 2592 struct ifnet *ifp; 2593 2594 ifp = &sc->arpcom.ac_if; 2595 2596 ifp->if_collisions += 2597 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2598 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2599 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2600 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2601 ifp->if_collisions; 2602 2603 return; 2604} 2605 2606/* 2607 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2608 * pointers to descriptors. 2609 */ 2610static int 2611ti_encap(sc, m_head, txidx) 2612 struct ti_softc *sc; 2613 struct mbuf *m_head; 2614 u_int32_t *txidx; 2615{ 2616 struct ti_tx_desc *f = NULL; 2617 struct mbuf *m; 2618 u_int32_t frag, cur, cnt = 0; 2619 u_int16_t csum_flags = 0; 2620 struct m_tag *mtag; 2621 2622 m = m_head; 2623 cur = frag = *txidx; 2624 2625 if (m_head->m_pkthdr.csum_flags) { 2626 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2627 csum_flags |= TI_BDFLAG_IP_CKSUM; 2628 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2629 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2630 if (m_head->m_flags & M_LASTFRAG) 2631 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2632 else if (m_head->m_flags & M_FRAG) 2633 csum_flags |= TI_BDFLAG_IP_FRAG; 2634 } 2635 2636 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2637 2638 /* 2639 * Start packing the mbufs in this chain into 2640 * the fragment pointers. Stop when we run out 2641 * of fragments or hit the end of the mbuf chain. 2642 */ 2643 for (m = m_head; m != NULL; m = m->m_next) { 2644 if (m->m_len != 0) { 2645 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2646 if (frag > 383) 2647 CSR_WRITE_4(sc, TI_WINBASE, 2648 TI_TX_RING_BASE + 6144); 2649 else if (frag > 255) 2650 CSR_WRITE_4(sc, TI_WINBASE, 2651 TI_TX_RING_BASE + 4096); 2652 else if (frag > 127) 2653 CSR_WRITE_4(sc, TI_WINBASE, 2654 TI_TX_RING_BASE + 2048); 2655 else 2656 CSR_WRITE_4(sc, TI_WINBASE, 2657 TI_TX_RING_BASE); 2658 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2659 } else 2660 f = &sc->ti_rdata->ti_tx_ring[frag]; 2661 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2662 break; 2663 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2664 f->ti_len = m->m_len; 2665 f->ti_flags = csum_flags; 2666 2667 if (mtag != NULL) { 2668 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2669 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2670 } else { 2671 f->ti_vlan_tag = 0; 2672 } 2673 2674 /* 2675 * Sanity check: avoid coming within 16 descriptors 2676 * of the end of the ring. 2677 */ 2678 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2679 return(ENOBUFS); 2680 cur = frag; 2681 TI_INC(frag, TI_TX_RING_CNT); 2682 cnt++; 2683 } 2684 } 2685 2686 if (m != NULL) 2687 return(ENOBUFS); 2688 2689 if (frag == sc->ti_tx_saved_considx) 2690 return(ENOBUFS); 2691 2692 if (sc->ti_hwrev == TI_HWREV_TIGON) 2693 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2694 TI_BDFLAG_END; 2695 else 2696 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2697 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2698 sc->ti_txcnt += cnt; 2699 2700 *txidx = frag; 2701 2702 return(0); 2703} 2704 2705/* 2706 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2707 * to the mbuf data regions directly in the transmit descriptors. 2708 */ 2709static void 2710ti_start(ifp) 2711 struct ifnet *ifp; 2712{ 2713 struct ti_softc *sc; 2714 struct mbuf *m_head = NULL; 2715 u_int32_t prodidx = 0; 2716 2717 sc = ifp->if_softc; 2718 TI_LOCK(sc); 2719 2720 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2721 2722 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2723 IF_DEQUEUE(&ifp->if_snd, m_head); 2724 if (m_head == NULL) 2725 break; 2726 2727 /* 2728 * XXX 2729 * safety overkill. If this is a fragmented packet chain 2730 * with delayed TCP/UDP checksums, then only encapsulate 2731 * it if we have enough descriptors to handle the entire 2732 * chain at once. 2733 * (paranoia -- may not actually be needed) 2734 */ 2735 if (m_head->m_flags & M_FIRSTFRAG && 2736 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2737 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2738 m_head->m_pkthdr.csum_data + 16) { 2739 IF_PREPEND(&ifp->if_snd, m_head); 2740 ifp->if_flags |= IFF_OACTIVE; 2741 break; 2742 } 2743 } 2744 2745 /* 2746 * Pack the data into the transmit ring. If we 2747 * don't have room, set the OACTIVE flag and wait 2748 * for the NIC to drain the ring. 2749 */ 2750 if (ti_encap(sc, m_head, &prodidx)) { 2751 IF_PREPEND(&ifp->if_snd, m_head); 2752 ifp->if_flags |= IFF_OACTIVE; 2753 break; 2754 } 2755 2756 /* 2757 * If there's a BPF listener, bounce a copy of this frame 2758 * to him. 2759 */ 2760 BPF_MTAP(ifp, m_head); 2761 } 2762 2763 /* Transmit */ 2764 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2765 2766 /* 2767 * Set a timeout in case the chip goes out to lunch. 2768 */ 2769 ifp->if_timer = 5; 2770 TI_UNLOCK(sc); 2771 2772 return; 2773} 2774 2775static void 2776ti_init(xsc) 2777 void *xsc; 2778{ 2779 struct ti_softc *sc = xsc; 2780 2781 /* Cancel pending I/O and flush buffers. */ 2782 ti_stop(sc); 2783 2784 TI_LOCK(sc); 2785 /* Init the gen info block, ring control blocks and firmware. */ 2786 if (ti_gibinit(sc)) { 2787 printf("ti%d: initialization failure\n", sc->ti_unit); 2788 TI_UNLOCK(sc); 2789 return; 2790 } 2791 2792 TI_UNLOCK(sc); 2793 2794 return; 2795} 2796 2797static void ti_init2(sc) 2798 struct ti_softc *sc; 2799{ 2800 struct ti_cmd_desc cmd; 2801 struct ifnet *ifp; 2802 u_int16_t *m; 2803 struct ifmedia *ifm; 2804 int tmp; 2805 2806 ifp = &sc->arpcom.ac_if; 2807 2808 /* Specify MTU and interface index. */ 2809 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 2810 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2811 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 2812 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2813 2814 /* Load our MAC address. */ 2815 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2816 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2817 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2818 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2819 2820 /* Enable or disable promiscuous mode as needed. */ 2821 if (ifp->if_flags & IFF_PROMISC) { 2822 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2823 } else { 2824 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2825 } 2826 2827 /* Program multicast filter. */ 2828 ti_setmulti(sc); 2829 2830 /* 2831 * If this is a Tigon 1, we should tell the 2832 * firmware to use software packet filtering. 2833 */ 2834 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2835 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2836 } 2837 2838 /* Init RX ring. */ 2839 ti_init_rx_ring_std(sc); 2840 2841 /* Init jumbo RX ring. */ 2842 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2843 ti_init_rx_ring_jumbo(sc); 2844 2845 /* 2846 * If this is a Tigon 2, we can also configure the 2847 * mini ring. 2848 */ 2849 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2850 ti_init_rx_ring_mini(sc); 2851 2852 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2853 sc->ti_rx_saved_considx = 0; 2854 2855 /* Init TX ring. */ 2856 ti_init_tx_ring(sc); 2857 2858 /* Tell firmware we're alive. */ 2859 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2860 2861 /* Enable host interrupts. */ 2862 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2863 2864 ifp->if_flags |= IFF_RUNNING; 2865 ifp->if_flags &= ~IFF_OACTIVE; 2866 2867 /* 2868 * Make sure to set media properly. We have to do this 2869 * here since we have to issue commands in order to set 2870 * the link negotiation and we can't issue commands until 2871 * the firmware is running. 2872 */ 2873 ifm = &sc->ifmedia; 2874 tmp = ifm->ifm_media; 2875 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2876 ti_ifmedia_upd(ifp); 2877 ifm->ifm_media = tmp; 2878 2879 return; 2880} 2881 2882/* 2883 * Set media options. 2884 */ 2885static int 2886ti_ifmedia_upd(ifp) 2887 struct ifnet *ifp; 2888{ 2889 struct ti_softc *sc; 2890 struct ifmedia *ifm; 2891 struct ti_cmd_desc cmd; 2892 u_int32_t flowctl; 2893 2894 sc = ifp->if_softc; 2895 ifm = &sc->ifmedia; 2896 2897 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2898 return(EINVAL); 2899 2900 flowctl = 0; 2901 2902 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2903 case IFM_AUTO: 2904 /* 2905 * Transmit flow control doesn't work on the Tigon 1. 2906 */ 2907 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2908 2909 /* 2910 * Transmit flow control can also cause problems on the 2911 * Tigon 2, apparantly with both the copper and fiber 2912 * boards. The symptom is that the interface will just 2913 * hang. This was reproduced with Alteon 180 switches. 2914 */ 2915#if 0 2916 if (sc->ti_hwrev != TI_HWREV_TIGON) 2917 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2918#endif 2919 2920 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2921 TI_GLNK_FULL_DUPLEX| flowctl | 2922 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2923 2924 flowctl = TI_LNK_RX_FLOWCTL_Y; 2925#if 0 2926 if (sc->ti_hwrev != TI_HWREV_TIGON) 2927 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2928#endif 2929 2930 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2931 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 2932 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2933 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2934 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2935 break; 2936 case IFM_1000_SX: 2937 case IFM_1000_T: 2938 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2939#if 0 2940 if (sc->ti_hwrev != TI_HWREV_TIGON) 2941 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2942#endif 2943 2944 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2945 flowctl |TI_GLNK_ENB); 2946 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2947 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2948 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2949 } 2950 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2951 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2952 break; 2953 case IFM_100_FX: 2954 case IFM_10_FL: 2955 case IFM_100_TX: 2956 case IFM_10_T: 2957 flowctl = TI_LNK_RX_FLOWCTL_Y; 2958#if 0 2959 if (sc->ti_hwrev != TI_HWREV_TIGON) 2960 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2961#endif 2962 2963 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2964 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 2965 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2966 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2967 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2968 } else { 2969 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2970 } 2971 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2972 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2973 } else { 2974 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2975 } 2976 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2977 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2978 break; 2979 } 2980 2981 return(0); 2982} 2983 2984/* 2985 * Report current media status. 2986 */ 2987static void 2988ti_ifmedia_sts(ifp, ifmr) 2989 struct ifnet *ifp; 2990 struct ifmediareq *ifmr; 2991{ 2992 struct ti_softc *sc; 2993 u_int32_t media = 0; 2994 2995 sc = ifp->if_softc; 2996 2997 ifmr->ifm_status = IFM_AVALID; 2998 ifmr->ifm_active = IFM_ETHER; 2999 3000 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3001 return; 3002 3003 ifmr->ifm_status |= IFM_ACTIVE; 3004 3005 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3006 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3007 if (sc->ti_copper) 3008 ifmr->ifm_active |= IFM_1000_T; 3009 else 3010 ifmr->ifm_active |= IFM_1000_SX; 3011 if (media & TI_GLNK_FULL_DUPLEX) 3012 ifmr->ifm_active |= IFM_FDX; 3013 else 3014 ifmr->ifm_active |= IFM_HDX; 3015 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3016 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3017 if (sc->ti_copper) { 3018 if (media & TI_LNK_100MB) 3019 ifmr->ifm_active |= IFM_100_TX; 3020 if (media & TI_LNK_10MB) 3021 ifmr->ifm_active |= IFM_10_T; 3022 } else { 3023 if (media & TI_LNK_100MB) 3024 ifmr->ifm_active |= IFM_100_FX; 3025 if (media & TI_LNK_10MB) 3026 ifmr->ifm_active |= IFM_10_FL; 3027 } 3028 if (media & TI_LNK_FULL_DUPLEX) 3029 ifmr->ifm_active |= IFM_FDX; 3030 if (media & TI_LNK_HALF_DUPLEX) 3031 ifmr->ifm_active |= IFM_HDX; 3032 } 3033 3034 return; 3035} 3036 3037static int 3038ti_ioctl(ifp, command, data) 3039 struct ifnet *ifp; 3040 u_long command; 3041 caddr_t data; 3042{ 3043 struct ti_softc *sc = ifp->if_softc; 3044 struct ifreq *ifr = (struct ifreq *) data; 3045 int mask, error = 0; 3046 struct ti_cmd_desc cmd; 3047 3048 TI_LOCK(sc); 3049 3050 switch(command) { 3051 case SIOCSIFMTU: 3052 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3053 error = EINVAL; 3054 else { 3055 ifp->if_mtu = ifr->ifr_mtu; 3056 ti_init(sc); 3057 } 3058 break; 3059 case SIOCSIFFLAGS: 3060 if (ifp->if_flags & IFF_UP) { 3061 /* 3062 * If only the state of the PROMISC flag changed, 3063 * then just use the 'set promisc mode' command 3064 * instead of reinitializing the entire NIC. Doing 3065 * a full re-init means reloading the firmware and 3066 * waiting for it to start up, which may take a 3067 * second or two. 3068 */ 3069 if (ifp->if_flags & IFF_RUNNING && 3070 ifp->if_flags & IFF_PROMISC && 3071 !(sc->ti_if_flags & IFF_PROMISC)) { 3072 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3073 TI_CMD_CODE_PROMISC_ENB, 0); 3074 } else if (ifp->if_flags & IFF_RUNNING && 3075 !(ifp->if_flags & IFF_PROMISC) && 3076 sc->ti_if_flags & IFF_PROMISC) { 3077 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3078 TI_CMD_CODE_PROMISC_DIS, 0); 3079 } else 3080 ti_init(sc); 3081 } else { 3082 if (ifp->if_flags & IFF_RUNNING) { 3083 ti_stop(sc); 3084 } 3085 } 3086 sc->ti_if_flags = ifp->if_flags; 3087 error = 0; 3088 break; 3089 case SIOCADDMULTI: 3090 case SIOCDELMULTI: 3091 if (ifp->if_flags & IFF_RUNNING) { 3092 ti_setmulti(sc); 3093 error = 0; 3094 } 3095 break; 3096 case SIOCSIFMEDIA: 3097 case SIOCGIFMEDIA: 3098 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3099 break; 3100 case SIOCSIFCAP: 3101 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3102 if (mask & IFCAP_HWCSUM) { 3103 if (IFCAP_HWCSUM & ifp->if_capenable) 3104 ifp->if_capenable &= ~IFCAP_HWCSUM; 3105 else 3106 ifp->if_capenable |= IFCAP_HWCSUM; 3107 if (ifp->if_flags & IFF_RUNNING) 3108 ti_init(sc); 3109 } 3110 error = 0; 3111 break; 3112 default: 3113 error = ether_ioctl(ifp, command, data); 3114 break; 3115 } 3116 3117 TI_UNLOCK(sc); 3118 3119 return(error); 3120} 3121 3122static int 3123ti_open(dev_t dev, int flags, int fmt, struct thread *td) 3124{ 3125 struct ti_softc *sc; 3126 3127 sc = dev->si_drv1; 3128 if (sc == NULL) 3129 return(ENODEV); 3130 3131 TI_LOCK(sc); 3132 sc->ti_flags |= TI_FLAG_DEBUGING; 3133 TI_UNLOCK(sc); 3134 3135 return(0); 3136} 3137 3138static int 3139ti_close(dev_t dev, int flag, int fmt, struct thread *td) 3140{ 3141 struct ti_softc *sc; 3142 3143 sc = dev->si_drv1; 3144 if (sc == NULL) 3145 return(ENODEV); 3146 3147 TI_LOCK(sc); 3148 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3149 TI_UNLOCK(sc); 3150 3151 return(0); 3152} 3153 3154/* 3155 * This ioctl routine goes along with the Tigon character device. 3156 */ 3157static int 3158ti_ioctl2(dev_t dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3159{ 3160 int error; 3161 struct ti_softc *sc; 3162 3163 sc = dev->si_drv1; 3164 if (sc == NULL) 3165 return(ENODEV); 3166 3167 error = 0; 3168 3169 switch(cmd) { 3170 case TIIOCGETSTATS: 3171 { 3172 struct ti_stats *outstats; 3173 3174 outstats = (struct ti_stats *)addr; 3175 3176 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3177 sizeof(struct ti_stats)); 3178 break; 3179 } 3180 case TIIOCGETPARAMS: 3181 { 3182 struct ti_params *params; 3183 3184 params = (struct ti_params *)addr; 3185 3186 params->ti_stat_ticks = sc->ti_stat_ticks; 3187 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3188 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3189 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3190 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3191 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3192 params->param_mask = TI_PARAM_ALL; 3193 3194 error = 0; 3195 3196 break; 3197 } 3198 case TIIOCSETPARAMS: 3199 { 3200 struct ti_params *params; 3201 3202 params = (struct ti_params *)addr; 3203 3204 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3205 sc->ti_stat_ticks = params->ti_stat_ticks; 3206 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3207 } 3208 3209 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3210 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3211 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3212 sc->ti_rx_coal_ticks); 3213 } 3214 3215 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3216 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3217 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3218 sc->ti_tx_coal_ticks); 3219 } 3220 3221 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3222 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3223 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3224 sc->ti_rx_max_coal_bds); 3225 } 3226 3227 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3228 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3229 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3230 sc->ti_tx_max_coal_bds); 3231 } 3232 3233 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3234 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3235 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3236 sc->ti_tx_buf_ratio); 3237 } 3238 3239 error = 0; 3240 3241 break; 3242 } 3243 case TIIOCSETTRACE: { 3244 ti_trace_type trace_type; 3245 3246 trace_type = *(ti_trace_type *)addr; 3247 3248 /* 3249 * Set tracing to whatever the user asked for. Setting 3250 * this register to 0 should have the effect of disabling 3251 * tracing. 3252 */ 3253 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3254 3255 error = 0; 3256 3257 break; 3258 } 3259 case TIIOCGETTRACE: { 3260 struct ti_trace_buf *trace_buf; 3261 u_int32_t trace_start, cur_trace_ptr, trace_len; 3262 3263 trace_buf = (struct ti_trace_buf *)addr; 3264 3265 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3266 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3267 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3268 3269#if 0 3270 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3271 "trace_len = %d\n", sc->ti_unit, trace_start, 3272 cur_trace_ptr, trace_len); 3273 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3274 trace_buf->buf_len); 3275#endif 3276 3277 error = ti_copy_mem(sc, trace_start, min(trace_len, 3278 trace_buf->buf_len), 3279 (caddr_t)trace_buf->buf, 1, 1); 3280 3281 if (error == 0) { 3282 trace_buf->fill_len = min(trace_len, 3283 trace_buf->buf_len); 3284 if (cur_trace_ptr < trace_start) 3285 trace_buf->cur_trace_ptr = 3286 trace_start - cur_trace_ptr; 3287 else 3288 trace_buf->cur_trace_ptr = 3289 cur_trace_ptr - trace_start; 3290 } else 3291 trace_buf->fill_len = 0; 3292 3293 3294 break; 3295 } 3296 3297 /* 3298 * For debugging, five ioctls are needed: 3299 * ALT_ATTACH 3300 * ALT_READ_TG_REG 3301 * ALT_WRITE_TG_REG 3302 * ALT_READ_TG_MEM 3303 * ALT_WRITE_TG_MEM 3304 */ 3305 case ALT_ATTACH: 3306 /* 3307 * From what I can tell, Alteon's Solaris Tigon driver 3308 * only has one character device, so you have to attach 3309 * to the Tigon board you're interested in. This seems 3310 * like a not-so-good way to do things, since unless you 3311 * subsequently specify the unit number of the device 3312 * you're interested in in every ioctl, you'll only be 3313 * able to debug one board at a time. 3314 */ 3315 error = 0; 3316 break; 3317 case ALT_READ_TG_MEM: 3318 case ALT_WRITE_TG_MEM: 3319 { 3320 struct tg_mem *mem_param; 3321 u_int32_t sram_end, scratch_end; 3322 3323 mem_param = (struct tg_mem *)addr; 3324 3325 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3326 sram_end = TI_END_SRAM_I; 3327 scratch_end = TI_END_SCRATCH_I; 3328 } else { 3329 sram_end = TI_END_SRAM_II; 3330 scratch_end = TI_END_SCRATCH_II; 3331 } 3332 3333 /* 3334 * For now, we'll only handle accessing regular SRAM, 3335 * nothing else. 3336 */ 3337 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3338 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3339 /* 3340 * In this instance, we always copy to/from user 3341 * space, so the user space argument is set to 1. 3342 */ 3343 error = ti_copy_mem(sc, mem_param->tgAddr, 3344 mem_param->len, 3345 mem_param->userAddr, 1, 3346 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3347 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3348 && (mem_param->tgAddr <= scratch_end)) { 3349 error = ti_copy_scratch(sc, mem_param->tgAddr, 3350 mem_param->len, 3351 mem_param->userAddr, 1, 3352 (cmd == ALT_READ_TG_MEM) ? 3353 1 : 0, TI_PROCESSOR_A); 3354 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3355 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3356 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3357 printf("ti%d: invalid memory range for " 3358 "Tigon I\n", sc->ti_unit); 3359 error = EINVAL; 3360 break; 3361 } 3362 error = ti_copy_scratch(sc, mem_param->tgAddr - 3363 TI_SCRATCH_DEBUG_OFF, 3364 mem_param->len, 3365 mem_param->userAddr, 1, 3366 (cmd == ALT_READ_TG_MEM) ? 3367 1 : 0, TI_PROCESSOR_B); 3368 } else { 3369 printf("ti%d: memory address %#x len %d is out of " 3370 "supported range\n", sc->ti_unit, 3371 mem_param->tgAddr, mem_param->len); 3372 error = EINVAL; 3373 } 3374 3375 break; 3376 } 3377 case ALT_READ_TG_REG: 3378 case ALT_WRITE_TG_REG: 3379 { 3380 struct tg_reg *regs; 3381 u_int32_t tmpval; 3382 3383 regs = (struct tg_reg *)addr; 3384 3385 /* 3386 * Make sure the address in question isn't out of range. 3387 */ 3388 if (regs->addr > TI_REG_MAX) { 3389 error = EINVAL; 3390 break; 3391 } 3392 if (cmd == ALT_READ_TG_REG) { 3393 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3394 regs->addr, &tmpval, 1); 3395 regs->data = ntohl(tmpval); 3396#if 0 3397 if ((regs->addr == TI_CPU_STATE) 3398 || (regs->addr == TI_CPU_CTL_B)) { 3399 printf("ti%d: register %#x = %#x\n", 3400 sc->ti_unit, regs->addr, tmpval); 3401 } 3402#endif 3403 } else { 3404 tmpval = htonl(regs->data); 3405 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3406 regs->addr, &tmpval, 1); 3407 } 3408 3409 break; 3410 } 3411 default: 3412 error = ENOTTY; 3413 break; 3414 } 3415 return(error); 3416} 3417 3418static void 3419ti_watchdog(ifp) 3420 struct ifnet *ifp; 3421{ 3422 struct ti_softc *sc; 3423 3424 sc = ifp->if_softc; 3425 TI_LOCK(sc); 3426 3427 /* 3428 * When we're debugging, the chip is often stopped for long periods 3429 * of time, and that would normally cause the watchdog timer to fire. 3430 * Since that impedes debugging, we don't want to do that. 3431 */ 3432 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3433 TI_UNLOCK(sc); 3434 return; 3435 } 3436 3437 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3438 ti_stop(sc); 3439 ti_init(sc); 3440 3441 ifp->if_oerrors++; 3442 TI_UNLOCK(sc); 3443 3444 return; 3445} 3446 3447/* 3448 * Stop the adapter and free any mbufs allocated to the 3449 * RX and TX lists. 3450 */ 3451static void 3452ti_stop(sc) 3453 struct ti_softc *sc; 3454{ 3455 struct ifnet *ifp; 3456 struct ti_cmd_desc cmd; 3457 3458 TI_LOCK(sc); 3459 3460 ifp = &sc->arpcom.ac_if; 3461 3462 /* Disable host interrupts. */ 3463 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3464 /* 3465 * Tell firmware we're shutting down. 3466 */ 3467 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3468 3469 /* Halt and reinitialize. */ 3470 ti_chipinit(sc); 3471 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3472 ti_chipinit(sc); 3473 3474 /* Free the RX lists. */ 3475 ti_free_rx_ring_std(sc); 3476 3477 /* Free jumbo RX list. */ 3478 ti_free_rx_ring_jumbo(sc); 3479 3480 /* Free mini RX list. */ 3481 ti_free_rx_ring_mini(sc); 3482 3483 /* Free TX buffers. */ 3484 ti_free_tx_ring(sc); 3485 3486 sc->ti_ev_prodidx.ti_idx = 0; 3487 sc->ti_return_prodidx.ti_idx = 0; 3488 sc->ti_tx_considx.ti_idx = 0; 3489 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3490 3491 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3492 TI_UNLOCK(sc); 3493 3494 return; 3495} 3496 3497/* 3498 * Stop all chip I/O so that the kernel's probe routines don't 3499 * get confused by errant DMAs when rebooting. 3500 */ 3501static void 3502ti_shutdown(dev) 3503 device_t dev; 3504{ 3505 struct ti_softc *sc; 3506 3507 sc = device_get_softc(dev); 3508 TI_LOCK(sc); 3509 ti_chipinit(sc); 3510 TI_UNLOCK(sc); 3511 3512 return; 3513} 3514