if_stgereg.h revision 169158
1/* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* $FreeBSD: head/sys/dev/stge/if_stgereg.h 169158 2007-05-01 03:35:48Z yongari $ */ 40 41/* 42 * Sundance Technology PCI vendor ID 43 */ 44#define VENDOR_SUNDANCETI 0x13f0 45 46/* 47 * Tamarack Microelectronics PCI vendor ID 48 */ 49#define VENDOR_TAMARACK 0x143d 50 51/* 52 * D-Link Systems PCI vendor ID 53 */ 54#define VENDOR_DLINK 0x1186 55 56/* 57 * Antares Microsystems PCI vendor ID 58 */ 59#define VENDOR_ANTARES 0x1754 60 61/* 62 * Sundance Technology device ID 63 */ 64#define DEVICEID_SUNDANCETI_ST1023 0x1023 65#define DEVICEID_SUNDANCETI_ST2021 0x2021 66#define DEVICEID_TAMARACK_TC9021 0x1021 67#define DEVICEID_TAMARACK_TC9021_ALT 0x9021 68 69/* 70 * D-Link Systems device ID 71 */ 72#define DEVICEID_DLINK_DL4000 0x4000 73 74/* 75 * Antares Microsystems device ID 76 */ 77#define DEVICEID_ANTARES_TC9021 0x1021 78 79/* 80 * Register description for the Sundance Tech. TC9021 10/100/1000 81 * Ethernet controller. 82 * 83 * Note that while DMA addresses are all in 64-bit fields, only 84 * the lower 40 bits of a DMA address are valid. 85 */ 86#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 87#define STGE_DMA_MAXADDR BUS_SPACE_MAXADDR 88#else 89#define STGE_DMA_MAXADDR 0xFFFFFFFFFF 90#endif 91 92/* 93 * Register access macros 94 */ 95#define CSR_WRITE_4(_sc, reg, val) \ 96 bus_write_4((_sc)->sc_res[0], (reg), (val)) 97#define CSR_WRITE_2(_sc, reg, val) \ 98 bus_write_2((_sc)->sc_res[0], (reg), (val)) 99#define CSR_WRITE_1(_sc, reg, val) \ 100 bus_write_1((_sc)->sc_res[0], (reg), (val)) 101 102#define CSR_READ_4(_sc, reg) \ 103 bus_read_4((_sc)->sc_res[0], (reg)) 104#define CSR_READ_2(_sc, reg) \ 105 bus_read_2((_sc)->sc_res[0], (reg)) 106#define CSR_READ_1(_sc, reg) \ 107 bus_read_1((_sc)->sc_res[0], (reg)) 108 109/* 110 * TC9021 buffer fragment descriptor. 111 */ 112struct stge_frag { 113 uint64_t frag_word0; /* address, length */ 114}; 115 116#define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 117#define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 118#define FRAG_LEN(x) (((uint64_t)(x)) << 48) 119#define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 120 121/* 122 * TC9021 Transmit Frame Descriptor. Note the number of fragments 123 * here is arbitrary, but we can't have any more than 15. 124 */ 125#define STGE_NTXFRAGS 15 126struct stge_tfd { 127 uint64_t tfd_next; /* next TFD in list */ 128 uint64_t tfd_control; /* control bits */ 129 /* the buffer fragments */ 130 struct stge_frag tfd_frags[STGE_NTXFRAGS]; 131}; 132 133#define TFD_FrameId(x) ((x) << 0) 134#define TFD_FrameId_MAX 0xffff 135#define TFD_WordAlign(x) ((x) << 16) 136#define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 137#define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 138#define TFD_WordAlign_disable 1 /* disable alignment */ 139#define TFD_TCPChecksumEnable (1ULL << 18) 140#define TFD_UDPChecksumEnable (1ULL << 19) 141#define TFD_IPChecksumEnable (1ULL << 20) 142#define TFD_FcsAppendDisable (1ULL << 21) 143#define TFD_TxIndicate (1ULL << 22) 144#define TFD_TxDMAIndicate (1ULL << 23) 145#define TFD_FragCount(x) ((x) << 24) 146#define TFD_VLANTagInsert (1ULL << 28) 147#define TFD_TFDDone (1ULL << 31) 148#define TFD_VID(x) (((uint64_t)(x)) << 32) 149#define TFD_CFI (1ULL << 44) 150#define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 151 152/* 153 * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 154 * in it, and the chip tells us the beginning and end of the frame. 155 */ 156struct stge_rfd { 157 uint64_t rfd_next; /* next RFD in list */ 158 uint64_t rfd_status; /* status bits */ 159 struct stge_frag rfd_frag; /* the buffer */ 160}; 161 162/* Low word of rfd_status */ 163#define RFD_RxStatus(x) ((x) & 0xffffffff) 164#define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 165#define RFD_RxFIFOOverrun 0x00010000 166#define RFD_RxRuntFrame 0x00020000 167#define RFD_RxAlignmentError 0x00040000 168#define RFD_RxFCSError 0x00080000 169#define RFD_RxOversizedFrame 0x00100000 170#define RFD_RxLengthError 0x00200000 171#define RFD_VLANDetected 0x00400000 172#define RFD_TCPDetected 0x00800000 173#define RFD_TCPError 0x01000000 174#define RFD_UDPDetected 0x02000000 175#define RFD_UDPError 0x04000000 176#define RFD_IPDetected 0x08000000 177#define RFD_IPError 0x10000000 178#define RFD_FrameStart 0x20000000 179#define RFD_FrameEnd 0x40000000 180#define RFD_RFDDone 0x80000000 181/* High word of rfd_status */ 182#define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 183 184/* 185 * EEPROM offsets. 186 */ 187#define STGE_EEPROM_ConfigParam 0x00 188#define STGE_EEPROM_AsicCtrl 0x01 189#define STGE_EEPROM_SubSystemVendorId 0x02 190#define STGE_EEPROM_SubSystemId 0x03 191#define STGE_EEPROM_LEDMode 0x06 192#define STGE_EEPROM_StationAddress0 0x10 193#define STGE_EEPROM_StationAddress1 0x11 194#define STGE_EEPROM_StationAddress2 0x12 195 196/* 197 * The TC9021 register space. 198 */ 199 200#define STGE_DMACtrl 0x00 201#define DMAC_RxDMAComplete (1U << 3) 202#define DMAC_RxDMAPollNow (1U << 4) 203#define DMAC_TxDMAComplete (1U << 11) 204#define DMAC_TxDMAPollNow (1U << 12) 205#define DMAC_TxDMAInProg (1U << 15) 206#define DMAC_RxEarlyDisable (1U << 16) 207#define DMAC_MWIDisable (1U << 18) 208#define DMAC_TxWriteBackDisable (1U << 19) 209#define DMAC_TxBurstLimit(x) ((x) << 20) 210#define DMAC_TargetAbort (1U << 30) 211#define DMAC_MasterAbort (1U << 31) 212 213#define STGE_RxDMAStatus 0x08 214 215#define STGE_TFDListPtrLo 0x10 216 217#define STGE_TFDListPtrHi 0x14 218 219#define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 220 221#define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 222 223#define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */ 224 225#define STGE_RFDListPtrLo 0x1c 226 227#define STGE_RFDListPtrHi 0x20 228 229#define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 230 231#define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 232 233#define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */ 234 235#define STGE_RxDMAIntCtrl 0x28 236#define RDIC_RxFrameCount(x) ((x) & 0xff) 237#define RDIC_PriorityThresh(x) ((x) << 10) 238#define RDIC_RxDMAWaitTime(x) ((x) << 16) 239/* 240 * Number of receive frames transferred via DMA before a Rx interrupt is issued. 241 */ 242#define STGE_RXINT_NFRAME_DEFAULT 8 243#define STGE_RXINT_NFRAME_MIN 1 244#define STGE_RXINT_NFRAME_MAX 255 245/* 246 * Maximum amount of time (in 64ns increments) to wait before issuing a Rx 247 * interrupt if number of frames recevied is less than STGE_RXINT_NFRAME 248 * (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX) 249 */ 250#define STGE_RXINT_DMAWAIT_DEFAULT 30 /* 30us */ 251#define STGE_RXINT_DMAWAIT_MIN 0 252#define STGE_RXINT_DMAWAIT_MAX 4194 253#define STGE_RXINT_USECS2TICK(x) (((x) * 1000)/64) 254 255#define STGE_DebugCtrl 0x2c /* 16-bit */ 256#define DC_GPIO0Ctrl (1U << 0) 257#define DC_GPIO1Ctrl (1U << 1) 258#define DC_GPIO0 (1U << 2) 259#define DC_GPIO1 (1U << 3) 260 261#define STGE_AsicCtrl 0x30 262#define AC_ExpRomDisable (1U << 0) 263#define AC_ExpRomSize (1U << 1) 264#define AC_PhySpeed10 (1U << 4) 265#define AC_PhySpeed100 (1U << 5) 266#define AC_PhySpeed1000 (1U << 6) 267#define AC_PhyMedia (1U << 7) 268#define AC_ForcedConfig(x) ((x) << 8) 269#define AC_ForcedConfig_MASK AC_ForcedConfig(7) 270#define AC_D3ResetDisable (1U << 11) 271#define AC_SpeedupMode (1U << 13) 272#define AC_LEDMode (1U << 14) 273#define AC_RstOutPolarity (1U << 15) 274#define AC_GlobalReset (1U << 16) 275#define AC_RxReset (1U << 17) 276#define AC_TxReset (1U << 18) 277#define AC_DMA (1U << 19) 278#define AC_FIFO (1U << 20) 279#define AC_Network (1U << 21) 280#define AC_Host (1U << 22) 281#define AC_AutoInit (1U << 23) 282#define AC_RstOut (1U << 24) 283#define AC_InterruptRequest (1U << 25) 284#define AC_ResetBusy (1U << 26) 285#define AC_LEDSpeed (1U << 27) 286#define AC_LEDModeBit1 (1U << 29) 287 288#define STGE_FIFOCtrl 0x38 /* 16-bit */ 289#define FC_RAMTestMode (1U << 0) 290#define FC_Transmitting (1U << 14) 291#define FC_Receiving (1U << 15) 292 293#define STGE_RxEarlyThresh 0x3a /* 16-bit */ 294 295#define STGE_FlowOffThresh 0x3c /* 16-bit */ 296 297#define STGE_FlowOnTresh 0x3e /* 16-bit */ 298 299#define STGE_TxStartThresh 0x44 /* 16-bit */ 300 301#define STGE_EepromData 0x48 /* 16-bit */ 302 303#define STGE_EepromCtrl 0x4a /* 16-bit */ 304#define EC_EepromAddress(x) ((x) & 0xff) 305#define EC_EepromOpcode(x) ((x) << 8) 306#define EC_OP_WE 0 307#define EC_OP_WR 1 308#define EC_OP_RR 2 309#define EC_OP_ER 3 310#define EC_EepromBusy (1U << 15) 311 312#define STGE_ExpRomAddr 0x4c 313 314#define STGE_ExpRomData 0x50 /* 8-bit */ 315 316#define STGE_WakeEvent 0x51 /* 8-bit */ 317 318#define STGE_Countdown 0x54 319#define CD_Count(x) ((x) & 0xffff) 320#define CD_CountdownSpeed (1U << 24) 321#define CD_CountdownMode (1U << 25) 322#define CD_CountdownIntEnabled (1U << 26) 323 324#define STGE_IntStatusAck 0x5a /* 16-bit */ 325 326#define STGE_IntEnable 0x5c /* 16-bit */ 327 328#define STGE_IntStatus 0x5e /* 16-bit */ 329 330#define IS_InterruptStatus (1U << 0) 331#define IS_HostError (1U << 1) 332#define IS_TxComplete (1U << 2) 333#define IS_MACControlFrame (1U << 3) 334#define IS_RxComplete (1U << 4) 335#define IS_RxEarly (1U << 5) 336#define IS_InRequested (1U << 6) 337#define IS_UpdateStats (1U << 7) 338#define IS_LinkEvent (1U << 8) 339#define IS_TxDMAComplete (1U << 9) 340#define IS_RxDMAComplete (1U << 10) 341#define IS_RFDListEnd (1U << 11) 342#define IS_RxDMAPriority (1U << 12) 343 344#define STGE_TxStatus 0x60 345#define TS_TxError (1U << 0) 346#define TS_LateCollision (1U << 2) 347#define TS_MaxCollisions (1U << 3) 348#define TS_TxUnderrun (1U << 4) 349#define TS_TxIndicateReqd (1U << 6) 350#define TS_TxComplete (1U << 7) 351#define TS_TxFrameId_get(x) ((x) >> 16) 352 353#define STGE_MACCtrl 0x6c 354#define MC_IFSSelect(x) ((x) & 3) 355#define MC_IFS96bit 0 356#define MC_IFS1024bit 1 357#define MC_IFS1792bit 2 358#define MC_IFS4352bit 3 359 360#define MC_DuplexSelect (1U << 5) 361#define MC_RcvLargeFrames (1U << 6) 362#define MC_TxFlowControlEnable (1U << 7) 363#define MC_RxFlowControlEnable (1U << 8) 364#define MC_RcvFCS (1U << 9) 365#define MC_FIFOLoopback (1U << 10) 366#define MC_MACLoopback (1U << 11) 367#define MC_AutoVLANtagging (1U << 12) 368#define MC_AutoVLANuntagging (1U << 13) 369#define MC_CollisionDetect (1U << 16) 370#define MC_CarrierSense (1U << 17) 371#define MC_StatisticsEnable (1U << 21) 372#define MC_StatisticsDisable (1U << 22) 373#define MC_StatisticsEnabled (1U << 23) 374#define MC_TxEnable (1U << 24) 375#define MC_TxDisable (1U << 25) 376#define MC_TxEnabled (1U << 26) 377#define MC_RxEnable (1U << 27) 378#define MC_RxDisable (1U << 28) 379#define MC_RxEnabled (1U << 29) 380#define MC_Paused (1U << 30) 381#define MC_MASK 0x7fe33fa3 382 383#define STGE_VLANTag 0x70 384 385#define STGE_PhySet 0x75 /* 8-bit */ 386#define PS_MemLenb9b (1U << 0) 387#define PS_MemLen (1U << 1) 388#define PS_NonCompdet (1U << 2) 389 390#define STGE_PhyCtrl 0x76 /* 8-bit */ 391#define PC_MgmtClk (1U << 0) 392#define PC_MgmtData (1U << 1) 393#define PC_MgmtDir (1U << 2) /* MAC->PHY */ 394#define PC_PhyDuplexPolarity (1U << 3) 395#define PC_PhyDuplexStatus (1U << 4) 396#define PC_PhyLnkPolarity (1U << 5) 397#define PC_LinkSpeed(x) (((x) >> 6) & 3) 398#define PC_LinkSpeed_Down 0 399#define PC_LinkSpeed_10 1 400#define PC_LinkSpeed_100 2 401#define PC_LinkSpeed_1000 3 402 403#define STGE_StationAddress0 0x78 /* 16-bit */ 404 405#define STGE_StationAddress1 0x7a /* 16-bit */ 406 407#define STGE_StationAddress2 0x7c /* 16-bit */ 408 409#define STGE_VLANHashTable 0x7e /* 16-bit */ 410 411#define STGE_VLANId 0x80 412 413#define STGE_MaxFrameSize 0x86 414 415#define STGE_ReceiveMode 0x88 /* 16-bit */ 416#define RM_ReceiveUnicast (1U << 0) 417#define RM_ReceiveMulticast (1U << 1) 418#define RM_ReceiveBroadcast (1U << 2) 419#define RM_ReceiveAllFrames (1U << 3) 420#define RM_ReceiveMulticastHash (1U << 4) 421#define RM_ReceiveIPMulticast (1U << 5) 422#define RM_ReceiveVLANMatch (1U << 8) 423#define RM_ReceiveVLANHash (1U << 9) 424 425#define STGE_HashTable0 0x8c 426 427#define STGE_HashTable1 0x90 428 429#define STGE_RMONStatisticsMask 0x98 /* set to disable */ 430 431#define STGE_StatisticsMask 0x9c /* set to disable */ 432 433#define STGE_RxJumboFrames 0xbc /* 16-bit */ 434 435#define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 436 437#define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 438 439#define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 440 441#define STGE_TxJumboFrames 0xf4 /* 16-bit */ 442 443/* 444 * TC9021 statistics. Available memory and I/O mapped. 445 */ 446 447#define STGE_OctetRcvOk 0xa8 448 449#define STGE_McstOctetRcvdOk 0xac 450 451#define STGE_BcstOctetRcvdOk 0xb0 452 453#define STGE_FramesRcvdOk 0xb4 454 455#define STGE_McstFramesRcvdOk 0xb8 456 457#define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 458 459#define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 460 461#define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 462 463#define STGE_InRangeLengthErrors 0xca /* 16-bit */ 464 465#define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 466 467#define STGE_FramesLostRxErrors 0xce /* 16-bit */ 468 469#define STGE_OctetXmtdOk 0xd0 470 471#define STGE_McstOctetXmtdOk 0xd4 472 473#define STGE_BcstOctetXmtdOk 0xd8 474 475#define STGE_FramesXmtdOk 0xdc 476 477#define STGE_McstFramesXmtdOk 0xe0 478 479#define STGE_FramesWDeferredXmt 0xe4 480 481#define STGE_LateCollisions 0xe8 482 483#define STGE_MultiColFrames 0xec 484 485#define STGE_SingleColFrames 0xf0 486 487#define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 488 489#define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 490 491#define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 492 493#define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 494 495#define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 496 497/* 498 * RMON-compatible statistics. Only accessible if memory-mapped. 499 */ 500 501#define STGE_EtherStatsCollisions 0x100 502 503#define STGE_EtherStatsOctetsTransmit 0x104 504 505#define STGE_EtherStatsPktsTransmit 0x108 506 507#define STGE_EtherStatsPkts64OctetsTransmit 0x10c 508 509#define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 510 511#define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 512 513#define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 514 515#define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 516 517#define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 518 519#define STGE_EtherStatsCRCAlignErrors 0x124 520 521#define STGE_EtherStatsUndersizePkts 0x128 522 523#define STGE_EtherStatsFragments 0x12c 524 525#define STGE_EtherStatsJabbers 0x130 526 527#define STGE_EtherStatsOctets 0x134 528 529#define STGE_EtherStatsPkts 0x138 530 531#define STGE_EtherStatsPkts64Octets 0x13c 532 533#define STGE_EtherStatsPkts65to127Octets 0x140 534 535#define STGE_EtherStatsPkts128to255Octets 0x144 536 537#define STGE_EtherStatsPkts256to511Octets 0x148 538 539#define STGE_EtherStatsPkts512to1023Octets 0x14c 540 541#define STGE_EtherStatsPkts1024to1518Octets 0x150 542 543/* 544 * Transmit descriptor list size. 545 */ 546#define STGE_TX_RING_CNT 256 547#define STGE_TX_LOWAT (STGE_TX_RING_CNT/32) 548#define STGE_TX_HIWAT (STGE_TX_RING_CNT - STGE_TX_LOWAT) 549 550/* 551 * Receive descriptor list size. 552 */ 553#define STGE_RX_RING_CNT 256 554 555#define STGE_MAXTXSEGS STGE_NTXFRAGS 556 557#define STGE_JUMBO_FRAMELEN 9022 558#define STGE_JUMBO_MTU \ 559 (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 560 561struct stge_txdesc { 562 struct mbuf *tx_m; /* head of our mbuf chain */ 563 bus_dmamap_t tx_dmamap; /* our DMA map */ 564 STAILQ_ENTRY(stge_txdesc) tx_q; 565}; 566 567STAILQ_HEAD(stge_txdq, stge_txdesc); 568 569struct stge_rxdesc { 570 struct mbuf *rx_m; 571 bus_dmamap_t rx_dmamap; 572}; 573 574#define STGE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 575#define STGE_ADDR_HI(x) ((u_int64_t) (x) >> 32) 576 577#define STGE_RING_ALIGN 8 578 579struct stge_chain_data{ 580 bus_dma_tag_t stge_parent_tag; 581 bus_dma_tag_t stge_tx_tag; 582 struct stge_txdesc stge_txdesc[STGE_TX_RING_CNT]; 583 struct stge_txdq stge_txfreeq; 584 struct stge_txdq stge_txbusyq; 585 bus_dma_tag_t stge_rx_tag; 586 struct stge_rxdesc stge_rxdesc[STGE_RX_RING_CNT]; 587 bus_dma_tag_t stge_tx_ring_tag; 588 bus_dmamap_t stge_tx_ring_map; 589 bus_dma_tag_t stge_rx_ring_tag; 590 bus_dmamap_t stge_rx_ring_map; 591 bus_dmamap_t stge_rx_sparemap; 592 593 int stge_tx_prod; 594 int stge_tx_cons; 595 int stge_tx_cnt; 596 int stge_rx_cons; 597#ifdef DEVICE_POLLING 598 int stge_rxcycles; 599#endif 600 int stge_rxlen; 601 struct mbuf *stge_rxhead; 602 struct mbuf *stge_rxtail; 603}; 604 605struct stge_ring_data { 606 struct stge_tfd *stge_tx_ring; 607 bus_addr_t stge_tx_ring_paddr; 608 struct stge_rfd *stge_rx_ring; 609 bus_addr_t stge_rx_ring_paddr; 610}; 611 612#define STGE_TX_RING_ADDR(sc, i) \ 613 ((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i)) 614#define STGE_RX_RING_ADDR(sc, i) \ 615 ((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i)) 616 617#define STGE_TX_RING_SZ \ 618 (sizeof(struct stge_tfd) * STGE_TX_RING_CNT) 619#define STGE_RX_RING_SZ \ 620 (sizeof(struct stge_rfd) * STGE_RX_RING_CNT) 621 622/* 623 * Software state per device. 624 */ 625struct stge_softc { 626 struct ifnet *sc_ifp; /* interface info */ 627 device_t sc_dev; 628 device_t sc_miibus; 629 struct resource *sc_res[2]; 630 struct resource_spec *sc_spec; 631 void *sc_ih; /* interrupt cookie */ 632 int sc_rev; /* silicon revision */ 633 634 struct callout sc_tick_ch; /* tick callout */ 635 636 struct stge_chain_data sc_cdata; 637 struct stge_ring_data sc_rdata; 638 int sc_if_flags; 639 int sc_if_framesize; 640 int sc_txthresh; /* Tx threshold */ 641 uint32_t sc_usefiber:1; /* if we're fiber */ 642 uint32_t sc_stge1023:1; /* are we a 1023 */ 643 uint32_t sc_DMACtrl; /* prototype DMACtrl reg. */ 644 uint32_t sc_MACCtrl; /* prototype MacCtrl reg. */ 645 uint16_t sc_IntEnable; /* prototype IntEnable reg. */ 646 uint16_t sc_led; /* LED conf. from EEPROM */ 647 uint8_t sc_PhyCtrl; /* prototype PhyCtrl reg. */ 648 int sc_suspended; 649 int sc_detach; 650 651 int sc_rxint_nframe; 652 int sc_rxint_dmawait; 653 int sc_nerr; 654 int sc_watchdog_timer; 655 int sc_link; 656 657 struct task sc_link_task; 658 struct mtx sc_mii_mtx; /* MII mutex */ 659 struct mtx sc_mtx; 660}; 661 662#define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 663#define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 664#define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 665#define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx) 666#define STGE_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mii_mtx) 667 668#define STGE_MAXERR 5 669 670#define STGE_RXCHAIN_RESET(_sc) \ 671do { \ 672 (_sc)->sc_cdata.stge_rxhead = NULL; \ 673 (_sc)->sc_cdata.stge_rxtail = NULL; \ 674 (_sc)->sc_cdata.stge_rxlen = 0; \ 675} while (/*CONSTCOND*/0) 676 677#define STGE_TIMEOUT 1000 678 679struct stge_mii_frame { 680 uint8_t mii_stdelim; 681 uint8_t mii_opcode; 682 uint8_t mii_phyaddr; 683 uint8_t mii_regaddr; 684 uint8_t mii_turnaround; 685 uint16_t mii_data; 686}; 687 688/* 689 * MII constants 690 */ 691#define STGE_MII_STARTDELIM 0x01 692#define STGE_MII_READOP 0x02 693#define STGE_MII_WRITEOP 0x01 694#define STGE_MII_TURNAROUND 0x02 695 696#define STGE_RESET_NONE 0x00 697#define STGE_RESET_TX 0x01 698#define STGE_RESET_RX 0x02 699#define STGE_RESET_FULL 0x04 700