ich.c revision 88108
1/* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <dev/sound/pcm/sound.h> 29#include <dev/sound/pcm/ac97.h> 30#include <dev/sound/pci/ich.h> 31 32#include <pci/pcireg.h> 33#include <pci/pcivar.h> 34 35SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 88108 2001-12-18 03:29:31Z orion $"); 36 37/* -------------------------------------------------------------------- */ 38 39#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40#define ICH_DTBL_LENGTH 32 41#define ICH_DEFAULT_BUFSZ 16384 42#define ICH_MAX_BUFSZ 65536 43 44/* buffer descriptor */ 45struct ich_desc { 46 volatile u_int32_t buffer; 47 volatile u_int32_t length; 48}; 49 50struct sc_info; 51 52/* channel registers */ 53struct sc_chinfo { 54 u_int32_t num, run; 55 u_int32_t blksz, blkcnt; 56 u_int32_t regbase, spdreg; 57 u_int32_t civ; 58 59 struct snd_dbuf *buffer; 60 struct pcm_channel *channel; 61 struct sc_info *parent; 62 63 struct ich_desc *dtbl; 64}; 65 66/* device private data */ 67struct sc_info { 68 device_t dev; 69 int hasvra, hasvrm, hasmic; 70 unsigned int chnum, bufsz; 71 72 struct resource *nambar, *nabmbar, *irq; 73 int nambarid, nabmbarid, irqid; 74 bus_space_tag_t nambart, nabmbart; 75 bus_space_handle_t nambarh, nabmbarh; 76 bus_dma_tag_t dmat; 77 bus_dmamap_t dtmap; 78 void *ih; 79 80 struct ac97_info *codec; 81 struct sc_chinfo ch[3]; 82 int ac97rate; 83 struct ich_desc *dtbl; 84}; 85 86/* -------------------------------------------------------------------- */ 87 88static u_int32_t ich_fmt[] = { 89 AFMT_STEREO | AFMT_S16_LE, 90 0 91}; 92static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 93static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 94 95/* -------------------------------------------------------------------- */ 96/* Hardware */ 97static u_int32_t 98ich_rd(struct sc_info *sc, int regno, int size) 99{ 100 switch (size) { 101 case 1: 102 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 103 case 2: 104 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 105 case 4: 106 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 107 default: 108 return 0xffffffff; 109 } 110} 111 112static void 113ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 114{ 115 switch (size) { 116 case 1: 117 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 118 break; 119 case 2: 120 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 121 break; 122 case 4: 123 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 124 break; 125 } 126} 127 128/* ac97 codec */ 129static int 130ich_waitcd(void *devinfo) 131{ 132 int i; 133 u_int32_t data; 134 struct sc_info *sc = (struct sc_info *)devinfo; 135 136 for (i = 0; i < ICH_TIMEOUT; i++) { 137 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 138 if ((data & 0x01) == 0) 139 return 0; 140 } 141 device_printf(sc->dev, "CODEC semaphore timeout\n"); 142 return ETIMEDOUT; 143} 144 145static int 146ich_rdcd(kobj_t obj, void *devinfo, int regno) 147{ 148 struct sc_info *sc = (struct sc_info *)devinfo; 149 150 regno &= 0xff; 151 ich_waitcd(sc); 152 153 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 154} 155 156static int 157ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 158{ 159 struct sc_info *sc = (struct sc_info *)devinfo; 160 161 regno &= 0xff; 162 ich_waitcd(sc); 163 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 164 165 return 0; 166} 167 168static kobj_method_t ich_ac97_methods[] = { 169 KOBJMETHOD(ac97_read, ich_rdcd), 170 KOBJMETHOD(ac97_write, ich_wrcd), 171 { 0, 0 } 172}; 173AC97_DECLARE(ich_ac97); 174 175/* -------------------------------------------------------------------- */ 176/* common routines */ 177 178static void 179ich_filldtbl(struct sc_chinfo *ch) 180{ 181 u_int32_t base; 182 int i; 183 184 base = vtophys(sndbuf_getbuf(ch->buffer)); 185 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 186 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 187 ch->blkcnt = 2; 188 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 189 } 190 191 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 192 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 193 ch->dtbl[i].length = ICH_BDC_IOC | (ch->blksz / 2); 194 } 195} 196 197static int 198ich_resetchan(struct sc_info *sc, int num) 199{ 200 int i, cr, regbase; 201 202 if (num == 0) 203 regbase = ICH_REG_PO_BASE; 204 else if (num == 1) 205 regbase = ICH_REG_PI_BASE; 206 else if (num == 2) 207 regbase = ICH_REG_MC_BASE; 208 else 209 return ENXIO; 210 211 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 212 DELAY(100); 213 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 214 for (i = 0; i < ICH_TIMEOUT; i++) { 215 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 216 if (cr == 0) 217 return 0; 218 } 219 220 device_printf(sc->dev, "cannot reset channel %d\n", num); 221 return ENXIO; 222} 223 224/* -------------------------------------------------------------------- */ 225/* channel interface */ 226 227static void * 228ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 229{ 230 struct sc_info *sc = devinfo; 231 struct sc_chinfo *ch; 232 unsigned int num; 233 234 num = sc->chnum++; 235 ch = &sc->ch[num]; 236 ch->num = num; 237 ch->buffer = b; 238 ch->channel = c; 239 ch->parent = sc; 240 ch->run = 0; 241 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 242 ch->blkcnt = 2; 243 ch->blksz = sc->bufsz / ch->blkcnt; 244 245 switch(ch->num) { 246 case 0: /* play */ 247 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 248 ch->regbase = ICH_REG_PO_BASE; 249 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 250 break; 251 252 case 1: /* record */ 253 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 254 ch->regbase = ICH_REG_PI_BASE; 255 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 256 break; 257 258 case 2: /* mic */ 259 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 260 ch->regbase = ICH_REG_MC_BASE; 261 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 262 break; 263 264 default: 265 return NULL; 266 } 267 268 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 269 return NULL; 270 271 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 272 273 return ch; 274} 275 276static int 277ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 278{ 279 return 0; 280} 281 282static int 283ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 284{ 285 struct sc_chinfo *ch = data; 286 struct sc_info *sc = ch->parent; 287 288 if (ch->spdreg) { 289 int r; 290 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 291 sc->ac97rate = 48000; 292 r = speed * 48000 / sc->ac97rate; 293 return ac97_setrate(sc->codec, ch->spdreg, r) * 294 sc->ac97rate / 48000; 295 } else { 296 return 48000; 297 } 298} 299 300static int 301ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 302{ 303 struct sc_chinfo *ch = data; 304 struct sc_info *sc = ch->parent; 305 306 ch->blksz = blocksize; 307 ich_filldtbl(ch); 308 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 309 310 return ch->blksz; 311} 312 313static int 314ichchan_trigger(kobj_t obj, void *data, int go) 315{ 316 struct sc_chinfo *ch = data; 317 struct sc_info *sc = ch->parent; 318 319 switch (go) { 320 case PCMTRIG_START: 321 ch->run = 1; 322 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4); 323 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE | ICH_X_CR_FEIE, 1); 324 break; 325 326 case PCMTRIG_ABORT: 327 ich_resetchan(sc, ch->num); 328 ch->run = 0; 329 break; 330 } 331 return 0; 332} 333 334static int 335ichchan_getptr(kobj_t obj, void *data) 336{ 337 struct sc_chinfo *ch = data; 338 struct sc_info *sc = ch->parent; 339 u_int32_t pos; 340 341 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 342 343 pos = ch->civ * ch->blksz; 344 345 return pos; 346} 347 348static struct pcmchan_caps * 349ichchan_getcaps(kobj_t obj, void *data) 350{ 351 struct sc_chinfo *ch = data; 352 353 return ch->spdreg? &ich_vrcaps : &ich_caps; 354} 355 356static kobj_method_t ichchan_methods[] = { 357 KOBJMETHOD(channel_init, ichchan_init), 358 KOBJMETHOD(channel_setformat, ichchan_setformat), 359 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 360 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 361 KOBJMETHOD(channel_trigger, ichchan_trigger), 362 KOBJMETHOD(channel_getptr, ichchan_getptr), 363 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 364 { 0, 0 } 365}; 366CHANNEL_DECLARE(ichchan); 367 368/* -------------------------------------------------------------------- */ 369/* The interrupt handler */ 370 371static void 372ich_intr(void *p) 373{ 374 struct sc_info *sc = (struct sc_info *)p; 375 struct sc_chinfo *ch; 376 u_int32_t cbi, lbi, lvi, st; 377 int i; 378 379 for (i = 0; i < 3; i++) { 380 ch = &sc->ch[i]; 381 /* check channel status */ 382 st = ich_rd(sc, ch->regbase + ICH_REG_X_SR, 2); 383 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 384 if (st != 0) { 385 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 386 /* block complete - update buffer */ 387 if (ch->run) 388 chn_intr(ch->channel); 389 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 390 cbi = ch->civ % ch->blkcnt; 391 if (cbi == 0) 392 cbi = ch->blkcnt - 1; 393 else 394 cbi--; 395 lbi = lvi % ch->blkcnt; 396 if (cbi >= lbi) 397 lvi += cbi - lbi; 398 else 399 lvi += cbi + ch->blkcnt - lbi; 400 lvi %= ICH_DTBL_LENGTH; 401 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 402 } 403 /* clear status bit */ 404 ich_wr(sc, ch->regbase + ICH_REG_X_SR, st, 2); 405 } 406 } 407} 408 409/* ------------------------------------------------------------------------- */ 410/* Sysctl to control ac97 speed (some boards overclocked ac97). */ 411 412static int 413ich_initsys(struct sc_info* sc) 414{ 415#ifdef SND_DYNSYSCTL 416 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 417 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 418 OID_AUTO, "ac97rate", CTLFLAG_RW, 419 &sc->ac97rate, 48000, 420 "AC97 link rate (default = 48000)"); 421#endif /* SND_DYNSYSCTL */ 422 return 0; 423} 424 425/* -------------------------------------------------------------------- */ 426/* Calibrate card (some boards are overclocked and need scaling) */ 427 428static 429unsigned int ich_calibrate(struct sc_info *sc) 430{ 431 /* Grab audio from input for fixed interval and compare how 432 * much we actually get with what we expect. Interval needs 433 * to be sufficiently short that no interrupts are 434 * generated. */ 435 struct sc_chinfo *ch = &sc->ch[1]; 436 u_int16_t target_picb, actual_picb; 437 u_int32_t wait_us; 438 int32_t actual_48k_rate; 439 440 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 441 442 ichchan_setspeed(0, ch, 48000); 443 ichchan_setblocksize(0, ch, ICH_DEFAULT_BUFSZ); 444 445 target_picb = ch->dtbl[0].length / 2; /* half interrupt interval */ 446 wait_us = target_picb * 1000 / (2 * 48); /* (2 == stereo -> mono) */ 447 448 if (bootverbose) 449 device_printf(sc->dev, "Calibration interval %d us\n", 450 wait_us); 451 452 ichchan_trigger(0, ch, PCMTRIG_START); 453 DELAY(wait_us); 454 actual_picb = ich_rd(sc, ch->regbase + ICH_REG_X_PICB, 2); 455 ichchan_trigger(0, ch, PCMTRIG_ABORT); 456 457 actual_48k_rate = 48000 * (2 * target_picb - actual_picb) / 458 (target_picb); 459 460 if (bootverbose) 461 device_printf(sc->dev, 462 "Tgt PICB %d, Act PICB %d, 48k rate %d\n", 463 target_picb, actual_picb, actual_48k_rate); 464 465 if ((actual_48k_rate - 48000) > 500 || 466 (actual_48k_rate - 48000) < -500) { 467 sc->ac97rate = actual_48k_rate; 468 } else { 469 sc->ac97rate = 48000; 470 } 471 return sc->ac97rate; 472} 473 474/* -------------------------------------------------------------------- */ 475/* Probe and attach the card */ 476 477static void 478ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 479{ 480 return; 481} 482 483static int 484ich_init(struct sc_info *sc) 485{ 486 u_int32_t stat; 487 int sz; 488 489 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 490 DELAY(600000); 491 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 492 493 if ((stat & ICH_GLOB_STA_PCR) == 0) 494 return ENXIO; 495 496 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 497 498 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 499 return ENXIO; 500 if (sc->hasmic && ich_resetchan(sc, 2)) 501 return ENXIO; 502 503 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 504 return ENOSPC; 505 506 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 507 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) { 508 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 509 return ENOSPC; 510 } 511 512 return 0; 513} 514 515static int 516ich_pci_probe(device_t dev) 517{ 518 switch(pci_get_devid(dev)) { 519 case 0x71958086: 520 device_set_desc(dev, "Intel 443MX"); 521 return 0; 522 523 case 0x24158086: 524 device_set_desc(dev, "Intel 82801AA (ICH)"); 525 return 0; 526 527 case 0x24258086: 528 device_set_desc(dev, "Intel 82801AB (ICH)"); 529 return 0; 530 531 case 0x24458086: 532 device_set_desc(dev, "Intel 82801BA (ICH2)"); 533 return 0; 534 535 case 0x24858086: 536 device_set_desc(dev, "Intel 82801CA (ICH3)"); 537 return 0; 538 539 default: 540 return ENXIO; 541 } 542} 543 544static int 545ich_pci_attach(device_t dev) 546{ 547 u_int32_t data; 548 u_int16_t extcaps; 549 struct sc_info *sc; 550 char status[SND_STATUSLEN]; 551 552 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 553 device_printf(dev, "cannot allocate softc\n"); 554 return ENXIO; 555 } 556 557 bzero(sc, sizeof(*sc)); 558 sc->dev = dev; 559 560 data = pci_read_config(dev, PCIR_COMMAND, 2); 561 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 562 pci_write_config(dev, PCIR_COMMAND, data, 2); 563 data = pci_read_config(dev, PCIR_COMMAND, 2); 564 565 sc->nambarid = PCIR_NAMBAR; 566 sc->nabmbarid = PCIR_NABMBAR; 567 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 568 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 569 570 if (!sc->nambar || !sc->nabmbar) { 571 device_printf(dev, "unable to map IO port space\n"); 572 goto bad; 573 } 574 575 sc->nambart = rman_get_bustag(sc->nambar); 576 sc->nambarh = rman_get_bushandle(sc->nambar); 577 sc->nabmbart = rman_get_bustag(sc->nabmbar); 578 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 579 580 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 581 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 582 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) { 583 device_printf(dev, "unable to create dma tag\n"); 584 goto bad; 585 } 586 587 if (ich_init(sc)) { 588 device_printf(dev, "unable to initialize the card\n"); 589 goto bad; 590 } 591 592 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 593 if (sc->codec == NULL) 594 goto bad; 595 mixer_init(dev, ac97_getmixerclass(), sc->codec); 596 597 /* check and set VRA function */ 598 extcaps = ac97_getextcaps(sc->codec); 599 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 600 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 601 sc->hasmic = extcaps & AC97_CAP_MICCHANNEL; 602 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm | sc->hasmic); 603 604 sc->irqid = 0; 605 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 606 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 607 device_printf(dev, "unable to map interrupt\n"); 608 goto bad; 609 } 610 611 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 612 goto bad; 613 614 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 615 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 616 if (sc->hasmic) 617 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 618 619 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 620 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 621 622 pcm_setstatus(dev, status); 623 624 ich_initsys(sc); 625 ich_calibrate(sc); 626 627 return 0; 628 629bad: 630 if (sc->codec) 631 ac97_destroy(sc->codec); 632 if (sc->nambar) 633 bus_release_resource(dev, SYS_RES_IOPORT, 634 sc->nambarid, sc->nambar); 635 if (sc->nabmbar) 636 bus_release_resource(dev, SYS_RES_IOPORT, 637 sc->nabmbarid, sc->nabmbar); 638 if (sc->ih) 639 bus_teardown_intr(dev, sc->irq, sc->ih); 640 if (sc->irq) 641 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 642 free(sc, M_DEVBUF); 643 return ENXIO; 644} 645 646static int 647ich_pci_detach(device_t dev) 648{ 649 struct sc_info *sc; 650 int r; 651 652 r = pcm_unregister(dev); 653 if (r) 654 return r; 655 sc = pcm_getdevinfo(dev); 656 657 bus_teardown_intr(dev, sc->irq, sc->ih); 658 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 659 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 660 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 661 bus_dma_tag_destroy(sc->dmat); 662 free(sc, M_DEVBUF); 663 return 0; 664} 665 666static int 667ich_pci_resume(device_t dev) 668{ 669 struct sc_info *sc; 670 671 sc = pcm_getdevinfo(dev); 672 673 /* Reinit audio device */ 674 if (ich_init(sc) == -1) { 675 device_printf(dev, "unable to reinitialize the card\n"); 676 return ENXIO; 677 } 678 /* Reinit mixer */ 679 if (mixer_reinit(dev) == -1) { 680 device_printf(dev, "unable to reinitialize the mixer\n"); 681 return ENXIO; 682 } 683 return 0; 684} 685 686static device_method_t ich_methods[] = { 687 /* Device interface */ 688 DEVMETHOD(device_probe, ich_pci_probe), 689 DEVMETHOD(device_attach, ich_pci_attach), 690 DEVMETHOD(device_detach, ich_pci_detach), 691 DEVMETHOD(device_resume, ich_pci_resume), 692 { 0, 0 } 693}; 694 695static driver_t ich_driver = { 696 "pcm", 697 ich_methods, 698 PCM_SOFTC_SIZE, 699}; 700 701DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 702MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 703MODULE_VERSION(snd_ich, 1); 704