ich.c revision 164614
1/*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <dev/sound/pcm/sound.h> 29#include <dev/sound/pcm/ac97.h> 30#include <dev/sound/pci/ich.h> 31 32#include <dev/pci/pcireg.h> 33#include <dev/pci/pcivar.h> 34 35SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 164614 2006-11-26 12:24:06Z ariff $"); 36 37/* -------------------------------------------------------------------- */ 38 39#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40#define ICH_DTBL_LENGTH 32 41#define ICH_DEFAULT_BUFSZ 16384 42#define ICH_MAX_BUFSZ 65536 43#define ICH_MIN_BUFSZ 4096 44#define ICH_DEFAULT_BLKCNT 2 45#define ICH_MAX_BLKCNT 32 46#define ICH_MIN_BLKCNT 2 47 48#define INTEL_VENDORID 0x8086 49#define SIS_VENDORID 0x1039 50#define NVIDIA_VENDORID 0x10de 51#define AMD_VENDORID 0x1022 52 53#define INTEL_82440MX 0x7195 54#define INTEL_82801AA 0x2415 55#define INTEL_82801AB 0x2425 56#define INTEL_82801BA 0x2445 57#define INTEL_82801CA 0x2485 58#define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 59#define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 60#define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 61#define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 62#define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 63#define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 64#define NVIDIA_NFORCE 0x01b1 65#define NVIDIA_NFORCE2 0x006a 66#define NVIDIA_NFORCE2_400 0x008a 67#define NVIDIA_NFORCE3 0x00da 68#define NVIDIA_NFORCE3_250 0x00ea 69#define NVIDIA_NFORCE4 0x0059 70#define NVIDIA_NFORCE_410_MCP 0x026b 71#define AMD_768 0x7445 72#define AMD_8111 0x746d 73 74#define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 75#define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 76#define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 77 78#if 0 79#define ICH_DEBUG(stmt) do { \ 80 stmt \ 81} while(0) 82#else 83#define ICH_DEBUG(stmt) 84#endif 85 86static const struct ich_type { 87 uint16_t vendor; 88 uint16_t devid; 89 uint32_t options; 90#define PROBE_LOW 0x01 91 char *name; 92} ich_devs[] = { 93 { INTEL_VENDORID, INTEL_82440MX, 0, 94 "Intel 440MX" }, 95 { INTEL_VENDORID, INTEL_82801AA, 0, 96 "Intel ICH (82801AA)" }, 97 { INTEL_VENDORID, INTEL_82801AB, 0, 98 "Intel ICH (82801AB)" }, 99 { INTEL_VENDORID, INTEL_82801BA, 0, 100 "Intel ICH2 (82801BA)" }, 101 { INTEL_VENDORID, INTEL_82801CA, 0, 102 "Intel ICH3 (82801CA)" }, 103 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 104 "Intel ICH4 (82801DB)" }, 105 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 106 "Intel ICH5 (82801EB)" }, 107 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 108 "Intel 6300ESB" }, 109 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 110 "Intel ICH6 (82801FB)" }, 111 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 112 "Intel ICH7 (82801GB)" }, 113 { SIS_VENDORID, SIS_7012, 0, 114 "SiS 7012" }, 115 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 116 "nVidia nForce" }, 117 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 118 "nVidia nForce2" }, 119 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 120 "nVidia nForce2 400" }, 121 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 122 "nVidia nForce3" }, 123 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 124 "nVidia nForce3 250" }, 125 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 126 "nVidia nForce4" }, 127 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0, 128 "nVidia nForce 410 MCP" }, 129 { AMD_VENDORID, AMD_768, 0, 130 "AMD-768" }, 131 { AMD_VENDORID, AMD_8111, 0, 132 "AMD-8111" } 133}; 134 135/* buffer descriptor */ 136struct ich_desc { 137 volatile uint32_t buffer; 138 volatile uint32_t length; 139}; 140 141struct sc_info; 142 143/* channel registers */ 144struct sc_chinfo { 145 uint32_t num:8, run:1, run_save:1; 146 uint32_t blksz, blkcnt, spd; 147 uint32_t regbase, spdreg; 148 uint32_t imask; 149 uint32_t civ; 150 151 struct snd_dbuf *buffer; 152 struct pcm_channel *channel; 153 struct sc_info *parent; 154 155 struct ich_desc *dtbl; 156 bus_addr_t desc_addr; 157}; 158 159/* device private data */ 160struct sc_info { 161 device_t dev; 162 int hasvra, hasvrm, hasmic; 163 unsigned int chnum, bufsz, blkcnt; 164 int sample_size, swap_reg, fixedrate; 165 166 struct resource *nambar, *nabmbar, *irq; 167 int regtype, nambarid, nabmbarid, irqid; 168 bus_space_tag_t nambart, nabmbart; 169 bus_space_handle_t nambarh, nabmbarh; 170 bus_dma_tag_t dmat; 171 bus_dmamap_t dtmap; 172 void *ih; 173 174 struct ac97_info *codec; 175 struct sc_chinfo ch[3]; 176 int ac97rate, calibrated; 177 struct ich_desc *dtbl; 178 bus_addr_t desc_addr; 179 struct intr_config_hook intrhook; 180 int use_intrhook; 181 uint16_t vendor; 182 uint16_t devid; 183 uint32_t flags; 184#define IGNORE_PCR 0x01 185 struct mtx *ich_lock; 186}; 187 188/* -------------------------------------------------------------------- */ 189 190static uint32_t ich_fmt[] = { 191 AFMT_STEREO | AFMT_S16_LE, 192 0 193}; 194static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 195static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 196 197/* -------------------------------------------------------------------- */ 198/* Hardware */ 199static __inline uint32_t 200ich_rd(struct sc_info *sc, int regno, int size) 201{ 202 switch (size) { 203 case 1: 204 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno)); 205 case 2: 206 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno)); 207 case 4: 208 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno)); 209 default: 210 return (0xffffffff); 211 } 212} 213 214static __inline void 215ich_wr(struct sc_info *sc, int regno, uint32_t data, int size) 216{ 217 switch (size) { 218 case 1: 219 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 220 break; 221 case 2: 222 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 223 break; 224 case 4: 225 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 226 break; 227 } 228} 229 230/* ac97 codec */ 231static int 232ich_waitcd(void *devinfo) 233{ 234 struct sc_info *sc = (struct sc_info *)devinfo; 235 uint32_t data; 236 int i; 237 238 for (i = 0; i < ICH_TIMEOUT; i++) { 239 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 240 if ((data & 0x01) == 0) 241 return (0); 242 DELAY(1); 243 } 244 if ((sc->flags & IGNORE_PCR) != 0) 245 return (0); 246 device_printf(sc->dev, "CODEC semaphore timeout\n"); 247 return (ETIMEDOUT); 248} 249 250static int 251ich_rdcd(kobj_t obj, void *devinfo, int regno) 252{ 253 struct sc_info *sc = (struct sc_info *)devinfo; 254 255 regno &= 0xff; 256 ich_waitcd(sc); 257 258 return (bus_space_read_2(sc->nambart, sc->nambarh, regno)); 259} 260 261static int 262ich_wrcd(kobj_t obj, void *devinfo, int regno, uint16_t data) 263{ 264 struct sc_info *sc = (struct sc_info *)devinfo; 265 266 regno &= 0xff; 267 ich_waitcd(sc); 268 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 269 270 return (0); 271} 272 273static kobj_method_t ich_ac97_methods[] = { 274 KOBJMETHOD(ac97_read, ich_rdcd), 275 KOBJMETHOD(ac97_write, ich_wrcd), 276 { 0, 0 } 277}; 278AC97_DECLARE(ich_ac97); 279 280/* -------------------------------------------------------------------- */ 281/* common routines */ 282 283static void 284ich_filldtbl(struct sc_chinfo *ch) 285{ 286 struct sc_info *sc = ch->parent; 287 uint32_t base; 288 int i; 289 290 base = sndbuf_getbufaddr(ch->buffer); 291 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer)) 292 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 293 if ((sndbuf_getblksz(ch->buffer) != ch->blksz || 294 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) && 295 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0) 296 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 297 __func__, ch->blksz, ch->blkcnt); 298 ch->blksz = sndbuf_getblksz(ch->buffer); 299 300 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 301 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 302 ch->dtbl[i].length = ICH_BDC_IOC 303 | (ch->blksz / ch->parent->sample_size); 304 } 305} 306 307static int 308ich_resetchan(struct sc_info *sc, int num) 309{ 310 int i, cr, regbase; 311 312 if (num == 0) 313 regbase = ICH_REG_PO_BASE; 314 else if (num == 1) 315 regbase = ICH_REG_PI_BASE; 316 else if (num == 2) 317 regbase = ICH_REG_MC_BASE; 318 else 319 return (ENXIO); 320 321 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 322#if 1 323 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 324 DELAY(100); 325#else 326 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 327#endif 328 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 329 for (i = 0; i < ICH_TIMEOUT; i++) { 330 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 331 if (cr == 0) 332 return (0); 333 } 334 335 device_printf(sc->dev, "cannot reset channel %d\n", num); 336 return (ENXIO); 337} 338 339/* -------------------------------------------------------------------- */ 340/* channel interface */ 341 342static void * 343ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 344{ 345 struct sc_info *sc = devinfo; 346 struct sc_chinfo *ch; 347 unsigned int num; 348 349 ICH_LOCK(sc); 350 num = sc->chnum++; 351 ch = &sc->ch[num]; 352 ch->num = num; 353 ch->buffer = b; 354 ch->channel = c; 355 ch->parent = sc; 356 ch->run = 0; 357 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 358 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 359 sizeof(struct ich_desc); 360 ch->blkcnt = sc->blkcnt; 361 ch->blksz = sc->bufsz / ch->blkcnt; 362 363 switch(ch->num) { 364 case 0: /* play */ 365 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 366 ch->regbase = ICH_REG_PO_BASE; 367 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0; 368 ch->imask = ICH_GLOB_STA_POINT; 369 break; 370 371 case 1: /* record */ 372 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 373 ch->regbase = ICH_REG_PI_BASE; 374 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0; 375 ch->imask = ICH_GLOB_STA_PIINT; 376 break; 377 378 case 2: /* mic */ 379 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 380 ch->regbase = ICH_REG_MC_BASE; 381 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0; 382 ch->imask = ICH_GLOB_STA_MINT; 383 break; 384 385 default: 386 return (NULL); 387 } 388 389 if (sc->fixedrate != 0) 390 ch->spdreg = 0; 391 392 ICH_UNLOCK(sc); 393 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 394 return (NULL); 395 396 ICH_LOCK(sc); 397 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 398 ICH_UNLOCK(sc); 399 400 return (ch); 401} 402 403static int 404ichchan_setformat(kobj_t obj, void *data, uint32_t format) 405{ 406 407 ICH_DEBUG( 408 struct sc_chinfo *ch = data; 409 struct sc_info *sc = ch->parent; 410 if (sc->calibrated == 0) 411 device_printf(sc->dev, 412 "WARNING: %s() called before calibration!\n", 413 __func__); 414 ); 415 416 return (0); 417} 418 419static int 420ichchan_setspeed(kobj_t obj, void *data, uint32_t speed) 421{ 422 struct sc_chinfo *ch = data; 423 struct sc_info *sc = ch->parent; 424 425 ICH_DEBUG( 426 if (sc->calibrated == 0) 427 device_printf(sc->dev, 428 "WARNING: %s() called before calibration!\n", 429 __func__); 430 ); 431 432 if (ch->spdreg) { 433 int r, ac97rate; 434 435 ICH_LOCK(sc); 436 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 437 sc->ac97rate = 48000; 438 ac97rate = sc->ac97rate; 439 ICH_UNLOCK(sc); 440 r = (speed * 48000) / ac97rate; 441 /* 442 * Cast the return value of ac97_setrate() to uint64 so that 443 * the math don't overflow into the negative range. 444 */ 445 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) * 446 ac97rate) / 48000; 447 } else { 448 ch->spd = 48000; 449 } 450 return (ch->spd); 451} 452 453static int 454ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 455{ 456 struct sc_chinfo *ch = data; 457 struct sc_info *sc = ch->parent; 458 459 ICH_DEBUG( 460 if (sc->calibrated == 0) 461 device_printf(sc->dev, 462 "WARNING: %s() called before calibration!\n", 463 __func__); 464 ); 465 466 ch->blksz = blocksize; 467 ich_filldtbl(ch); 468 ICH_LOCK(sc); 469 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 470 ICH_UNLOCK(sc); 471 472 return (ch->blksz); 473} 474 475static int 476ichchan_trigger(kobj_t obj, void *data, int go) 477{ 478 struct sc_chinfo *ch = data; 479 struct sc_info *sc = ch->parent; 480 481 ICH_DEBUG( 482 if (sc->calibrated == 0) 483 device_printf(sc->dev, 484 "WARNING: %s() called before calibration!\n", 485 __func__); 486 ); 487 488 switch (go) { 489 case PCMTRIG_START: 490 ch->run = 1; 491 ICH_LOCK(sc); 492 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 493 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 494 ICH_UNLOCK(sc); 495 break; 496 497 case PCMTRIG_ABORT: 498 ICH_LOCK(sc); 499 ich_resetchan(sc, ch->num); 500 ICH_UNLOCK(sc); 501 ch->run = 0; 502 break; 503 } 504 return (0); 505} 506 507static int 508ichchan_getptr(kobj_t obj, void *data) 509{ 510 struct sc_chinfo *ch = data; 511 struct sc_info *sc = ch->parent; 512 uint32_t pos; 513 514 ICH_DEBUG( 515 if (sc->calibrated == 0) 516 device_printf(sc->dev, 517 "WARNING: %s() called before calibration!\n", 518 __func__); 519 ); 520 521 ICH_LOCK(sc); 522 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 523 ICH_UNLOCK(sc); 524 525 pos = ch->civ * ch->blksz; 526 527 return (pos); 528} 529 530static struct pcmchan_caps * 531ichchan_getcaps(kobj_t obj, void *data) 532{ 533 struct sc_chinfo *ch = data; 534 535 ICH_DEBUG( 536 struct sc_info *sc = ch->parent; 537 538 if (sc->calibrated == 0) 539 device_printf(ch->parent->dev, 540 "WARNING: %s() called before calibration!\n", 541 __func__); 542 ); 543 544 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps); 545} 546 547static kobj_method_t ichchan_methods[] = { 548 KOBJMETHOD(channel_init, ichchan_init), 549 KOBJMETHOD(channel_setformat, ichchan_setformat), 550 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 551 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 552 KOBJMETHOD(channel_trigger, ichchan_trigger), 553 KOBJMETHOD(channel_getptr, ichchan_getptr), 554 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 555 { 0, 0 } 556}; 557CHANNEL_DECLARE(ichchan); 558 559/* -------------------------------------------------------------------- */ 560/* The interrupt handler */ 561 562static void 563ich_intr(void *p) 564{ 565 struct sc_info *sc = (struct sc_info *)p; 566 struct sc_chinfo *ch; 567 uint32_t cbi, lbi, lvi, st, gs; 568 int i; 569 570 ICH_LOCK(sc); 571 572 ICH_DEBUG( 573 if (sc->calibrated == 0) 574 device_printf(sc->dev, 575 "WARNING: %s() called before calibration!\n", 576 __func__); 577 ); 578 579 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 580 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 581 /* Clear resume interrupt(s) - nothing doing with them */ 582 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 583 } 584 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 585 586 for (i = 0; i < 3; i++) { 587 ch = &sc->ch[i]; 588 if ((ch->imask & gs) == 0) 589 continue; 590 gs &= ~ch->imask; 591 st = ich_rd(sc, ch->regbase + 592 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 593 2); 594 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 595 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 596 /* block complete - update buffer */ 597 if (ch->run) { 598 ICH_UNLOCK(sc); 599 chn_intr(ch->channel); 600 ICH_LOCK(sc); 601 } 602 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 603 cbi = ch->civ % ch->blkcnt; 604 if (cbi == 0) 605 cbi = ch->blkcnt - 1; 606 else 607 cbi--; 608 lbi = lvi % ch->blkcnt; 609 if (cbi >= lbi) 610 lvi += cbi - lbi; 611 else 612 lvi += cbi + ch->blkcnt - lbi; 613 lvi %= ICH_DTBL_LENGTH; 614 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 615 616 } 617 /* clear status bit */ 618 ich_wr(sc, ch->regbase + 619 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 620 st, 2); 621 } 622 ICH_UNLOCK(sc); 623 if (gs != 0) { 624 device_printf(sc->dev, 625 "Unhandled interrupt, gs_intr = %x\n", gs); 626 } 627} 628 629/* ------------------------------------------------------------------------- */ 630/* Sysctl to control ac97 speed (some boards appear to end up using 631 * XTAL_IN rather than BIT_CLK for link timing). 632 */ 633 634static int 635ich_initsys(struct sc_info* sc) 636{ 637#ifdef SND_DYNSYSCTL 638 /* XXX: this should move to a device specific sysctl "dev.pcm.X.yyy" 639 via device_get_sysctl_*() as discussed on multimedia@ in msg-id 640 <861wujij2q.fsf@xps.des.no> */ 641 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 642 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 643 OID_AUTO, "ac97rate", CTLFLAG_RW, 644 &sc->ac97rate, 48000, 645 "AC97 link rate (default = 48000)"); 646#endif /* SND_DYNSYSCTL */ 647 return (0); 648} 649 650static void 651ich_setstatus(struct sc_info *sc) 652{ 653 char status[SND_STATUSLEN]; 654 655 snprintf(status, SND_STATUSLEN, 656 "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 657 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), 658 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 659 660 pcm_setstatus(sc->dev, status); 661} 662 663/* -------------------------------------------------------------------- */ 664/* Calibrate card to determine the clock source. The source maybe a 665 * function of the ac97 codec initialization code (to be investigated). 666 */ 667 668static void 669ich_calibrate(void *arg) 670{ 671 struct sc_info *sc; 672 struct sc_chinfo *ch; 673 struct timeval t1, t2; 674 uint8_t ociv, nciv; 675 uint32_t wait_us, actual_48k_rate, oblkcnt; 676 677 sc = (struct sc_info *)arg; 678 ICH_LOCK(sc); 679 ch = &sc->ch[1]; 680 681 if (sc->use_intrhook) 682 config_intrhook_disestablish(&sc->intrhook); 683 684 /* 685 * Grab audio from input for fixed interval and compare how 686 * much we actually get with what we expect. Interval needs 687 * to be sufficiently short that no interrupts are 688 * generated. 689 */ 690 691 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 692 693 oblkcnt = ch->blkcnt; 694 ch->blkcnt = 2; 695 sc->calibrated = 1; 696 ICH_UNLOCK(sc); 697 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1); 698 ICH_LOCK(sc); 699 sc->calibrated = 0; 700 701 /* 702 * our data format is stereo, 16 bit so each sample is 4 bytes. 703 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 704 * we're going to start recording with interrupts disabled and measure 705 * the time taken for one block to complete. we know the block size, 706 * we know the time in microseconds, we calculate the sample rate: 707 * 708 * actual_rate [bps] = bytes / (time [s] * 4) 709 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 710 * actual_rate [Hz] = (bytes * 250000) / time [us] 711 */ 712 713 /* prepare */ 714 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 715 nciv = ociv; 716 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 717 718 /* start */ 719 microtime(&t1); 720 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 721 722 /* wait */ 723 do { 724 microtime(&t2); 725 if (t2.tv_sec - t1.tv_sec > 1) 726 break; 727 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 728 } while (nciv == ociv); 729 730 /* stop */ 731 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 732 733 /* reset */ 734 DELAY(100); 735 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 736 ch->blkcnt = oblkcnt; 737 738 /* turn time delta into us */ 739 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 740 741 if (nciv == ociv) { 742 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 743 sc->calibrated = 1; 744 ICH_UNLOCK(sc); 745 ich_setstatus(sc); 746 return; 747 } 748 749 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us; 750 751 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 752 sc->ac97rate = actual_48k_rate; 753 } else { 754 sc->ac97rate = 48000; 755 } 756 757 if (bootverbose || sc->ac97rate != 48000) { 758 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 759 if (sc->ac97rate != actual_48k_rate) 760 printf(", will use %d Hz", sc->ac97rate); 761 printf("\n"); 762 } 763 sc->calibrated = 1; 764 ICH_UNLOCK(sc); 765 766 ich_setstatus(sc); 767 768 return; 769} 770 771/* -------------------------------------------------------------------- */ 772/* Probe and attach the card */ 773 774static void 775ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 776{ 777 struct sc_info *sc = (struct sc_info *)arg; 778 sc->desc_addr = segs->ds_addr; 779 return; 780} 781 782static int 783ich_init(struct sc_info *sc) 784{ 785 uint32_t stat; 786 787 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 788 DELAY(600000); 789 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 790 791 if ((stat & ICH_GLOB_STA_PCR) == 0) { 792 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 793 if (sc->vendor == INTEL_VENDORID && ( 794 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 795 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 796 sc->devid == INTEL_82801GB)) { 797 sc->flags |= IGNORE_PCR; 798 device_printf(sc->dev, "primary codec not ready!\n"); 799 } 800 } 801 802#if 0 803 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 804#else 805 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 806#endif 807 808 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 809 return (ENXIO); 810 if (sc->hasmic && ich_resetchan(sc, 2)) 811 return (ENXIO); 812 813 return (0); 814} 815 816static int 817ich_pci_probe(device_t dev) 818{ 819 int i; 820 uint16_t devid, vendor; 821 822 vendor = pci_get_vendor(dev); 823 devid = pci_get_device(dev); 824 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 825 if (vendor == ich_devs[i].vendor && 826 devid == ich_devs[i].devid) { 827 device_set_desc(dev, ich_devs[i].name); 828 /* allow a better driver to override us */ 829 if ((ich_devs[i].options & PROBE_LOW) != 0) 830 return (BUS_PROBE_LOW_PRIORITY); 831 return (BUS_PROBE_DEFAULT); 832 } 833 } 834 return (ENXIO); 835} 836 837static int 838ich_pci_attach(device_t dev) 839{ 840 uint32_t subdev; 841 uint16_t extcaps; 842 uint16_t devid, vendor; 843 struct sc_info *sc; 844 int i; 845 846 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 847 device_printf(dev, "cannot allocate softc\n"); 848 return (ENXIO); 849 } 850 851 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 852 sc->dev = dev; 853 854 vendor = sc->vendor = pci_get_vendor(dev); 855 devid = sc->devid = pci_get_device(dev); 856 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev); 857 /* 858 * The SiS 7012 register set isn't quite like the standard ich. 859 * There really should be a general "quirks" mechanism. 860 */ 861 if (vendor == SIS_VENDORID && devid == SIS_7012) { 862 sc->swap_reg = 1; 863 sc->sample_size = 1; 864 } else { 865 sc->swap_reg = 0; 866 sc->sample_size = 2; 867 } 868 869 /* 870 * Enable bus master. On ich4/5 this may prevent the detection of 871 * the primary codec becoming ready in ich_init(). 872 */ 873 pci_enable_busmaster(dev); 874 875 /* 876 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 877 * read-only. Need to enable "legacy support", by poking into 878 * pci config space. The driver should use MMBAR and MBBAR, 879 * but doing so will mess things up here. ich4 has enough new 880 * features it warrants it's own driver. 881 */ 882 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 883 devid == INTEL_82801EB || devid == INTEL_6300ESB || 884 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 885 sc->nambarid = PCIR_MMBAR; 886 sc->nabmbarid = PCIR_MBBAR; 887 sc->regtype = SYS_RES_MEMORY; 888 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 889 } else { 890 sc->nambarid = PCIR_NAMBAR; 891 sc->nabmbarid = PCIR_NABMBAR; 892 sc->regtype = SYS_RES_IOPORT; 893 } 894 895 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 896 &sc->nambarid, RF_ACTIVE); 897 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 898 &sc->nabmbarid, RF_ACTIVE); 899 900 if (!sc->nambar || !sc->nabmbar) { 901 device_printf(dev, "unable to map IO port space\n"); 902 goto bad; 903 } 904 905 sc->nambart = rman_get_bustag(sc->nambar); 906 sc->nambarh = rman_get_bushandle(sc->nambar); 907 sc->nabmbart = rman_get_bustag(sc->nabmbar); 908 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 909 910 sc->bufsz = pcm_getbuffersize(dev, 911 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 912 913 if (resource_int_value(device_get_name(sc->dev), 914 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 915 sc->blkcnt = sc->bufsz / i; 916 i = 0; 917 while (sc->blkcnt >> i) 918 i++; 919 sc->blkcnt = 1 << (i - 1); 920 if (sc->blkcnt < ICH_MIN_BLKCNT) 921 sc->blkcnt = ICH_MIN_BLKCNT; 922 else if (sc->blkcnt > ICH_MAX_BLKCNT) 923 sc->blkcnt = ICH_MAX_BLKCNT; 924 } else 925 sc->blkcnt = ICH_DEFAULT_BLKCNT; 926 927 if (resource_int_value(device_get_name(sc->dev), 928 device_get_unit(sc->dev), "fixedrate", &i) == 0 && 929 i != 0) 930 sc->fixedrate = 1; 931 else 932 sc->fixedrate = 0; 933 934 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 935 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 936 NULL, NULL, &sc->dmat) != 0) { 937 device_printf(dev, "unable to create dma tag\n"); 938 goto bad; 939 } 940 941 sc->irqid = 0; 942 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 943 RF_ACTIVE | RF_SHAREABLE); 944 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 945 device_printf(dev, "unable to map interrupt\n"); 946 goto bad; 947 } 948 949 if (ich_init(sc)) { 950 device_printf(dev, "unable to initialize the card\n"); 951 goto bad; 952 } 953 954 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, 955 BUS_DMA_NOWAIT, &sc->dtmap)) 956 goto bad; 957 958 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, 959 sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3, 960 ich_setmap, sc, 0)) 961 goto bad; 962 963 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 964 if (sc->codec == NULL) 965 goto bad; 966 967 /* 968 * Turn on inverted external amplifier sense flags for few 969 * 'special' boards. 970 */ 971 switch (subdev) { 972 case 0x202f161f: /* Gateway 7326GZ */ 973 case 0x203a161f: /* Gateway 4028GZ */ 974 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 975 case 0x8144104d: /* Sony VAIO PCG-TR* */ 976 case 0x8197104d: /* Sony S1XP */ 977 case 0x81c0104d: /* Sony VAIO type T */ 978 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */ 979 case 0x3089103c: /* Compaq Presario B3800 */ 980 case 0x82131033: /* NEC VersaPro VJ10F/BH */ 981 case 0x82be1033: /* NEC VersaPro VJ12F/CH */ 982 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 983 break; 984 default: 985 break; 986 } 987 988 mixer_init(dev, ac97_getmixerclass(), sc->codec); 989 990 /* check and set VRA function */ 991 extcaps = ac97_getextcaps(sc->codec); 992 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 993 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 994 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 995 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 996 997 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1)) 998 goto bad; 999 1000 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 1001 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 1002 if (sc->hasmic) 1003 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 1004 1005 if (sc->fixedrate == 0) { 1006 ich_initsys(sc); 1007 1008 sc->intrhook.ich_func = ich_calibrate; 1009 sc->intrhook.ich_arg = sc; 1010 sc->use_intrhook = 1; 1011 if (config_intrhook_establish(&sc->intrhook) != 0) { 1012 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 1013 sc->use_intrhook = 0; 1014 ich_calibrate(sc); 1015 } 1016 } else { 1017 sc->calibrated = 1; 1018 ich_setstatus(sc); 1019 } 1020 1021 return (0); 1022 1023bad: 1024 if (sc->codec) 1025 ac97_destroy(sc->codec); 1026 if (sc->ih) 1027 bus_teardown_intr(dev, sc->irq, sc->ih); 1028 if (sc->irq) 1029 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1030 if (sc->nambar) 1031 bus_release_resource(dev, sc->regtype, 1032 sc->nambarid, sc->nambar); 1033 if (sc->nabmbar) 1034 bus_release_resource(dev, sc->regtype, 1035 sc->nabmbarid, sc->nabmbar); 1036 if (sc->dtmap) 1037 bus_dmamap_unload(sc->dmat, sc->dtmap); 1038 if (sc->dmat) 1039 bus_dma_tag_destroy(sc->dmat); 1040 if (sc->ich_lock) 1041 snd_mtxfree(sc->ich_lock); 1042 free(sc, M_DEVBUF); 1043 return (ENXIO); 1044} 1045 1046static int 1047ich_pci_detach(device_t dev) 1048{ 1049 struct sc_info *sc; 1050 int r; 1051 1052 r = pcm_unregister(dev); 1053 if (r) 1054 return (r); 1055 sc = pcm_getdevinfo(dev); 1056 1057 bus_teardown_intr(dev, sc->irq, sc->ih); 1058 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1059 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 1060 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 1061 bus_dmamap_unload(sc->dmat, sc->dtmap); 1062 bus_dma_tag_destroy(sc->dmat); 1063 snd_mtxfree(sc->ich_lock); 1064 free(sc, M_DEVBUF); 1065 return (0); 1066} 1067 1068static void 1069ich_pci_codec_reset(struct sc_info *sc) 1070{ 1071 int i; 1072 uint32_t control; 1073 1074 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 1075 control &= ~(ICH_GLOB_CTL_SHUT); 1076 control |= (control & ICH_GLOB_CTL_COLD) ? 1077 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 1078 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 1079 1080 for (i = 500000; i; i--) { 1081 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 1082 break; /* or ICH_SCR? */ 1083 DELAY(1); 1084 } 1085 1086 if (i <= 0) 1087 printf("%s: time out\n", __func__); 1088} 1089 1090static int 1091ich_pci_suspend(device_t dev) 1092{ 1093 struct sc_info *sc; 1094 int i; 1095 1096 sc = pcm_getdevinfo(dev); 1097 ICH_LOCK(sc); 1098 for (i = 0 ; i < 3; i++) { 1099 sc->ch[i].run_save = sc->ch[i].run; 1100 if (sc->ch[i].run) { 1101 ICH_UNLOCK(sc); 1102 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 1103 ICH_LOCK(sc); 1104 } 1105 } 1106 ICH_UNLOCK(sc); 1107 return (0); 1108} 1109 1110static int 1111ich_pci_resume(device_t dev) 1112{ 1113 struct sc_info *sc; 1114 int i; 1115 1116 sc = pcm_getdevinfo(dev); 1117 1118 if (sc->regtype == SYS_RES_IOPORT) 1119 pci_enable_io(dev, SYS_RES_IOPORT); 1120 else 1121 pci_enable_io(dev, SYS_RES_MEMORY); 1122 pci_enable_busmaster(dev); 1123 1124 ICH_LOCK(sc); 1125 /* Reinit audio device */ 1126 if (ich_init(sc) == -1) { 1127 device_printf(dev, "unable to reinitialize the card\n"); 1128 ICH_UNLOCK(sc); 1129 return (ENXIO); 1130 } 1131 /* Reinit mixer */ 1132 ich_pci_codec_reset(sc); 1133 ICH_UNLOCK(sc); 1134 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1135 if (mixer_reinit(dev) == -1) { 1136 device_printf(dev, "unable to reinitialize the mixer\n"); 1137 return (ENXIO); 1138 } 1139 /* Re-start DMA engines */ 1140 for (i = 0 ; i < 3; i++) { 1141 struct sc_chinfo *ch = &sc->ch[i]; 1142 if (sc->ch[i].run_save) { 1143 ichchan_setblocksize(0, ch, ch->blksz); 1144 ichchan_setspeed(0, ch, ch->spd); 1145 ichchan_trigger(0, ch, PCMTRIG_START); 1146 } 1147 } 1148 return (0); 1149} 1150 1151static device_method_t ich_methods[] = { 1152 /* Device interface */ 1153 DEVMETHOD(device_probe, ich_pci_probe), 1154 DEVMETHOD(device_attach, ich_pci_attach), 1155 DEVMETHOD(device_detach, ich_pci_detach), 1156 DEVMETHOD(device_suspend, ich_pci_suspend), 1157 DEVMETHOD(device_resume, ich_pci_resume), 1158 { 0, 0 } 1159}; 1160 1161static driver_t ich_driver = { 1162 "pcm", 1163 ich_methods, 1164 PCM_SOFTC_SIZE, 1165}; 1166 1167DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 1168MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1169MODULE_VERSION(snd_ich, 1); 1170