ich.c revision 152644
1/*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <dev/sound/pcm/sound.h> 29#include <dev/sound/pcm/ac97.h> 30#include <dev/sound/pci/ich.h> 31 32#include <dev/pci/pcireg.h> 33#include <dev/pci/pcivar.h> 34 35SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 152644 2005-11-21 03:37:43Z yongari $"); 36 37/* -------------------------------------------------------------------- */ 38 39#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40#define ICH_DTBL_LENGTH 32 41#define ICH_DEFAULT_BUFSZ 16384 42#define ICH_MAX_BUFSZ 65536 43 44#define INTEL_VENDORID 0x8086 45#define SIS_VENDORID 0x1039 46#define NVIDIA_VENDORID 0x10de 47#define AMD_VENDORID 0x1022 48 49#define INTEL_82440MX 0x7195 50#define INTEL_82801AA 0x2415 51#define INTEL_82801AB 0x2425 52#define INTEL_82801BA 0x2445 53#define INTEL_82801CA 0x2485 54#define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 55#define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 56#define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 57#define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 58#define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 59#define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 60#define NVIDIA_NFORCE 0x01b1 61#define NVIDIA_NFORCE2 0x006a 62#define NVIDIA_NFORCE2_400 0x008a 63#define NVIDIA_NFORCE3 0x00da 64#define NVIDIA_NFORCE3_250 0x00ea 65#define NVIDIA_NFORCE4 0x0059 66#define AMD_768 0x7445 67#define AMD_8111 0x746d 68 69#define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 70#define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 71#define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 72 73static const struct ich_type { 74 uint16_t vendor; 75 uint16_t devid; 76 uint32_t options; 77#define PROBE_LOW 0x01 78 char *name; 79} ich_devs[] = { 80 { INTEL_VENDORID, INTEL_82440MX, 0, 81 "Intel 440MX" }, 82 { INTEL_VENDORID, INTEL_82801AA, 0, 83 "Intel ICH (82801AA)" }, 84 { INTEL_VENDORID, INTEL_82801AB, 0, 85 "Intel ICH (82801AB)" }, 86 { INTEL_VENDORID, INTEL_82801BA, 0, 87 "Intel ICH2 (82801BA)" }, 88 { INTEL_VENDORID, INTEL_82801CA, 0, 89 "Intel ICH3 (82801CA)" }, 90 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 91 "Intel ICH4 (82801DB)" }, 92 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 93 "Intel ICH5 (82801EB)" }, 94 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 95 "Intel 6300ESB" }, 96 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 97 "Intel ICH6 (82801FB)" }, 98 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 99 "Intel ICH7 (82801GB)" }, 100 { SIS_VENDORID, SIS_7012, 0, 101 "SiS 7012" }, 102 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 103 "nVidia nForce" }, 104 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 105 "nVidia nForce2" }, 106 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 107 "nVidia nForce2 400" }, 108 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 109 "nVidia nForce3" }, 110 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 111 "nVidia nForce3 250" }, 112 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 113 "nVidia nForce4" }, 114 { AMD_VENDORID, AMD_768, 0, 115 "AMD-768" }, 116 { AMD_VENDORID, AMD_8111, 0, 117 "AMD-8111" } 118}; 119 120/* buffer descriptor */ 121struct ich_desc { 122 volatile u_int32_t buffer; 123 volatile u_int32_t length; 124}; 125 126struct sc_info; 127 128/* channel registers */ 129struct sc_chinfo { 130 u_int32_t num:8, run:1, run_save:1; 131 u_int32_t blksz, blkcnt, spd; 132 u_int32_t regbase, spdreg; 133 u_int32_t imask; 134 u_int32_t civ; 135 136 struct snd_dbuf *buffer; 137 struct pcm_channel *channel; 138 struct sc_info *parent; 139 140 struct ich_desc *dtbl; 141 bus_addr_t desc_addr; 142}; 143 144/* device private data */ 145struct sc_info { 146 device_t dev; 147 int hasvra, hasvrm, hasmic; 148 unsigned int chnum, bufsz; 149 int sample_size, swap_reg; 150 151 struct resource *nambar, *nabmbar, *irq; 152 int regtype, nambarid, nabmbarid, irqid; 153 bus_space_tag_t nambart, nabmbart; 154 bus_space_handle_t nambarh, nabmbarh; 155 bus_dma_tag_t dmat; 156 bus_dmamap_t dtmap; 157 void *ih; 158 159 struct ac97_info *codec; 160 struct sc_chinfo ch[3]; 161 int ac97rate; 162 struct ich_desc *dtbl; 163 bus_addr_t desc_addr; 164 struct intr_config_hook intrhook; 165 int use_intrhook; 166 uint16_t vendor; 167 uint16_t devid; 168 uint32_t flags; 169#define IGNORE_PCR 0x01 170 struct mtx *ich_lock; 171}; 172 173/* -------------------------------------------------------------------- */ 174 175static u_int32_t ich_fmt[] = { 176 AFMT_STEREO | AFMT_S16_LE, 177 0 178}; 179static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 180static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 181 182/* -------------------------------------------------------------------- */ 183/* Hardware */ 184static __inline u_int32_t 185ich_rd(struct sc_info *sc, int regno, int size) 186{ 187 switch (size) { 188 case 1: 189 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 190 case 2: 191 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 192 case 4: 193 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 194 default: 195 return 0xffffffff; 196 } 197} 198 199static __inline void 200ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 201{ 202 switch (size) { 203 case 1: 204 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 205 break; 206 case 2: 207 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 208 break; 209 case 4: 210 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 211 break; 212 } 213} 214 215/* ac97 codec */ 216static int 217ich_waitcd(void *devinfo) 218{ 219 int i; 220 u_int32_t data; 221 struct sc_info *sc = (struct sc_info *)devinfo; 222 223 for (i = 0; i < ICH_TIMEOUT; i++) { 224 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 225 if ((data & 0x01) == 0) 226 return 0; 227 DELAY(1); 228 } 229 if ((sc->flags & IGNORE_PCR) != 0) 230 return (0); 231 device_printf(sc->dev, "CODEC semaphore timeout\n"); 232 return ETIMEDOUT; 233} 234 235static int 236ich_rdcd(kobj_t obj, void *devinfo, int regno) 237{ 238 struct sc_info *sc = (struct sc_info *)devinfo; 239 240 regno &= 0xff; 241 ich_waitcd(sc); 242 243 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 244} 245 246static int 247ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 248{ 249 struct sc_info *sc = (struct sc_info *)devinfo; 250 251 regno &= 0xff; 252 ich_waitcd(sc); 253 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 254 255 return 0; 256} 257 258static kobj_method_t ich_ac97_methods[] = { 259 KOBJMETHOD(ac97_read, ich_rdcd), 260 KOBJMETHOD(ac97_write, ich_wrcd), 261 { 0, 0 } 262}; 263AC97_DECLARE(ich_ac97); 264 265/* -------------------------------------------------------------------- */ 266/* common routines */ 267 268static void 269ich_filldtbl(struct sc_chinfo *ch) 270{ 271 struct sc_info *sc = ch->parent; 272 u_int32_t base; 273 int i; 274 275 base = sndbuf_getbufaddr(ch->buffer); 276 if (ch->blksz > sc->bufsz / ch->blkcnt) 277 ch->blksz = sc->bufsz / ch->blkcnt; 278 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz); 279 ch->blksz = sndbuf_getblksz(ch->buffer); 280 281 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 282 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 283 ch->dtbl[i].length = ICH_BDC_IOC 284 | (ch->blksz / ch->parent->sample_size); 285 } 286} 287 288static int 289ich_resetchan(struct sc_info *sc, int num) 290{ 291 int i, cr, regbase; 292 293 if (num == 0) 294 regbase = ICH_REG_PO_BASE; 295 else if (num == 1) 296 regbase = ICH_REG_PI_BASE; 297 else if (num == 2) 298 regbase = ICH_REG_MC_BASE; 299 else 300 return ENXIO; 301 302 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 303#if 1 304 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 305 DELAY(100); 306#else 307 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 308#endif 309 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 310 for (i = 0; i < ICH_TIMEOUT; i++) { 311 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 312 if (cr == 0) 313 return 0; 314 } 315 316 device_printf(sc->dev, "cannot reset channel %d\n", num); 317 return ENXIO; 318} 319 320/* -------------------------------------------------------------------- */ 321/* channel interface */ 322 323static void * 324ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 325{ 326 struct sc_info *sc = devinfo; 327 struct sc_chinfo *ch; 328 unsigned int num; 329 330 ICH_LOCK(sc); 331 num = sc->chnum++; 332 ch = &sc->ch[num]; 333 ch->num = num; 334 ch->buffer = b; 335 ch->channel = c; 336 ch->parent = sc; 337 ch->run = 0; 338 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 339 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 340 sizeof(struct ich_desc); 341 ch->blkcnt = 2; 342 ch->blksz = sc->bufsz / ch->blkcnt; 343 344 switch(ch->num) { 345 case 0: /* play */ 346 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 347 ch->regbase = ICH_REG_PO_BASE; 348 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 349 ch->imask = ICH_GLOB_STA_POINT; 350 break; 351 352 case 1: /* record */ 353 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 354 ch->regbase = ICH_REG_PI_BASE; 355 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 356 ch->imask = ICH_GLOB_STA_PIINT; 357 break; 358 359 case 2: /* mic */ 360 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 361 ch->regbase = ICH_REG_MC_BASE; 362 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 363 ch->imask = ICH_GLOB_STA_MINT; 364 break; 365 366 default: 367 return NULL; 368 } 369 370 ICH_UNLOCK(sc); 371 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 372 return NULL; 373 374 ICH_LOCK(sc); 375 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 376 ICH_UNLOCK(sc); 377 378 return ch; 379} 380 381static int 382ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 383{ 384 return 0; 385} 386 387static int 388ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 389{ 390 struct sc_chinfo *ch = data; 391 struct sc_info *sc = ch->parent; 392 393 if (ch->spdreg) { 394 int r, ac97rate; 395 396 ICH_LOCK(sc); 397 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 398 sc->ac97rate = 48000; 399 ac97rate = sc->ac97rate; 400 ICH_UNLOCK(sc); 401 r = (speed * 48000) / ac97rate; 402 /* 403 * Cast the return value of ac97_setrate() to u_int so that 404 * the math don't overflow into the negative range. 405 */ 406 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 407 ac97rate) / 48000; 408 } else { 409 ch->spd = 48000; 410 } 411 return ch->spd; 412} 413 414static int 415ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 416{ 417 struct sc_chinfo *ch = data; 418 struct sc_info *sc = ch->parent; 419 420 ch->blksz = blocksize; 421 ich_filldtbl(ch); 422 ICH_LOCK(sc); 423 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 424 ICH_UNLOCK(sc); 425 426 return ch->blksz; 427} 428 429static int 430ichchan_trigger(kobj_t obj, void *data, int go) 431{ 432 struct sc_chinfo *ch = data; 433 struct sc_info *sc = ch->parent; 434 435 switch (go) { 436 case PCMTRIG_START: 437 ch->run = 1; 438 ICH_LOCK(sc); 439 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 440 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 441 ICH_UNLOCK(sc); 442 break; 443 444 case PCMTRIG_ABORT: 445 ICH_LOCK(sc); 446 ich_resetchan(sc, ch->num); 447 ICH_UNLOCK(sc); 448 ch->run = 0; 449 break; 450 } 451 return 0; 452} 453 454static int 455ichchan_getptr(kobj_t obj, void *data) 456{ 457 struct sc_chinfo *ch = data; 458 struct sc_info *sc = ch->parent; 459 u_int32_t pos; 460 461 ICH_LOCK(sc); 462 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 463 ICH_UNLOCK(sc); 464 465 pos = ch->civ * ch->blksz; 466 467 return pos; 468} 469 470static struct pcmchan_caps * 471ichchan_getcaps(kobj_t obj, void *data) 472{ 473 struct sc_chinfo *ch = data; 474 475 return ch->spdreg? &ich_vrcaps : &ich_caps; 476} 477 478static kobj_method_t ichchan_methods[] = { 479 KOBJMETHOD(channel_init, ichchan_init), 480 KOBJMETHOD(channel_setformat, ichchan_setformat), 481 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 482 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 483 KOBJMETHOD(channel_trigger, ichchan_trigger), 484 KOBJMETHOD(channel_getptr, ichchan_getptr), 485 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 486 { 0, 0 } 487}; 488CHANNEL_DECLARE(ichchan); 489 490/* -------------------------------------------------------------------- */ 491/* The interrupt handler */ 492 493static void 494ich_intr(void *p) 495{ 496 struct sc_info *sc = (struct sc_info *)p; 497 struct sc_chinfo *ch; 498 u_int32_t cbi, lbi, lvi, st, gs; 499 int i; 500 501 ICH_LOCK(sc); 502 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 503 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 504 /* Clear resume interrupt(s) - nothing doing with them */ 505 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 506 } 507 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 508 509 for (i = 0; i < 3; i++) { 510 ch = &sc->ch[i]; 511 if ((ch->imask & gs) == 0) 512 continue; 513 gs &= ~ch->imask; 514 st = ich_rd(sc, ch->regbase + 515 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 516 2); 517 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 518 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 519 /* block complete - update buffer */ 520 if (ch->run) { 521 ICH_UNLOCK(sc); 522 chn_intr(ch->channel); 523 ICH_LOCK(sc); 524 } 525 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 526 cbi = ch->civ % ch->blkcnt; 527 if (cbi == 0) 528 cbi = ch->blkcnt - 1; 529 else 530 cbi--; 531 lbi = lvi % ch->blkcnt; 532 if (cbi >= lbi) 533 lvi += cbi - lbi; 534 else 535 lvi += cbi + ch->blkcnt - lbi; 536 lvi %= ICH_DTBL_LENGTH; 537 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 538 539 } 540 /* clear status bit */ 541 ich_wr(sc, ch->regbase + 542 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 543 st, 2); 544 } 545 ICH_UNLOCK(sc); 546 if (gs != 0) { 547 device_printf(sc->dev, 548 "Unhandled interrupt, gs_intr = %x\n", gs); 549 } 550} 551 552/* ------------------------------------------------------------------------- */ 553/* Sysctl to control ac97 speed (some boards appear to end up using 554 * XTAL_IN rather than BIT_CLK for link timing). 555 */ 556 557static int 558ich_initsys(struct sc_info* sc) 559{ 560#ifdef SND_DYNSYSCTL 561 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 562 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 563 OID_AUTO, "ac97rate", CTLFLAG_RW, 564 &sc->ac97rate, 48000, 565 "AC97 link rate (default = 48000)"); 566#endif /* SND_DYNSYSCTL */ 567 return 0; 568} 569 570/* -------------------------------------------------------------------- */ 571/* Calibrate card to determine the clock source. The source maybe a 572 * function of the ac97 codec initialization code (to be investigated). 573 */ 574 575static 576void ich_calibrate(void *arg) 577{ 578 struct sc_info *sc; 579 struct sc_chinfo *ch; 580 struct timeval t1, t2; 581 u_int8_t ociv, nciv; 582 u_int32_t wait_us, actual_48k_rate, bytes; 583 584 sc = (struct sc_info *)arg; 585 ch = &sc->ch[1]; 586 587 if (sc->use_intrhook) 588 config_intrhook_disestablish(&sc->intrhook); 589 590 /* 591 * Grab audio from input for fixed interval and compare how 592 * much we actually get with what we expect. Interval needs 593 * to be sufficiently short that no interrupts are 594 * generated. 595 */ 596 597 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 598 599 bytes = sndbuf_getsize(ch->buffer) / 2; 600 ichchan_setblocksize(0, ch, bytes); 601 602 /* 603 * our data format is stereo, 16 bit so each sample is 4 bytes. 604 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 605 * we're going to start recording with interrupts disabled and measure 606 * the time taken for one block to complete. we know the block size, 607 * we know the time in microseconds, we calculate the sample rate: 608 * 609 * actual_rate [bps] = bytes / (time [s] * 4) 610 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 611 * actual_rate [Hz] = (bytes * 250000) / time [us] 612 */ 613 614 /* prepare */ 615 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 616 nciv = ociv; 617 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 618 619 /* start */ 620 microtime(&t1); 621 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 622 623 /* wait */ 624 while (nciv == ociv) { 625 microtime(&t2); 626 if (t2.tv_sec - t1.tv_sec > 1) 627 break; 628 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 629 } 630 microtime(&t2); 631 632 /* stop */ 633 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 634 635 /* reset */ 636 DELAY(100); 637 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 638 639 /* turn time delta into us */ 640 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 641 642 if (nciv == ociv) { 643 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 644 return; 645 } 646 647 actual_48k_rate = (bytes * 250000) / wait_us; 648 649 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 650 sc->ac97rate = actual_48k_rate; 651 } else { 652 sc->ac97rate = 48000; 653 } 654 655 if (bootverbose || sc->ac97rate != 48000) { 656 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 657 if (sc->ac97rate != actual_48k_rate) 658 printf(", will use %d Hz", sc->ac97rate); 659 printf("\n"); 660 } 661 662 return; 663} 664 665/* -------------------------------------------------------------------- */ 666/* Probe and attach the card */ 667 668static void 669ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 670{ 671 struct sc_info *sc = (struct sc_info *)arg; 672 sc->desc_addr = segs->ds_addr; 673 return; 674} 675 676static int 677ich_init(struct sc_info *sc) 678{ 679 u_int32_t stat; 680 int sz; 681 682 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 683 DELAY(600000); 684 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 685 686 if ((stat & ICH_GLOB_STA_PCR) == 0) { 687 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 688 if (sc->vendor == INTEL_VENDORID && ( 689 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 690 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 691 sc->devid == INTEL_82801GB)) { 692 sc->flags |= IGNORE_PCR; 693 device_printf(sc->dev, "primary codec not ready!\n"); 694 } 695 } 696 697 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 698 699 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 700 return ENXIO; 701 if (sc->hasmic && ich_resetchan(sc, 2)) 702 return ENXIO; 703 704 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 705 return ENOSPC; 706 707 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 708 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) { 709 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 710 return ENOSPC; 711 } 712 713 return 0; 714} 715 716static int 717ich_pci_probe(device_t dev) 718{ 719 int i; 720 uint16_t devid, vendor; 721 722 vendor = pci_get_vendor(dev); 723 devid = pci_get_device(dev); 724 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 725 if (vendor == ich_devs[i].vendor && 726 devid == ich_devs[i].devid) { 727 device_set_desc(dev, ich_devs[i].name); 728 /* allow a better driver to override us */ 729 if ((ich_devs[i].options & PROBE_LOW) != 0) 730 return (BUS_PROBE_LOW_PRIORITY); 731 return (BUS_PROBE_DEFAULT); 732 } 733 } 734 return (ENXIO); 735} 736 737static int 738ich_pci_attach(device_t dev) 739{ 740 u_int16_t extcaps; 741 uint16_t devid, vendor; 742 struct sc_info *sc; 743 char status[SND_STATUSLEN]; 744 745 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 746 device_printf(dev, "cannot allocate softc\n"); 747 return ENXIO; 748 } 749 750 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 751 sc->dev = dev; 752 753 vendor = sc->vendor = pci_get_vendor(dev); 754 devid = sc->devid = pci_get_device(dev); 755 /* 756 * The SiS 7012 register set isn't quite like the standard ich. 757 * There really should be a general "quirks" mechanism. 758 */ 759 if (vendor == SIS_VENDORID && devid == SIS_7012) { 760 sc->swap_reg = 1; 761 sc->sample_size = 1; 762 } else { 763 sc->swap_reg = 0; 764 sc->sample_size = 2; 765 } 766 767 /* 768 * Enable bus master. On ich4/5 this may prevent the detection of 769 * the primary codec becoming ready in ich_init(). 770 */ 771 pci_enable_busmaster(dev); 772 773 /* 774 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 775 * read-only. Need to enable "legacy support", by poking into 776 * pci config space. The driver should use MMBAR and MBBAR, 777 * but doing so will mess things up here. ich4 has enough new 778 * features it warrants it's own driver. 779 */ 780 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 781 devid == INTEL_82801EB || devid == INTEL_6300ESB || 782 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 783 sc->nambarid = PCIR_MMBAR; 784 sc->nabmbarid = PCIR_MBBAR; 785 sc->regtype = SYS_RES_MEMORY; 786 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 787 } else { 788 sc->nambarid = PCIR_NAMBAR; 789 sc->nabmbarid = PCIR_NABMBAR; 790 sc->regtype = SYS_RES_IOPORT; 791 } 792 793 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 794 &sc->nambarid, RF_ACTIVE); 795 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 796 &sc->nabmbarid, RF_ACTIVE); 797 798 if (!sc->nambar || !sc->nabmbar) { 799 device_printf(dev, "unable to map IO port space\n"); 800 goto bad; 801 } 802 803 sc->nambart = rman_get_bustag(sc->nambar); 804 sc->nambarh = rman_get_bushandle(sc->nambar); 805 sc->nabmbart = rman_get_bustag(sc->nabmbar); 806 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 807 808 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 809 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 810 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 811 NULL, NULL, &sc->dmat) != 0) { 812 device_printf(dev, "unable to create dma tag\n"); 813 goto bad; 814 } 815 816 sc->irqid = 0; 817 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 818 RF_ACTIVE | RF_SHAREABLE); 819 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 820 device_printf(dev, "unable to map interrupt\n"); 821 goto bad; 822 } 823 824 if (ich_init(sc)) { 825 device_printf(dev, "unable to initialize the card\n"); 826 goto bad; 827 } 828 829 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 830 if (sc->codec == NULL) 831 goto bad; 832 mixer_init(dev, ac97_getmixerclass(), sc->codec); 833 834 /* check and set VRA function */ 835 extcaps = ac97_getextcaps(sc->codec); 836 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 837 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 838 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 839 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 840 841 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 842 goto bad; 843 844 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 845 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 846 if (sc->hasmic) 847 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 848 849 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 850 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 851 852 pcm_setstatus(dev, status); 853 854 ich_initsys(sc); 855 856 sc->intrhook.ich_func = ich_calibrate; 857 sc->intrhook.ich_arg = sc; 858 sc->use_intrhook = 1; 859 if (config_intrhook_establish(&sc->intrhook) != 0) { 860 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 861 sc->use_intrhook = 0; 862 ich_calibrate(sc); 863 } 864 865 return 0; 866 867bad: 868 if (sc->codec) 869 ac97_destroy(sc->codec); 870 if (sc->ih) 871 bus_teardown_intr(dev, sc->irq, sc->ih); 872 if (sc->irq) 873 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 874 if (sc->nambar) 875 bus_release_resource(dev, sc->regtype, 876 sc->nambarid, sc->nambar); 877 if (sc->nabmbar) 878 bus_release_resource(dev, sc->regtype, 879 sc->nabmbarid, sc->nabmbar); 880 if (sc->ich_lock) 881 snd_mtxfree(sc->ich_lock); 882 free(sc, M_DEVBUF); 883 return ENXIO; 884} 885 886static int 887ich_pci_detach(device_t dev) 888{ 889 struct sc_info *sc; 890 int r; 891 892 r = pcm_unregister(dev); 893 if (r) 894 return r; 895 sc = pcm_getdevinfo(dev); 896 897 bus_teardown_intr(dev, sc->irq, sc->ih); 898 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 899 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 900 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 901 bus_dma_tag_destroy(sc->dmat); 902 snd_mtxfree(sc->ich_lock); 903 free(sc, M_DEVBUF); 904 return 0; 905} 906 907static void 908ich_pci_codec_reset(struct sc_info *sc) 909{ 910 int i; 911 uint32_t control; 912 913 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 914 control &= ~(ICH_GLOB_CTL_SHUT); 915 control |= (control & ICH_GLOB_CTL_COLD) ? 916 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 917 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 918 919 for (i = 500000; i; i--) { 920 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 921 break; /* or ICH_SCR? */ 922 DELAY(1); 923 } 924 925 if (i <= 0) 926 printf("%s: time out\n", __func__); 927} 928 929static int 930ich_pci_suspend(device_t dev) 931{ 932 struct sc_info *sc; 933 int i; 934 935 sc = pcm_getdevinfo(dev); 936 ICH_LOCK(sc); 937 for (i = 0 ; i < 3; i++) { 938 sc->ch[i].run_save = sc->ch[i].run; 939 if (sc->ch[i].run) { 940 ICH_UNLOCK(sc); 941 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 942 ICH_LOCK(sc); 943 } 944 } 945 ICH_UNLOCK(sc); 946 return 0; 947} 948 949static int 950ich_pci_resume(device_t dev) 951{ 952 struct sc_info *sc; 953 int i; 954 955 sc = pcm_getdevinfo(dev); 956 957 if (sc->regtype == SYS_RES_IOPORT) 958 pci_enable_io(dev, SYS_RES_IOPORT); 959 else 960 pci_enable_io(dev, SYS_RES_MEMORY); 961 pci_enable_busmaster(dev); 962 963 ICH_LOCK(sc); 964 /* Reinit audio device */ 965 if (ich_init(sc) == -1) { 966 device_printf(dev, "unable to reinitialize the card\n"); 967 ICH_UNLOCK(sc); 968 return ENXIO; 969 } 970 /* Reinit mixer */ 971 ich_pci_codec_reset(sc); 972 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 973 if (mixer_reinit(dev) == -1) { 974 device_printf(dev, "unable to reinitialize the mixer\n"); 975 ICH_UNLOCK(sc); 976 return ENXIO; 977 } 978 /* Re-start DMA engines */ 979 for (i = 0 ; i < 3; i++) { 980 struct sc_chinfo *ch = &sc->ch[i]; 981 if (sc->ch[i].run_save) { 982 ICH_UNLOCK(sc); 983 ichchan_setblocksize(0, ch, ch->blksz); 984 ichchan_setspeed(0, ch, ch->spd); 985 ichchan_trigger(0, ch, PCMTRIG_START); 986 ICH_LOCK(sc); 987 } 988 } 989 ICH_UNLOCK(sc); 990 return 0; 991} 992 993static device_method_t ich_methods[] = { 994 /* Device interface */ 995 DEVMETHOD(device_probe, ich_pci_probe), 996 DEVMETHOD(device_attach, ich_pci_attach), 997 DEVMETHOD(device_detach, ich_pci_detach), 998 DEVMETHOD(device_suspend, ich_pci_suspend), 999 DEVMETHOD(device_resume, ich_pci_resume), 1000 { 0, 0 } 1001}; 1002 1003static driver_t ich_driver = { 1004 "pcm", 1005 ich_methods, 1006 PCM_SOFTC_SIZE, 1007}; 1008 1009DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 1010MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1011MODULE_VERSION(snd_ich, 1); 1012