ich.c revision 150979
1/*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <dev/sound/pcm/sound.h> 29#include <dev/sound/pcm/ac97.h> 30#include <dev/sound/pci/ich.h> 31 32#include <dev/pci/pcireg.h> 33#include <dev/pci/pcivar.h> 34 35SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 150979 2005-10-05 20:00:12Z netchild $"); 36 37/* -------------------------------------------------------------------- */ 38 39#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40#define ICH_DTBL_LENGTH 32 41#define ICH_DEFAULT_BUFSZ 16384 42#define ICH_MAX_BUFSZ 65536 43 44#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45#define ICH4ID 0x24c58086 /* ICH4 needs special handling too */ 46#define ICH5ID 0x24d58086 /* ICH5 needs to be treated as ICH4 */ 47#define I6300ESBID 0x25a68086 /* 6300ESB needs to be treated as ICH4 */ 48#define ICH6ID 0x266e8086 /* ICH6 needs to be treated as ICH4 */ 49 50/* buffer descriptor */ 51struct ich_desc { 52 volatile u_int32_t buffer; 53 volatile u_int32_t length; 54}; 55 56struct sc_info; 57 58/* channel registers */ 59struct sc_chinfo { 60 u_int32_t num:8, run:1, run_save:1; 61 u_int32_t blksz, blkcnt, spd; 62 u_int32_t regbase, spdreg; 63 u_int32_t imask; 64 u_int32_t civ; 65 66 struct snd_dbuf *buffer; 67 struct pcm_channel *channel; 68 struct sc_info *parent; 69 70 struct ich_desc *dtbl; 71 bus_addr_t desc_addr; 72}; 73 74/* device private data */ 75struct sc_info { 76 device_t dev; 77 int hasvra, hasvrm, hasmic; 78 unsigned int chnum, bufsz; 79 int sample_size, swap_reg; 80 81 struct resource *nambar, *nabmbar, *irq; 82 int regtype, nambarid, nabmbarid, irqid; 83 bus_space_tag_t nambart, nabmbart; 84 bus_space_handle_t nambarh, nabmbarh; 85 bus_dma_tag_t dmat; 86 bus_dmamap_t dtmap; 87 void *ih; 88 89 struct ac97_info *codec; 90 struct sc_chinfo ch[3]; 91 int ac97rate; 92 struct ich_desc *dtbl; 93 bus_addr_t desc_addr; 94 struct intr_config_hook intrhook; 95 int use_intrhook; 96}; 97 98/* -------------------------------------------------------------------- */ 99 100static u_int32_t ich_fmt[] = { 101 AFMT_STEREO | AFMT_S16_LE, 102 0 103}; 104static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 105static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 106 107/* -------------------------------------------------------------------- */ 108/* Hardware */ 109static u_int32_t 110ich_rd(struct sc_info *sc, int regno, int size) 111{ 112 switch (size) { 113 case 1: 114 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 115 case 2: 116 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 117 case 4: 118 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 119 default: 120 return 0xffffffff; 121 } 122} 123 124static void 125ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 126{ 127 switch (size) { 128 case 1: 129 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 130 break; 131 case 2: 132 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 133 break; 134 case 4: 135 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 136 break; 137 } 138} 139 140/* ac97 codec */ 141static int 142ich_waitcd(void *devinfo) 143{ 144 int i; 145 u_int32_t data; 146 struct sc_info *sc = (struct sc_info *)devinfo; 147 148 for (i = 0; i < ICH_TIMEOUT; i++) { 149 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 150 if ((data & 0x01) == 0) 151 return 0; 152 } 153 device_printf(sc->dev, "CODEC semaphore timeout\n"); 154 return ETIMEDOUT; 155} 156 157static int 158ich_rdcd(kobj_t obj, void *devinfo, int regno) 159{ 160 struct sc_info *sc = (struct sc_info *)devinfo; 161 162 regno &= 0xff; 163 ich_waitcd(sc); 164 165 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 166} 167 168static int 169ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 170{ 171 struct sc_info *sc = (struct sc_info *)devinfo; 172 173 regno &= 0xff; 174 ich_waitcd(sc); 175 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 176 177 return 0; 178} 179 180static kobj_method_t ich_ac97_methods[] = { 181 KOBJMETHOD(ac97_read, ich_rdcd), 182 KOBJMETHOD(ac97_write, ich_wrcd), 183 { 0, 0 } 184}; 185AC97_DECLARE(ich_ac97); 186 187/* -------------------------------------------------------------------- */ 188/* common routines */ 189 190static void 191ich_filldtbl(struct sc_chinfo *ch) 192{ 193 u_int32_t base; 194 int i; 195 196 base = sndbuf_getbufaddr(ch->buffer); 197 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 198 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 199 ch->blkcnt = 2; 200 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 201 } 202 203 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 204 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 205 ch->dtbl[i].length = ICH_BDC_IOC 206 | (ch->blksz / ch->parent->sample_size); 207 } 208} 209 210static int 211ich_resetchan(struct sc_info *sc, int num) 212{ 213 int i, cr, regbase; 214 215 if (num == 0) 216 regbase = ICH_REG_PO_BASE; 217 else if (num == 1) 218 regbase = ICH_REG_PI_BASE; 219 else if (num == 2) 220 regbase = ICH_REG_MC_BASE; 221 else 222 return ENXIO; 223 224 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 225#if 1 226 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 227 DELAY(100); 228#else 229 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 230#endif 231 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 232 for (i = 0; i < ICH_TIMEOUT; i++) { 233 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 234 if (cr == 0) 235 return 0; 236 } 237 238 device_printf(sc->dev, "cannot reset channel %d\n", num); 239 return ENXIO; 240} 241 242/* -------------------------------------------------------------------- */ 243/* channel interface */ 244 245static void * 246ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 247{ 248 struct sc_info *sc = devinfo; 249 struct sc_chinfo *ch; 250 unsigned int num; 251 252 num = sc->chnum++; 253 ch = &sc->ch[num]; 254 ch->num = num; 255 ch->buffer = b; 256 ch->channel = c; 257 ch->parent = sc; 258 ch->run = 0; 259 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 260 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 261 sizeof(struct ich_desc); 262 ch->blkcnt = 2; 263 ch->blksz = sc->bufsz / ch->blkcnt; 264 265 switch(ch->num) { 266 case 0: /* play */ 267 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 268 ch->regbase = ICH_REG_PO_BASE; 269 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 270 ch->imask = ICH_GLOB_STA_POINT; 271 break; 272 273 case 1: /* record */ 274 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 275 ch->regbase = ICH_REG_PI_BASE; 276 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 277 ch->imask = ICH_GLOB_STA_PIINT; 278 break; 279 280 case 2: /* mic */ 281 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 282 ch->regbase = ICH_REG_MC_BASE; 283 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 284 ch->imask = ICH_GLOB_STA_MINT; 285 break; 286 287 default: 288 return NULL; 289 } 290 291 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 292 return NULL; 293 294 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 295 296 return ch; 297} 298 299static int 300ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 301{ 302 return 0; 303} 304 305static int 306ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 307{ 308 struct sc_chinfo *ch = data; 309 struct sc_info *sc = ch->parent; 310 311 if (ch->spdreg) { 312 int r; 313 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 314 sc->ac97rate = 48000; 315 r = (speed * 48000) / sc->ac97rate; 316 /* 317 * Cast the return value of ac97_setrate() to u_int so that 318 * the math don't overflow into the negative range. 319 */ 320 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 321 sc->ac97rate) / 48000; 322 } else { 323 ch->spd = 48000; 324 } 325 return ch->spd; 326} 327 328static int 329ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 330{ 331 struct sc_chinfo *ch = data; 332 struct sc_info *sc = ch->parent; 333 334 ch->blksz = blocksize; 335 ich_filldtbl(ch); 336 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 337 338 return ch->blksz; 339} 340 341static int 342ichchan_trigger(kobj_t obj, void *data, int go) 343{ 344 struct sc_chinfo *ch = data; 345 struct sc_info *sc = ch->parent; 346 347 switch (go) { 348 case PCMTRIG_START: 349 ch->run = 1; 350 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 351 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 352 break; 353 354 case PCMTRIG_ABORT: 355 ich_resetchan(sc, ch->num); 356 ch->run = 0; 357 break; 358 } 359 return 0; 360} 361 362static int 363ichchan_getptr(kobj_t obj, void *data) 364{ 365 struct sc_chinfo *ch = data; 366 struct sc_info *sc = ch->parent; 367 u_int32_t pos; 368 369 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 370 371 pos = ch->civ * ch->blksz; 372 373 return pos; 374} 375 376static struct pcmchan_caps * 377ichchan_getcaps(kobj_t obj, void *data) 378{ 379 struct sc_chinfo *ch = data; 380 381 return ch->spdreg? &ich_vrcaps : &ich_caps; 382} 383 384static kobj_method_t ichchan_methods[] = { 385 KOBJMETHOD(channel_init, ichchan_init), 386 KOBJMETHOD(channel_setformat, ichchan_setformat), 387 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 388 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 389 KOBJMETHOD(channel_trigger, ichchan_trigger), 390 KOBJMETHOD(channel_getptr, ichchan_getptr), 391 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 392 { 0, 0 } 393}; 394CHANNEL_DECLARE(ichchan); 395 396/* -------------------------------------------------------------------- */ 397/* The interrupt handler */ 398 399static void 400ich_intr(void *p) 401{ 402 struct sc_info *sc = (struct sc_info *)p; 403 struct sc_chinfo *ch; 404 u_int32_t cbi, lbi, lvi, st, gs; 405 int i; 406 407 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 408 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 409 /* Clear resume interrupt(s) - nothing doing with them */ 410 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 411 } 412 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 413 414 for (i = 0; i < 3; i++) { 415 ch = &sc->ch[i]; 416 if ((ch->imask & gs) == 0) 417 continue; 418 gs &= ~ch->imask; 419 st = ich_rd(sc, ch->regbase + 420 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 421 2); 422 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 423 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 424 /* block complete - update buffer */ 425 if (ch->run) 426 chn_intr(ch->channel); 427 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 428 cbi = ch->civ % ch->blkcnt; 429 if (cbi == 0) 430 cbi = ch->blkcnt - 1; 431 else 432 cbi--; 433 lbi = lvi % ch->blkcnt; 434 if (cbi >= lbi) 435 lvi += cbi - lbi; 436 else 437 lvi += cbi + ch->blkcnt - lbi; 438 lvi %= ICH_DTBL_LENGTH; 439 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 440 441 } 442 /* clear status bit */ 443 ich_wr(sc, ch->regbase + 444 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 445 st, 2); 446 } 447 if (gs != 0) { 448 device_printf(sc->dev, 449 "Unhandled interrupt, gs_intr = %x\n", gs); 450 } 451} 452 453/* ------------------------------------------------------------------------- */ 454/* Sysctl to control ac97 speed (some boards appear to end up using 455 * XTAL_IN rather than BIT_CLK for link timing). 456 */ 457 458static int 459ich_initsys(struct sc_info* sc) 460{ 461#ifdef SND_DYNSYSCTL 462 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 463 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 464 OID_AUTO, "ac97rate", CTLFLAG_RW, 465 &sc->ac97rate, 48000, 466 "AC97 link rate (default = 48000)"); 467#endif /* SND_DYNSYSCTL */ 468 return 0; 469} 470 471/* -------------------------------------------------------------------- */ 472/* Calibrate card to determine the clock source. The source maybe a 473 * function of the ac97 codec initialization code (to be investigated). 474 */ 475 476static 477void ich_calibrate(void *arg) 478{ 479 struct sc_info *sc; 480 struct sc_chinfo *ch; 481 struct timeval t1, t2; 482 u_int8_t ociv, nciv; 483 u_int32_t wait_us, actual_48k_rate, bytes; 484 485 sc = (struct sc_info *)arg; 486 ch = &sc->ch[1]; 487 488 if (sc->use_intrhook) 489 config_intrhook_disestablish(&sc->intrhook); 490 491 /* 492 * Grab audio from input for fixed interval and compare how 493 * much we actually get with what we expect. Interval needs 494 * to be sufficiently short that no interrupts are 495 * generated. 496 */ 497 498 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 499 500 bytes = sndbuf_getsize(ch->buffer) / 2; 501 ichchan_setblocksize(0, ch, bytes); 502 503 /* 504 * our data format is stereo, 16 bit so each sample is 4 bytes. 505 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 506 * we're going to start recording with interrupts disabled and measure 507 * the time taken for one block to complete. we know the block size, 508 * we know the time in microseconds, we calculate the sample rate: 509 * 510 * actual_rate [bps] = bytes / (time [s] * 4) 511 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 512 * actual_rate [Hz] = (bytes * 250000) / time [us] 513 */ 514 515 /* prepare */ 516 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 517 nciv = ociv; 518 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 519 520 /* start */ 521 microtime(&t1); 522 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 523 524 /* wait */ 525 while (nciv == ociv) { 526 microtime(&t2); 527 if (t2.tv_sec - t1.tv_sec > 1) 528 break; 529 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 530 } 531 microtime(&t2); 532 533 /* stop */ 534 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 535 536 /* reset */ 537 DELAY(100); 538 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 539 540 /* turn time delta into us */ 541 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 542 543 if (nciv == ociv) { 544 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 545 return; 546 } 547 548 actual_48k_rate = (bytes * 250000) / wait_us; 549 550 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 551 sc->ac97rate = actual_48k_rate; 552 } else { 553 sc->ac97rate = 48000; 554 } 555 556 if (bootverbose || sc->ac97rate != 48000) { 557 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 558 if (sc->ac97rate != actual_48k_rate) 559 printf(", will use %d Hz", sc->ac97rate); 560 printf("\n"); 561 } 562 563 return; 564} 565 566/* -------------------------------------------------------------------- */ 567/* Probe and attach the card */ 568 569static void 570ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 571{ 572 struct sc_info *sc = (struct sc_info *)arg; 573 sc->desc_addr = segs->ds_addr; 574 return; 575} 576 577static int 578ich_init(struct sc_info *sc) 579{ 580 u_int32_t stat; 581 int sz; 582 583 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 584 DELAY(600000); 585 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 586 587 if ((stat & ICH_GLOB_STA_PCR) == 0) { 588 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 589 if ((pci_get_devid(sc->dev) != ICH4ID) && 590 (pci_get_devid(sc->dev) != ICH5ID) && 591 (pci_get_devid(sc->dev) != I6300ESBID) && 592 (pci_get_devid(sc->dev) != ICH6ID)) { 593 return ENXIO; 594 } 595 } 596 597 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 598 599 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 600 return ENXIO; 601 if (sc->hasmic && ich_resetchan(sc, 2)) 602 return ENXIO; 603 604 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 605 return ENOSPC; 606 607 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 608 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) { 609 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 610 return ENOSPC; 611 } 612 613 return 0; 614} 615 616static int 617ich_pci_probe(device_t dev) 618{ 619 switch(pci_get_devid(dev)) { 620 case 0x71958086: 621 device_set_desc(dev, "Intel 443MX"); 622 return BUS_PROBE_DEFAULT; 623 624 case 0x24158086: 625 device_set_desc(dev, "Intel ICH (82801AA)"); 626 return BUS_PROBE_DEFAULT; 627 628 case 0x24258086: 629 device_set_desc(dev, "Intel ICH (82801AB)"); 630 return BUS_PROBE_DEFAULT; 631 632 case 0x24458086: 633 device_set_desc(dev, "Intel ICH2 (82801BA)"); 634 return BUS_PROBE_DEFAULT; 635 636 case 0x24858086: 637 device_set_desc(dev, "Intel ICH3 (82801CA)"); 638 return BUS_PROBE_DEFAULT; 639 640 case ICH4ID: 641 device_set_desc(dev, "Intel ICH4 (82801DB)"); 642 return BUS_PROBE_LOW_PRIORITY; 643 644 case ICH5ID: 645 device_set_desc(dev, "Intel ICH5 (82801EB)"); 646 return BUS_PROBE_LOW_PRIORITY; 647 648 case I6300ESBID: 649 device_set_desc(dev, "Intel 6300ESB"); 650 return BUS_PROBE_LOW_PRIORITY; 651 652 case ICH6ID: 653 device_set_desc(dev, "Intel ICH6 (82801FB)"); 654 return BUS_PROBE_LOW_PRIORITY; 655 656 case SIS7012ID: 657 device_set_desc(dev, "SiS 7012"); 658 return BUS_PROBE_DEFAULT; 659 660 case 0x01b110de: 661 device_set_desc(dev, "nVidia nForce"); 662 return BUS_PROBE_DEFAULT; 663 664 case 0x006a10de: 665 device_set_desc(dev, "nVidia nForce2"); 666 return BUS_PROBE_DEFAULT; 667 668 case 0x008a10de: 669 device_set_desc(dev, "nVidia nForce2 400"); 670 return BUS_PROBE_DEFAULT; 671 672 case 0x00da10de: 673 device_set_desc(dev, "nVidia nForce3"); 674 return BUS_PROBE_DEFAULT; 675 676 case 0x00ea10de: 677 device_set_desc(dev, "nVidia nForce3 250"); 678 return BUS_PROBE_DEFAULT; 679 680 case 0x005910de: 681 device_set_desc(dev, "nVidia nForce4"); 682 return BUS_PROBE_DEFAULT; 683 684 case 0x74451022: 685 device_set_desc(dev, "AMD-768"); 686 return BUS_PROBE_DEFAULT; 687 688 case 0x746d1022: 689 device_set_desc(dev, "AMD-8111"); 690 return BUS_PROBE_DEFAULT; 691 692 default: 693 return ENXIO; 694 } 695} 696 697static int 698ich_pci_attach(device_t dev) 699{ 700 u_int16_t extcaps; 701 struct sc_info *sc; 702 char status[SND_STATUSLEN]; 703 704 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 705 device_printf(dev, "cannot allocate softc\n"); 706 return ENXIO; 707 } 708 709 bzero(sc, sizeof(*sc)); 710 sc->dev = dev; 711 712 /* 713 * The SiS 7012 register set isn't quite like the standard ich. 714 * There really should be a general "quirks" mechanism. 715 */ 716 if (pci_get_devid(dev) == SIS7012ID) { 717 sc->swap_reg = 1; 718 sc->sample_size = 1; 719 } else { 720 sc->swap_reg = 0; 721 sc->sample_size = 2; 722 } 723 724 /* 725 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 726 * read-only. Need to enable "legacy support", by poking into 727 * pci config space. The driver should use MMBAR and MBBAR, 728 * but doing so will mess things up here. ich4 has enough new 729 * features it warrants it's own driver. 730 */ 731 if (pci_get_devid(dev) == ICH4ID) { 732 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 733 } 734 735 /* 736 * Enable bus master. On ich4/5 this may prevent the detection of 737 * the primary codec becoming ready in ich_init(). 738 */ 739 pci_enable_busmaster(dev); 740 741 if (pci_get_devid(dev) == ICH5ID || 742 pci_get_devid(dev) == I6300ESBID || 743 pci_get_devid(dev) == ICH6ID) { 744 sc->nambarid = PCIR_MMBAR; 745 sc->nabmbarid = PCIR_MBBAR; 746 sc->regtype = SYS_RES_MEMORY; 747 } else { 748 sc->nambarid = PCIR_NAMBAR; 749 sc->nabmbarid = PCIR_NABMBAR; 750 sc->regtype = SYS_RES_IOPORT; 751 } 752 753 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 754 &sc->nambarid, RF_ACTIVE); 755 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 756 &sc->nabmbarid, RF_ACTIVE); 757 758 if (!sc->nambar || !sc->nabmbar) { 759 device_printf(dev, "unable to map IO port space\n"); 760 goto bad; 761 } 762 763 sc->nambart = rman_get_bustag(sc->nambar); 764 sc->nambarh = rman_get_bushandle(sc->nambar); 765 sc->nabmbart = rman_get_bustag(sc->nabmbar); 766 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 767 768 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 769 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 770 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 771 busdma_lock_mutex, &Giant, &sc->dmat) != 0) { 772 device_printf(dev, "unable to create dma tag\n"); 773 goto bad; 774 } 775 776 sc->irqid = 0; 777 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 778 RF_ACTIVE | RF_SHAREABLE); 779 if (!sc->irq || snd_setup_intr(dev, sc->irq, 0, ich_intr, sc, &sc->ih)) { 780 device_printf(dev, "unable to map interrupt\n"); 781 goto bad; 782 } 783 784 if (ich_init(sc)) { 785 device_printf(dev, "unable to initialize the card\n"); 786 goto bad; 787 } 788 789 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 790 if (sc->codec == NULL) 791 goto bad; 792 mixer_init(dev, ac97_getmixerclass(), sc->codec); 793 794 /* check and set VRA function */ 795 extcaps = ac97_getextcaps(sc->codec); 796 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 797 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 798 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 799 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 800 801 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 802 goto bad; 803 804 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 805 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 806 if (sc->hasmic) 807 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 808 809 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 810 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 811 812 pcm_setstatus(dev, status); 813 814 ich_initsys(sc); 815 816 sc->intrhook.ich_func = ich_calibrate; 817 sc->intrhook.ich_arg = sc; 818 sc->use_intrhook = 1; 819 if (config_intrhook_establish(&sc->intrhook) != 0) { 820 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 821 sc->use_intrhook = 0; 822 ich_calibrate(sc); 823 } 824 825 return 0; 826 827bad: 828 if (sc->codec) 829 ac97_destroy(sc->codec); 830 if (sc->ih) 831 bus_teardown_intr(dev, sc->irq, sc->ih); 832 if (sc->irq) 833 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 834 if (sc->nambar) 835 bus_release_resource(dev, sc->regtype, 836 sc->nambarid, sc->nambar); 837 if (sc->nabmbar) 838 bus_release_resource(dev, sc->regtype, 839 sc->nabmbarid, sc->nabmbar); 840 free(sc, M_DEVBUF); 841 return ENXIO; 842} 843 844static int 845ich_pci_detach(device_t dev) 846{ 847 struct sc_info *sc; 848 int r; 849 850 r = pcm_unregister(dev); 851 if (r) 852 return r; 853 sc = pcm_getdevinfo(dev); 854 855 bus_teardown_intr(dev, sc->irq, sc->ih); 856 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 857 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 858 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 859 bus_dma_tag_destroy(sc->dmat); 860 free(sc, M_DEVBUF); 861 return 0; 862} 863 864static void 865ich_pci_codec_reset(struct sc_info *sc) 866{ 867 int i; 868 uint32_t control; 869 870 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 871 control &= ~(ICH_GLOB_CTL_SHUT); 872 control |= (control & ICH_GLOB_CTL_COLD) ? 873 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 874 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 875 876 for (i = 500000; i; i--) { 877 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 878 break; /* or ICH_SCR? */ 879 DELAY(1); 880 } 881 882 if (i <= 0) 883 printf("%s: time out\n", __func__); 884} 885 886static int 887ich_pci_suspend(device_t dev) 888{ 889 struct sc_info *sc; 890 int i; 891 892 sc = pcm_getdevinfo(dev); 893 for (i = 0 ; i < 3; i++) { 894 sc->ch[i].run_save = sc->ch[i].run; 895 if (sc->ch[i].run) { 896 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 897 } 898 } 899 return 0; 900} 901 902static int 903ich_pci_resume(device_t dev) 904{ 905 struct sc_info *sc; 906 int i; 907 908 sc = pcm_getdevinfo(dev); 909 910 if (sc->regtype == SYS_RES_IOPORT) 911 pci_enable_io(dev, SYS_RES_IOPORT); 912 else 913 pci_enable_io(dev, SYS_RES_MEMORY); 914 pci_enable_busmaster(dev); 915 916 /* Reinit audio device */ 917 if (ich_init(sc) == -1) { 918 device_printf(dev, "unable to reinitialize the card\n"); 919 return ENXIO; 920 } 921 /* Reinit mixer */ 922 ich_pci_codec_reset(sc); 923 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 924 if (mixer_reinit(dev) == -1) { 925 device_printf(dev, "unable to reinitialize the mixer\n"); 926 return ENXIO; 927 } 928 /* Re-start DMA engines */ 929 for (i = 0 ; i < 3; i++) { 930 struct sc_chinfo *ch = &sc->ch[i]; 931 if (sc->ch[i].run_save) { 932 ichchan_setblocksize(0, ch, ch->blksz); 933 ichchan_setspeed(0, ch, ch->spd); 934 ichchan_trigger(0, ch, PCMTRIG_START); 935 } 936 } 937 return 0; 938} 939 940static device_method_t ich_methods[] = { 941 /* Device interface */ 942 DEVMETHOD(device_probe, ich_pci_probe), 943 DEVMETHOD(device_attach, ich_pci_attach), 944 DEVMETHOD(device_detach, ich_pci_detach), 945 DEVMETHOD(device_suspend, ich_pci_suspend), 946 DEVMETHOD(device_resume, ich_pci_resume), 947 { 0, 0 } 948}; 949 950static driver_t ich_driver = { 951 "pcm", 952 ich_methods, 953 PCM_SOFTC_SIZE, 954}; 955 956DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 957MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 958MODULE_VERSION(snd_ich, 1); 959