ich.c revision 135867
1/* 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <dev/sound/pcm/sound.h> 29#include <dev/sound/pcm/ac97.h> 30#include <dev/sound/pci/ich.h> 31 32#include <dev/pci/pcireg.h> 33#include <dev/pci/pcivar.h> 34 35SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 135867 2004-09-28 01:32:58Z ps $"); 36 37/* -------------------------------------------------------------------- */ 38 39#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40#define ICH_DTBL_LENGTH 32 41#define ICH_DEFAULT_BUFSZ 16384 42#define ICH_MAX_BUFSZ 65536 43 44#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45#define ICH4ID 0x24c58086 /* ICH4 needs special handling too */ 46#define ICH5ID 0x24d58086 /* ICH5 needs to be treated as ICH4 */ 47#define ICH6ID 0x266e8086 /* ICH6 needs to be treated as ICH4 */ 48 49/* buffer descriptor */ 50struct ich_desc { 51 volatile u_int32_t buffer; 52 volatile u_int32_t length; 53}; 54 55struct sc_info; 56 57/* channel registers */ 58struct sc_chinfo { 59 u_int32_t num:8, run:1, run_save:1; 60 u_int32_t blksz, blkcnt, spd; 61 u_int32_t regbase, spdreg; 62 u_int32_t imask; 63 u_int32_t civ; 64 65 struct snd_dbuf *buffer; 66 struct pcm_channel *channel; 67 struct sc_info *parent; 68 69 struct ich_desc *dtbl; 70 bus_addr_t desc_addr; 71}; 72 73/* device private data */ 74struct sc_info { 75 device_t dev; 76 int hasvra, hasvrm, hasmic; 77 unsigned int chnum, bufsz; 78 int sample_size, swap_reg; 79 80 struct resource *nambar, *nabmbar, *irq; 81 int regtype, nambarid, nabmbarid, irqid; 82 bus_space_tag_t nambart, nabmbart; 83 bus_space_handle_t nambarh, nabmbarh; 84 bus_dma_tag_t dmat; 85 bus_dmamap_t dtmap; 86 void *ih; 87 88 struct ac97_info *codec; 89 struct sc_chinfo ch[3]; 90 int ac97rate; 91 struct ich_desc *dtbl; 92 bus_addr_t desc_addr; 93 struct intr_config_hook intrhook; 94 int use_intrhook; 95}; 96 97/* -------------------------------------------------------------------- */ 98 99static u_int32_t ich_fmt[] = { 100 AFMT_STEREO | AFMT_S16_LE, 101 0 102}; 103static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 104static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 105 106/* -------------------------------------------------------------------- */ 107/* Hardware */ 108static u_int32_t 109ich_rd(struct sc_info *sc, int regno, int size) 110{ 111 switch (size) { 112 case 1: 113 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 114 case 2: 115 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 116 case 4: 117 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 118 default: 119 return 0xffffffff; 120 } 121} 122 123static void 124ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 125{ 126 switch (size) { 127 case 1: 128 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 129 break; 130 case 2: 131 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 132 break; 133 case 4: 134 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 135 break; 136 } 137} 138 139/* ac97 codec */ 140static int 141ich_waitcd(void *devinfo) 142{ 143 int i; 144 u_int32_t data; 145 struct sc_info *sc = (struct sc_info *)devinfo; 146 147 for (i = 0; i < ICH_TIMEOUT; i++) { 148 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 149 if ((data & 0x01) == 0) 150 return 0; 151 } 152 device_printf(sc->dev, "CODEC semaphore timeout\n"); 153 return ETIMEDOUT; 154} 155 156static int 157ich_rdcd(kobj_t obj, void *devinfo, int regno) 158{ 159 struct sc_info *sc = (struct sc_info *)devinfo; 160 161 regno &= 0xff; 162 ich_waitcd(sc); 163 164 return bus_space_read_2(sc->nambart, sc->nambarh, regno); 165} 166 167static int 168ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 169{ 170 struct sc_info *sc = (struct sc_info *)devinfo; 171 172 regno &= 0xff; 173 ich_waitcd(sc); 174 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 175 176 return 0; 177} 178 179static kobj_method_t ich_ac97_methods[] = { 180 KOBJMETHOD(ac97_read, ich_rdcd), 181 KOBJMETHOD(ac97_write, ich_wrcd), 182 { 0, 0 } 183}; 184AC97_DECLARE(ich_ac97); 185 186/* -------------------------------------------------------------------- */ 187/* common routines */ 188 189static void 190ich_filldtbl(struct sc_chinfo *ch) 191{ 192 u_int32_t base; 193 int i; 194 195 base = sndbuf_getbufaddr(ch->buffer); 196 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 197 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 198 ch->blkcnt = 2; 199 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 200 } 201 202 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 203 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 204 ch->dtbl[i].length = ICH_BDC_IOC 205 | (ch->blksz / ch->parent->sample_size); 206 } 207} 208 209static int 210ich_resetchan(struct sc_info *sc, int num) 211{ 212 int i, cr, regbase; 213 214 if (num == 0) 215 regbase = ICH_REG_PO_BASE; 216 else if (num == 1) 217 regbase = ICH_REG_PI_BASE; 218 else if (num == 2) 219 regbase = ICH_REG_MC_BASE; 220 else 221 return ENXIO; 222 223 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 224 DELAY(100); 225 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 226 for (i = 0; i < ICH_TIMEOUT; i++) { 227 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 228 if (cr == 0) 229 return 0; 230 } 231 232 device_printf(sc->dev, "cannot reset channel %d\n", num); 233 return ENXIO; 234} 235 236/* -------------------------------------------------------------------- */ 237/* channel interface */ 238 239static void * 240ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 241{ 242 struct sc_info *sc = devinfo; 243 struct sc_chinfo *ch; 244 unsigned int num; 245 246 num = sc->chnum++; 247 ch = &sc->ch[num]; 248 ch->num = num; 249 ch->buffer = b; 250 ch->channel = c; 251 ch->parent = sc; 252 ch->run = 0; 253 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 254 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 255 sizeof(struct ich_desc); 256 ch->blkcnt = 2; 257 ch->blksz = sc->bufsz / ch->blkcnt; 258 259 switch(ch->num) { 260 case 0: /* play */ 261 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 262 ch->regbase = ICH_REG_PO_BASE; 263 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 264 ch->imask = ICH_GLOB_STA_POINT; 265 break; 266 267 case 1: /* record */ 268 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 269 ch->regbase = ICH_REG_PI_BASE; 270 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 271 ch->imask = ICH_GLOB_STA_PIINT; 272 break; 273 274 case 2: /* mic */ 275 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 276 ch->regbase = ICH_REG_MC_BASE; 277 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 278 ch->imask = ICH_GLOB_STA_MINT; 279 break; 280 281 default: 282 return NULL; 283 } 284 285 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 286 return NULL; 287 288 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 289 290 return ch; 291} 292 293static int 294ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 295{ 296 return 0; 297} 298 299static int 300ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 301{ 302 struct sc_chinfo *ch = data; 303 struct sc_info *sc = ch->parent; 304 305 if (ch->spdreg) { 306 int r; 307 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 308 sc->ac97rate = 48000; 309 r = (speed * 48000) / sc->ac97rate; 310 /* 311 * Cast the return value of ac97_setrate() to u_int so that 312 * the math don't overflow into the negative range. 313 */ 314 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 315 sc->ac97rate) / 48000; 316 } else { 317 ch->spd = 48000; 318 } 319 return ch->spd; 320} 321 322static int 323ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 324{ 325 struct sc_chinfo *ch = data; 326 struct sc_info *sc = ch->parent; 327 328 ch->blksz = blocksize; 329 ich_filldtbl(ch); 330 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 331 332 return ch->blksz; 333} 334 335static int 336ichchan_trigger(kobj_t obj, void *data, int go) 337{ 338 struct sc_chinfo *ch = data; 339 struct sc_info *sc = ch->parent; 340 341 switch (go) { 342 case PCMTRIG_START: 343 ch->run = 1; 344 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 345 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 346 break; 347 348 case PCMTRIG_ABORT: 349 ich_resetchan(sc, ch->num); 350 ch->run = 0; 351 break; 352 } 353 return 0; 354} 355 356static int 357ichchan_getptr(kobj_t obj, void *data) 358{ 359 struct sc_chinfo *ch = data; 360 struct sc_info *sc = ch->parent; 361 u_int32_t pos; 362 363 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 364 365 pos = ch->civ * ch->blksz; 366 367 return pos; 368} 369 370static struct pcmchan_caps * 371ichchan_getcaps(kobj_t obj, void *data) 372{ 373 struct sc_chinfo *ch = data; 374 375 return ch->spdreg? &ich_vrcaps : &ich_caps; 376} 377 378static kobj_method_t ichchan_methods[] = { 379 KOBJMETHOD(channel_init, ichchan_init), 380 KOBJMETHOD(channel_setformat, ichchan_setformat), 381 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 382 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 383 KOBJMETHOD(channel_trigger, ichchan_trigger), 384 KOBJMETHOD(channel_getptr, ichchan_getptr), 385 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 386 { 0, 0 } 387}; 388CHANNEL_DECLARE(ichchan); 389 390/* -------------------------------------------------------------------- */ 391/* The interrupt handler */ 392 393static void 394ich_intr(void *p) 395{ 396 struct sc_info *sc = (struct sc_info *)p; 397 struct sc_chinfo *ch; 398 u_int32_t cbi, lbi, lvi, st, gs; 399 int i; 400 401 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 402 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 403 /* Clear resume interrupt(s) - nothing doing with them */ 404 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 405 } 406 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 407 408 for (i = 0; i < 3; i++) { 409 ch = &sc->ch[i]; 410 if ((ch->imask & gs) == 0) 411 continue; 412 gs &= ~ch->imask; 413 st = ich_rd(sc, ch->regbase + 414 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 415 2); 416 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 417 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 418 /* block complete - update buffer */ 419 if (ch->run) 420 chn_intr(ch->channel); 421 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 422 cbi = ch->civ % ch->blkcnt; 423 if (cbi == 0) 424 cbi = ch->blkcnt - 1; 425 else 426 cbi--; 427 lbi = lvi % ch->blkcnt; 428 if (cbi >= lbi) 429 lvi += cbi - lbi; 430 else 431 lvi += cbi + ch->blkcnt - lbi; 432 lvi %= ICH_DTBL_LENGTH; 433 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 434 435 } 436 /* clear status bit */ 437 ich_wr(sc, ch->regbase + 438 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 439 st, 2); 440 } 441 if (gs != 0) { 442 device_printf(sc->dev, 443 "Unhandled interrupt, gs_intr = %x\n", gs); 444 } 445} 446 447/* ------------------------------------------------------------------------- */ 448/* Sysctl to control ac97 speed (some boards appear to end up using 449 * XTAL_IN rather than BIT_CLK for link timing). 450 */ 451 452static int 453ich_initsys(struct sc_info* sc) 454{ 455#ifdef SND_DYNSYSCTL 456 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 457 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 458 OID_AUTO, "ac97rate", CTLFLAG_RW, 459 &sc->ac97rate, 48000, 460 "AC97 link rate (default = 48000)"); 461#endif /* SND_DYNSYSCTL */ 462 return 0; 463} 464 465/* -------------------------------------------------------------------- */ 466/* Calibrate card to determine the clock source. The source maybe a 467 * function of the ac97 codec initialization code (to be investigated). 468 */ 469 470static 471void ich_calibrate(void *arg) 472{ 473 struct sc_info *sc; 474 struct sc_chinfo *ch; 475 struct timeval t1, t2; 476 u_int8_t ociv, nciv; 477 u_int32_t wait_us, actual_48k_rate, bytes; 478 479 sc = (struct sc_info *)arg; 480 ch = &sc->ch[1]; 481 482 if (sc->use_intrhook) 483 config_intrhook_disestablish(&sc->intrhook); 484 485 /* 486 * Grab audio from input for fixed interval and compare how 487 * much we actually get with what we expect. Interval needs 488 * to be sufficiently short that no interrupts are 489 * generated. 490 */ 491 492 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 493 494 bytes = sndbuf_getsize(ch->buffer) / 2; 495 ichchan_setblocksize(0, ch, bytes); 496 497 /* 498 * our data format is stereo, 16 bit so each sample is 4 bytes. 499 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 500 * we're going to start recording with interrupts disabled and measure 501 * the time taken for one block to complete. we know the block size, 502 * we know the time in microseconds, we calculate the sample rate: 503 * 504 * actual_rate [bps] = bytes / (time [s] * 4) 505 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 506 * actual_rate [Hz] = (bytes * 250000) / time [us] 507 */ 508 509 /* prepare */ 510 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 511 nciv = ociv; 512 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 513 514 /* start */ 515 microtime(&t1); 516 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 517 518 /* wait */ 519 while (nciv == ociv) { 520 microtime(&t2); 521 if (t2.tv_sec - t1.tv_sec > 1) 522 break; 523 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 524 } 525 microtime(&t2); 526 527 /* stop */ 528 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 529 530 /* reset */ 531 DELAY(100); 532 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 533 534 /* turn time delta into us */ 535 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 536 537 if (nciv == ociv) { 538 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 539 return; 540 } 541 542 actual_48k_rate = (bytes * 250000) / wait_us; 543 544 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 545 sc->ac97rate = actual_48k_rate; 546 } else { 547 sc->ac97rate = 48000; 548 } 549 550 if (bootverbose || sc->ac97rate != 48000) { 551 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 552 if (sc->ac97rate != actual_48k_rate) 553 printf(", will use %d Hz", sc->ac97rate); 554 printf("\n"); 555 } 556 557 return; 558} 559 560/* -------------------------------------------------------------------- */ 561/* Probe and attach the card */ 562 563static void 564ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 565{ 566 struct sc_info *sc = (struct sc_info *)arg; 567 sc->desc_addr = segs->ds_addr; 568 return; 569} 570 571static int 572ich_init(struct sc_info *sc) 573{ 574 u_int32_t stat; 575 int sz; 576 577 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 578 DELAY(600000); 579 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 580 581 if ((stat & ICH_GLOB_STA_PCR) == 0) { 582 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 583 if ((pci_get_devid(sc->dev) != ICH4ID) && 584 (pci_get_devid(sc->dev) != ICH5ID) && 585 (pci_get_devid(sc->dev) != ICH6ID)) { 586 return ENXIO; 587 } 588 } 589 590 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 591 592 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 593 return ENXIO; 594 if (sc->hasmic && ich_resetchan(sc, 2)) 595 return ENXIO; 596 597 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 598 return ENOSPC; 599 600 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 601 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) { 602 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 603 return ENOSPC; 604 } 605 606 return 0; 607} 608 609static int 610ich_pci_probe(device_t dev) 611{ 612 switch(pci_get_devid(dev)) { 613 case 0x71958086: 614 device_set_desc(dev, "Intel 443MX"); 615 return 0; 616 617 case 0x24158086: 618 device_set_desc(dev, "Intel ICH (82801AA)"); 619 return 0; 620 621 case 0x24258086: 622 device_set_desc(dev, "Intel ICH (82801AB)"); 623 return 0; 624 625 case 0x24458086: 626 device_set_desc(dev, "Intel ICH2 (82801BA)"); 627 return 0; 628 629 case 0x24858086: 630 device_set_desc(dev, "Intel ICH3 (82801CA)"); 631 return 0; 632 633 case ICH4ID: 634 device_set_desc(dev, "Intel ICH4 (82801DB)"); 635 return -1000; /* allow a better driver to override us */ 636 637 case ICH5ID: 638 device_set_desc(dev, "Intel ICH5 (82801EB)"); 639 return -1000; /* allow a better driver to override us */ 640 641 case ICH6ID: 642 device_set_desc(dev, "Intel ICH6 (82801FB)"); 643 return -1000; /* allow a better driver to override us */ 644 645 case SIS7012ID: 646 device_set_desc(dev, "SiS 7012"); 647 return 0; 648 649 case 0x01b110de: 650 device_set_desc(dev, "nVidia nForce"); 651 return 0; 652 653 case 0x006a10de: 654 device_set_desc(dev, "nVidia nForce2"); 655 return 0; 656 657 case 0x008a10de: 658 device_set_desc(dev, "nVidia nForce2 400"); 659 return 0; 660 661 case 0x00da10de: 662 device_set_desc(dev, "nVidia nForce3"); 663 return 0; 664 665 case 0x00ea10de: 666 device_set_desc(dev, "nVidia nForce3 250"); 667 return 0; 668 669 case 0x74451022: 670 device_set_desc(dev, "AMD-768"); 671 return 0; 672 673 case 0x746d1022: 674 device_set_desc(dev, "AMD-8111"); 675 return 0; 676 677 default: 678 return ENXIO; 679 } 680} 681 682static int 683ich_pci_attach(device_t dev) 684{ 685 u_int16_t extcaps; 686 struct sc_info *sc; 687 char status[SND_STATUSLEN]; 688 689 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 690 device_printf(dev, "cannot allocate softc\n"); 691 return ENXIO; 692 } 693 694 bzero(sc, sizeof(*sc)); 695 sc->dev = dev; 696 697 /* 698 * The SiS 7012 register set isn't quite like the standard ich. 699 * There really should be a general "quirks" mechanism. 700 */ 701 if (pci_get_devid(dev) == SIS7012ID) { 702 sc->swap_reg = 1; 703 sc->sample_size = 1; 704 } else { 705 sc->swap_reg = 0; 706 sc->sample_size = 2; 707 } 708 709 /* 710 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 711 * read-only. Need to enable "legacy support", by poking into 712 * pci config space. The driver should use MMBAR and MBBAR, 713 * but doing so will mess things up here. ich4 has enough new 714 * features it warrants it's own driver. 715 */ 716 if (pci_get_devid(dev) == ICH4ID) { 717 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 718 } 719 720 /* 721 * Enable bus master. On ich4/5 this may prevent the detection of 722 * the primary codec becoming ready in ich_init(). 723 */ 724 pci_enable_busmaster(dev); 725 726 if (pci_get_devid(dev) == ICH5ID || pci_get_devid(dev) == ICH6ID) { 727 sc->nambarid = PCIR_MMBAR; 728 sc->nabmbarid = PCIR_MBBAR; 729 sc->regtype = SYS_RES_MEMORY; 730 } else { 731 sc->nambarid = PCIR_NAMBAR; 732 sc->nabmbarid = PCIR_NABMBAR; 733 sc->regtype = SYS_RES_IOPORT; 734 } 735 736 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 737 &sc->nambarid, RF_ACTIVE); 738 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 739 &sc->nabmbarid, RF_ACTIVE); 740 741 if (!sc->nambar || !sc->nabmbar) { 742 device_printf(dev, "unable to map IO port space\n"); 743 goto bad; 744 } 745 746 sc->nambart = rman_get_bustag(sc->nambar); 747 sc->nambarh = rman_get_bushandle(sc->nambar); 748 sc->nabmbart = rman_get_bustag(sc->nabmbar); 749 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 750 751 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 752 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 753 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 754 busdma_lock_mutex, &Giant, &sc->dmat) != 0) { 755 device_printf(dev, "unable to create dma tag\n"); 756 goto bad; 757 } 758 759 sc->irqid = 0; 760 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 761 RF_ACTIVE | RF_SHAREABLE); 762 if (!sc->irq || snd_setup_intr(dev, sc->irq, 0, ich_intr, sc, &sc->ih)) { 763 device_printf(dev, "unable to map interrupt\n"); 764 goto bad; 765 } 766 767 if (ich_init(sc)) { 768 device_printf(dev, "unable to initialize the card\n"); 769 goto bad; 770 } 771 772 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 773 if (sc->codec == NULL) 774 goto bad; 775 mixer_init(dev, ac97_getmixerclass(), sc->codec); 776 777 /* check and set VRA function */ 778 extcaps = ac97_getextcaps(sc->codec); 779 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 780 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 781 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 782 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 783 784 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 785 goto bad; 786 787 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 788 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 789 if (sc->hasmic) 790 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 791 792 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 793 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 794 795 pcm_setstatus(dev, status); 796 797 ich_initsys(sc); 798 799 sc->intrhook.ich_func = ich_calibrate; 800 sc->intrhook.ich_arg = sc; 801 sc->use_intrhook = 1; 802 if (config_intrhook_establish(&sc->intrhook) != 0) { 803 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 804 sc->use_intrhook = 0; 805 ich_calibrate(sc); 806 } 807 808 return 0; 809 810bad: 811 if (sc->codec) 812 ac97_destroy(sc->codec); 813 if (sc->ih) 814 bus_teardown_intr(dev, sc->irq, sc->ih); 815 if (sc->irq) 816 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 817 if (sc->nambar) 818 bus_release_resource(dev, sc->regtype, 819 sc->nambarid, sc->nambar); 820 if (sc->nabmbar) 821 bus_release_resource(dev, sc->regtype, 822 sc->nabmbarid, sc->nabmbar); 823 free(sc, M_DEVBUF); 824 return ENXIO; 825} 826 827static int 828ich_pci_detach(device_t dev) 829{ 830 struct sc_info *sc; 831 int r; 832 833 r = pcm_unregister(dev); 834 if (r) 835 return r; 836 sc = pcm_getdevinfo(dev); 837 838 bus_teardown_intr(dev, sc->irq, sc->ih); 839 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 840 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 841 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 842 bus_dma_tag_destroy(sc->dmat); 843 free(sc, M_DEVBUF); 844 return 0; 845} 846 847static void 848ich_pci_codec_reset(struct sc_info *sc) 849{ 850 int i; 851 uint32_t control; 852 853 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 854 control &= ~(ICH_GLOB_CTL_SHUT); 855 control |= (control & ICH_GLOB_CTL_COLD) ? 856 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 857 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 858 859 for (i = 500000; i; i--) { 860 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 861 break; /* or ICH_SCR? */ 862 DELAY(1); 863 } 864 865 if (i <= 0) 866 printf("%s: time out\n", __func__); 867} 868 869static int 870ich_pci_suspend(device_t dev) 871{ 872 struct sc_info *sc; 873 int i; 874 875 sc = pcm_getdevinfo(dev); 876 for (i = 0 ; i < 3; i++) { 877 sc->ch[i].run_save = sc->ch[i].run; 878 if (sc->ch[i].run) { 879 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 880 } 881 } 882 return 0; 883} 884 885static int 886ich_pci_resume(device_t dev) 887{ 888 struct sc_info *sc; 889 int i; 890 891 sc = pcm_getdevinfo(dev); 892 893 if (sc->regtype == SYS_RES_IOPORT) 894 pci_enable_io(dev, SYS_RES_IOPORT); 895 else 896 pci_enable_io(dev, SYS_RES_MEMORY); 897 pci_enable_busmaster(dev); 898 899 /* Reinit audio device */ 900 if (ich_init(sc) == -1) { 901 device_printf(dev, "unable to reinitialize the card\n"); 902 return ENXIO; 903 } 904 /* Reinit mixer */ 905 ich_pci_codec_reset(sc); 906 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 907 if (mixer_reinit(dev) == -1) { 908 device_printf(dev, "unable to reinitialize the mixer\n"); 909 return ENXIO; 910 } 911 /* Re-start DMA engines */ 912 for (i = 0 ; i < 3; i++) { 913 struct sc_chinfo *ch = &sc->ch[i]; 914 if (sc->ch[i].run_save) { 915 ichchan_setblocksize(0, ch, ch->blksz); 916 ichchan_setspeed(0, ch, ch->spd); 917 ichchan_trigger(0, ch, PCMTRIG_START); 918 } 919 } 920 return 0; 921} 922 923static device_method_t ich_methods[] = { 924 /* Device interface */ 925 DEVMETHOD(device_probe, ich_pci_probe), 926 DEVMETHOD(device_attach, ich_pci_attach), 927 DEVMETHOD(device_detach, ich_pci_detach), 928 DEVMETHOD(device_suspend, ich_pci_suspend), 929 DEVMETHOD(device_resume, ich_pci_resume), 930 { 0, 0 } 931}; 932 933static driver_t ich_driver = { 934 "pcm", 935 ich_methods, 936 PCM_SOFTC_SIZE, 937}; 938 939DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 940MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 941MODULE_VERSION(snd_ich, 1); 942