ich.c revision 117272
1222613Snwhitehorn/* 2222613Snwhitehorn * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3222613Snwhitehorn * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4222613Snwhitehorn * All rights reserved. 5222613Snwhitehorn * 6222613Snwhitehorn * Redistribution and use in source and binary forms, with or without 7222613Snwhitehorn * modification, are permitted provided that the following conditions 8222613Snwhitehorn * are met: 9222613Snwhitehorn * 1. Redistributions of source code must retain the above copyright 10222613Snwhitehorn * notice, this list of conditions and the following disclaimer. 11222613Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 12222613Snwhitehorn * notice, this list of conditions and the following disclaimer in the 13222613Snwhitehorn * documentation and/or other materials provided with the distribution. 14222613Snwhitehorn * 15222613Snwhitehorn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16222613Snwhitehorn * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17222613Snwhitehorn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18222613Snwhitehorn * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19222613Snwhitehorn * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20222613Snwhitehorn * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21222613Snwhitehorn * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22222613Snwhitehorn * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23222613Snwhitehorn * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24222613Snwhitehorn * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25222613Snwhitehorn * SUCH DAMAGE. 26222613Snwhitehorn */ 27222613Snwhitehorn 28222613Snwhitehorn#include <dev/sound/pcm/sound.h> 29222613Snwhitehorn#include <dev/sound/pcm/ac97.h> 30222613Snwhitehorn#include <dev/sound/pci/ich.h> 31222613Snwhitehorn 32222613Snwhitehorn#include <pci/pcireg.h> 33222613Snwhitehorn#include <pci/pcivar.h> 34222613Snwhitehorn 35222613SnwhitehornSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 117272 2003-07-06 03:11:06Z cg $"); 36222613Snwhitehorn 37222613Snwhitehorn/* -------------------------------------------------------------------- */ 38222613Snwhitehorn 39222613Snwhitehorn#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40222613Snwhitehorn#define ICH_DTBL_LENGTH 32 41222613Snwhitehorn#define ICH_DEFAULT_BUFSZ 16384 42222613Snwhitehorn#define ICH_MAX_BUFSZ 65536 43222613Snwhitehorn 44222613Snwhitehorn#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45222613Snwhitehorn#define ICH4ID 0x24c58086 /* ICH4 needs special handling too */ 46222613Snwhitehorn 47222613Snwhitehorn/* buffer descriptor */ 48222613Snwhitehornstruct ich_desc { 49222613Snwhitehorn volatile u_int32_t buffer; 50222613Snwhitehorn volatile u_int32_t length; 51222613Snwhitehorn}; 52222613Snwhitehorn 53222613Snwhitehornstruct sc_info; 54222613Snwhitehorn 55222613Snwhitehorn/* channel registers */ 56222613Snwhitehornstruct sc_chinfo { 57222613Snwhitehorn u_int32_t num:8, run:1, run_save:1; 58222613Snwhitehorn u_int32_t blksz, blkcnt, spd; 59230400Sandreast u_int32_t regbase, spdreg; 60222613Snwhitehorn u_int32_t imask; 61222613Snwhitehorn u_int32_t civ; 62222613Snwhitehorn 63222613Snwhitehorn struct snd_dbuf *buffer; 64222613Snwhitehorn struct pcm_channel *channel; 65222613Snwhitehorn struct sc_info *parent; 66222613Snwhitehorn 67222613Snwhitehorn struct ich_desc *dtbl; 68222613Snwhitehorn bus_addr_t desc_addr; 69222613Snwhitehorn}; 70222613Snwhitehorn 71222613Snwhitehorn/* device private data */ 72222613Snwhitehornstruct sc_info { 73222613Snwhitehorn device_t dev; 74222613Snwhitehorn int hasvra, hasvrm, hasmic; 75222613Snwhitehorn unsigned int chnum, bufsz; 76222613Snwhitehorn int sample_size, swap_reg; 77222613Snwhitehorn 78222613Snwhitehorn struct resource *nambar, *nabmbar, *irq; 79222613Snwhitehorn int nambarid, nabmbarid, irqid; 80222613Snwhitehorn bus_space_tag_t nambart, nabmbart; 81222613Snwhitehorn bus_space_handle_t nambarh, nabmbarh; 82222613Snwhitehorn bus_dma_tag_t dmat; 83222613Snwhitehorn bus_dmamap_t dtmap; 84222613Snwhitehorn void *ih; 85222613Snwhitehorn 86222613Snwhitehorn struct ac97_info *codec; 87222613Snwhitehorn struct sc_chinfo ch[3]; 88222613Snwhitehorn int ac97rate; 89222613Snwhitehorn struct ich_desc *dtbl; 90222613Snwhitehorn bus_addr_t desc_addr; 91222613Snwhitehorn struct intr_config_hook intrhook; 92222613Snwhitehorn int use_intrhook; 93222613Snwhitehorn}; 94222613Snwhitehorn 95222613Snwhitehorn/* -------------------------------------------------------------------- */ 96222613Snwhitehorn 97222613Snwhitehornstatic u_int32_t ich_fmt[] = { 98222613Snwhitehorn AFMT_STEREO | AFMT_S16_LE, 99222613Snwhitehorn 0 100222613Snwhitehorn}; 101222613Snwhitehornstatic struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 102222613Snwhitehornstatic struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 103222613Snwhitehorn 104222613Snwhitehorn/* -------------------------------------------------------------------- */ 105222613Snwhitehorn/* Hardware */ 106222613Snwhitehornstatic u_int32_t 107222613Snwhitehornich_rd(struct sc_info *sc, int regno, int size) 108222613Snwhitehorn{ 109222613Snwhitehorn switch (size) { 110222613Snwhitehorn case 1: 111222613Snwhitehorn return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 112222613Snwhitehorn case 2: 113222613Snwhitehorn return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 114222613Snwhitehorn case 4: 115222613Snwhitehorn return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 116222613Snwhitehorn default: 117222613Snwhitehorn return 0xffffffff; 118222613Snwhitehorn } 119222613Snwhitehorn} 120222613Snwhitehorn 121222613Snwhitehornstatic void 122222613Snwhitehornich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 123222613Snwhitehorn{ 124222613Snwhitehorn switch (size) { 125222613Snwhitehorn case 1: 126222613Snwhitehorn bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 127222613Snwhitehorn break; 128222613Snwhitehorn case 2: 129222613Snwhitehorn bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 130222613Snwhitehorn break; 131222613Snwhitehorn case 4: 132222613Snwhitehorn bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 133222613Snwhitehorn break; 134222613Snwhitehorn } 135222613Snwhitehorn} 136222613Snwhitehorn 137222613Snwhitehorn/* ac97 codec */ 138222613Snwhitehornstatic int 139222613Snwhitehornich_waitcd(void *devinfo) 140222613Snwhitehorn{ 141222613Snwhitehorn int i; 142222613Snwhitehorn u_int32_t data; 143222613Snwhitehorn struct sc_info *sc = (struct sc_info *)devinfo; 144222613Snwhitehorn 145222613Snwhitehorn for (i = 0; i < ICH_TIMEOUT; i++) { 146222613Snwhitehorn data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 147222613Snwhitehorn if ((data & 0x01) == 0) 148222613Snwhitehorn return 0; 149222613Snwhitehorn } 150222613Snwhitehorn device_printf(sc->dev, "CODEC semaphore timeout\n"); 151222613Snwhitehorn return ETIMEDOUT; 152222613Snwhitehorn} 153222613Snwhitehorn 154222613Snwhitehornstatic int 155222613Snwhitehornich_rdcd(kobj_t obj, void *devinfo, int regno) 156222613Snwhitehorn{ 157222613Snwhitehorn struct sc_info *sc = (struct sc_info *)devinfo; 158222613Snwhitehorn 159222613Snwhitehorn regno &= 0xff; 160222613Snwhitehorn ich_waitcd(sc); 161222613Snwhitehorn 162222613Snwhitehorn return bus_space_read_2(sc->nambart, sc->nambarh, regno); 163222613Snwhitehorn} 164222613Snwhitehorn 165222613Snwhitehornstatic int 166222613Snwhitehornich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 167222613Snwhitehorn{ 168222613Snwhitehorn struct sc_info *sc = (struct sc_info *)devinfo; 169222613Snwhitehorn 170222613Snwhitehorn regno &= 0xff; 171222613Snwhitehorn ich_waitcd(sc); 172222613Snwhitehorn bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 173222613Snwhitehorn 174222613Snwhitehorn return 0; 175222613Snwhitehorn} 176222613Snwhitehorn 177222613Snwhitehornstatic kobj_method_t ich_ac97_methods[] = { 178230400Sandreast KOBJMETHOD(ac97_read, ich_rdcd), 179222613Snwhitehorn KOBJMETHOD(ac97_write, ich_wrcd), 180222613Snwhitehorn { 0, 0 } 181222613Snwhitehorn}; 182222613SnwhitehornAC97_DECLARE(ich_ac97); 183222613Snwhitehorn 184222613Snwhitehorn/* -------------------------------------------------------------------- */ 185222613Snwhitehorn/* common routines */ 186222613Snwhitehorn 187222613Snwhitehornstatic void 188222613Snwhitehornich_filldtbl(struct sc_chinfo *ch) 189222613Snwhitehorn{ 190222613Snwhitehorn u_int32_t base; 191222613Snwhitehorn int i; 192222613Snwhitehorn 193222613Snwhitehorn base = sndbuf_getbufaddr(ch->buffer); 194222613Snwhitehorn ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 195222613Snwhitehorn if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 196222613Snwhitehorn ch->blkcnt = 2; 197222613Snwhitehorn ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 198222613Snwhitehorn } 199222613Snwhitehorn 200222613Snwhitehorn for (i = 0; i < ICH_DTBL_LENGTH; i++) { 201222613Snwhitehorn ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 202222613Snwhitehorn ch->dtbl[i].length = ICH_BDC_IOC 203222613Snwhitehorn | (ch->blksz / ch->parent->sample_size); 204222613Snwhitehorn } 205222613Snwhitehorn} 206222613Snwhitehorn 207222613Snwhitehornstatic int 208222613Snwhitehornich_resetchan(struct sc_info *sc, int num) 209222613Snwhitehorn{ 210222613Snwhitehorn int i, cr, regbase; 211222613Snwhitehorn 212222613Snwhitehorn if (num == 0) 213222613Snwhitehorn regbase = ICH_REG_PO_BASE; 214222613Snwhitehorn else if (num == 1) 215222613Snwhitehorn regbase = ICH_REG_PI_BASE; 216222613Snwhitehorn else if (num == 2) 217222613Snwhitehorn regbase = ICH_REG_MC_BASE; 218222613Snwhitehorn else 219222613Snwhitehorn return ENXIO; 220222613Snwhitehorn 221222613Snwhitehorn ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 222222613Snwhitehorn DELAY(100); 223222613Snwhitehorn ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 224222613Snwhitehorn for (i = 0; i < ICH_TIMEOUT; i++) { 225222613Snwhitehorn cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 226222613Snwhitehorn if (cr == 0) 227222613Snwhitehorn return 0; 228222613Snwhitehorn } 229222613Snwhitehorn 230222613Snwhitehorn device_printf(sc->dev, "cannot reset channel %d\n", num); 231222613Snwhitehorn return ENXIO; 232222613Snwhitehorn} 233222613Snwhitehorn 234222613Snwhitehorn/* -------------------------------------------------------------------- */ 235222613Snwhitehorn/* channel interface */ 236222613Snwhitehorn 237222613Snwhitehornstatic void * 238222613Snwhitehornichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 239222613Snwhitehorn{ 240222613Snwhitehorn struct sc_info *sc = devinfo; 241222613Snwhitehorn struct sc_chinfo *ch; 242222613Snwhitehorn unsigned int num; 243222613Snwhitehorn 244222613Snwhitehorn num = sc->chnum++; 245222613Snwhitehorn ch = &sc->ch[num]; 246222613Snwhitehorn ch->num = num; 247222613Snwhitehorn ch->buffer = b; 248222613Snwhitehorn ch->channel = c; 249222613Snwhitehorn ch->parent = sc; 250222613Snwhitehorn ch->run = 0; 251222613Snwhitehorn ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 252222613Snwhitehorn ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 253222613Snwhitehorn sizeof(struct ich_desc); 254222613Snwhitehorn ch->blkcnt = 2; 255222613Snwhitehorn ch->blksz = sc->bufsz / ch->blkcnt; 256222613Snwhitehorn 257222613Snwhitehorn switch(ch->num) { 258222613Snwhitehorn case 0: /* play */ 259222613Snwhitehorn KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 260222613Snwhitehorn ch->regbase = ICH_REG_PO_BASE; 261222613Snwhitehorn ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 262222613Snwhitehorn ch->imask = ICH_GLOB_STA_POINT; 263222613Snwhitehorn break; 264222613Snwhitehorn 265222613Snwhitehorn case 1: /* record */ 266222613Snwhitehorn KASSERT(dir == PCMDIR_REC, ("wrong direction")); 267222613Snwhitehorn ch->regbase = ICH_REG_PI_BASE; 268222613Snwhitehorn ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 269222613Snwhitehorn ch->imask = ICH_GLOB_STA_PIINT; 270222613Snwhitehorn break; 271222613Snwhitehorn 272222613Snwhitehorn case 2: /* mic */ 273222613Snwhitehorn KASSERT(dir == PCMDIR_REC, ("wrong direction")); 274222613Snwhitehorn ch->regbase = ICH_REG_MC_BASE; 275222613Snwhitehorn ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 276222613Snwhitehorn ch->imask = ICH_GLOB_STA_MINT; 277222613Snwhitehorn break; 278222613Snwhitehorn 279222613Snwhitehorn default: 280222613Snwhitehorn return NULL; 281222613Snwhitehorn } 282222613Snwhitehorn 283222613Snwhitehorn if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz)) 284222613Snwhitehorn return NULL; 285222613Snwhitehorn 286222613Snwhitehorn ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 287222613Snwhitehorn 288222613Snwhitehorn return ch; 289222613Snwhitehorn} 290222613Snwhitehorn 291static int 292ichchan_setformat(kobj_t obj, void *data, u_int32_t format) 293{ 294 return 0; 295} 296 297static int 298ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 299{ 300 struct sc_chinfo *ch = data; 301 struct sc_info *sc = ch->parent; 302 303 if (ch->spdreg) { 304 int r; 305 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 306 sc->ac97rate = 48000; 307 r = (speed * 48000) / sc->ac97rate; 308 /* 309 * Cast the return value of ac97_setrate() to u_int so that 310 * the math don't overflow into the negative range. 311 */ 312 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 313 sc->ac97rate) / 48000; 314 } else { 315 ch->spd = 48000; 316 } 317 return ch->spd; 318} 319 320static int 321ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 322{ 323 struct sc_chinfo *ch = data; 324 struct sc_info *sc = ch->parent; 325 326 ch->blksz = blocksize; 327 ich_filldtbl(ch); 328 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 329 330 return ch->blksz; 331} 332 333static int 334ichchan_trigger(kobj_t obj, void *data, int go) 335{ 336 struct sc_chinfo *ch = data; 337 struct sc_info *sc = ch->parent; 338 339 switch (go) { 340 case PCMTRIG_START: 341 ch->run = 1; 342 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 343 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 344 break; 345 346 case PCMTRIG_ABORT: 347 ich_resetchan(sc, ch->num); 348 ch->run = 0; 349 break; 350 } 351 return 0; 352} 353 354static int 355ichchan_getptr(kobj_t obj, void *data) 356{ 357 struct sc_chinfo *ch = data; 358 struct sc_info *sc = ch->parent; 359 u_int32_t pos; 360 361 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 362 363 pos = ch->civ * ch->blksz; 364 365 return pos; 366} 367 368static struct pcmchan_caps * 369ichchan_getcaps(kobj_t obj, void *data) 370{ 371 struct sc_chinfo *ch = data; 372 373 return ch->spdreg? &ich_vrcaps : &ich_caps; 374} 375 376static kobj_method_t ichchan_methods[] = { 377 KOBJMETHOD(channel_init, ichchan_init), 378 KOBJMETHOD(channel_setformat, ichchan_setformat), 379 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 380 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 381 KOBJMETHOD(channel_trigger, ichchan_trigger), 382 KOBJMETHOD(channel_getptr, ichchan_getptr), 383 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 384 { 0, 0 } 385}; 386CHANNEL_DECLARE(ichchan); 387 388/* -------------------------------------------------------------------- */ 389/* The interrupt handler */ 390 391static void 392ich_intr(void *p) 393{ 394 struct sc_info *sc = (struct sc_info *)p; 395 struct sc_chinfo *ch; 396 u_int32_t cbi, lbi, lvi, st, gs; 397 int i; 398 399 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 400 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 401 /* Clear resume interrupt(s) - nothing doing with them */ 402 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 403 } 404 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 405 406 for (i = 0; i < 3; i++) { 407 ch = &sc->ch[i]; 408 if ((ch->imask & gs) == 0) 409 continue; 410 gs &= ~ch->imask; 411 st = ich_rd(sc, ch->regbase + 412 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 413 2); 414 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 415 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 416 /* block complete - update buffer */ 417 if (ch->run) 418 chn_intr(ch->channel); 419 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 420 cbi = ch->civ % ch->blkcnt; 421 if (cbi == 0) 422 cbi = ch->blkcnt - 1; 423 else 424 cbi--; 425 lbi = lvi % ch->blkcnt; 426 if (cbi >= lbi) 427 lvi += cbi - lbi; 428 else 429 lvi += cbi + ch->blkcnt - lbi; 430 lvi %= ICH_DTBL_LENGTH; 431 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 432 433 } 434 /* clear status bit */ 435 ich_wr(sc, ch->regbase + 436 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 437 st, 2); 438 } 439 if (gs != 0) { 440 device_printf(sc->dev, 441 "Unhandled interrupt, gs_intr = %x\n", gs); 442 } 443} 444 445/* ------------------------------------------------------------------------- */ 446/* Sysctl to control ac97 speed (some boards appear to end up using 447 * XTAL_IN rather than BIT_CLK for link timing). 448 */ 449 450static int 451ich_initsys(struct sc_info* sc) 452{ 453#ifdef SND_DYNSYSCTL 454 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 455 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 456 OID_AUTO, "ac97rate", CTLFLAG_RW, 457 &sc->ac97rate, 48000, 458 "AC97 link rate (default = 48000)"); 459#endif /* SND_DYNSYSCTL */ 460 return 0; 461} 462 463/* -------------------------------------------------------------------- */ 464/* Calibrate card to determine the clock source. The source maybe a 465 * function of the ac97 codec initialization code (to be investigated). 466 */ 467 468static 469void ich_calibrate(void *arg) 470{ 471 struct sc_info *sc; 472 struct sc_chinfo *ch; 473 struct timeval t1, t2; 474 u_int8_t ociv, nciv; 475 u_int32_t wait_us, actual_48k_rate, bytes; 476 477 sc = (struct sc_info *)arg; 478 ch = &sc->ch[1]; 479 480 if (sc->use_intrhook) 481 config_intrhook_disestablish(&sc->intrhook); 482 483 /* 484 * Grab audio from input for fixed interval and compare how 485 * much we actually get with what we expect. Interval needs 486 * to be sufficiently short that no interrupts are 487 * generated. 488 */ 489 490 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 491 492 bytes = sndbuf_getsize(ch->buffer) / 2; 493 ichchan_setblocksize(0, ch, bytes); 494 495 /* 496 * our data format is stereo, 16 bit so each sample is 4 bytes. 497 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 498 * we're going to start recording with interrupts disabled and measure 499 * the time taken for one block to complete. we know the block size, 500 * we know the time in microseconds, we calculate the sample rate: 501 * 502 * actual_rate [bps] = bytes / (time [s] * 4) 503 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 504 * actual_rate [Hz] = (bytes * 250000) / time [us] 505 */ 506 507 /* prepare */ 508 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 509 nciv = ociv; 510 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 511 512 /* start */ 513 microtime(&t1); 514 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 515 516 /* wait */ 517 while (nciv == ociv) { 518 microtime(&t2); 519 if (t2.tv_sec - t1.tv_sec > 1) 520 break; 521 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 522 } 523 microtime(&t2); 524 525 /* stop */ 526 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 527 528 /* reset */ 529 DELAY(100); 530 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 531 532 /* turn time delta into us */ 533 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 534 535 if (nciv == ociv) { 536 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 537 return; 538 } 539 540 actual_48k_rate = (bytes * 250000) / wait_us; 541 542 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 543 sc->ac97rate = actual_48k_rate; 544 } else { 545 sc->ac97rate = 48000; 546 } 547 548 if (bootverbose || sc->ac97rate != 48000) { 549 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 550 if (sc->ac97rate != actual_48k_rate) 551 printf(", will use %d Hz", sc->ac97rate); 552 printf("\n"); 553 } 554 555 return; 556} 557 558/* -------------------------------------------------------------------- */ 559/* Probe and attach the card */ 560 561static void 562ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 563{ 564 struct sc_info *sc = (struct sc_info *)arg; 565 sc->desc_addr = segs->ds_addr; 566 return; 567} 568 569static int 570ich_init(struct sc_info *sc) 571{ 572 u_int32_t stat; 573 int sz; 574 575 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 576 DELAY(600000); 577 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 578 579 if ((stat & ICH_GLOB_STA_PCR) == 0) { 580 /* ICH4 may fail when busmastering is enabled. Continue */ 581 if (pci_get_devid(sc->dev) != ICH4ID) { 582 return ENXIO; 583 } 584 } 585 586 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 587 588 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 589 return ENXIO; 590 if (sc->hasmic && ich_resetchan(sc, 2)) 591 return ENXIO; 592 593 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 594 return ENOSPC; 595 596 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 597 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) { 598 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 599 return ENOSPC; 600 } 601 602 return 0; 603} 604 605static int 606ich_pci_probe(device_t dev) 607{ 608 switch(pci_get_devid(dev)) { 609 case 0x71958086: 610 device_set_desc(dev, "Intel 443MX"); 611 return 0; 612 613 case 0x24158086: 614 device_set_desc(dev, "Intel ICH (82801AA)"); 615 return 0; 616 617 case 0x24258086: 618 device_set_desc(dev, "Intel ICH (82801AB)"); 619 return 0; 620 621 case 0x24458086: 622 device_set_desc(dev, "Intel ICH2 (82801BA)"); 623 return 0; 624 625 case 0x24858086: 626 device_set_desc(dev, "Intel ICH3 (82801CA)"); 627 return 0; 628 629 case ICH4ID: 630 device_set_desc(dev, "Intel ICH4 (82801DB)"); 631 return 0; 632 633 case SIS7012ID: 634 device_set_desc(dev, "SiS 7012"); 635 return 0; 636 637 case 0x01b110de: 638 device_set_desc(dev, "Nvidia nForce"); 639 return 0; 640 641 case 0x006a10de: 642 device_set_desc(dev, "Nvidia nForce2"); 643 return 0; 644 645 case 0x74451022: 646 device_set_desc(dev, "AMD-768"); 647 return 0; 648 649 default: 650 return ENXIO; 651 } 652} 653 654static int 655ich_pci_attach(device_t dev) 656{ 657 u_int16_t extcaps; 658 struct sc_info *sc; 659 char status[SND_STATUSLEN]; 660 661 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 662 device_printf(dev, "cannot allocate softc\n"); 663 return ENXIO; 664 } 665 666 bzero(sc, sizeof(*sc)); 667 sc->dev = dev; 668 669 /* 670 * The SiS 7012 register set isn't quite like the standard ich. 671 * There really should be a general "quirks" mechanism. 672 */ 673 if (pci_get_devid(dev) == SIS7012ID) { 674 sc->swap_reg = 1; 675 sc->sample_size = 1; 676 } else { 677 sc->swap_reg = 0; 678 sc->sample_size = 2; 679 } 680 681 /* 682 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 683 * read-only. Need to enable "legacy support", by poking into 684 * pci config space. The driver should use MMBAR and MBBAR, 685 * but doing so will mess things up here. ich4 has enough new 686 * features it warrants it's own driver. 687 */ 688 if (pci_get_devid(dev) == ICH4ID) { 689 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 690 } 691 692 /* 693 * Enable bus master. On ich4 this may prevent the detection of 694 * the primary codec becoming ready in ich_init(). 695 */ 696 pci_enable_busmaster(dev); 697 698 sc->nambarid = PCIR_NAMBAR; 699 sc->nabmbarid = PCIR_NABMBAR; 700 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE); 701 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE); 702 703 if (!sc->nambar || !sc->nabmbar) { 704 device_printf(dev, "unable to map IO port space\n"); 705 goto bad; 706 } 707 708 sc->nambart = rman_get_bustag(sc->nambar); 709 sc->nambarh = rman_get_bushandle(sc->nambar); 710 sc->nabmbart = rman_get_bustag(sc->nabmbar); 711 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 712 713 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 714 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 715 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 716 busdma_lock_mutex, &Giant, &sc->dmat) != 0) { 717 device_printf(dev, "unable to create dma tag\n"); 718 goto bad; 719 } 720 721 sc->irqid = 0; 722 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 723 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 724 device_printf(dev, "unable to map interrupt\n"); 725 goto bad; 726 } 727 728 if (ich_init(sc)) { 729 device_printf(dev, "unable to initialize the card\n"); 730 goto bad; 731 } 732 733 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 734 if (sc->codec == NULL) 735 goto bad; 736 mixer_init(dev, ac97_getmixerclass(), sc->codec); 737 738 /* check and set VRA function */ 739 extcaps = ac97_getextcaps(sc->codec); 740 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 741 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 742 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 743 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 744 745 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 746 goto bad; 747 748 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 749 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 750 if (sc->hasmic) 751 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 752 753 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u", 754 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz); 755 756 pcm_setstatus(dev, status); 757 758 ich_initsys(sc); 759 760 sc->intrhook.ich_func = ich_calibrate; 761 sc->intrhook.ich_arg = sc; 762 sc->use_intrhook = 1; 763 if (config_intrhook_establish(&sc->intrhook) != 0) { 764 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 765 sc->use_intrhook = 0; 766 ich_calibrate(sc); 767 } 768 769 return 0; 770 771bad: 772 if (sc->codec) 773 ac97_destroy(sc->codec); 774 if (sc->ih) 775 bus_teardown_intr(dev, sc->irq, sc->ih); 776 if (sc->irq) 777 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 778 if (sc->nambar) 779 bus_release_resource(dev, SYS_RES_IOPORT, 780 sc->nambarid, sc->nambar); 781 if (sc->nabmbar) 782 bus_release_resource(dev, SYS_RES_IOPORT, 783 sc->nabmbarid, sc->nabmbar); 784 free(sc, M_DEVBUF); 785 return ENXIO; 786} 787 788static int 789ich_pci_detach(device_t dev) 790{ 791 struct sc_info *sc; 792 int r; 793 794 r = pcm_unregister(dev); 795 if (r) 796 return r; 797 sc = pcm_getdevinfo(dev); 798 799 bus_teardown_intr(dev, sc->irq, sc->ih); 800 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 801 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar); 802 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar); 803 bus_dma_tag_destroy(sc->dmat); 804 free(sc, M_DEVBUF); 805 return 0; 806} 807 808static int 809ich_pci_suspend(device_t dev) 810{ 811 struct sc_info *sc; 812 int i; 813 814 sc = pcm_getdevinfo(dev); 815 for (i = 0 ; i < 3; i++) { 816 sc->ch[i].run_save = sc->ch[i].run; 817 if (sc->ch[i].run) { 818 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 819 } 820 } 821 return 0; 822} 823 824static int 825ich_pci_resume(device_t dev) 826{ 827 struct sc_info *sc; 828 int i; 829 830 sc = pcm_getdevinfo(dev); 831 832 /* Reinit audio device */ 833 if (ich_init(sc) == -1) { 834 device_printf(dev, "unable to reinitialize the card\n"); 835 return ENXIO; 836 } 837 /* Reinit mixer */ 838 if (mixer_reinit(dev) == -1) { 839 device_printf(dev, "unable to reinitialize the mixer\n"); 840 return ENXIO; 841 } 842 /* Re-start DMA engines */ 843 for (i = 0 ; i < 3; i++) { 844 struct sc_chinfo *ch = &sc->ch[i]; 845 if (sc->ch[i].run_save) { 846 ichchan_setblocksize(0, ch, ch->blksz); 847 ichchan_setspeed(0, ch, ch->spd); 848 ichchan_trigger(0, ch, PCMTRIG_START); 849 } 850 } 851 return 0; 852} 853 854static device_method_t ich_methods[] = { 855 /* Device interface */ 856 DEVMETHOD(device_probe, ich_pci_probe), 857 DEVMETHOD(device_attach, ich_pci_attach), 858 DEVMETHOD(device_detach, ich_pci_detach), 859 DEVMETHOD(device_suspend, ich_pci_suspend), 860 DEVMETHOD(device_resume, ich_pci_resume), 861 { 0, 0 } 862}; 863 864static driver_t ich_driver = { 865 "pcm", 866 ich_methods, 867 PCM_SOFTC_SIZE, 868}; 869 870DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 871MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 872MODULE_VERSION(snd_ich, 1); 873