hdac_reg.h revision 162922
1285SN/A/*- 2641Smkos * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3285SN/A * All rights reserved. 4285SN/A * 5285SN/A * Redistribution and use in source and binary forms, with or without 6285SN/A * modification, are permitted provided that the following conditions 7285SN/A * are met: 8285SN/A * 1. Redistributions of source code must retain the above copyright 9285SN/A * notice, this list of conditions and the following disclaimer. 10285SN/A * 2. Redistributions in binary form must reproduce the above copyright 11285SN/A * notice, this list of conditions and the following disclaimer in the 12285SN/A * documentation and/or other materials provided with the distribution. 13285SN/A * 14285SN/A * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15285SN/A * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16285SN/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17285SN/A * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18285SN/A * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19285SN/A * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20285SN/A * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21285SN/A * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22285SN/A * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23285SN/A * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24285SN/A * SUCH DAMAGE. 25285SN/A * 26285SN/A * $FreeBSD: head/sys/dev/sound/pci/hda/hdac_reg.h 162922 2006-10-01 11:13:00Z ariff $ 27285SN/A */ 28285SN/A 29285SN/A#ifndef _HDAC_REG_H_ 30285SN/A#define _HDAC_REG_H_ 31285SN/A 32285SN/A/**************************************************************************** 33285SN/A * HDA Controller Register Set 34285SN/A ****************************************************************************/ 35285SN/A#define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/ 36285SN/A#define HDAC_VMIN 0x02 /* 1 - Minor Version */ 37285SN/A#define HDAC_VMAJ 0x03 /* 1 - Major Version */ 38285SN/A#define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */ 39285SN/A#define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */ 40285SN/A#define HDAC_GCTL 0x08 /* 4 - Global Control */ 41285SN/A#define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */ 42285SN/A#define HDAC_STATESTS 0x0e /* 2 - State Change Status */ 43285SN/A#define HDAC_GSTS 0x10 /* 2 - Global Status */ 44285SN/A#define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */ 45285SN/A#define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */ 46285SN/A#define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */ 47285SN/A#define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */ 48285SN/A#define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */ 49285SN/A#define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */ 50285SN/A#define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */ 51285SN/A#define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */ 52285SN/A#define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */ 53285SN/A#define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */ 54285SN/A#define HDAC_CORBCTL 0x4c /* 1 - CORB Control */ 55285SN/A#define HDAC_CORBSTS 0x4d /* 1 - CORB Status */ 56285SN/A#define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */ 57285SN/A#define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */ 58285SN/A#define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */ 59285SN/A#define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */ 60285SN/A#define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */ 61285SN/A#define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */ 62285SN/A#define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */ 63641Smkos#define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */ 64285SN/A#define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */ 65285SN/A#define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */ 66285SN/A#define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */ 67285SN/A#define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */ 68285SN/A#define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */ 69285SN/A#define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */ 70285SN/A#define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */ 71285SN/A#define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */ 72#define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */ 73#define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */ 74#define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */ 75#define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */ 76#define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */ 77#define HDAC_SDFMT 0x92 /* 2 - fmt */ 78#define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */ 79#define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */ 80 81#define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20)) 82#define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss)) 83#define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss)) 84#define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss)) 85#define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss)) 86#define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss)) 87#define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss)) 88#define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss)) 89#define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss)) 90#define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss)) 91 92#define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20)) 93#define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss)) 94#define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss)) 95#define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss)) 96#define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss)) 97#define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss)) 98#define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss)) 99#define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss)) 100#define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss)) 101#define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss)) 102 103#define _HDAC_BSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20)) 104#define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss)) 105#define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss)) 106#define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss)) 107#define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss)) 108#define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss)) 109#define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss)) 110#define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss)) 111#define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss)) 112#define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss)) 113 114/**************************************************************************** 115 * HDA Controller Register Fields 116 ****************************************************************************/ 117 118/* GCAP - Global Capabilities */ 119#define HDAC_GCAP_64OK 0x0001 120#define HDAC_GCAP_NSDO_MASK 0x0006 121#define HDAC_GCAP_NSDO_SHIFT 1 122#define HDAC_GCAP_BSS_MASK 0x00f8 123#define HDAC_GCAP_BSS_SHIFT 3 124#define HDAC_GCAP_ISS_MASK 0x0f00 125#define HDAC_GCAP_ISS_SHIFT 8 126#define HDAC_GCAP_OSS_MASK 0xf000 127#define HDAC_GCAP_OSS_SHIFT 12 128 129#define HDAC_GCAP_NSDO_1SDO 0x00 130#define HDAC_GCAP_NSDO_2SDO 0x02 131#define HDAC_GCAP_NSDO_4SDO 0x04 132 133#define HDAC_GCAP_BSS(gcap) \ 134 (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT) 135#define HDAC_GCAP_ISS(gcap) \ 136 (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT) 137#define HDAC_GCAP_OSS(gcap) \ 138 (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT) 139 140/* GCTL - Global Control */ 141#define HDAC_GCTL_CRST 0x00000001 142#define HDAC_GCTL_FCNTRL 0x00000002 143#define HDAC_GCTL_UNSOL 0x00000100 144 145/* WAKEEN - Wake Enable */ 146#define HDAC_WAKEEN_SDIWEN_MASK 0x7fff 147#define HDAC_WAKEEN_SDIWEN_SHIFT 0 148 149/* STATESTS - State Change Status */ 150#define HDAC_STATESTS_SDIWAKE_MASK 0x7fff 151#define HDAC_STATESTS_SDIWAKE_SHIFT 0 152 153#define HDAC_STATESTS_SDIWAKE(statests, n) \ 154 (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \ 155 HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001) 156 157/* GSTS - Global Status */ 158#define HDAC_GSTS_FSTS 0x0002 159 160/* INTCTL - Interrut Control */ 161#define HDAC_INTCTL_SIE_MASK 0x3fffffff 162#define HDAC_INTCTL_SIE_SHIFT 0 163#define HDAC_INTCTL_CIE 0x40000000 164#define HDAC_INTCTL_GIE 0x80000000 165 166/* INTSTS - Interrupt Status */ 167#define HDAC_INTSTS_SIS_MASK 0x3fffffff 168#define HDAC_INTSTS_SIS_SHIFT 0 169#define HDAC_INTSTS_CIS 0x40000000 170#define HDAC_INTSTS_GIS 0x80000000 171 172/* SSYNC - Stream Synchronization */ 173#define HDAC_SSYNC_SSYNC_MASK 0x3fffffff 174#define HDAC_SSYNC_SSYNC_SHIFT 0 175 176/* CORBWP - CORB Write Pointer */ 177#define HDAC_CORBWP_CORBWP_MASK 0x00ff 178#define HDAC_CORBWP_CORBWP_SHIFT 0 179 180/* CORBRP - CORB Read Pointer */ 181#define HDAC_CORBRP_CORBRP_MASK 0x00ff 182#define HDAC_CORBRP_CORBRP_SHIFT 0 183#define HDAC_CORBRP_CORBRPRST 0x8000 184 185/* CORBCTL - CORB Control */ 186#define HDAC_CORBCTL_CMEIE 0x01 187#define HDAC_CORBCTL_CORBRUN 0x02 188 189/* CORBSTS - CORB Status */ 190#define HDAC_CORBSTS_CMEI 0x01 191 192/* CORBSIZE - CORB Size */ 193#define HDAC_CORBSIZE_CORBSIZE_MASK 0x03 194#define HDAC_CORBSIZE_CORBSIZE_SHIFT 0 195#define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0 196#define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4 197 198#define HDAC_CORBSIZE_CORBSIZE_2 0x00 199#define HDAC_CORBSIZE_CORBSIZE_16 0x01 200#define HDAC_CORBSIZE_CORBSIZE_256 0x02 201 202#define HDAC_CORBSIZE_CORBSZCAP_2 0x10 203#define HDAC_CORBSIZE_CORBSZCAP_16 0x20 204#define HDAC_CORBSIZE_CORBSZCAP_256 0x40 205 206#define HDAC_CORBSIZE_CORBSIZE(corbsize) \ 207 (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT) 208 209/* RIRBWP - RIRB Write Pointer */ 210#define HDAC_RIRBWP_RIRBWP_MASK 0x00ff 211#define HDAC_RIRBWP_RIRBWP_SHIFT 0 212#define HDAC_RIRBWP_RIRBWPRST 0x8000 213 214/* RINTCTN - Response Interrupt Count */ 215#define HDAC_RINTCNT_MASK 0x00ff 216#define HDAC_RINTCNT_SHIFT 0 217 218/* RIRBCTL - RIRB Control */ 219#define HDAC_RIRBCTL_RINTCTL 0x01 220#define HDAC_RIRBCTL_RIRBDMAEN 0x02 221#define HDAC_RIRBCTL_RIRBOIC 0x04 222 223/* RIRBSTS - RIRB Status */ 224#define HDAC_RIRBSTS_RINTFL 0x01 225#define HDAC_RIRBSTS_RIRBOIS 0x04 226 227/* RIRBSIZE - RIRB Size */ 228#define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03 229#define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0 230#define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0 231#define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4 232 233#define HDAC_RIRBSIZE_RIRBSIZE_2 0x00 234#define HDAC_RIRBSIZE_RIRBSIZE_16 0x01 235#define HDAC_RIRBSIZE_RIRBSIZE_256 0x02 236 237#define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10 238#define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20 239#define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40 240 241#define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \ 242 (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT) 243 244/* DPLBASE - DMA Position Lower Base Address */ 245#define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80 246#define HDAC_DPLBASE_DPLBASE_SHIFT 7 247#define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001 248 249/* SDCTL - Stream Descriptor Control */ 250#define HDAC_SDCTL_SRST 0x000001 251#define HDAC_SDCTL_RUN 0x000002 252#define HDAC_SDCTL_IOCE 0x000004 253#define HDAC_SDCTL_FEIE 0x000008 254#define HDAC_SDCTL_DEIE 0x000010 255#define HDAC_SDCTL_STRIPE_MASK 0x030000 256#define HDAC_SDCTL_STRIPE_SHIFT 16 257#define HDAC_SDCTL_TP 0x040000 258#define HDAC_SDCTL_DIR 0x080000 259#define HDAC_SDCTL2_STRM_MASK 0xf0 260#define HDAC_SDCTL2_STRM_SHIFT 4 261 262#define HDAC_SDSTS_DESE (1 << 4) 263#define HDAC_SDSTS_FIFOE (1 << 3) 264#define HDAC_SDSTS_BCIS (1 << 2) 265 266#endif 267