1162922Sariff/*- 2162922Sariff * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3162922Sariff * All rights reserved. 4162922Sariff * 5162922Sariff * Redistribution and use in source and binary forms, with or without 6162922Sariff * modification, are permitted provided that the following conditions 7162922Sariff * are met: 8162922Sariff * 1. Redistributions of source code must retain the above copyright 9162922Sariff * notice, this list of conditions and the following disclaimer. 10162922Sariff * 2. Redistributions in binary form must reproduce the above copyright 11162922Sariff * notice, this list of conditions and the following disclaimer in the 12162922Sariff * documentation and/or other materials provided with the distribution. 13162922Sariff * 14162922Sariff * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15162922Sariff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16162922Sariff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17162922Sariff * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18162922Sariff * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19162922Sariff * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20162922Sariff * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21162922Sariff * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22162922Sariff * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23162922Sariff * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24162922Sariff * SUCH DAMAGE. 25162922Sariff * 26162922Sariff * $FreeBSD: releng/10.2/sys/dev/sound/pci/hda/hdac_reg.h 230130 2012-01-15 13:21:36Z mav $ 27162922Sariff */ 28162922Sariff 29162922Sariff#ifndef _HDAC_REG_H_ 30162922Sariff#define _HDAC_REG_H_ 31162922Sariff 32162922Sariff/**************************************************************************** 33162922Sariff * HDA Controller Register Set 34162922Sariff ****************************************************************************/ 35162922Sariff#define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/ 36162922Sariff#define HDAC_VMIN 0x02 /* 1 - Minor Version */ 37162922Sariff#define HDAC_VMAJ 0x03 /* 1 - Major Version */ 38162922Sariff#define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */ 39162922Sariff#define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */ 40162922Sariff#define HDAC_GCTL 0x08 /* 4 - Global Control */ 41162922Sariff#define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */ 42162922Sariff#define HDAC_STATESTS 0x0e /* 2 - State Change Status */ 43162922Sariff#define HDAC_GSTS 0x10 /* 2 - Global Status */ 44162922Sariff#define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */ 45162922Sariff#define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */ 46162922Sariff#define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */ 47162922Sariff#define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */ 48162922Sariff#define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */ 49162922Sariff#define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */ 50162922Sariff#define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */ 51162922Sariff#define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */ 52162922Sariff#define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */ 53162922Sariff#define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */ 54162922Sariff#define HDAC_CORBCTL 0x4c /* 1 - CORB Control */ 55162922Sariff#define HDAC_CORBSTS 0x4d /* 1 - CORB Status */ 56162922Sariff#define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */ 57162922Sariff#define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */ 58162922Sariff#define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */ 59162922Sariff#define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */ 60162922Sariff#define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */ 61162922Sariff#define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */ 62162922Sariff#define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */ 63162922Sariff#define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */ 64162922Sariff#define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */ 65162922Sariff#define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */ 66162922Sariff#define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */ 67162922Sariff#define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */ 68162922Sariff#define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */ 69162922Sariff#define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */ 70162922Sariff#define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */ 71162922Sariff#define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */ 72162922Sariff#define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */ 73162922Sariff#define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */ 74162922Sariff#define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */ 75162922Sariff#define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */ 76162922Sariff#define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */ 77162922Sariff#define HDAC_SDFMT 0x92 /* 2 - fmt */ 78162922Sariff#define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */ 79162922Sariff#define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */ 80162922Sariff 81162922Sariff#define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20)) 82162922Sariff#define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss)) 83162922Sariff#define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss)) 84162922Sariff#define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss)) 85162922Sariff#define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss)) 86162922Sariff#define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss)) 87162922Sariff#define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss)) 88162922Sariff#define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss)) 89162922Sariff#define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss)) 90162922Sariff#define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss)) 91162922Sariff 92162922Sariff#define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20)) 93162922Sariff#define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss)) 94162922Sariff#define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss)) 95162922Sariff#define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss)) 96162922Sariff#define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss)) 97162922Sariff#define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss)) 98162922Sariff#define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss)) 99162922Sariff#define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss)) 100162922Sariff#define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss)) 101162922Sariff#define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss)) 102162922Sariff 103162922Sariff#define _HDAC_BSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20)) 104162922Sariff#define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss)) 105162922Sariff#define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss)) 106162922Sariff#define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss)) 107162922Sariff#define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss)) 108162922Sariff#define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss)) 109162922Sariff#define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss)) 110162922Sariff#define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss)) 111162922Sariff#define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss)) 112162922Sariff#define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss)) 113162922Sariff 114162922Sariff/**************************************************************************** 115162922Sariff * HDA Controller Register Fields 116162922Sariff ****************************************************************************/ 117162922Sariff 118162922Sariff/* GCAP - Global Capabilities */ 119162922Sariff#define HDAC_GCAP_64OK 0x0001 120162922Sariff#define HDAC_GCAP_NSDO_MASK 0x0006 121162922Sariff#define HDAC_GCAP_NSDO_SHIFT 1 122162922Sariff#define HDAC_GCAP_BSS_MASK 0x00f8 123162922Sariff#define HDAC_GCAP_BSS_SHIFT 3 124162922Sariff#define HDAC_GCAP_ISS_MASK 0x0f00 125162922Sariff#define HDAC_GCAP_ISS_SHIFT 8 126162922Sariff#define HDAC_GCAP_OSS_MASK 0xf000 127162922Sariff#define HDAC_GCAP_OSS_SHIFT 12 128162922Sariff 129162922Sariff#define HDAC_GCAP_NSDO_1SDO 0x00 130162922Sariff#define HDAC_GCAP_NSDO_2SDO 0x02 131162922Sariff#define HDAC_GCAP_NSDO_4SDO 0x04 132162922Sariff 133162922Sariff#define HDAC_GCAP_BSS(gcap) \ 134162922Sariff (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT) 135162922Sariff#define HDAC_GCAP_ISS(gcap) \ 136162922Sariff (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT) 137162922Sariff#define HDAC_GCAP_OSS(gcap) \ 138162922Sariff (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT) 139196762Smav#define HDAC_GCAP_NSDO(gcap) \ 140196762Smav (((gcap) & HDAC_GCAP_NSDO_MASK) >> HDAC_GCAP_NSDO_SHIFT) 141162922Sariff 142162922Sariff/* GCTL - Global Control */ 143162922Sariff#define HDAC_GCTL_CRST 0x00000001 144162922Sariff#define HDAC_GCTL_FCNTRL 0x00000002 145162922Sariff#define HDAC_GCTL_UNSOL 0x00000100 146162922Sariff 147162922Sariff/* WAKEEN - Wake Enable */ 148162922Sariff#define HDAC_WAKEEN_SDIWEN_MASK 0x7fff 149162922Sariff#define HDAC_WAKEEN_SDIWEN_SHIFT 0 150162922Sariff 151162922Sariff/* STATESTS - State Change Status */ 152162922Sariff#define HDAC_STATESTS_SDIWAKE_MASK 0x7fff 153162922Sariff#define HDAC_STATESTS_SDIWAKE_SHIFT 0 154162922Sariff 155162922Sariff#define HDAC_STATESTS_SDIWAKE(statests, n) \ 156162922Sariff (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \ 157162922Sariff HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001) 158162922Sariff 159162922Sariff/* GSTS - Global Status */ 160162922Sariff#define HDAC_GSTS_FSTS 0x0002 161162922Sariff 162162922Sariff/* INTCTL - Interrut Control */ 163162922Sariff#define HDAC_INTCTL_SIE_MASK 0x3fffffff 164162922Sariff#define HDAC_INTCTL_SIE_SHIFT 0 165162922Sariff#define HDAC_INTCTL_CIE 0x40000000 166162922Sariff#define HDAC_INTCTL_GIE 0x80000000 167162922Sariff 168162922Sariff/* INTSTS - Interrupt Status */ 169162922Sariff#define HDAC_INTSTS_SIS_MASK 0x3fffffff 170162922Sariff#define HDAC_INTSTS_SIS_SHIFT 0 171162922Sariff#define HDAC_INTSTS_CIS 0x40000000 172162922Sariff#define HDAC_INTSTS_GIS 0x80000000 173162922Sariff 174162922Sariff/* SSYNC - Stream Synchronization */ 175162922Sariff#define HDAC_SSYNC_SSYNC_MASK 0x3fffffff 176162922Sariff#define HDAC_SSYNC_SSYNC_SHIFT 0 177162922Sariff 178162922Sariff/* CORBWP - CORB Write Pointer */ 179162922Sariff#define HDAC_CORBWP_CORBWP_MASK 0x00ff 180162922Sariff#define HDAC_CORBWP_CORBWP_SHIFT 0 181162922Sariff 182162922Sariff/* CORBRP - CORB Read Pointer */ 183162922Sariff#define HDAC_CORBRP_CORBRP_MASK 0x00ff 184162922Sariff#define HDAC_CORBRP_CORBRP_SHIFT 0 185162922Sariff#define HDAC_CORBRP_CORBRPRST 0x8000 186162922Sariff 187162922Sariff/* CORBCTL - CORB Control */ 188162922Sariff#define HDAC_CORBCTL_CMEIE 0x01 189162922Sariff#define HDAC_CORBCTL_CORBRUN 0x02 190162922Sariff 191162922Sariff/* CORBSTS - CORB Status */ 192162922Sariff#define HDAC_CORBSTS_CMEI 0x01 193162922Sariff 194162922Sariff/* CORBSIZE - CORB Size */ 195162922Sariff#define HDAC_CORBSIZE_CORBSIZE_MASK 0x03 196162922Sariff#define HDAC_CORBSIZE_CORBSIZE_SHIFT 0 197162922Sariff#define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0 198162922Sariff#define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4 199162922Sariff 200162922Sariff#define HDAC_CORBSIZE_CORBSIZE_2 0x00 201162922Sariff#define HDAC_CORBSIZE_CORBSIZE_16 0x01 202162922Sariff#define HDAC_CORBSIZE_CORBSIZE_256 0x02 203162922Sariff 204162922Sariff#define HDAC_CORBSIZE_CORBSZCAP_2 0x10 205162922Sariff#define HDAC_CORBSIZE_CORBSZCAP_16 0x20 206162922Sariff#define HDAC_CORBSIZE_CORBSZCAP_256 0x40 207162922Sariff 208162922Sariff#define HDAC_CORBSIZE_CORBSIZE(corbsize) \ 209162922Sariff (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT) 210162922Sariff 211162922Sariff/* RIRBWP - RIRB Write Pointer */ 212162922Sariff#define HDAC_RIRBWP_RIRBWP_MASK 0x00ff 213162922Sariff#define HDAC_RIRBWP_RIRBWP_SHIFT 0 214162922Sariff#define HDAC_RIRBWP_RIRBWPRST 0x8000 215162922Sariff 216162922Sariff/* RINTCTN - Response Interrupt Count */ 217162922Sariff#define HDAC_RINTCNT_MASK 0x00ff 218162922Sariff#define HDAC_RINTCNT_SHIFT 0 219162922Sariff 220162922Sariff/* RIRBCTL - RIRB Control */ 221162922Sariff#define HDAC_RIRBCTL_RINTCTL 0x01 222162922Sariff#define HDAC_RIRBCTL_RIRBDMAEN 0x02 223162922Sariff#define HDAC_RIRBCTL_RIRBOIC 0x04 224162922Sariff 225162922Sariff/* RIRBSTS - RIRB Status */ 226162922Sariff#define HDAC_RIRBSTS_RINTFL 0x01 227162922Sariff#define HDAC_RIRBSTS_RIRBOIS 0x04 228162922Sariff 229162922Sariff/* RIRBSIZE - RIRB Size */ 230162922Sariff#define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03 231162922Sariff#define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0 232162922Sariff#define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0 233162922Sariff#define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4 234162922Sariff 235162922Sariff#define HDAC_RIRBSIZE_RIRBSIZE_2 0x00 236162922Sariff#define HDAC_RIRBSIZE_RIRBSIZE_16 0x01 237162922Sariff#define HDAC_RIRBSIZE_RIRBSIZE_256 0x02 238162922Sariff 239162922Sariff#define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10 240162922Sariff#define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20 241162922Sariff#define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40 242162922Sariff 243162922Sariff#define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \ 244162922Sariff (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT) 245162922Sariff 246162922Sariff/* DPLBASE - DMA Position Lower Base Address */ 247162922Sariff#define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80 248162922Sariff#define HDAC_DPLBASE_DPLBASE_SHIFT 7 249162922Sariff#define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001 250162922Sariff 251162922Sariff/* SDCTL - Stream Descriptor Control */ 252162922Sariff#define HDAC_SDCTL_SRST 0x000001 253162922Sariff#define HDAC_SDCTL_RUN 0x000002 254162922Sariff#define HDAC_SDCTL_IOCE 0x000004 255162922Sariff#define HDAC_SDCTL_FEIE 0x000008 256162922Sariff#define HDAC_SDCTL_DEIE 0x000010 257230130Smav#define HDAC_SDCTL2_STRIPE_MASK 0x03 258230130Smav#define HDAC_SDCTL2_STRIPE_SHIFT 0 259230130Smav#define HDAC_SDCTL2_TP 0x04 260230130Smav#define HDAC_SDCTL2_DIR 0x08 261162922Sariff#define HDAC_SDCTL2_STRM_MASK 0xf0 262162922Sariff#define HDAC_SDCTL2_STRM_SHIFT 4 263162922Sariff 264162922Sariff#define HDAC_SDSTS_DESE (1 << 4) 265162922Sariff#define HDAC_SDSTS_FIFOE (1 << 3) 266162922Sariff#define HDAC_SDSTS_BCIS (1 << 2) 267162922Sariff 268162922Sariff#endif 269