1162922Sariff/*- 2162922Sariff * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3162922Sariff * All rights reserved. 4162922Sariff * 5162922Sariff * Redistribution and use in source and binary forms, with or without 6162922Sariff * modification, are permitted provided that the following conditions 7162922Sariff * are met: 8162922Sariff * 1. Redistributions of source code must retain the above copyright 9162922Sariff * notice, this list of conditions and the following disclaimer. 10162922Sariff * 2. Redistributions in binary form must reproduce the above copyright 11162922Sariff * notice, this list of conditions and the following disclaimer in the 12162922Sariff * documentation and/or other materials provided with the distribution. 13162922Sariff * 14162922Sariff * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15162922Sariff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16162922Sariff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17162922Sariff * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18162922Sariff * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19162922Sariff * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20162922Sariff * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21162922Sariff * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22162922Sariff * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23162922Sariff * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24162922Sariff * SUCH DAMAGE. 25162922Sariff * 26162922Sariff * $FreeBSD: releng/10.2/sys/dev/sound/pci/hda/hda_reg.h 230312 2012-01-18 19:12:33Z mav $ 27162922Sariff */ 28162922Sariff 29162922Sariff#ifndef _HDA_REG_H_ 30162922Sariff#define _HDA_REG_H_ 31162922Sariff 32162922Sariff/**************************************************************************** 33162922Sariff * HDA Device Verbs 34162922Sariff ****************************************************************************/ 35162922Sariff 36162922Sariff/* HDA Command */ 37162922Sariff#define HDA_CMD_VERB_MASK 0x000fffff 38162922Sariff#define HDA_CMD_VERB_SHIFT 0 39162922Sariff#define HDA_CMD_NID_MASK 0x0ff00000 40162922Sariff#define HDA_CMD_NID_SHIFT 20 41162922Sariff#define HDA_CMD_CAD_MASK 0xf0000000 42162922Sariff#define HDA_CMD_CAD_SHIFT 28 43162922Sariff 44162922Sariff#define HDA_CMD_VERB_4BIT_SHIFT 16 45162922Sariff#define HDA_CMD_VERB_12BIT_SHIFT 8 46162922Sariff 47162922Sariff#define HDA_CMD_VERB_4BIT(verb, payload) \ 48162922Sariff (((verb) << HDA_CMD_VERB_4BIT_SHIFT) | (payload)) 49162922Sariff#define HDA_CMD_4BIT(cad, nid, verb, payload) \ 50162922Sariff (((cad) << HDA_CMD_CAD_SHIFT) | \ 51162922Sariff ((nid) << HDA_CMD_NID_SHIFT) | \ 52162922Sariff (HDA_CMD_VERB_4BIT((verb), (payload)))) 53162922Sariff 54162922Sariff#define HDA_CMD_VERB_12BIT(verb, payload) \ 55162922Sariff (((verb) << HDA_CMD_VERB_12BIT_SHIFT) | (payload)) 56162922Sariff#define HDA_CMD_12BIT(cad, nid, verb, payload) \ 57162922Sariff (((cad) << HDA_CMD_CAD_SHIFT) | \ 58162922Sariff ((nid) << HDA_CMD_NID_SHIFT) | \ 59162922Sariff (HDA_CMD_VERB_12BIT((verb), (payload)))) 60162922Sariff 61162922Sariff/* Get Parameter */ 62162922Sariff#define HDA_CMD_VERB_GET_PARAMETER 0xf00 63162922Sariff 64162922Sariff#define HDA_CMD_GET_PARAMETER(cad, nid, payload) \ 65162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 66162922Sariff HDA_CMD_VERB_GET_PARAMETER, (payload))) 67162922Sariff 68162922Sariff/* Connection Select Control */ 69162922Sariff#define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01 70162922Sariff#define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701 71162922Sariff 72162922Sariff#define HDA_CMD_GET_CONN_SELECT_CONTROL(cad, nid) \ 73162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 74162922Sariff HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0)) 75162922Sariff#define HDA_CMD_SET_CONNECTION_SELECT_CONTROL(cad, nid, payload) \ 76162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 77162922Sariff HDA_CMD_VERB_SET_CONN_SELECT_CONTROL, (payload))) 78162922Sariff 79162922Sariff/* Connection List Entry */ 80162922Sariff#define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02 81162922Sariff 82162922Sariff#define HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, payload) \ 83162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 84162922Sariff HDA_CMD_VERB_GET_CONN_LIST_ENTRY, (payload))) 85162922Sariff 86162922Sariff#define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_SHORT 1 87162922Sariff#define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_LONG 2 88162922Sariff 89162922Sariff/* Processing State */ 90162922Sariff#define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03 91162922Sariff#define HDA_CMD_VERB_SET_PROCESSING_STATE 0x703 92162922Sariff 93162922Sariff#define HDA_CMD_GET_PROCESSING_STATE(cad, nid) \ 94162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 95162922Sariff HDA_CMD_VERB_GET_PROCESSING_STATE, 0x0)) 96162922Sariff#define HDA_CMD_SET_PROCESSING_STATE(cad, nid, payload) \ 97162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 98162922Sariff HDA_CMD_VERB_SET_PROCESSING_STATE, (payload))) 99162922Sariff 100162922Sariff#define HDA_CMD_GET_PROCESSING_STATE_STATE_OFF 0x00 101162922Sariff#define HDA_CMD_GET_PROCESSING_STATE_STATE_ON 0x01 102162922Sariff#define HDA_CMD_GET_PROCESSING_STATE_STATE_BENIGN 0x02 103162922Sariff 104162922Sariff/* Coefficient Index */ 105162922Sariff#define HDA_CMD_VERB_GET_COEFF_INDEX 0xd 106162922Sariff#define HDA_CMD_VERB_SET_COEFF_INDEX 0x5 107162922Sariff 108162922Sariff#define HDA_CMD_GET_COEFF_INDEX(cad, nid) \ 109162922Sariff (HDA_CMD_4BIT((cad), (nid), \ 110162922Sariff HDA_CMD_VERB_GET_COEFF_INDEX, 0x0)) 111162922Sariff#define HDA_CMD_SET_COEFF_INDEX(cad, nid, payload) \ 112162922Sariff (HDA_CMD_4BIT((cad), (nid), \ 113162922Sariff HDA_CMD_VERB_SET_COEFF_INDEX, (payload))) 114162922Sariff 115162922Sariff/* Processing Coefficient */ 116162922Sariff#define HDA_CMD_VERB_GET_PROCESSING_COEFF 0xc 117162922Sariff#define HDA_CMD_VERB_SET_PROCESSING_COEFF 0x4 118162922Sariff 119162922Sariff#define HDA_CMD_GET_PROCESSING_COEFF(cad, nid) \ 120162922Sariff (HDA_CMD_4BIT((cad), (nid), \ 121162922Sariff HDA_CMD_VERB_GET_PROCESSING_COEFF, 0x0)) 122162922Sariff#define HDA_CMD_SET_PROCESSING_COEFF(cad, nid, payload) \ 123162922Sariff (HDA_CMD_4BIT((cad), (nid), \ 124162922Sariff HDA_CMD_VERB_SET_PROCESSING_COEFF, (payload))) 125162922Sariff 126162922Sariff/* Amplifier Gain/Mute */ 127162922Sariff#define HDA_CMD_VERB_GET_AMP_GAIN_MUTE 0xb 128162922Sariff#define HDA_CMD_VERB_SET_AMP_GAIN_MUTE 0x3 129162922Sariff 130162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE(cad, nid, payload) \ 131162922Sariff (HDA_CMD_4BIT((cad), (nid), \ 132162922Sariff HDA_CMD_VERB_GET_AMP_GAIN_MUTE, (payload))) 133162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, payload) \ 134162922Sariff (HDA_CMD_4BIT((cad), (nid), \ 135162922Sariff HDA_CMD_VERB_SET_AMP_GAIN_MUTE, (payload))) 136162922Sariff 137162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_INPUT 0x0000 138162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_OUTPUT 0x8000 139162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_RIGHT 0x0000 140162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_LEFT 0x2000 141162922Sariff 142162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK 0x00000008 143162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT 7 144162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK 0x00000007 145162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT 0 146162922Sariff 147162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE(rsp) \ 148162922Sariff (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK) >> \ 149162922Sariff HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT) 150162922Sariff#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN(rsp) \ 151162922Sariff (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK) >> \ 152162922Sariff HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT) 153162922Sariff 154162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_OUTPUT 0x8000 155162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_INPUT 0x4000 156162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_LEFT 0x2000 157162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_RIGHT 0x1000 158162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK 0x0f00 159162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT 8 160162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_MUTE 0x0080 161162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK 0x0007 162162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT 0 163162922Sariff 164162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX(index) \ 165162922Sariff (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT) & \ 166162922Sariff HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK) 167162922Sariff#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN(index) \ 168162922Sariff (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT) & \ 169162922Sariff HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK) 170162922Sariff 171162922Sariff/* Converter format */ 172162922Sariff#define HDA_CMD_VERB_GET_CONV_FMT 0xa 173162922Sariff#define HDA_CMD_VERB_SET_CONV_FMT 0x2 174162922Sariff 175162922Sariff#define HDA_CMD_GET_CONV_FMT(cad, nid) \ 176162922Sariff (HDA_CMD_4BIT((cad), (nid), \ 177162922Sariff HDA_CMD_VERB_GET_CONV_FMT, 0x0)) 178162922Sariff#define HDA_CMD_SET_CONV_FMT(cad, nid, payload) \ 179162922Sariff (HDA_CMD_4BIT((cad), (nid), \ 180162922Sariff HDA_CMD_VERB_SET_CONV_FMT, (payload))) 181162922Sariff 182162922Sariff/* Digital Converter Control */ 183182999Smav#define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1 0xf0d 184182999Smav#define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT2 0xf0e 185162922Sariff#define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1 0x70d 186162922Sariff#define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2 0x70e 187162922Sariff 188162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT(cad, nid) \ 189162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 190182999Smav HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1, 0x0)) 191162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, nid, payload) \ 192162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 193162922Sariff HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1, (payload))) 194162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT2(cad, nid, payload) \ 195162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 196162922Sariff HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2, (payload))) 197162922Sariff 198162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK 0x7f00 199162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT 8 200162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK 0x0080 201162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT 7 202162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK 0x0040 203162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT 6 204162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK 0x0020 205162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT 5 206162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK 0x0010 207162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT 4 208162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK 0x0008 209162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT 3 210162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK 0x0004 211162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT 2 212162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK 0x0002 213162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT 1 214162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK 0x0001 215162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT 0 216162922Sariff 217162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC(rsp) \ 218162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK) >> \ 219162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT) 220162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_L(rsp) \ 221162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK) >> \ 222162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT) 223162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO(rsp) \ 224162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK) >> \ 225162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT) 226162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO(rsp) \ 227162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK) >> \ 228162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT) 229162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY(rsp) \ 230162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK) >> \ 231162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT) 232162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE(rsp) \ 233162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK) >> \ 234162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT) 235162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG(rsp) \ 236162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK) >> \ 237162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT) 238162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_V(rsp) \ 239162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK) >> \ 240162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT) 241162922Sariff#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN(rsp) \ 242162922Sariff (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK) >> \ 243162922Sariff HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT) 244162922Sariff 245162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1_L 0x80 246162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRO 0x40 247162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO 0x20 248162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1_COPY 0x10 249162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRE 0x08 250162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1_VCFG 0x04 251162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1_V 0x02 252162922Sariff#define HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN 0x01 253162922Sariff 254162922Sariff/* Power State */ 255162922Sariff#define HDA_CMD_VERB_GET_POWER_STATE 0xf05 256162922Sariff#define HDA_CMD_VERB_SET_POWER_STATE 0x705 257162922Sariff 258162922Sariff#define HDA_CMD_GET_POWER_STATE(cad, nid) \ 259162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 260162922Sariff HDA_CMD_VERB_GET_POWER_STATE, 0x0)) 261162922Sariff#define HDA_CMD_SET_POWER_STATE(cad, nid, payload) \ 262162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 263162922Sariff HDA_CMD_VERB_SET_POWER_STATE, (payload))) 264162922Sariff 265162922Sariff#define HDA_CMD_POWER_STATE_D0 0x00 266162922Sariff#define HDA_CMD_POWER_STATE_D1 0x01 267162922Sariff#define HDA_CMD_POWER_STATE_D2 0x02 268162922Sariff#define HDA_CMD_POWER_STATE_D3 0x03 269162922Sariff 270162922Sariff#define HDA_CMD_POWER_STATE_ACT_MASK 0x000000f0 271162922Sariff#define HDA_CMD_POWER_STATE_ACT_SHIFT 4 272162922Sariff#define HDA_CMD_POWER_STATE_SET_MASK 0x0000000f 273162922Sariff#define HDA_CMD_POWER_STATE_SET_SHIFT 0 274162922Sariff 275162922Sariff#define HDA_CMD_GET_POWER_STATE_ACT(rsp) \ 276162922Sariff (((rsp) & HDA_CMD_POWER_STATE_ACT_MASK) >> \ 277162922Sariff HDA_CMD_POWER_STATE_ACT_SHIFT) 278162922Sariff#define HDA_CMD_GET_POWER_STATE_SET(rsp) \ 279162922Sariff (((rsp) & HDA_CMD_POWER_STATE_SET_MASK) >> \ 280162922Sariff HDA_CMD_POWER_STATE_SET_SHIFT) 281162922Sariff 282162922Sariff#define HDA_CMD_SET_POWER_STATE_ACT(ps) \ 283162922Sariff (((ps) << HDA_CMD_POWER_STATE_ACT_SHIFT) & \ 284162922Sariff HDA_CMD_POWER_STATE_ACT_MASK) 285162922Sariff#define HDA_CMD_SET_POWER_STATE_SET(ps) \ 286162922Sariff (((ps) << HDA_CMD_POWER_STATE_SET_SHIFT) & \ 287162922Sariff HDA_CMD_POWER_STATE_ACT_MASK) 288162922Sariff 289162922Sariff/* Converter Stream, Channel */ 290162922Sariff#define HDA_CMD_VERB_GET_CONV_STREAM_CHAN 0xf06 291162922Sariff#define HDA_CMD_VERB_SET_CONV_STREAM_CHAN 0x706 292162922Sariff 293162922Sariff#define HDA_CMD_GET_CONV_STREAM_CHAN(cad, nid) \ 294162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 295162922Sariff HDA_CMD_VERB_GET_CONV_STREAM_CHAN, 0x0)) 296162922Sariff#define HDA_CMD_SET_CONV_STREAM_CHAN(cad, nid, payload) \ 297162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 298162922Sariff HDA_CMD_VERB_SET_CONV_STREAM_CHAN, (payload))) 299162922Sariff 300162922Sariff#define HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK 0x000000f0 301162922Sariff#define HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT 4 302162922Sariff#define HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK 0x0000000f 303162922Sariff#define HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT 0 304162922Sariff 305162922Sariff#define HDA_CMD_GET_CONV_STREAM_CHAN_STREAM(rsp) \ 306162922Sariff (((rsp) & HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) >> \ 307162922Sariff HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) 308162922Sariff#define HDA_CMD_GET_CONV_STREAM_CHAN_CHAN(rsp) \ 309162922Sariff (((rsp) & HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) >> \ 310162922Sariff HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) 311162922Sariff 312162922Sariff#define HDA_CMD_SET_CONV_STREAM_CHAN_STREAM(param) \ 313162922Sariff (((param) << HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) & \ 314162922Sariff HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) 315162922Sariff#define HDA_CMD_SET_CONV_STREAM_CHAN_CHAN(param) \ 316162922Sariff (((param) << HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) & \ 317162922Sariff HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) 318162922Sariff 319162922Sariff/* Input Converter SDI Select */ 320162922Sariff#define HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04 321162922Sariff#define HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT 0x704 322162922Sariff 323162922Sariff#define HDA_CMD_GET_INPUT_CONVERTER_SDI_SELECT(cad, nid) \ 324162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 325162922Sariff HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT, 0x0)) 326162922Sariff#define HDA_CMD_SET_INPUT_CONVERTER_SDI_SELECT(cad, nid, payload) \ 327162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 328162922Sariff HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT, (payload))) 329162922Sariff 330162922Sariff/* Pin Widget Control */ 331162922Sariff#define HDA_CMD_VERB_GET_PIN_WIDGET_CTRL 0xf07 332162922Sariff#define HDA_CMD_VERB_SET_PIN_WIDGET_CTRL 0x707 333162922Sariff 334162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid) \ 335162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 336162922Sariff HDA_CMD_VERB_GET_PIN_WIDGET_CTRL, 0x0)) 337162922Sariff#define HDA_CMD_SET_PIN_WIDGET_CTRL(cad, nid, payload) \ 338162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 339162922Sariff HDA_CMD_VERB_SET_PIN_WIDGET_CTRL, (payload))) 340162922Sariff 341162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK 0x00000080 342162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT 7 343162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK 0x00000040 344162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT 6 345162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK 0x00000020 346162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT 5 347162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x00000007 348162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0 349162922Sariff 350162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE(rsp) \ 351162922Sariff (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK) >> \ 352162922Sariff HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT) 353162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE(rsp) \ 354162922Sariff (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK) >> \ 355162922Sariff HDA_GET_CMD_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT) 356162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE(rsp) \ 357162922Sariff (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK) >> \ 358162922Sariff HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT) 359162922Sariff#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE(rsp) \ 360162922Sariff (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) >> \ 361162922Sariff HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) 362162922Sariff 363162922Sariff#define HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE 0x80 364162922Sariff#define HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE 0x40 365162922Sariff#define HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE 0x20 366162922Sariff#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x07 367162922Sariff#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0 368162922Sariff 369162922Sariff#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(param) \ 370162922Sariff (((param) << HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) & \ 371162922Sariff HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 372162922Sariff 373162922Sariff#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_HIZ 0 374162922Sariff#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 1 375162922Sariff#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_GROUND 2 376162922Sariff#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4 377162922Sariff#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 5 378162922Sariff 379162922Sariff/* Unsolicited Response */ 380162922Sariff#define HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE 0xf08 381162922Sariff#define HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE 0x708 382162922Sariff 383162922Sariff#define HDA_CMD_GET_UNSOLICITED_RESPONSE(cad, nid) \ 384162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 385162922Sariff HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE, 0x0)) 386162922Sariff#define HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, nid, payload) \ 387162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 388162922Sariff HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE, (payload))) 389162922Sariff 390162922Sariff#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000080 391162922Sariff#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT 7 392162922Sariff#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK 0x0000001f 393162922Sariff#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT 0 394162922Sariff 395162922Sariff#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE(rsp) \ 396162922Sariff (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK) >> \ 397162922Sariff HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT) 398162922Sariff#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG(rsp) \ 399162922Sariff (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK) >> \ 400162922Sariff HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT) 401162922Sariff 402162922Sariff#define HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE 0x80 403230130Smav#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x3f 404162922Sariff#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT 0 405162922Sariff 406162922Sariff#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG(param) \ 407162922Sariff (((param) << HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT) & \ 408162922Sariff HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK) 409162922Sariff 410162922Sariff/* Pin Sense */ 411162922Sariff#define HDA_CMD_VERB_GET_PIN_SENSE 0xf09 412162922Sariff#define HDA_CMD_VERB_SET_PIN_SENSE 0x709 413162922Sariff 414162922Sariff#define HDA_CMD_GET_PIN_SENSE(cad, nid) \ 415162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 416162922Sariff HDA_CMD_VERB_GET_PIN_SENSE, 0x0)) 417162922Sariff#define HDA_CMD_SET_PIN_SENSE(cad, nid, payload) \ 418162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 419162922Sariff HDA_CMD_VERB_SET_PIN_SENSE, (payload))) 420162922Sariff 421230130Smav#define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT 0x80000000 422230312Smav#define HDA_CMD_GET_PIN_SENSE_ELD_VALID 0x40000000 423162922Sariff#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK 0x7fffffff 424162922Sariff#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT 0 425162922Sariff 426162922Sariff#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE(rsp) \ 427162922Sariff (((rsp) & HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK) >> \ 428162922Sariff HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT) 429162922Sariff 430162922Sariff#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_INVALID 0x7fffffff 431162922Sariff 432162922Sariff#define HDA_CMD_SET_PIN_SENSE_LEFT_CHANNEL 0x00 433162922Sariff#define HDA_CMD_SET_PIN_SENSE_RIGHT_CHANNEL 0x01 434162922Sariff 435162922Sariff/* EAPD/BTL Enable */ 436162922Sariff#define HDA_CMD_VERB_GET_EAPD_BTL_ENABLE 0xf0c 437162922Sariff#define HDA_CMD_VERB_SET_EAPD_BTL_ENABLE 0x70c 438162922Sariff 439162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid) \ 440162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 441162922Sariff HDA_CMD_VERB_GET_EAPD_BTL_ENABLE, 0x0)) 442162922Sariff#define HDA_CMD_SET_EAPD_BTL_ENABLE(cad, nid, payload) \ 443162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 444162922Sariff HDA_CMD_VERB_SET_EAPD_BTL_ENABLE, (payload))) 445162922Sariff 446162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK 0x00000004 447162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT 2 448162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK 0x00000002 449162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT 1 450162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK 0x00000001 451162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT 0 452162922Sariff 453162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP(rsp) \ 454162922Sariff (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK) >> \ 455162922Sariff HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT) 456162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD(rsp) \ 457162922Sariff (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK) >> \ 458162922Sariff HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT) 459162922Sariff#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL(rsp) \ 460162922Sariff (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK) >> \ 461162922Sariff HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT) 462162922Sariff 463162922Sariff#define HDA_CMD_SET_EAPD_BTL_ENABLE_LR_SWAP 0x04 464162922Sariff#define HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD 0x02 465162922Sariff#define HDA_CMD_SET_EAPD_BTL_ENABLE_BTL 0x01 466162922Sariff 467162922Sariff/* GPI Data */ 468162922Sariff#define HDA_CMD_VERB_GET_GPI_DATA 0xf10 469162922Sariff#define HDA_CMD_VERB_SET_GPI_DATA 0x710 470162922Sariff 471162922Sariff#define HDA_CMD_GET_GPI_DATA(cad, nid) \ 472162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 473162922Sariff HDA_CMD_VERB_GET_GPI_DATA, 0x0)) 474162922Sariff#define HDA_CMD_SET_GPI_DATA(cad, nid) \ 475162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 476162922Sariff HDA_CMD_VERB_SET_GPI_DATA, (payload))) 477162922Sariff 478162922Sariff/* GPI Wake Enable Mask */ 479162922Sariff#define HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK 0xf11 480162922Sariff#define HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK 0x711 481162922Sariff 482162922Sariff#define HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, nid) \ 483162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 484162922Sariff HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK, 0x0)) 485162922Sariff#define HDA_CMD_SET_GPI_WAKE_ENABLE_MASK(cad, nid, payload) \ 486162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 487162922Sariff HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK, (payload))) 488162922Sariff 489162922Sariff/* GPI Unsolicited Enable Mask */ 490162922Sariff#define HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12 491162922Sariff#define HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712 492162922Sariff 493162922Sariff#define HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid) \ 494162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 495162922Sariff HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK, 0x0)) 496162922Sariff#define HDA_CMD_SET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \ 497162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 498162922Sariff HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK, (payload))) 499162922Sariff 500162922Sariff/* GPI Sticky Mask */ 501162922Sariff#define HDA_CMD_VERB_GET_GPI_STICKY_MASK 0xf13 502162922Sariff#define HDA_CMD_VERB_SET_GPI_STICKY_MASK 0x713 503162922Sariff 504162922Sariff#define HDA_CMD_GET_GPI_STICKY_MASK(cad, nid) \ 505162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 506162922Sariff HDA_CMD_VERB_GET_GPI_STICKY_MASK, 0x0)) 507162922Sariff#define HDA_CMD_SET_GPI_STICKY_MASK(cad, nid, payload) \ 508162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 509162922Sariff HDA_CMD_VERB_SET_GPI_STICKY_MASK, (payload))) 510162922Sariff 511162922Sariff/* GPO Data */ 512162922Sariff#define HDA_CMD_VERB_GET_GPO_DATA 0xf14 513162922Sariff#define HDA_CMD_VERB_SET_GPO_DATA 0x714 514162922Sariff 515162922Sariff#define HDA_CMD_GET_GPO_DATA(cad, nid) \ 516162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 517162922Sariff HDA_CMD_VERB_GET_GPO_DATA, 0x0)) 518162922Sariff#define HDA_CMD_SET_GPO_DATA(cad, nid, payload) \ 519162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 520162922Sariff HDA_CMD_VERB_SET_GPO_DATA, (payload))) 521162922Sariff 522162922Sariff/* GPIO Data */ 523162922Sariff#define HDA_CMD_VERB_GET_GPIO_DATA 0xf15 524162922Sariff#define HDA_CMD_VERB_SET_GPIO_DATA 0x715 525162922Sariff 526162922Sariff#define HDA_CMD_GET_GPIO_DATA(cad, nid) \ 527162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 528162922Sariff HDA_CMD_VERB_GET_GPIO_DATA, 0x0)) 529162922Sariff#define HDA_CMD_SET_GPIO_DATA(cad, nid, payload) \ 530162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 531162922Sariff HDA_CMD_VERB_SET_GPIO_DATA, (payload))) 532162922Sariff 533162922Sariff/* GPIO Enable Mask */ 534162922Sariff#define HDA_CMD_VERB_GET_GPIO_ENABLE_MASK 0xf16 535162922Sariff#define HDA_CMD_VERB_SET_GPIO_ENABLE_MASK 0x716 536162922Sariff 537162922Sariff#define HDA_CMD_GET_GPIO_ENABLE_MASK(cad, nid) \ 538162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 539162922Sariff HDA_CMD_VERB_GET_GPIO_ENABLE_MASK, 0x0)) 540162922Sariff#define HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, payload) \ 541162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 542162922Sariff HDA_CMD_VERB_SET_GPIO_ENABLE_MASK, (payload))) 543162922Sariff 544162922Sariff/* GPIO Direction */ 545162922Sariff#define HDA_CMD_VERB_GET_GPIO_DIRECTION 0xf17 546162922Sariff#define HDA_CMD_VERB_SET_GPIO_DIRECTION 0x717 547162922Sariff 548162922Sariff#define HDA_CMD_GET_GPIO_DIRECTION(cad, nid) \ 549162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 550162922Sariff HDA_CMD_VERB_GET_GPIO_DIRECTION, 0x0)) 551162922Sariff#define HDA_CMD_SET_GPIO_DIRECTION(cad, nid, payload) \ 552162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 553162922Sariff HDA_CMD_VERB_SET_GPIO_DIRECTION, (payload))) 554162922Sariff 555162922Sariff/* GPIO Wake Enable Mask */ 556162922Sariff#define HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK 0xf18 557162922Sariff#define HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK 0x718 558162922Sariff 559162922Sariff#define HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, nid) \ 560162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 561162922Sariff HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK, 0x0)) 562162922Sariff#define HDA_CMD_SET_GPIO_WAKE_ENABLE_MASK(cad, nid, payload) \ 563162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 564162922Sariff HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK, (payload))) 565162922Sariff 566162922Sariff/* GPIO Unsolicited Enable Mask */ 567162922Sariff#define HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19 568162922Sariff#define HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719 569162922Sariff 570162922Sariff#define HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid) \ 571162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 572162922Sariff HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK, 0x0)) 573162922Sariff#define HDA_CMD_SET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \ 574162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 575162922Sariff HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK, (payload))) 576162922Sariff 577162922Sariff/* GPIO_STICKY_MASK */ 578162922Sariff#define HDA_CMD_VERB_GET_GPIO_STICKY_MASK 0xf1a 579162922Sariff#define HDA_CMD_VERB_SET_GPIO_STICKY_MASK 0x71a 580162922Sariff 581162922Sariff#define HDA_CMD_GET_GPIO_STICKY_MASK(cad, nid) \ 582162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 583162922Sariff HDA_CMD_VERB_GET_GPIO_STICKY_MASK, 0x0)) 584162922Sariff#define HDA_CMD_SET_GPIO_STICKY_MASK(cad, nid, payload) \ 585162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 586162922Sariff HDA_CMD_VERB_SET_GPIO_STICKY_MASK, (payload))) 587162922Sariff 588162922Sariff/* Beep Generation */ 589162922Sariff#define HDA_CMD_VERB_GET_BEEP_GENERATION 0xf0a 590162922Sariff#define HDA_CMD_VERB_SET_BEEP_GENERATION 0x70a 591162922Sariff 592162922Sariff#define HDA_CMD_GET_BEEP_GENERATION(cad, nid) \ 593162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 594162922Sariff HDA_CMD_VERB_GET_BEEP_GENERATION, 0x0)) 595162922Sariff#define HDA_CMD_SET_BEEP_GENERATION(cad, nid, payload) \ 596162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 597162922Sariff HDA_CMD_VERB_SET_BEEP_GENERATION, (payload))) 598162922Sariff 599162922Sariff/* Volume Knob */ 600162922Sariff#define HDA_CMD_VERB_GET_VOLUME_KNOB 0xf0f 601162922Sariff#define HDA_CMD_VERB_SET_VOLUME_KNOB 0x70f 602162922Sariff 603162922Sariff#define HDA_CMD_GET_VOLUME_KNOB(cad, nid) \ 604162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 605162922Sariff HDA_CMD_VERB_GET_VOLUME_KNOB, 0x0)) 606162922Sariff#define HDA_CMD_SET_VOLUME_KNOB(cad, nid, payload) \ 607162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 608162922Sariff HDA_CMD_VERB_SET_VOLUME_KNOB, (payload))) 609162922Sariff 610162922Sariff/* Subsystem ID */ 611162922Sariff#define HDA_CMD_VERB_GET_SUBSYSTEM_ID 0xf20 612162922Sariff#define HDA_CMD_VERB_SET_SUSBYSTEM_ID1 0x720 613162922Sariff#define HDA_CMD_VERB_SET_SUBSYSTEM_ID2 0x721 614162922Sariff#define HDA_CMD_VERB_SET_SUBSYSTEM_ID3 0x722 615162922Sariff#define HDA_CMD_VERB_SET_SUBSYSTEM_ID4 0x723 616162922Sariff 617162922Sariff#define HDA_CMD_GET_SUBSYSTEM_ID(cad, nid) \ 618162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 619162922Sariff HDA_CMD_VERB_GET_SUBSYSTEM_ID, 0x0)) 620162922Sariff#define HDA_CMD_SET_SUBSYSTEM_ID1(cad, nid, payload) \ 621162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 622162922Sariff HDA_CMD_VERB_SET_SUSBYSTEM_ID1, (payload))) 623162922Sariff#define HDA_CMD_SET_SUBSYSTEM_ID2(cad, nid, payload) \ 624162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 625162922Sariff HDA_CMD_VERB_SET_SUSBYSTEM_ID2, (payload))) 626162922Sariff#define HDA_CMD_SET_SUBSYSTEM_ID3(cad, nid, payload) \ 627162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 628162922Sariff HDA_CMD_VERB_SET_SUSBYSTEM_ID3, (payload))) 629162922Sariff#define HDA_CMD_SET_SUBSYSTEM_ID4(cad, nid, payload) \ 630162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 631162922Sariff HDA_CMD_VERB_SET_SUSBYSTEM_ID4, (payload))) 632162922Sariff 633162922Sariff/* Configuration Default */ 634162922Sariff#define HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT 0xf1c 635162922Sariff#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1 0x71c 636162922Sariff#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2 0x71d 637162922Sariff#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3 0x71e 638162922Sariff#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4 0x71f 639162922Sariff 640162922Sariff#define HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid) \ 641162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 642162922Sariff HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT, 0x0)) 643162922Sariff#define HDA_CMD_SET_CONFIGURATION_DEFAULT1(cad, nid, payload) \ 644162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 645162922Sariff HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1, (payload))) 646162922Sariff#define HDA_CMD_SET_CONFIGURATION_DEFAULT2(cad, nid, payload) \ 647162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 648162922Sariff HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2, (payload))) 649162922Sariff#define HDA_CMD_SET_CONFIGURATION_DEFAULT3(cad, nid, payload) \ 650162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 651162922Sariff HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3, (payload))) 652162922Sariff#define HDA_CMD_SET_CONFIGURATION_DEFAULT4(cad, nid, payload) \ 653162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 654162922Sariff HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4, (payload))) 655162922Sariff 656162922Sariff/* Stripe Control */ 657162922Sariff#define HDA_CMD_VERB_GET_STRIPE_CONTROL 0xf24 658162922Sariff#define HDA_CMD_VERB_SET_STRIPE_CONTROL 0x724 659162922Sariff 660197611Smav#define HDA_CMD_GET_STRIPE_CONTROL(cad, nid) \ 661162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 662162922Sariff HDA_CMD_VERB_GET_STRIPE_CONTROL, 0x0)) 663197611Smav#define HDA_CMD_SET_STRIPE_CONTROL(cad, nid, payload) \ 664162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 665162922Sariff HDA_CMD_VERB_SET_STRIPE_CONTROL, (payload))) 666162922Sariff 667197611Smav/* Channel Count Control */ 668197611Smav#define HDA_CMD_VERB_GET_CONV_CHAN_COUNT 0xf2d 669197611Smav#define HDA_CMD_VERB_SET_CONV_CHAN_COUNT 0x72d 670197611Smav 671197611Smav#define HDA_CMD_GET_CONV_CHAN_COUNT(cad, nid) \ 672197611Smav (HDA_CMD_12BIT((cad), (nid), \ 673197611Smav HDA_CMD_VERB_GET_CONV_CHAN_COUNT, 0x0)) 674197611Smav#define HDA_CMD_SET_CONV_CHAN_COUNT(cad, nid, payload) \ 675197611Smav (HDA_CMD_12BIT((cad), (nid), \ 676197611Smav HDA_CMD_VERB_SET_CONV_CHAN_COUNT, (payload))) 677197611Smav 678197611Smav#define HDA_CMD_VERB_GET_HDMI_DIP_SIZE 0xf2e 679230312Smav 680230312Smav#define HDA_CMD_GET_HDMI_DIP_SIZE(cad, nid, arg) \ 681230312Smav (HDA_CMD_12BIT((cad), (nid), \ 682230312Smav HDA_CMD_VERB_GET_HDMI_DIP_SIZE, (arg))) 683230312Smav 684197611Smav#define HDA_CMD_VERB_GET_HDMI_ELDD 0xf2f 685197611Smav 686230312Smav#define HDA_CMD_GET_HDMI_ELDD(cad, nid, off) \ 687230312Smav (HDA_CMD_12BIT((cad), (nid), \ 688230312Smav HDA_CMD_VERB_GET_HDMI_ELDD, (off))) 689230312Smav 690197611Smav#define HDA_CMD_VERB_GET_HDMI_DIP_INDEX 0xf30 691197611Smav#define HDA_CMD_VERB_SET_HDMI_DIP_INDEX 0x730 692197611Smav 693230312Smav#define HDA_CMD_GET_HDMI_DIP_INDEX(cad, nid) \ 694230312Smav (HDA_CMD_12BIT((cad), (nid), \ 695230312Smav HDA_CMD_VERB_GET_HDMI_DIP_INDEX, 0x0)) 696230312Smav#define HDA_CMD_SET_HDMI_DIP_INDEX(cad, nid, payload) \ 697230312Smav (HDA_CMD_12BIT((cad), (nid), \ 698230312Smav HDA_CMD_VERB_SET_HDMI_DIP_INDEX, (payload))) 699230312Smav 700197611Smav#define HDA_CMD_VERB_GET_HDMI_DIP_DATA 0xf31 701197611Smav#define HDA_CMD_VERB_SET_HDMI_DIP_DATA 0x731 702197611Smav 703230312Smav#define HDA_CMD_GET_HDMI_DIP_DATA(cad, nid) \ 704230312Smav (HDA_CMD_12BIT((cad), (nid), \ 705230312Smav HDA_CMD_VERB_GET_HDMI_DIP_DATA, 0x0)) 706230312Smav#define HDA_CMD_SET_HDMI_DIP_DATA(cad, nid, payload) \ 707230312Smav (HDA_CMD_12BIT((cad), (nid), \ 708230312Smav HDA_CMD_VERB_SET_HDMI_DIP_DATA, (payload))) 709230312Smav 710197611Smav#define HDA_CMD_VERB_GET_HDMI_DIP_XMIT 0xf32 711197611Smav#define HDA_CMD_VERB_SET_HDMI_DIP_XMIT 0x732 712197611Smav 713230312Smav#define HDA_CMD_GET_HDMI_DIP_XMIT(cad, nid) \ 714230312Smav (HDA_CMD_12BIT((cad), (nid), \ 715230312Smav HDA_CMD_VERB_GET_HDMI_DIP_XMIT, 0x0)) 716230312Smav#define HDA_CMD_SET_HDMI_DIP_XMIT(cad, nid, payload) \ 717230312Smav (HDA_CMD_12BIT((cad), (nid), \ 718230312Smav HDA_CMD_VERB_SET_HDMI_DIP_XMIT, (payload))) 719230312Smav 720197611Smav#define HDA_CMD_VERB_GET_HDMI_CP_CTRL 0xf33 721197611Smav#define HDA_CMD_VERB_SET_HDMI_CP_CTRL 0x733 722197611Smav 723197611Smav#define HDA_CMD_VERB_GET_HDMI_CHAN_SLOT 0xf34 724197611Smav#define HDA_CMD_VERB_SET_HDMI_CHAN_SLOT 0x734 725197611Smav 726197611Smav#define HDA_CMD_GET_HDMI_CHAN_SLOT(cad, nid) \ 727197611Smav (HDA_CMD_12BIT((cad), (nid), \ 728197611Smav HDA_CMD_VERB_GET_HDMI_CHAN_SLOT, 0x0)) 729197611Smav#define HDA_CMD_SET_HDMI_CHAN_SLOT(cad, nid, payload) \ 730197611Smav (HDA_CMD_12BIT((cad), (nid), \ 731197611Smav HDA_CMD_VERB_SET_HDMI_CHAN_SLOT, (payload))) 732197611Smav 733230312Smav#define HDA_HDMI_CODING_TYPE_REF_STREAM_HEADER 0 734230312Smav#define HDA_HDMI_CODING_TYPE_LPCM 1 735230312Smav#define HDA_HDMI_CODING_TYPE_AC3 2 736230312Smav#define HDA_HDMI_CODING_TYPE_MPEG1 3 737230312Smav#define HDA_HDMI_CODING_TYPE_MP3 4 738230312Smav#define HDA_HDMI_CODING_TYPE_MPEG2 5 739230312Smav#define HDA_HDMI_CODING_TYPE_AACLC 6 740230312Smav#define HDA_HDMI_CODING_TYPE_DTS 7 741230312Smav#define HDA_HDMI_CODING_TYPE_ATRAC 8 742230312Smav#define HDA_HDMI_CODING_TYPE_SACD 9 743230312Smav#define HDA_HDMI_CODING_TYPE_EAC3 10 744230312Smav#define HDA_HDMI_CODING_TYPE_DTS_HD 11 745230312Smav#define HDA_HDMI_CODING_TYPE_MLP 12 746230312Smav#define HDA_HDMI_CODING_TYPE_DST 13 747230312Smav#define HDA_HDMI_CODING_TYPE_WMAPRO 14 748230312Smav#define HDA_HDMI_CODING_TYPE_REF_CTX 15 749230312Smav 750162922Sariff/* Function Reset */ 751162922Sariff#define HDA_CMD_VERB_FUNCTION_RESET 0x7ff 752162922Sariff 753162922Sariff#define HDA_CMD_FUNCTION_RESET(cad, nid) \ 754162922Sariff (HDA_CMD_12BIT((cad), (nid), \ 755162922Sariff HDA_CMD_VERB_FUNCTION_RESET, 0x0)) 756162922Sariff 757162922Sariff 758162922Sariff/**************************************************************************** 759162922Sariff * HDA Device Parameters 760162922Sariff ****************************************************************************/ 761162922Sariff 762162922Sariff/* Vendor ID */ 763162922Sariff#define HDA_PARAM_VENDOR_ID 0x00 764162922Sariff 765162922Sariff#define HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK 0xffff0000 766162922Sariff#define HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT 16 767162922Sariff#define HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK 0x0000ffff 768162922Sariff#define HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT 0 769162922Sariff 770162922Sariff#define HDA_PARAM_VENDOR_ID_VENDOR_ID(param) \ 771162922Sariff (((param) & HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK) >> \ 772162922Sariff HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT) 773162922Sariff#define HDA_PARAM_VENDOR_ID_DEVICE_ID(param) \ 774162922Sariff (((param) & HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK) >> \ 775162922Sariff HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT) 776162922Sariff 777162922Sariff/* Revision ID */ 778162922Sariff#define HDA_PARAM_REVISION_ID 0x02 779162922Sariff 780162922Sariff#define HDA_PARAM_REVISION_ID_MAJREV_MASK 0x00f00000 781162922Sariff#define HDA_PARAM_REVISION_ID_MAJREV_SHIFT 20 782162922Sariff#define HDA_PARAM_REVISION_ID_MINREV_MASK 0x000f0000 783162922Sariff#define HDA_PARAM_REVISION_ID_MINREV_SHIFT 16 784162922Sariff#define HDA_PARAM_REVISION_ID_REVISION_ID_MASK 0x0000ff00 785162922Sariff#define HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT 8 786162922Sariff#define HDA_PARAM_REVISION_ID_STEPPING_ID_MASK 0x000000ff 787162922Sariff#define HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT 0 788162922Sariff 789162922Sariff#define HDA_PARAM_REVISION_ID_MAJREV(param) \ 790162922Sariff (((param) & HDA_PARAM_REVISION_ID_MAJREV_MASK) >> \ 791162922Sariff HDA_PARAM_REVISION_ID_MAJREV_SHIFT) 792162922Sariff#define HDA_PARAM_REVISION_ID_MINREV(param) \ 793162922Sariff (((param) & HDA_PARAM_REVISION_ID_MINREV_MASK) >> \ 794162922Sariff HDA_PARAM_REVISION_ID_MINREV_SHIFT) 795162922Sariff#define HDA_PARAM_REVISION_ID_REVISION_ID(param) \ 796162922Sariff (((param) & HDA_PARAM_REVISION_ID_REVISION_ID_MASK) >> \ 797162922Sariff HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT) 798162922Sariff#define HDA_PARAM_REVISION_ID_STEPPING_ID(param) \ 799162922Sariff (((param) & HDA_PARAM_REVISION_ID_STEPPING_ID_MASK) >> \ 800162922Sariff HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT) 801162922Sariff 802162922Sariff/* Subordinate Node Cound */ 803162922Sariff#define HDA_PARAM_SUB_NODE_COUNT 0x04 804162922Sariff 805162922Sariff#define HDA_PARAM_SUB_NODE_COUNT_START_MASK 0x00ff0000 806162922Sariff#define HDA_PARAM_SUB_NODE_COUNT_START_SHIFT 16 807162922Sariff#define HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK 0x000000ff 808162922Sariff#define HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT 0 809162922Sariff 810162922Sariff#define HDA_PARAM_SUB_NODE_COUNT_START(param) \ 811162922Sariff (((param) & HDA_PARAM_SUB_NODE_COUNT_START_MASK) >> \ 812162922Sariff HDA_PARAM_SUB_NODE_COUNT_START_SHIFT) 813162922Sariff#define HDA_PARAM_SUB_NODE_COUNT_TOTAL(param) \ 814162922Sariff (((param) & HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK) >> \ 815162922Sariff HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT) 816162922Sariff 817162922Sariff/* Function Group Type */ 818162922Sariff#define HDA_PARAM_FCT_GRP_TYPE 0x05 819162922Sariff 820162922Sariff#define HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK 0x00000100 821162922Sariff#define HDA_PARAM_FCT_GRP_TYPE_UNSOL_SHIFT 8 822162922Sariff#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK 0x000000ff 823162922Sariff#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT 0 824162922Sariff 825162922Sariff#define HDA_PARAM_FCT_GRP_TYPE_UNSOL(param) \ 826162922Sariff (((param) & HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK) >> \ 827162922Sariff HDA_PARAM_FCT_GROUP_TYPE_UNSOL_SHIFT) 828162922Sariff#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(param) \ 829162922Sariff (((param) & HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK) >> \ 830162922Sariff HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT) 831162922Sariff 832162922Sariff#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO 0x01 833162922Sariff#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM 0x02 834162922Sariff 835162922Sariff/* Audio Function Group Capabilities */ 836162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP 0x08 837162922Sariff 838162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK 0x00010000 839162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT 16 840162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK 0x00000f00 841162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT 8 842162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK 0x0000000f 843162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT 0 844162922Sariff 845162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN(param) \ 846162922Sariff (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK) >> \ 847162922Sariff HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT) 848162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY(param) \ 849162922Sariff (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK) >> \ 850162922Sariff HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT) 851162922Sariff#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY(param) \ 852162922Sariff (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK) >> \ 853162922Sariff HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT) 854162922Sariff 855162922Sariff/* Audio Widget Capabilities */ 856162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP 0x09 857162922Sariff 858162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK 0x00f00000 859162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT 20 860162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK 0x000f0000 861162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT 16 862197611Smav#define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK 0x0000e000 863197611Smav#define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT 13 864197611Smav#define HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK 0x00001000 865197611Smav#define HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT 12 866162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK 0x00000800 867162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT 11 868162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK 0x00000400 869162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT 10 870162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK 0x00000200 871162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT 9 872162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK 0x00000100 873162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT 8 874162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK 0x00000080 875162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT 7 876162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK 0x00000040 877162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT 6 878162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK 0x00000020 879162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT 5 880162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK 0x00000010 881162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT 4 882162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK 0x00000008 883162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT 3 884162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK 0x00000004 885162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT 2 886162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK 0x00000002 887162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT 1 888162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK 0x00000001 889162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT 0 890162922Sariff 891162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(param) \ 892162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK) >> \ 893162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT) 894162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY(param) \ 895162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK) >> \ 896162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT) 897197611Smav#define HDA_PARAM_AUDIO_WIDGET_CAP_CC(param) \ 898197611Smav ((((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK) >> \ 899197611Smav (HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT - 1)) | \ 900197611Smav (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \ 901197611Smav HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT)) 902197611Smav#define HDA_PARAM_AUDIO_WIDGET_CAP_CP(param) \ 903197611Smav (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK) >> \ 904197611Smav HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT) 905162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(param) \ 906162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK) >> \ 907162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT) 908162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(param) \ 909162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK) >> \ 910162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT) 911162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(param) \ 912162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK) >> \ 913162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT) 914162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST(param) \ 915162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK) >> \ 916162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT) 917162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(param) \ 918162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK) >> \ 919162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT) 920162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(param) \ 921162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK) >> \ 922162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT) 923162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(param) \ 924162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK) >> \ 925162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT) 926162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(param) \ 927162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK) >> \ 928162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT) 929162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(param) \ 930162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK) >> \ 931162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT) 932162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(param) \ 933162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK) >> \ 934162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT) 935162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(param) \ 936162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK) >> \ 937162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT) 938162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(param) \ 939162922Sariff (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \ 940162922Sariff HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT) 941162922Sariff 942162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT 0x0 943162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT 0x1 944162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 0x2 945162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR 0x3 946162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 0x4 947162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET 0x5 948162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET 0x6 949162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET 0x7 950162922Sariff#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET 0xf 951162922Sariff 952162922Sariff/* Supported PCM Size, Rates */ 953162922Sariff 954162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE 0x0a 955162922Sariff 956162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK 0x00100000 957162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT 20 958162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK 0x00080000 959162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT 19 960162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK 0x00040000 961162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT 18 962162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK 0x00020000 963162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT 17 964162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK 0x00010000 965162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT 16 966164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK 0x00000001 967164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT 0 968164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK 0x00000002 969164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT 1 970164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK 0x00000004 971164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT 2 972164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK 0x00000008 973164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT 3 974164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK 0x00000010 975164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT 4 976164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK 0x00000020 977164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT 5 978164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK 0x00000040 979164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT 6 980164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK 0x00000080 981164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT 7 982164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK 0x00000100 983164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT 8 984164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK 0x00000200 985164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT 9 986164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK 0x00000400 987164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT 10 988164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK 0x00000800 989164614Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT 11 990162922Sariff 991162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(param) \ 992162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK) >> \ 993162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT) 994162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(param) \ 995162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK) >> \ 996162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT) 997162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(param) \ 998162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK) >> \ 999162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT) 1000162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(param) \ 1001162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK) >> \ 1002162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT) 1003162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(param) \ 1004162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK) >> \ 1005162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT) 1006162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(param) \ 1007162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK) >> \ 1008162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT) 1009162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(param) \ 1010162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK) >> \ 1011162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT) 1012162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(param) \ 1013162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK) >> \ 1014162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT) 1015162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(param) \ 1016162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK) >> \ 1017162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT) 1018162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(param) \ 1019162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK) >> \ 1020162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT) 1021162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(param) \ 1022162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK) >> \ 1023162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT) 1024162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(param) \ 1025162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK) >> \ 1026162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT) 1027162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(param) \ 1028162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK) >> \ 1029162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT) 1030162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(param) \ 1031162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK) >> \ 1032162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT) 1033162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(param) \ 1034162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK) >> \ 1035162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT) 1036162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(param) \ 1037162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK) >> \ 1038162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT) 1039162922Sariff#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(param) \ 1040162922Sariff (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK) >> \ 1041162922Sariff HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT) 1042162922Sariff 1043162922Sariff/* Supported Stream Formats */ 1044162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS 0x0b 1045162922Sariff 1046162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK 0x00000004 1047162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT 2 1048162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK 0x00000002 1049162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT 1 1050162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK 0x00000001 1051162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT 0 1052162922Sariff 1053162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3(param) \ 1054162922Sariff (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK) >> \ 1055162922Sariff HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT) 1056162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(param) \ 1057162922Sariff (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK) >> \ 1058162922Sariff HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT) 1059162922Sariff#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM(param) \ 1060162922Sariff (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK) >> \ 1061162922Sariff HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT) 1062162922Sariff 1063162922Sariff/* Pin Capabilities */ 1064162922Sariff#define HDA_PARAM_PIN_CAP 0x0c 1065162922Sariff 1066197611Smav#define HDA_PARAM_PIN_CAP_HBR_MASK 0x08000000 1067197611Smav#define HDA_PARAM_PIN_CAP_HBR_SHIFT 27 1068197611Smav#define HDA_PARAM_PIN_CAP_DP_MASK 0x01000000 1069197611Smav#define HDA_PARAM_PIN_CAP_DP_SHIFT 24 1070162922Sariff#define HDA_PARAM_PIN_CAP_EAPD_CAP_MASK 0x00010000 1071162922Sariff#define HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT 16 1072162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_MASK 0x0000ff00 1073162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT 8 1074162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK 0x00002000 1075162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT 13 1076162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK 0x00001000 1077162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT 12 1078162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK 0x00000400 1079162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT 10 1080162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK 0x00000200 1081162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT 9 1082162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK 0x00000100 1083162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT 8 1084197611Smav#define HDA_PARAM_PIN_CAP_HDMI_MASK 0x00000080 1085197611Smav#define HDA_PARAM_PIN_CAP_HDMI_SHIFT 7 1086162922Sariff#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK 0x00000040 1087162922Sariff#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT 6 1088162922Sariff#define HDA_PARAM_PIN_CAP_INPUT_CAP_MASK 0x00000020 1089162922Sariff#define HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT 5 1090162922Sariff#define HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK 0x00000010 1091162922Sariff#define HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT 4 1092162922Sariff#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK 0x00000008 1093162922Sariff#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT 3 1094162922Sariff#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK 0x00000004 1095162922Sariff#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT 2 1096162922Sariff#define HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK 0x00000002 1097162922Sariff#define HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT 1 1098162922Sariff#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK 0x00000001 1099162922Sariff#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT 0 1100162922Sariff 1101197611Smav#define HDA_PARAM_PIN_CAP_HBR(param) \ 1102197611Smav (((param) & HDA_PARAM_PIN_CAP_HBR_MASK) >> \ 1103197611Smav HDA_PARAM_PIN_CAP_HBR_SHIFT) 1104197611Smav#define HDA_PARAM_PIN_CAP_DP(param) \ 1105197611Smav (((param) & HDA_PARAM_PIN_CAP_DP_MASK) >> \ 1106197611Smav HDA_PARAM_PIN_CAP_DP_SHIFT) 1107162922Sariff#define HDA_PARAM_PIN_CAP_EAPD_CAP(param) \ 1108162922Sariff (((param) & HDA_PARAM_PIN_CAP_EAPD_CAP_MASK) >> \ 1109162922Sariff HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT) 1110162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL(param) \ 1111162922Sariff (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_MASK) >> \ 1112162922Sariff HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT) 1113162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_100(param) \ 1114162922Sariff (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK) >> \ 1115162922Sariff HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT) 1116162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_80(param) \ 1117162922Sariff (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK) >> \ 1118162922Sariff HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT) 1119162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(param) \ 1120162922Sariff (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK) >> \ 1121162922Sariff HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT) 1122162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_50(param) \ 1123162922Sariff (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK) >> \ 1124162922Sariff HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT) 1125162922Sariff#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(param) \ 1126162922Sariff (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK) >> \ 1127162922Sariff HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT) 1128197611Smav#define HDA_PARAM_PIN_CAP_HDMI(param) \ 1129197611Smav (((param) & HDA_PARAM_PIN_CAP_HDMI_MASK) >> \ 1130197611Smav HDA_PARAM_PIN_CAP_HDMI_SHIFT) 1131162922Sariff#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(param) \ 1132162922Sariff (((param) & HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK) >> \ 1133162922Sariff HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT) 1134162922Sariff#define HDA_PARAM_PIN_CAP_INPUT_CAP(param) \ 1135162922Sariff (((param) & HDA_PARAM_PIN_CAP_INPUT_CAP_MASK) >> \ 1136162922Sariff HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT) 1137162922Sariff#define HDA_PARAM_PIN_CAP_OUTPUT_CAP(param) \ 1138162922Sariff (((param) & HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK) >> \ 1139162922Sariff HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT) 1140162922Sariff#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP(param) \ 1141162922Sariff (((param) & HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK) >> \ 1142162922Sariff HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT) 1143162922Sariff#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(param) \ 1144162922Sariff (((param) & HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK) >> \ 1145182999Smav HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT) 1146162922Sariff#define HDA_PARAM_PIN_CAP_TRIGGER_REQD(param) \ 1147162922Sariff (((param) & HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK) >> \ 1148162922Sariff HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT) 1149162922Sariff#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(param) \ 1150162922Sariff (((param) & HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK) >> \ 1151162922Sariff HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT) 1152162922Sariff 1153162922Sariff/* Input Amplifier Capabilities */ 1154162922Sariff#define HDA_PARAM_INPUT_AMP_CAP 0x0d 1155162922Sariff 1156162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000 1157162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT 31 1158162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000 1159162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT 16 1160162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00 1161162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT 8 1162162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK 0x0000007f 1163162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT 0 1164162922Sariff 1165162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(param) \ 1166162922Sariff (((param) & HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK) >> \ 1167162922Sariff HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT) 1168162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(param) \ 1169162922Sariff (((param) & HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK) >> \ 1170162922Sariff HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT) 1171162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(param) \ 1172162922Sariff (((param) & HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK) >> \ 1173162922Sariff HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT) 1174162922Sariff#define HDA_PARAM_INPUT_AMP_CAP_OFFSET(param) \ 1175162922Sariff (((param) & HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK) >> \ 1176162922Sariff HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT) 1177162922Sariff 1178162922Sariff/* Output Amplifier Capabilities */ 1179162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP 0x12 1180162922Sariff 1181162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000 1182162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT 31 1183162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000 1184162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT 16 1185162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00 1186162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT 8 1187162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK 0x0000007f 1188162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT 0 1189162922Sariff 1190162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(param) \ 1191162922Sariff (((param) & HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK) >> \ 1192162922Sariff HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT) 1193162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(param) \ 1194162922Sariff (((param) & HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK) >> \ 1195162922Sariff HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT) 1196162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(param) \ 1197162922Sariff (((param) & HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK) >> \ 1198162922Sariff HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT) 1199162922Sariff#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(param) \ 1200162922Sariff (((param) & HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK) >> \ 1201162922Sariff HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT) 1202162922Sariff 1203162922Sariff/* Connection List Length */ 1204162922Sariff#define HDA_PARAM_CONN_LIST_LENGTH 0x0e 1205162922Sariff 1206162922Sariff#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK 0x00000080 1207162922Sariff#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT 7 1208162922Sariff#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK 0x0000007f 1209162922Sariff#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT 0 1210162922Sariff 1211162922Sariff#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(param) \ 1212162922Sariff (((param) & HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK) >> \ 1213162922Sariff HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT) 1214162922Sariff#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(param) \ 1215162922Sariff (((param) & HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK) >> \ 1216162922Sariff HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT) 1217162922Sariff 1218162922Sariff/* Supported Power States */ 1219162922Sariff#define HDA_PARAM_SUPP_POWER_STATES 0x0f 1220162922Sariff 1221162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D3_MASK 0x00000008 1222162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT 3 1223162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D2_MASK 0x00000004 1224162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT 2 1225162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D1_MASK 0x00000002 1226162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT 1 1227162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D0_MASK 0x00000001 1228162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT 0 1229162922Sariff 1230162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D3(param) \ 1231162922Sariff (((param) & HDA_PARAM_SUPP_POWER_STATES_D3_MASK) >> \ 1232162922Sariff HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT) 1233162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D2(param) \ 1234162922Sariff (((param) & HDA_PARAM_SUPP_POWER_STATES_D2_MASK) >> \ 1235162922Sariff HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT) 1236162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D1(param) \ 1237162922Sariff (((param) & HDA_PARAM_SUPP_POWER_STATES_D1_MASK) >> \ 1238162922Sariff HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT) 1239162922Sariff#define HDA_PARAM_SUPP_POWER_STATES_D0(param) \ 1240162922Sariff (((param) & HDA_PARAM_SUPP_POWER_STATES_D0_MASK) >> \ 1241162922Sariff HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT) 1242162922Sariff 1243162922Sariff/* Processing Capabilities */ 1244162922Sariff#define HDA_PARAM_PROCESSING_CAP 0x10 1245162922Sariff 1246162922Sariff#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK 0x0000ff00 1247162922Sariff#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT 8 1248162922Sariff#define HDA_PARAM_PROCESSING_CAP_BENIGN_MASK 0x00000001 1249162922Sariff#define HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT 0 1250162922Sariff 1251162922Sariff#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF(param) \ 1252162922Sariff (((param) & HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK) >> \ 1253162922Sariff HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT) 1254162922Sariff#define HDA_PARAM_PROCESSING_CAP_BENIGN(param) \ 1255162922Sariff (((param) & HDA_PARAM_PROCESSING_CAP_BENIGN_MASK) >> \ 1256162922Sariff HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT) 1257162922Sariff 1258162922Sariff/* GPIO Count */ 1259162922Sariff#define HDA_PARAM_GPIO_COUNT 0x11 1260162922Sariff 1261162922Sariff#define HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK 0x80000000 1262162922Sariff#define HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT 31 1263162922Sariff#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK 0x40000000 1264162922Sariff#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT 30 1265162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK 0x00ff0000 1266162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT 16 1267162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK 0x0000ff00 1268162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT 8 1269162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK 0x000000ff 1270162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT 0 1271162922Sariff 1272162922Sariff#define HDA_PARAM_GPIO_COUNT_GPI_WAKE(param) \ 1273162922Sariff (((param) & HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK) >> \ 1274162922Sariff HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT) 1275162922Sariff#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL(param) \ 1276162922Sariff (((param) & HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK) >> \ 1277162922Sariff HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT) 1278162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPI(param) \ 1279162922Sariff (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK) >> \ 1280162922Sariff HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT) 1281162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPO(param) \ 1282162922Sariff (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK) >> \ 1283162922Sariff HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT) 1284162922Sariff#define HDA_PARAM_GPIO_COUNT_NUM_GPIO(param) \ 1285162922Sariff (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK) >> \ 1286162922Sariff HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT) 1287162922Sariff 1288162922Sariff/* Volume Knob Capabilities */ 1289162922Sariff#define HDA_PARAM_VOLUME_KNOB_CAP 0x13 1290162922Sariff 1291162922Sariff#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK 0x00000080 1292162922Sariff#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT 7 1293162922Sariff#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK 0x0000007f 1294162922Sariff#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT 0 1295162922Sariff 1296162922Sariff#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA(param) \ 1297162922Sariff (((param) & HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK) >> \ 1298162922Sariff HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT) 1299162922Sariff#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS(param) \ 1300162922Sariff (((param) & HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK) >> \ 1301162922Sariff HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT) 1302162922Sariff 1303162922Sariff 1304182999Smav#define HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK 0x0000000f 1305182999Smav#define HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT 0 1306182999Smav#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK 0x000000f0 1307182999Smav#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT 4 1308182999Smav#define HDA_CONFIG_DEFAULTCONF_MISC_MASK 0x00000f00 1309182999Smav#define HDA_CONFIG_DEFAULTCONF_MISC_SHIFT 8 1310182999Smav#define HDA_CONFIG_DEFAULTCONF_COLOR_MASK 0x0000f000 1311182999Smav#define HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT 12 1312182999Smav#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK 0x000f0000 1313182999Smav#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT 16 1314182999Smav#define HDA_CONFIG_DEFAULTCONF_DEVICE_MASK 0x00f00000 1315182999Smav#define HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT 20 1316182999Smav#define HDA_CONFIG_DEFAULTCONF_LOCATION_MASK 0x3f000000 1317182999Smav#define HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT 24 1318182999Smav#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK 0xc0000000 1319182999Smav#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT 30 1320162922Sariff 1321182999Smav#define HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf) \ 1322182999Smav (((conf) & HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK) >> \ 1323182999Smav HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) 1324182999Smav#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf) \ 1325182999Smav (((conf) & HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) >> \ 1326182999Smav HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) 1327182999Smav#define HDA_CONFIG_DEFAULTCONF_MISC(conf) \ 1328182999Smav (((conf) & HDA_CONFIG_DEFAULTCONF_MISC_MASK) >> \ 1329182999Smav HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) 1330182999Smav#define HDA_CONFIG_DEFAULTCONF_COLOR(conf) \ 1331182999Smav (((conf) & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> \ 1332182999Smav HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) 1333182999Smav#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf) \ 1334182999Smav (((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK) >> \ 1335182999Smav HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) 1336182999Smav#define HDA_CONFIG_DEFAULTCONF_DEVICE(conf) \ 1337182999Smav (((conf) & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> \ 1338182999Smav HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) 1339182999Smav#define HDA_CONFIG_DEFAULTCONF_LOCATION(conf) \ 1340182999Smav (((conf) & HDA_CONFIG_DEFAULTCONF_LOCATION_MASK) >> \ 1341182999Smav HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) 1342182999Smav#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf) \ 1343182999Smav (((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> \ 1344182999Smav HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) 1345182999Smav 1346162922Sariff#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK (0<<30) 1347162922Sariff#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE (1<<30) 1348162922Sariff#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED (2<<30) 1349162922Sariff#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH (3<<30) 1350162922Sariff 1351162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT (0<<20) 1352162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER (1<<20) 1353162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT (2<<20) 1354162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_CD (3<<20) 1355162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT (4<<20) 1356162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT (5<<20) 1357162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE (6<<20) 1358162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET (7<<20) 1359162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN (8<<20) 1360162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_AUX (9<<20) 1361162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN (10<<20) 1362162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY (11<<20) 1363162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN (12<<20) 1364162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN (13<<20) 1365162922Sariff#define HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER (15<<20) 1366162922Sariff 1367162922Sariff#endif 1368