emuxkireg.h revision 229430
1275970Scy/* $FreeBSD: head/sys/dev/sound/pci/emuxkireg.h 229430 2012-01-03 21:04:54Z pfg $ */ 2275970Scy/* $NetBSD: emuxkireg.h,v 1.8 2008/04/28 20:23:54 martin Exp $ */ 3275970Scy 4275970Scy/*- 5275970Scy * Copyright (c) 2001 The NetBSD Foundation, Inc. 6275970Scy * All rights reserved. 7275970Scy * 8275970Scy * This code is derived from software contributed to The NetBSD Foundation 9275970Scy * by Yannick Montulet. 10275970Scy * 11275970Scy * Redistribution and use in source and binary forms, with or without 12275970Scy * modification, are permitted provided that the following conditions 13275970Scy * are met: 14275970Scy * 1. Redistributions of source code must retain the above copyright 15275970Scy * notice, this list of conditions and the following disclaimer. 16275970Scy * 2. Redistributions in binary form must reproduce the above copyright 17275970Scy * notice, this list of conditions and the following disclaimer in the 18275970Scy * documentation and/or other materials provided with the distribution. 19275970Scy * 20275970Scy * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21275970Scy * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22275970Scy * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23275970Scy * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24275970Scy * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25275970Scy * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26275970Scy * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27275970Scy * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28275970Scy * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29275970Scy * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30275970Scy * POSSIBILITY OF SUCH DAMAGE. 31275970Scy */ 32275970Scy 33275970Scy#ifndef _DEV_PCI_EMUXKIREG_H_ 34275970Scy#define _DEV_PCI_EMUXKIREG_H_ 35275970Scy 36275970Scy/* 37275970Scy * Register values for Creative EMU10000. The register values have been 38275970Scy * taken from GPLed SBLive! header file published by Creative. The comments 39275970Scy * have been stripped to avoid GPL pollution in kernel. The Creative version 40275970Scy * including comments is available in Linux 2.4.* kernel as file 41275970Scy * drivers/sound/emu10k1/8010.h 42275970Scy */ 43275970Scy 44275970Scy/* 45275970Scy * Audigy specific registers contain an '_A_' 46275970Scy * Audigy2 specific registers contain an '_A2_' 47275970Scy */ 48275970Scy 49275970Scy#define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg)) 50275970Scy 51275970Scy#define EMU_PTR 0x00 52275970Scy#define EMU_PTR_CHNO_MASK 0x0000003f 53275970Scy#define EMU_PTR_ADDR_MASK 0x07ff0000 54275970Scy#define EMU_A_PTR_ADDR_MASK 0x0fff0000 55275970Scy 56275970Scy#define EMU_DATA 0x04 57275970Scy 58275970Scy#define EMU_IPR 0x08 59275970Scy#define EMU_IPR_RATETRCHANGE 0x01000000 60275970Scy#define EMU_IPR_FXDSP 0x00800000 61275970Scy#define EMU_IPR_FORCEINT 0x00400000 62275970Scy#define EMU_PCIERROR 0x00200000 63275970Scy#define EMU_IPR_VOLINCR 0x00100000 64275970Scy#define EMU_IPR_VOLDECR 0x00080000 65275970Scy#define EMU_IPR_MUTE 0x00040000 66275970Scy#define EMU_IPR_MICBUFFULL 0x00020000 67275970Scy#define EMU_IPR_MICBUFHALFFULL 0x00010000 68275970Scy#define EMU_IPR_ADCBUFFULL 0x00008000 69275970Scy#define EMU_IPR_ADCBUFHALFFULL 0x00004000 70275970Scy#define EMU_IPR_EFXBUFFULL 0x00002000 71275970Scy#define EMU_IPR_EFXBUFHALFFULL 0x00001000 72275970Scy#define EMU_IPR_GPSPDIFSTCHANGE 0x00000800 73275970Scy#define EMU_IPR_CDROMSTCHANGE 0x00000400 74275970Scy#define EMU_IPR_INTERVALTIMER 0x00000200 75275970Scy#define EMU_IPR_MIDITRANSBUFE 0x00000100 76275970Scy#define EMU_IPR_MIDIRECVBUFE 0x00000080 77275970Scy#define EMU_IPR_A_MIDITRANSBUFE2 0x10000000 78275970Scy#define EMU_IPR_A_MIDIRECBUFE2 0x08000000 79275970Scy#define EMU_IPR_CHANNELLOOP 0x00000040 80275970Scy#define EMU_IPR_CHNOMASK 0x0000003f 81275970Scy 82275970Scy#define EMU_INTE 0x0c 83275970Scy 84275970Scy#define EMU_INTE_VSB_MASK 0xc0000000 85275970Scy#define EMU_INTE_VSB_220 0x00000000 86275970Scy#define EMU_INTE_VSB_240 0x40000000 87275970Scy#define EMU_INTE_VSB_260 0x80000000 88275970Scy#define EMU_INTE_VSB_280 0xc0000000 89275970Scy 90275970Scy#define EMU_INTE_VMPU_MASK 0x30000000 91275970Scy#define EMU_INTE_VMPU_300 0x00000000 92275970Scy#define EMU_INTE_VMPU_310 0x10000000 93275970Scy#define EMU_INTE_VMPU_320 0x20000000 94275970Scy#define EMU_INTE_VMPU_330 0x30000000 95275970Scy#define EMU_INTE_MDMAENABLE 0x08000000 96275970Scy#define EMU_INTE_SDMAENABLE 0x04000000 97275970Scy#define EMU_INTE_MPICENABLE 0x02000000 98275970Scy#define EMU_INTE_SPICENABLE 0x01000000 99275970Scy#define EMU_INTE_VSBENABLE 0x00800000 100275970Scy#define EMU_INTE_ADLIBENABLE 0x00400000 101275970Scy#define EMU_INTE_MPUENABLE 0x00200000 102275970Scy#define EMU_INTE_FORCEINT 0x00100000 103275970Scy#define EMU_INTE_MRHANDENABLE 0x00080000 104275970Scy#define EMU_INTE_SAMPLERATER 0x00002000 105275970Scy#define EMU_INTE_FXDSPENABLE 0x00001000 106275970Scy#define EMU_INTE_PCIERRENABLE 0x00000800 107275970Scy#define EMU_INTE_VOLINCRENABLE 0x00000400 108275970Scy#define EMU_INTE_VOLDECRENABLE 0x00000200 109275970Scy#define EMU_INTE_MUTEENABLE 0x00000100 110275970Scy#define EMU_INTE_MICBUFENABLE 0x00000080 111275970Scy#define EMU_INTE_ADCBUFENABLE 0x00000040 112275970Scy#define EMU_INTE_EFXBUFENABLE 0x00000020 113275970Scy#define EMU_INTE_GPSPDIFENABLE 0x00000010 114275970Scy#define EMU_INTE_CDSPDIFENABLE 0x00000008 115275970Scy#define EMU_INTE_INTERTIMERENB 0x00000004 116275970Scy#define EMU_INTE_MIDITXENABLE 0x00000002 117275970Scy#define EMU_INTE_MIDIRXENABLE 0x00000001 118275970Scy#define EMU_INTE_A_MIDITXENABLE2 0x00020000 119275970Scy#define EMU_INTE_A_MIDIRXENABLE2 0x00010000 120275970Scy 121275970Scy#define EMU_WC 0x10 122275970Scy#define EMU_WC_SAMPLECOUNTER_MASK 0x03FFFFC0 123275970Scy#define EMU_WC_SAMPLECOUNTER EMU_MKSUBREG(20, 6, EMU_WC) 124275970Scy#define EMU_WC_CURRENTCHANNEL 0x0000003F 125275970Scy 126275970Scy#define EMU_HCFG 0x14 127275970Scy#define EMU_HCFG_LEGACYFUNC_MASK 0xe0000000 128275970Scy#define EMU_HCFG_LEGACYFUNC_MPU 0x00000000 129275970Scy#define EMU_HCFG_LEGACYFUNC_SB 0x40000000 130275970Scy#define EMU_HCFG_LEGACYFUNC_AD 0x60000000 131275970Scy#define EMU_HCFG_LEGACYFUNC_MPIC 0x80000000 132275970Scy#define EMU_HCFG_LEGACYFUNC_MDMA 0xa0000000 133275970Scy#define EMU_HCFG_LEGACYFUNC_SPCI 0xc0000000 134275970Scy#define EMU_HCFG_LEGACYFUNC_SDMA 0xe0000000 135275970Scy#define EMU_HCFG_IOCAPTUREADDR 0x1f000000 136275970Scy#define EMU_HCFG_LEGACYWRITE 0x00800000 137275970Scy#define EMU_HCFG_LEGACYWORD 0x00400000 138275970Scy#define EMU_HCFG_LEGACYINT 0x00200000 139275970Scy 140275970Scy#define EMU_HCFG_CODECFMT_MASK 0x00070000 141275970Scy#define EMU_HCFG_CODECFMT_AC97 0x00000000 142275970Scy#define EMU_HCFG_CODECFMT_I2S 0x00010000 143275970Scy#define EMU_HCFG_GPINPUT0 0x00004000 144275970Scy#define EMU_HCFG_GPINPUT1 0x00002000 145275970Scy#define EMU_HCFG_GPOUTPUT_MASK 0x00001c00 146275970Scy#define EMU_HCFG_JOYENABLE 0x00000200 147275970Scy#define EMU_HCFG_PHASETRACKENABLE 0x00000100 148275970Scy#define EMU_HCFG_AC3ENABLE_MASK 0x000000e0 149275970Scy#define EMU_HCFG_AC3ENABLE_ZVIDEO 0x00000080 150275970Scy#define EMU_HCFG_AC3ENABLE_CDSPDIF 0x00000040 151275970Scy#define EMU_HCFG_AC3ENABLE_GPSPDIF 0x00000020 152275970Scy#define EMU_HCFG_AUTOMUTE 0x00000010 153275970Scy#define EMU_HCFG_LOCKSOUNDCACHE 0x00000008 154275970Scy#define EMU_HCFG_LOCKTANKCACHE_MASK 0x00000004 155275970Scy#define EMU_HCFG_LOCKTANKCACHE EMU_MKSUBREG(1, 2, EMU_HCFG) 156275970Scy#define EMU_HCFG_MUTEBUTTONENABLE 0x00000002 157275970Scy#define EMU_HCFG_AUDIOENABLE 0x00000001 158275970Scy 159275970Scy#define EMU_MUDATA 0x18 160275970Scy#define EMU_MUCMD 0x19 161275970Scy#define EMU_MUCMD_RESET 0xff 162275970Scy#define EMU_MUCMD_ENTERUARTMODE 0x3f 163275970Scy 164275970Scy#define EMU_MUSTAT EMU_MUCMD 165275970Scy#define EMU_MUSTAT_IRDYN 0x80 166275970Scy#define EMU_MUSTAT_ORDYN 0x40 167275970Scy 168275970Scy#define EMU_A_IOCFG 0x18 169275970Scy#define EMU_A_GPINPUT_MASK 0xff00 170275970Scy#define EMU_A_GPOUTPUT_MASK 0x00ff 171275970Scy#define EMU_A_IOCFG_GPOUT0 0x0040 172275970Scy#define EMU_A_IOCFG_GPOUT1 0x0004 173275970Scy 174275970Scy#define EMU_TIMER 0x1a 175275970Scy#define EMU_TIMER_RATE_MASK 0x000003ff 176275970Scy#define EMU_TIMER_RATE EMU_MKSUBREG(10, 0, EMU_TIMER) 177275970Scy 178275970Scy#define EMU_AC97DATA 0x1c 179275970Scy#define EMU_AC97ADDR 0x1e 180275970Scy#define EMU_AC97ADDR_RDY 0x80 181275970Scy#define EMU_AC97ADDR_ADDR 0x7f 182275970Scy 183275970Scy#define EMU_A2_PTR 0x20 184275970Scy#define EMU_A2_DATA 0x24 185275970Scy 186275970Scy#define EMU_A2_SRCSEL 0x600000 187275970Scy#define EMU_A2_SRCSEL_ENABLE_SPDIF 0x00000004 188275970Scy#define EMU_A2_SRCSEL_ENABLE_SRCMULTI 0x00000010 189275970Scy#define EMU_A2_SRCMULTI 0x6e0000 190275970Scy#define EMU_A2_SRCMULTI_ENABLE_INPUT 0xff00ff00 191275970Scy 192275970Scy/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */ 193275970Scy 194275970Scy#define EMU_CHAN_CPF 0x00 195275970Scy 196275970Scy#define EMU_CHAN_CPF_PITCH_MASK 0xffff0000 197275970Scy#define EMU_CHAN_CPF_PITCH EMU_MKSUBREG(16, 16, EMU_CHAN_CPF) 198275970Scy#define EMU_CHAN_CPF_STEREO_MASK 0x00008000 199275970Scy#define EMU_CHAN_CPF_STEREO EMU_MKSUBREG(1, 15, EMU_CHAN_CPF) 200275970Scy#define EMU_CHAN_CPF_STOP_MASK 0x00004000 201275970Scy#define EMU_CHAN_CPF_FRACADDRESS_MASK 0x00003fff 202275970Scy 203275970Scy 204275970Scy#define EMU_CHAN_PTRX 0x01 205275970Scy#define EMU_CHAN_PTRX_PITCHTARGET_MASK 0xffff0000 206275970Scy#define EMU_CHAN_PTRX_PITCHTARGET EMU_MKSUBREG(16, 16, EMU_CHAN_PTRX) 207275970Scy#define EMU_CHAN_PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 208275970Scy#define EMU_CHAN_PTRX_FXSENDAMOUNT_A EMU_MKSUBREG(8, 8, EMU_CHAN_PTRX) 209275970Scy#define EMU_CHAN_PTRX_FXSENDAMOUNT_B_MASK 0x000000ff 210275970Scy#define EMU_CHAN_PTRX_FXSENDAMOUNT_B EMU_MKSUBREG(8, 0, EMU_CHAN_PTRX) 211275970Scy 212275970Scy#define EMU_CHAN_CVCF 0x02 213275970Scy#define EMU_CHAN_CVCF_CURRVOL_MASK 0xffff0000 214275970Scy#define EMU_CHAN_CVCF_CURRVOL EMU_MKSUBREG(16, 16, EMU_CHAN_CVCF) 215275970Scy#define EMU_CHAN_CVCF_CURRFILTER_MASK 0x0000ffff 216275970Scy#define EMU_CHAN_CVCF_CURRFILTER EMU_MKSUBREG(16, 0, EMU_CHAN_CVCF) 217275970Scy 218275970Scy#define EMU_CHAN_VTFT 0x03 219275970Scy#define EMU_CHAN_VTFT_VOLUMETARGET_MASK 0xffff0000 220275970Scy#define EMU_CHAN_VTFT_VOLUMETARGET EMU_MKSUBREG(16, 16, EMU_CHAN_VTFT) 221275970Scy#define EMU_CHAN_VTFT_FILTERTARGET_MASK 0x0000ffff 222275970Scy#define EMU_CHAN_VTFT_FILTERTARGET EMU_MKSUBREG(16, 0, EMU_CHAN_VTFT) 223275970Scy 224275970Scy#define EMU_CHAN_Z1 0x05 225275970Scy#define EMU_CHAN_Z2 0x04 226275970Scy 227275970Scy#define EMU_CHAN_PSST 0x06 228275970Scy#define EMU_CHAN_PSST_FXSENDAMOUNT_C_MASK 0xff000000 229275970Scy#define EMU_CHAN_PSST_FXSENDAMOUNT_C EMU_MKSUBREG(8, 24, EMU_CHAN_PSST) 230275970Scy#define EMU_CHAN_PSST_LOOPSTARTADDR_MASK 0x00ffffff 231275970Scy#define EMU_CHAN_PSST_LOOPSTARTADDR EMU_MKSUBREG(24, 0, EMU_CHAN_PSST) 232275970Scy 233275970Scy#define EMU_CHAN_DSL 0x07 234275970Scy#define EMU_CHAN_DSL_FXSENDAMOUNT_D_MASK 0xff000000 235275970Scy#define EMU_CHAN_DSL_FXSENDAMOUNT_D EMU_MKSUBREG(8, 24, EMU_CHAN_DSL) 236275970Scy#define EMU_CHAN_DSL_LOOPENDADDR_MASK 0x00ffffff 237275970Scy#define EMU_CHAN_DSL_LOOPENDADDR EMU_MKSUBREG(24, 0, EMU_CHAN_DSL) 238275970Scy 239275970Scy#define EMU_CHAN_CCCA 0x08 240275970Scy#define EMU_CHAN_CCCA_RESONANCE 0xf0000000 241275970Scy#define EMU_CHAN_CCCA_INTERPROMMASK 0x0e000000 242275970Scy#define EMU_CHAN_CCCA_INTERPROM_0 0x00000000 243275970Scy#define EMU_CHAN_CCCA_INTERPROM_1 0x02000000 244275970Scy#define EMU_CHAN_CCCA_INTERPROM_2 0x04000000 245275970Scy#define EMU_CHAN_CCCA_INTERPROM_3 0x06000000 246275970Scy#define EMU_CHAN_CCCA_INTERPROM_4 0x08000000 247275970Scy#define EMU_CHAN_CCCA_INTERPROM_5 0x0a000000 248275970Scy#define EMU_CHAN_CCCA_INTERPROM_6 0x0c000000 249275970Scy#define EMU_CHAN_CCCA_INTERPROM_7 0x0e000000 250275970Scy#define EMU_CHAN_CCCA_8BITSELECT 0x01000000 251275970Scy#define EMU_CHAN_CCCA_CURRADDR_MASK 0x00ffffff 252275970Scy#define EMU_CHAN_CCCA_CURRADDR EMU_MKSUBREG(24, 0, EMU_CHAN_CCCA) 253275970Scy 254275970Scy#define EMU_CHAN_CCR 0x09 255275970Scy#define EMU_CHAN_CCR_CACHEINVALIDSIZE_MASK 0xfe000000 256275970Scy#define EMU_CHAN_CCR_CACHEINVALIDSIZE EMU_MKSUBREG(7, 25, EMU_CHAN_CCR) 257275970Scy#define EMU_CHAN_CCR_CACHELOOPFLAG 0x01000000 258275970Scy#define EMU_CHAN_CCR_INTERLEAVEDSAMPLES 0x00800000 259275970Scy#define EMU_CHAN_CCR_WORDSIZEDSAMPLES 0x00400000 260275970Scy#define EMU_CHAN_CCR_READADDRESS_MASK 0x003f0000 261275970Scy#define EMU_CHAN_CCR_READADDRESS EMU_MKSUBREG(6, 16, EMU_CHAN_CCR) 262275970Scy#define EMU_CHAN_CCR_LOOPINVALSIZE 0x0000fe00 263275970Scy#define EMU_CHAN_CCR_LOOPFLAG 0x00000100 264275970Scy#define EMU_CHAN_CCR_CACHELOOPADDRHI 0x000000ff 265275970Scy 266275970Scy#define EMU_CHAN_CLP 0x0a 267275970Scy#define EMU_CHAN_CLP_CACHELOOPADDR 0x0000ffff 268275970Scy 269275970Scy#define EMU_CHAN_FXRT 0x0b 270275970Scy#define EMU_CHAN_FXRT_CHANNELA 0x000f0000 271275970Scy#define EMU_CHAN_FXRT_CHANNELB 0x00f00000 272275970Scy#define EMU_CHAN_FXRT_CHANNELC 0x0f000000 273275970Scy#define EMU_CHAN_FXRT_CHANNELD 0xf0000000 274275970Scy 275275970Scy#define EMU_CHAN_MAPA 0x0c 276275970Scy#define EMU_CHAN_MAPB 0x0d 277275970Scy 278275970Scy#define EMU_CHAN_MAP_PTE_MASK 0xffffe000 279275970Scy#define EMU_CHAN_MAP_PTI_MASK 0x00001fff 280275970Scy 281275970Scy 282275970Scy#define EMU_CHAN_ENVVOL 0x10 283275970Scy#define EMU_CHAN_ENVVOL_MASK 0x0000ffff 284275970Scy 285275970Scy 286275970Scy#define EMU_CHAN_ATKHLDV 0x11 287275970Scy#define EMU_CHAN_ATKHLDV_PHASE0 0x00008000 288275970Scy#define EMU_CHAN_ATKHLDV_HOLDTIME_MASK 0x00007f00 289275970Scy#define EMU_CHAN_ATKHLDV_ATTACKTIME_MASK 0x0000007f 290275970Scy 291275970Scy 292275970Scy#define EMU_CHAN_DCYSUSV 0x12 293275970Scy#define EMU_CHAN_DCYSUSV_PHASE1_MASK 0x00008000 294275970Scy#define EMU_CHAN_DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 295275970Scy#define EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK 0x00000080 296275970Scy#define EMU_CHAN_DCYSUSV_DECAYTIME_MASK 0x0000007f 297275970Scy 298275970Scy 299275970Scy#define EMU_CHAN_LFOVAL1 0x13 300275970Scy#define EMU_CHAN_LFOVAL_MASK 0x0000ffff 301275970Scy 302275970Scy#define EMU_CHAN_ENVVAL 0x14 303275970Scy#define EMU_CHAN_ENVVAL_MASK 0x0000ffff 304275970Scy 305275970Scy#define EMU_CHAN_ATKHLDM 0x15 306275970Scy#define EMU_CHAN_ATKHLDM_PHASE0 0x00008000 307275970Scy#define EMU_CHAN_ATKHLDM_HOLDTIME 0x00007f00 308275970Scy#define EMU_CHAN_ATKHLDM_ATTACKTIME 0x0000007f 309275970Scy 310275970Scy#define EMU_CHAN_DCYSUSM 0x16 311275970Scy#define EMU_CHAN_DCYSUSM_PHASE1_MASK 0x00008000 312275970Scy#define EMU_CHAN_DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 313275970Scy#define EMU_CHAN_DCYSUSM_DECAYTIME_MASK 0x0000007f 314275970Scy 315275970Scy#define EMU_CHAN_LFOVAL2 0x17 316275970Scy#define EMU_CHAN_LFOVAL2_MASK 0x0000ffff 317275970Scy 318275970Scy#define EMU_CHAN_IP 0x18 319275970Scy#define EMU_CHAN_IP_MASK 0x0000ffff 320275970Scy#define EMU_CHAN_IP_UNITY 0x0000e000 321275970Scy 322275970Scy#define EMU_CHAN_IFATN 0x19 323275970Scy#define EMU_CHAN_IFATN_FILTERCUTOFF_MASK 0x0000ff00 324275970Scy#define EMU_CHAN_IFATN_FILTERCUTOFF EMU_MKSUBREG(8, 8, EMU_CHAN_IFATN) 325275970Scy#define EMU_CHAN_IFATN_ATTENUATION_MASK 0x000000ff 326275970Scy#define EMU_CHAN_IFATN_ATTENUATION EMU_MKSUBREG(8, 0, EMU_CHAN_IFATN) 327275970Scy 328275970Scy#define EMU_CHAN_PEFE 0x1a 329275970Scy#define EMU_CHAN_PEFE_PITCHAMOUNT_MASK 0x0000ff00 330275970Scy#define EMU_CHAN_PEFE_PITCHAMOUNT EMU_MKSUBREG(8, 8, EMU_CHAN_PEFE) 331275970Scy#define EMU_CHAN_PEFE_FILTERAMOUNT_MASK 0x000000ff 332275970Scy#define EMU_CHAN_PEFE_FILTERAMOUNT EMU_MKSUBREG(8, 0, EMU_CHAN_PEFE) 333275970Scy 334275970Scy#define EMU_CHAN_FMMOD 0x1b 335275970Scy#define EMU_CHAN_FMMOD_MODVIBRATO 0x0000ff00 336275970Scy#define EMU_CHAN_FMMOD_MOFILTER 0x000000ff 337275970Scy 338275970Scy#define EMU_CHAN_TREMFRQ 0x1c 339275970Scy#define EMU_CHAN_TREMFRQ_DEPTH 0x0000ff00 340275970Scy 341275970Scy#define EMU_CHAN_FM2FRQ2 0x1d 342275970Scy#define EMU_CHAN_FM2FRQ2_DEPTH 0x0000ff00 343275970Scy#define EMU_CHAN_FM2FRQ2_FREQUENCY 0x000000ff 344275970Scy 345275970Scy#define EMU_CHAN_TEMPENV 0x1e 346275970Scy#define EMU_CHAN_TEMPENV_MASK 0x0000ffff 347275970Scy 348275970Scy#define EMU_CHAN_CD0 0x20 349275970Scy#define EMU_CHAN_CD1 0x21 350275970Scy#define EMU_CHAN_CD2 0x22 351275970Scy#define EMU_CHAN_CD3 0x23 352275970Scy#define EMU_CHAN_CD4 0x24 353275970Scy#define EMU_CHAN_CD5 0x25 354275970Scy#define EMU_CHAN_CD6 0x26 355275970Scy#define EMU_CHAN_CD7 0x27 356275970Scy#define EMU_CHAN_CD8 0x28 357275970Scy#define EMU_CHAN_CD9 0x29 358275970Scy#define EMU_CHAN_CDA 0x2a 359275970Scy#define EMU_CHAN_CDB 0x2b 360275970Scy#define EMU_CHAN_CDC 0x2c 361275970Scy#define EMU_CHAN_CDD 0x2d 362275970Scy#define EMU_CHAN_CDE 0x2e 363275970Scy#define EMU_CHAN_CDF 0x2f 364275970Scy 365275970Scy/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */ 366275970Scy 367275970Scy#define EMU_PTB 0x40 368275970Scy#define EMU_PTB_MASK 0xfffff000 369275970Scy 370275970Scy#define EMU_TCB 0x41 371275970Scy#define EMU_TCB_MASK 0xfffff000 372275970Scy 373275970Scy#define EMU_ADCCR 0x42 374275970Scy#define EMU_ADCCR_RCHANENABLE 0x00000010 375275970Scy#define EMU_A_ADCCR_RCHANENABLE 0x00000020 376275970Scy#define EMU_ADCCR_LCHANENABLE 0x00000008 377275970Scy#define EMU_A_ADCCR_LCHANENABLE 0x00000010 378275970Scy#define EMU_ADCCR_SAMPLERATE_MASK 0x00000007 379275970Scy#define EMU_A_ADCCR_SAMPLERATE_MASK 0x0000000f 380275970Scy#define EMU_ADCCR_SAMPLERATE_48 0x00000000 381275970Scy#define EMU_ADCCR_SAMPLERATE_44 0x00000001 382275970Scy#define EMU_ADCCR_SAMPLERATE_32 0x00000002 383275970Scy#define EMU_ADCCR_SAMPLERATE_24 0x00000003 384275970Scy#define EMU_ADCCR_SAMPLERATE_22 0x00000004 385275970Scy#define EMU_ADCCR_SAMPLERATE_16 0x00000005 386275970Scy#define EMU_A_ADCCR_SAMPLERATE_12 0x00000006 387275970Scy#define EMU_ADCCR_SAMPLERATE_11 0x00000006 388275970Scy#define EMU_A_ADCCR_SAMPLERATE_11 0x00000007 389275970Scy#define EMU_ADCCR_SAMPLERATE_8 0x00000007 390275970Scy#define EMU_A_ADCCR_SAMPLERATE_8 0x00000008 391275970Scy 392275970Scy#define EMU_FXWC 0x43 393275970Scy#define EMU_TCBS 0x44 394275970Scy#define EMU_TCBS_MASK 0x00000007 395275970Scy#define EMU_TCBS_BUFFSIZE_16K 0x00000000 396275970Scy#define EMU_TCBS_BUFFSIZE_32K 0x00000001 397275970Scy#define EMU_TCBS_BUFFSIZE_64K 0x00000002 398275970Scy#define EMU_TCBS_BUFFSIZE_128K 0x00000003 399275970Scy#define EMU_TCBS_BUFFSIZE_256K 0x00000004 400275970Scy#define EMU_TCBS_BUFFSIZE_512K 0x00000005 401275970Scy#define EMU_TCBS_BUFFSIZE_1024K 0x00000006 402275970Scy#define EMU_TCBS_BUFFSIZE_2048K 0x00000007 403275970Scy 404275970Scy#define EMU_MICBA 0x45 405275970Scy#define EMU_ADCBA 0x46 406275970Scy#define EMU_FXBA 0x47 407275970Scy#define EMU_RECBA_MASK 0xfffff000 408275970Scy 409275970Scy#define EMU_MICBS 0x49 410275970Scy#define EMU_ADCBS 0x4a 411275970Scy#define EMU_FXBS 0x4b 412275970Scy#define EMU_RECBS_BUFSIZE_NONE 0x00000000 413275970Scy#define EMU_RECBS_BUFSIZE_384 0x00000001 414275970Scy#define EMU_RECBS_BUFSIZE_448 0x00000002 415275970Scy#define EMU_RECBS_BUFSIZE_512 0x00000003 416275970Scy#define EMU_RECBS_BUFSIZE_640 0x00000004 417275970Scy#define EMU_RECBS_BUFSIZE_768 0x00000005 418275970Scy#define EMU_RECBS_BUFSIZE_896 0x00000006 419275970Scy#define EMU_RECBS_BUFSIZE_1024 0x00000007 420275970Scy#define EMU_RECBS_BUFSIZE_1280 0x00000008 421275970Scy#define EMU_RECBS_BUFSIZE_1536 0x00000009 422275970Scy#define EMU_RECBS_BUFSIZE_1792 0x0000000a 423275970Scy#define EMU_RECBS_BUFSIZE_2048 0x0000000b 424275970Scy#define EMU_RECBS_BUFSIZE_2560 0x0000000c 425275970Scy#define EMU_RECBS_BUFSIZE_3072 0x0000000d 426275970Scy#define EMU_RECBS_BUFSIZE_3584 0x0000000e 427275970Scy#define EMU_RECBS_BUFSIZE_4096 0x0000000f 428275970Scy#define EMU_RECBS_BUFSIZE_5120 0x00000010 429275970Scy#define EMU_RECBS_BUFSIZE_6144 0x00000011 430275970Scy#define EMU_RECBS_BUFSIZE_7168 0x00000012 431275970Scy#define EMU_RECBS_BUFSIZE_8192 0x00000013 432275970Scy#define EMU_RECBS_BUFSIZE_10240 0x00000014 433275970Scy#define EMU_RECBS_BUFSIZE_12288 0x00000015 434275970Scy#define EMU_RECBS_BUFSIZE_14366 0x00000016 435275970Scy#define EMU_RECBS_BUFSIZE_16384 0x00000017 436275970Scy#define EMU_RECBS_BUFSIZE_20480 0x00000018 437275970Scy#define EMU_RECBS_BUFSIZE_24576 0x00000019 438275970Scy#define EMU_RECBS_BUFSIZE_28672 0x0000001a 439275970Scy#define EMU_RECBS_BUFSIZE_32768 0x0000001b 440275970Scy#define EMU_RECBS_BUFSIZE_40960 0x0000001c 441275970Scy#define EMU_RECBS_BUFSIZE_49152 0x0000001d 442275970Scy#define EMU_RECBS_BUFSIZE_57344 0x0000001e 443275970Scy#define EMU_RECBS_BUFSIZE_65536 0x0000001f 444275970Scy 445275970Scy#define EMU_CDCS 0x50 446275970Scy#define EMU_GPSCS 0x51 447275970Scy 448275970Scy#define EMU_DBG 0x52 449275970Scy#define EMU_DBG_ZC 0x80000000 450275970Scy#define EMU_DBG_SATURATION_OCCURRED 0x02000000 451275970Scy#define EMU_DBG_SATURATION_ADDR 0x01ff0000 452275970Scy#define EMU_DBG_SINGLE_STEP 0x00008000 453275970Scy#define EMU_DBG_STEP 0x00004000 454275970Scy#define EMU_DBG_CONDITION_CODE 0x00003e00 455275970Scy#define EMU_DBG_SINGLE_STEP_ADDR 0x000001ff 456275970Scy 457275970Scy#define EMU_A_DBG 0x53 458275970Scy#define EMU_A_DBG_SINGLE_STEP 0x00020000 459275970Scy#define EMU_A_DBG_ZC 0x40000000 460275970Scy#define EMU_A_DBG_STEP_ADDR 0x000003ff 461275970Scy#define EMU_A_DBG_SATURATION_OCCRD 0x20000000 462275970Scy#define EMU_A_DBG_SATURATION_ADDR 0x0ffc0000 463275970Scy 464275970Scy#define EMU_SPCS0 0x54 465275970Scy#define EMU_SPCS1 0x55 466275970Scy#define EMU_SPCS2 0x56 467275970Scy#define EMU_SPCS_CLKACCYMASK 0x30000000 468275970Scy#define EMU_SPCS_CLKACCY_1000PPM 0x00000000 469275970Scy#define EMU_SPCS_CLKACCY_50PPM 0x10000000 470275970Scy#define EMU_SPCS_CLKACCY_VARIABLE 0x20000000 471275970Scy#define EMU_SPCS_SAMPLERATEMASK 0x0f000000 472275970Scy#define EMU_SPCS_SAMPLERATE_44 0x00000000 473275970Scy#define EMU_SPCS_SAMPLERATE_48 0x02000000 474275970Scy#define EMU_SPCS_SAMPLERATE_32 0x03000000 475275970Scy#define EMU_SPCS_CHANNELNUMMASK 0x00f00000 476275970Scy#define EMU_SPCS_CHANNELNUM_UNSPEC 0x00000000 477275970Scy#define EMU_SPCS_CHANNELNUM_LEFT 0x00100000 478275970Scy#define EMU_SPCS_CHANNELNUM_RIGHT 0x00200000 479275970Scy#define EMU_SPCS_SOURCENUMMASK 0x000f0000 480275970Scy#define EMU_SPCS_SOURCENUM_UNSPEC 0x00000000 481275970Scy#define EMU_SPCS_GENERATIONSTATUS 0x00008000 482275970Scy#define EMU_SPCS_CATEGORYCODEMASK 0x00007f00 483275970Scy#define EMU_SPCS_MODEMASK 0x000000c0 484275970Scy#define EMU_SPCS_EMPHASISMASK 0x00000038 485275970Scy#define EMU_SPCS_EMPHASIS_NONE 0x00000000 486275970Scy#define EMU_SPCS_EMPHASIS_50_15 0x00000008 487275970Scy#define EMU_SPCS_COPYRIGHT 0x00000004 488275970Scy#define EMU_SPCS_NOTAUDIODATA 0x00000002 489275970Scy#define EMU_SPCS_PROFESSIONAL 0x00000001 490275970Scy 491275970Scy#define EMU_CLIEL 0x58 492275970Scy#define EMU_CLIEH 0x59 493275970Scy#define EMU_CLIPL 0x5a 494275970Scy#define EMU_CLIPH 0x5b 495275970Scy#define EMU_SOLEL 0x5c 496275970Scy#define EMU_SOLEH 0x5d 497275970Scy 498275970Scy#define EMU_SPBYPASS 0x5e 499275970Scy#define EMU_SPBYPASS_ENABLE 0x00000001 500275970Scy#define EMU_SPBYPASS_24_BITS 0x00000f00 501275970Scy 502275970Scy#define EMU_AC97SLOT 0x5f 503275970Scy#define EMU_AC97SLOT_CENTER 0x00000010 504275970Scy#define EMU_AC97SLOT_LFE 0x00000020 505275970Scy 506275970Scy#define EMU_CDSRCS 0x60 507275970Scy#define EMU_GPSRCS 0x61 508275970Scy#define EMU_ZVSRCS 0x62 509275970Scy#define EMU_SRCS_SPDIFLOCKED 0x02000000 510275970Scy#define EMU_SRCS_RATELOCKED 0x01000000 511275970Scy#define EMU_SRCS_ESTSAMPLERATE 0x0007ffff 512275970Scy 513275970Scy#define EMU_MICIDX 0x63 514275970Scy#define EMU_A_MICIDX 0x64 515275970Scy#define EMU_ADCIDX 0x64 516275970Scy#define EMU_A_ADCIDX 0x63 517275970Scy#define EMU_FXIDX 0x65 518275970Scy#define EMU_RECIDX_MASK 0x0000ffff 519275970Scy#define EMU_RECIDX(idxreg) (0x10000000|(idxreg)) 520275970Scy/* 521275970Scy#define EMU_MICIDX_IDX 0x10000063 522275970Scy#define EMU_ADCIDX_IDX 0x10000064 523275970Scy#define EMU_FXIDX_IDX 0x10000065 524275970Scy*/ 525275970Scy 526275970Scy#define EMU_A_MUDATA1 0x70 527275970Scy#define EMU_A_MUCMD1 0x71 528275970Scy#define EMU_A_MUSTAT1 EMU_A_MUCMD1 529275970Scy#define EMU_A_MUDATA2 0x72 530275970Scy#define EMU_A_MUCMD2 0x73 531275970Scy#define EMU_A_MUSTAT2 EMU_A_MUCMD2 532275970Scy#define EMU_A_FXWC1 0x74 533275970Scy#define EMU_A_FXWC2 0x75 534275970Scy#define EMU_A_SPDIF_SAMPLERATE 0x76 535275970Scy#define EMU_A_SPDIF_48000 0x00000080 536275970Scy#define EMU_A_SPDIF_44100 0x00000000 537275970Scy#define EMU_A_SPDIF_96000 0x00000040 538275970Scy#define EMU_A2_SPDIF_SAMPLERATE EMU_MKSUBREG(3, 9, EMU_A_SPDIF_SAMPLERATE) 539275970Scy#define EMU_A2_SPDIF_MASK 0x00000e00 540275970Scy#define EMU_A2_SPDIF_UNKNOWN 0x2 541275970Scy 542275970Scy#define EMU_A_CHAN_FXRT2 0x7c 543275970Scy#define EMU_A_CHAN_FXRT_CHANNELE 0x0000003f 544275970Scy#define EMU_A_CHAN_FXRT_CHANNELF 0x00003f00 545275970Scy#define EMU_A_CHAN_FXRT_CHANNELG 0x003f0000 546275970Scy#define EMU_A_CHAN_FXRT_CHANNELH 0x3f000000 547275970Scy#define EMU_A_CHAN_SENDAMOUNTS 0x7d 548275970Scy#define EMU_A_CHAN_FXSENDAMOUNTS_E_MASK 0xff000000 549275970Scy#define EMU_A_CHAN_FXSENDAMOUNTS_F_MASK 0x00ff0000 550275970Scy#define EMU_A_CHAN_FXSENDAMOUNTS_G_MASK 0x0000ff00 551275970Scy#define EMU_A_CHAN_FXSENDAMOUNTS_H_MASK 0x000000ff 552275970Scy#define EMU_A_CHAN_FXRT1 0x7e 553275970Scy#define EMU_A_CHAN_FXRT_CHANNELA 0x0000003f 554275970Scy#define EMU_A_CHAN_FXRT_CHANNELB 0x00003f00 555275970Scy#define EMU_A_CHAN_FXRT_CHANNELC 0x003f0000 556275970Scy#define EMU_A_CHAN_FXRT_CHANNELD 0x3f000000 557275970Scy 558275970Scy#define EMU_FXGPREGBASE 0x100 559275970Scy#define EMU_A_FXGPREGBASE 0x400 560275970Scy 561275970Scy#define EMU_TANKMEMDATAREGBASE 0x200 562275970Scy#define EMU_TANKMEMDATAREG_MASK 0x000fffff 563275970Scy 564275970Scy#define EMU_TANKMEMADDRREGBASE 0x300 565275970Scy#define EMU_TANKMEMADDRREG_ADDR_MASK 0x000fffff 566275970Scy#define EMU_TANKMEMADDRREG_CLEAR 0x00800000 567275970Scy#define EMU_TANKMEMADDRREG_ALIGN 0x00400000 568275970Scy#define EMU_TANKMEMADDRREG_WRITE 0x00200000 569275970Scy#define EMU_TANKMEMADDRREG_READ 0x00100000 570275970Scy 571275970Scy#define EMU_MICROCODEBASE 0x400 572275970Scy#define EMU_A_MICROCODEBASE 0x600 573275970Scy#define EMU_DSP_LOWORD_OPX_MASK 0x000ffc00 574275970Scy#define EMU_DSP_LOWORD_OPY_MASK 0x000003ff 575275970Scy#define EMU_DSP_HIWORD_OPCODE_MASK 0x00f00000 576275970Scy#define EMU_DSP_HIWORD_RESULT_MASK 0x000ffc00 577275970Scy#define EMU_DSP_HIWORD_OPA_MASK 0x000003ff 578275970Scy#define EMU_A_DSP_LOWORD_OPX_MASK 0x007ff000 579275970Scy#define EMU_A_DSP_LOWORD_OPY_MASK 0x000007ff 580275970Scy#define EMU_A_DSP_HIWORD_OPCODE_MASK 0x0f000000 581275970Scy#define EMU_A_DSP_HIWORD_RESULT_MASK 0x007ff000 582275970Scy#define EMU_A_DSP_HIWORD_OPA_MASK 0x000007ff 583275970Scy 584275970Scy#define EMU_DSP_OP_MACS 0x0 585275970Scy#define EMU_DSP_OP_MACS1 0x1 586275970Scy#define EMU_DSP_OP_MACW 0x2 587275970Scy#define EMU_DSP_OP_MACW1 0x3 588275970Scy#define EMU_DSP_OP_MACINTS 0x4 589275970Scy#define EMU_DSP_OP_MACINTW 0x5 590275970Scy#define EMU_DSP_OP_ACC3 0x6 591275970Scy#define EMU_DSP_OP_MACMV 0x7 592275970Scy#define EMU_DSP_OP_ANDXOR 0x8 593275970Scy#define EMU_DSP_OP_TSTNEG 0x9 594275970Scy#define EMU_DSP_OP_LIMIT 0xA 595275970Scy#define EMU_DSP_OP_LIMIT1 0xB 596275970Scy#define EMU_DSP_OP_LOG 0xC 597275970Scy#define EMU_DSP_OP_EXP 0xD 598275970Scy#define EMU_DSP_OP_INTERP 0xE 599275970Scy#define EMU_DSP_OP_SKIP 0xF 600275970Scy 601275970Scy 602275970Scy#define EMU_DSP_FX(num) (num) 603275970Scy 604275970Scy#define EMU_DSP_IOL(base, num) (base + (num << 1)) 605275970Scy#define EMU_DSP_IOR(base, num) (EMU_DSP_IOL(base, num) + 1) 606275970Scy 607275970Scy#define EMU_DSP_INL_BASE 0x010 608275970Scy#define EMU_DSP_INL(num) (EMU_DSP_IOL(EMU_DSP_INL_BASE, num)) 609275970Scy#define EMU_DSP_INR(num) (EMU_DSP_IOR(EMU_DSP_INL_BASE, num)) 610275970Scy#define EMU_A_DSP_INL_BASE 0x040 611275970Scy#define EMU_A_DSP_INL(num) (EMU_DSP_IOL(EMU_A_DSP_INL_BASE, num)) 612275970Scy#define EMU_A_DSP_INR(num) (EMU_DSP_IOR(EMU_A_DSP_INL_BASE, num)) 613275970Scy#define EMU_DSP_IN_AC97 0 614275970Scy#define EMU_DSP_IN_CDSPDIF 1 615275970Scy#define EMU_DSP_IN_ZOOM 2 616275970Scy#define EMU_DSP_IN_TOSOPT 3 617275970Scy#define EMU_DSP_IN_LVDLM1 4 618275970Scy#define EMU_DSP_IN_LVDCOS 5 619275970Scy#define EMU_DSP_IN_LVDLM2 6 620275970Scy#define EMU_DSP_IN_UNKNOWN 7 621275970Scy 622275970Scy#define EMU_DSP_OUTL_BASE 0x020 623275970Scy#define EMU_DSP_OUTL(num) (EMU_DSP_IOL(EMU_DSP_OUTL_BASE, num)) 624275970Scy#define EMU_DSP_OUTR(num) (EMU_DSP_IOR(EMU_DSP_OUTL_BASE, num)) 625275970Scy#define EMU_DSP_OUT_A_FRONT 0 626275970Scy#define EMU_DSP_OUT_D_FRONT 1 627275970Scy#define EMU_DSP_OUT_D_CENTER 2 628275970Scy#define EMU_DSP_OUT_DRIVE_HP 3 629275970Scy#define EMU_DSP_OUT_AD_REAR 4 630275970Scy#define EMU_DSP_OUT_ADC 5 631275970Scy#define EMU_DSP_OUTL_MIC 6 632275970Scy 633275970Scy#define EMU_A_DSP_OUTL_BASE 0x060 634275970Scy#define EMU_A_DSP_OUTL(num) (EMU_DSP_IOL(EMU_A_DSP_OUTL_BASE, num)) 635275970Scy#define EMU_A_DSP_OUTR(num) (EMU_DSP_IOR(EMU_A_DSP_OUTL_BASE, num)) 636275970Scy#define EMU_A_DSP_OUT_D_FRONT 0 637275970Scy#define EMU_A_DSP_OUT_D_CENTER 1 638275970Scy#define EMU_A_DSP_OUT_DRIVE_HP 2 639275970Scy#define EMU_A_DSP_OUT_DREAR 3 640275970Scy#define EMU_A_DSP_OUT_A_FRONT 4 641275970Scy#define EMU_A_DSP_OUT_A_CENTER 5 642275970Scy#define EMU_A_DSP_OUT_A_REAR 7 643275970Scy#define EMU_A_DSP_OUT_ADC 11 644275970Scy 645275970Scy#define EMU_DSP_CST_BASE 0x40 646275970Scy#define EMU_A_DSP_CST_BASE 0xc0 647275970Scy#define EMU_DSP_CST(num) (EMU_DSP_CST_BASE + num) 648275970Scy#define EMU_A_DSP_CST(num) (EMU_A_DSP_CST_BASE + num) 649275970Scy/* 650275970Scy00 = 0x00000000 651275970Scy01 = 0x00000001 652275970Scy02 = 0x00000002 653275970Scy03 = 0x00000003 654275970Scy04 = 0x00000004 655275970Scy05 = 0x00000008 656275970Scy06 = 0x00000010 657275970Scy07 = 0x00000020 658275970Scy08 = 0x00000100 659275970Scy09 = 0x00010000 660275970Scy0A = 0x00080000 661275970Scy0B = 0x10000000 662275970Scy0C = 0x20000000 663275970Scy0D = 0x40000000 664275970Scy0E = 0x80000000 665275970Scy0F = 0x7FFFFFFF 666275970Scy10 = 0xFFFFFFFF 667275970Scy11 = 0xFFFFFFFE 668275970Scy12 = 0xC0000000 669275970Scy13 = 0x4F1BBCDC 670275970Scy14 = 0x5A7EF9DB 671275970Scy15 = 0x00100000 672275970Scy*/ 673275970Scy 674275970Scy#define EMU_DSP_HWR_ACC 0x056 675275970Scy#define EMU_DSP_HWR_CCR 0x057 676275970Scy#define EMU_DSP_HWR_CCR_S 0x04 677275970Scy#define EMU_DSP_HWR_CCR_Z 0x03 678275970Scy#define EMU_DSP_HWR_CCR_M 0x02 679275970Scy#define EMU_DSP_HWR_CCR_N 0x01 680275970Scy#define EMU_DSP_HWR_CCR_B 0x00 681275970Scy#define EMU_DSP_HWR_NOISE0 0x058 682275970Scy#define EMU_DSP_HWR_NOISE1 0x059 683275970Scy#define EMU_DSP_HWR_INTR 0x05A 684275970Scy#define EMU_DSP_HWR_DBAC 0x05B 685275970Scy 686275970Scy#define EMU_DSP_GPR(num) (EMU_FXGPREGBASE + num) 687275970Scy#define EMU_A_DSP_GPR(num) (EMU_A_FXGPREGBASE + num) 688275970Scy 689275970Scy#endif /* _DEV_PCI_EMUXKIREG_H_ */ 690275970Scy