csa.c revision 82180
1/* 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <machine/resource.h> 38#include <machine/bus.h> 39#include <sys/rman.h> 40#include <sys/soundcard.h> 41#include <dev/sound/pcm/sound.h> 42#include <dev/sound/chip.h> 43#include <dev/sound/pci/csareg.h> 44#include <dev/sound/pci/csavar.h> 45 46#include <pci/pcireg.h> 47#include <pci/pcivar.h> 48 49#include <gnu/dev/sound/pci/csaimg.h> 50 51SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/csa.c 82180 2001-08-23 11:30:52Z cg $"); 52 53/* This is the pci device id. */ 54#define CS4610_PCI_ID 0x60011013 55#define CS4614_PCI_ID 0x60031013 56#define CS4615_PCI_ID 0x60041013 57 58/* Here is the parameter structure per a device. */ 59struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73}; 74 75typedef struct csa_softc *sc_p; 76 77static int csa_probe(device_t dev); 78static int csa_attach(device_t dev); 79static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 driver_intr_t *intr, void *arg, void **cookiep); 86static int csa_teardown_intr(device_t bus, device_t child, 87 struct resource *irq, void *cookie); 88static driver_intr_t csa_intr; 89static int csa_initialize(sc_p scp); 90static void csa_resetdsp(csa_res *resp); 91static int csa_downloadimage(csa_res *resp); 92 93static devclass_t csa_devclass; 94 95static void 96amp_none(void) 97{ 98} 99 100static void 101amp_voyetra(void) 102{ 103} 104 105static int 106clkrun_hack(int run) 107{ 108#ifdef __i386__ 109 devclass_t pci_devclass; 110 device_t *pci_devices, *pci_children, *busp, *childp; 111 int pci_count = 0, pci_childcount = 0; 112 int i, j, port; 113 u_int16_t control; 114 bus_space_tag_t btag; 115 116 if ((pci_devclass = devclass_find("pci")) == NULL) { 117 return ENXIO; 118 } 119 120 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 121 122 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 123 pci_childcount = 0; 124 device_get_children(*busp, &pci_children, &pci_childcount); 125 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 126 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 127 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 128 /* XXX */ 129 btag = I386_BUS_SPACE_IO; 130 131 control = bus_space_read_2(btag, 0x0, port); 132 control &= ~0x2000; 133 control |= run? 0 : 0x2000; 134 bus_space_write_2(btag, 0x0, port, control); 135 free(pci_devices, M_TEMP); 136 free(pci_children, M_TEMP); 137 return 0; 138 } 139 } 140 free(pci_children, M_TEMP); 141 } 142 143 free(pci_devices, M_TEMP); 144 return ENXIO; 145#else 146 return 0; 147#endif 148} 149 150static struct csa_card cards_4610[] = { 151 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 152}; 153 154static struct csa_card cards_4614[] = { 155 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 156 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 157 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 158 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 159 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 160 /* Not sure if the 570 needs the clkrun hack */ 161 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, clkrun_hack, 0}, 162 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 163 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 164 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 165}; 166 167static struct csa_card cards_4615[] = { 168 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 169}; 170 171static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 172 173struct card_type { 174 u_int32_t devid; 175 char *name; 176 struct csa_card *cards; 177}; 178 179static struct card_type cards[] = { 180 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 181 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 182 {CS4615_PCI_ID, "CS4615", cards_4615}, 183 {0, NULL, NULL}, 184}; 185 186static struct card_type * 187csa_findcard(device_t dev) 188{ 189 int i; 190 191 i = 0; 192 while (cards[i].devid != 0) { 193 if (pci_get_devid(dev) == cards[i].devid) 194 return &cards[i]; 195 i++; 196 } 197 return NULL; 198} 199 200struct csa_card * 201csa_findsubcard(device_t dev) 202{ 203 int i; 204 struct card_type *card; 205 struct csa_card *subcard; 206 207 card = csa_findcard(dev); 208 if (card == NULL) 209 return &nocard; 210 subcard = card->cards; 211 i = 0; 212 while (subcard[i].subvendor != 0) { 213 if (pci_get_subvendor(dev) == subcard[i].subvendor 214 && pci_get_subdevice(dev) == subcard[i].subdevice) { 215 return &subcard[i]; 216 } 217 i++; 218 } 219 return &subcard[i]; 220} 221 222static int 223csa_probe(device_t dev) 224{ 225 struct card_type *card; 226 227 card = csa_findcard(dev); 228 if (card) { 229 device_set_desc(dev, card->name); 230 return 0; 231 } 232 return ENXIO; 233} 234 235static int 236csa_attach(device_t dev) 237{ 238 u_int32_t stcmd; 239 sc_p scp; 240 csa_res *resp; 241 struct sndcard_func *func; 242 int error = ENXIO; 243 244 scp = device_get_softc(dev); 245 246 /* Fill in the softc. */ 247 bzero(scp, sizeof(*scp)); 248 scp->dev = dev; 249 250 /* Wake up the device. */ 251 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 252 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 253 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 254 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 255 } 256 257 /* Allocate the resources. */ 258 resp = &scp->res; 259 scp->card = csa_findsubcard(dev); 260 scp->binfo.card = scp->card; 261 printf("csa: card is %s\n", scp->card->name); 262 resp->io_rid = PCIR_MAPS; 263 resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, 1, RF_ACTIVE); 264 if (resp->io == NULL) 265 return (ENXIO); 266 resp->mem_rid = PCIR_MAPS + 4; 267 resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, 1, RF_ACTIVE); 268 if (resp->mem == NULL) 269 goto err_io; 270 resp->irq_rid = 0; 271 resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 272 if (resp->irq == NULL) 273 goto err_mem; 274 275 /* Enable interrupt. */ 276 if (snd_setup_intr(dev, resp->irq, INTR_MPSAFE, csa_intr, scp, &scp->ih)) 277 goto err_intr; 278#if 0 279 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 280 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 281#endif 282 283 /* Initialize the chip. */ 284 if (csa_initialize(scp)) 285 goto err_teardown; 286 287 /* Reset the Processor. */ 288 csa_resetdsp(resp); 289 290 /* Download the Processor Image to the processor. */ 291 if (csa_downloadimage(resp)) 292 goto err_teardown; 293 294 /* Attach the children. */ 295 296 /* PCM Audio */ 297 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 298 if (func == NULL) { 299 error = ENOMEM; 300 goto err_teardown; 301 } 302 func->varinfo = &scp->binfo; 303 func->func = SCF_PCM; 304 scp->pcm = device_add_child(dev, "pcm", -1); 305 device_set_ivars(scp->pcm, func); 306 307 /* Midi Interface */ 308 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 309 if (func == NULL) { 310 error = ENOMEM; 311 goto err_teardown; 312 } 313 func->varinfo = &scp->binfo; 314 func->func = SCF_MIDI; 315 scp->midi = device_add_child(dev, "midi", -1); 316 device_set_ivars(scp->midi, func); 317 318 bus_generic_attach(dev); 319 320 return (0); 321 322err_teardown: 323 bus_teardown_intr(dev, resp->irq, scp->ih); 324err_intr: 325 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 326err_mem: 327 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 328err_io: 329 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 330 return (error); 331} 332 333static int 334csa_detach(device_t dev) 335{ 336 sc_p scp; 337 338 scp = device_get_softc(dev); 339 device_delete_child(dev, scp->midi); 340 device_delete_child(dev, scp->pcm); 341 return bus_generic_detach(dev); 342} 343 344static struct resource * 345csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 346 u_long start, u_long end, u_long count, u_int flags) 347{ 348 sc_p scp; 349 csa_res *resp; 350 struct resource *res; 351 352 scp = device_get_softc(bus); 353 resp = &scp->res; 354 switch (type) { 355 case SYS_RES_IRQ: 356 if (*rid != 0) 357 return (NULL); 358 res = resp->irq; 359 break; 360 case SYS_RES_MEMORY: 361 switch (*rid) { 362 case PCIR_MAPS: 363 res = resp->io; 364 break; 365 case PCIR_MAPS + 4: 366 res = resp->mem; 367 break; 368 default: 369 return (NULL); 370 } 371 break; 372 default: 373 return (NULL); 374 } 375 376 return res; 377} 378 379static int 380csa_release_resource(device_t bus, device_t child, int type, int rid, 381 struct resource *r) 382{ 383 return (0); 384} 385 386/* 387 * The following three functions deal with interrupt handling. 388 * An interrupt is primarily handled by the bridge driver. 389 * The bridge driver then determines the child devices to pass 390 * the interrupt. Certain information of the device can be read 391 * only once(eg the value of HISR). The bridge driver is responsible 392 * to pass such the information to the children. 393 */ 394 395static int 396csa_setup_intr(device_t bus, device_t child, 397 struct resource *irq, int flags, 398 driver_intr_t *intr, void *arg, void **cookiep) 399{ 400 sc_p scp; 401 csa_res *resp; 402 struct sndcard_func *func; 403 404 scp = device_get_softc(bus); 405 resp = &scp->res; 406 407 /* 408 * Look at the function code of the child to determine 409 * the appropriate hander for it. 410 */ 411 func = device_get_ivars(child); 412 if (func == NULL || irq != resp->irq) 413 return (EINVAL); 414 415 switch (func->func) { 416 case SCF_PCM: 417 scp->pcmintr = intr; 418 scp->pcmintr_arg = arg; 419 break; 420 421 case SCF_MIDI: 422 scp->midiintr = intr; 423 scp->midiintr_arg = arg; 424 break; 425 426 default: 427 return (EINVAL); 428 } 429 *cookiep = scp; 430 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 431 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 432 433 return (0); 434} 435 436static int 437csa_teardown_intr(device_t bus, device_t child, 438 struct resource *irq, void *cookie) 439{ 440 sc_p scp; 441 csa_res *resp; 442 struct sndcard_func *func; 443 444 scp = device_get_softc(bus); 445 resp = &scp->res; 446 447 /* 448 * Look at the function code of the child to determine 449 * the appropriate hander for it. 450 */ 451 func = device_get_ivars(child); 452 if (func == NULL || irq != resp->irq || cookie != scp) 453 return (EINVAL); 454 455 switch (func->func) { 456 case SCF_PCM: 457 scp->pcmintr = NULL; 458 scp->pcmintr_arg = NULL; 459 break; 460 461 case SCF_MIDI: 462 scp->midiintr = NULL; 463 scp->midiintr_arg = NULL; 464 break; 465 466 default: 467 return (EINVAL); 468 } 469 470 return (0); 471} 472 473/* The interrupt handler */ 474static void 475csa_intr(void *arg) 476{ 477 sc_p scp = arg; 478 csa_res *resp; 479 u_int32_t hisr; 480 481 resp = &scp->res; 482 483 /* Is this interrupt for us? */ 484 hisr = csa_readio(resp, BA0_HISR); 485 if ((hisr & 0x7fffffff) == 0) { 486 /* Throw an eoi. */ 487 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 488 return; 489 } 490 491 /* 492 * Pass the value of HISR via struct csa_bridgeinfo. 493 * The children get access through their ivars. 494 */ 495 scp->binfo.hisr = hisr; 496 497 /* Invoke the handlers of the children. */ 498 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 499 scp->pcmintr(scp->pcmintr_arg); 500 hisr &= ~(HISR_VC0 | HISR_VC1); 501 } 502 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 503 scp->midiintr(scp->midiintr_arg); 504 hisr &= ~HISR_MIDI; 505 } 506 507 /* Throw an eoi. */ 508 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 509} 510 511static int 512csa_initialize(sc_p scp) 513{ 514 int i; 515 u_int32_t acsts, acisv; 516 csa_res *resp; 517 518 resp = &scp->res; 519 520 /* 521 * First, blast the clock control register to zero so that the PLL starts 522 * out in a known state, and blast the master serial port control register 523 * to zero so that the serial ports also start out in a known state. 524 */ 525 csa_writeio(resp, BA0_CLKCR1, 0); 526 csa_writeio(resp, BA0_SERMC1, 0); 527 528 /* 529 * If we are in AC97 mode, then we must set the part to a host controlled 530 * AC-link. Otherwise, we won't be able to bring up the link. 531 */ 532#if 1 533 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 534#else 535 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 536#endif /* 1 */ 537 538 /* 539 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 540 * spec) and then drive it high. This is done for non AC97 modes since 541 * there might be logic external to the CS461x that uses the ARST# line 542 * for a reset. 543 */ 544 csa_writeio(resp, BA0_ACCTL, 1); 545 DELAY(50); 546 csa_writeio(resp, BA0_ACCTL, 0); 547 DELAY(50); 548 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 549 550 /* 551 * The first thing we do here is to enable sync generation. As soon 552 * as we start receiving bit clock, we'll start producing the SYNC 553 * signal. 554 */ 555 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 556 557 /* 558 * Now wait for a short while to allow the AC97 part to start 559 * generating bit clock (so we don't try to start the PLL without an 560 * input clock). 561 */ 562 DELAY(50000); 563 564 /* 565 * Set the serial port timing configuration, so that 566 * the clock control circuit gets its clock from the correct place. 567 */ 568 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 569 DELAY(700000); 570 571 /* 572 * Write the selected clock control setup to the hardware. Do not turn on 573 * SWCE yet (if requested), so that the devices clocked by the output of 574 * PLL are not clocked until the PLL is stable. 575 */ 576 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 577 csa_writeio(resp, BA0_PLLM, 0x3a); 578 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 579 580 /* 581 * Power up the PLL. 582 */ 583 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 584 585 /* 586 * Wait until the PLL has stabilized. 587 */ 588 DELAY(5000); 589 590 /* 591 * Turn on clocking of the core so that we can setup the serial ports. 592 */ 593 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 594 595 /* 596 * Fill the serial port FIFOs with silence. 597 */ 598 csa_clearserialfifos(resp); 599 600 /* 601 * Set the serial port FIFO pointer to the first sample in the FIFO. 602 */ 603#if notdef 604 csa_writeio(resp, BA0_SERBSP, 0); 605#endif /* notdef */ 606 607 /* 608 * Write the serial port configuration to the part. The master 609 * enable bit is not set until all other values have been written. 610 */ 611 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 612 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 613 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 614 615 /* 616 * Wait for the codec ready signal from the AC97 codec. 617 */ 618 acsts = 0; 619 for (i = 0 ; i < 1000 ; i++) { 620 /* 621 * First, lets wait a short while to let things settle out a bit, 622 * and to prevent retrying the read too quickly. 623 */ 624 DELAY(125); 625 626 /* 627 * Read the AC97 status register to see if we've seen a CODEC READY 628 * signal from the AC97 codec. 629 */ 630 acsts = csa_readio(resp, BA0_ACSTS); 631 if ((acsts & ACSTS_CRDY) != 0) 632 break; 633 } 634 635 /* 636 * Make sure we sampled CODEC READY. 637 */ 638 if ((acsts & ACSTS_CRDY) == 0) 639 return (ENXIO); 640 641 /* 642 * Assert the vaid frame signal so that we can start sending commands 643 * to the AC97 codec. 644 */ 645 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 646 647 /* 648 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 649 * the codec is pumping ADC data across the AC-link. 650 */ 651 acisv = 0; 652 for (i = 0 ; i < 1000 ; i++) { 653 /* 654 * First, lets wait a short while to let things settle out a bit, 655 * and to prevent retrying the read too quickly. 656 */ 657#if notdef 658 DELAY(10000000L); /* clw */ 659#else 660 DELAY(1000); 661#endif /* notdef */ 662 /* 663 * Read the input slot valid register and see if input slots 3 and 664 * 4 are valid yet. 665 */ 666 acisv = csa_readio(resp, BA0_ACISV); 667 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 668 break; 669 } 670 /* 671 * Make sure we sampled valid input slots 3 and 4. If not, then return 672 * an error. 673 */ 674 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 675 return (ENXIO); 676 677 /* 678 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 679 * commense the transfer of digital audio data to the AC97 codec. 680 */ 681 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 682 683 /* 684 * Power down the DAC and ADC. We will power them up (if) when we need 685 * them. 686 */ 687#if notdef 688 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 689#endif /* notdef */ 690 691 /* 692 * Turn off the Processor by turning off the software clock enable flag in 693 * the clock control register. 694 */ 695#if notdef 696 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 697 csa_writeio(resp, BA0_CLKCR1, clkcr1); 698#endif /* notdef */ 699 700 /* 701 * Enable interrupts on the part. 702 */ 703#if 0 704 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 705#endif /* notdef */ 706 707 return (0); 708} 709 710void 711csa_clearserialfifos(csa_res *resp) 712{ 713 int i, j, pwr; 714 u_int8_t clkcr1, serbst; 715 716 /* 717 * See if the devices are powered down. If so, we must power them up first 718 * or they will not respond. 719 */ 720 pwr = 1; 721 clkcr1 = csa_readio(resp, BA0_CLKCR1); 722 if ((clkcr1 & CLKCR1_SWCE) == 0) { 723 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 724 pwr = 0; 725 } 726 727 /* 728 * We want to clear out the serial port FIFOs so we don't end up playing 729 * whatever random garbage happens to be in them. We fill the sample FIFOs 730 * with zero (silence). 731 */ 732 csa_writeio(resp, BA0_SERBWP, 0); 733 734 /* Fill all 256 sample FIFO locations. */ 735 serbst = 0; 736 for (i = 0 ; i < 256 ; i++) { 737 /* Make sure the previous FIFO write operation has completed. */ 738 for (j = 0 ; j < 5 ; j++) { 739 DELAY(100); 740 serbst = csa_readio(resp, BA0_SERBST); 741 if ((serbst & SERBST_WBSY) == 0) 742 break; 743 } 744 if ((serbst & SERBST_WBSY) != 0) { 745 if (!pwr) 746 csa_writeio(resp, BA0_CLKCR1, clkcr1); 747 } 748 /* Write the serial port FIFO index. */ 749 csa_writeio(resp, BA0_SERBAD, i); 750 /* Tell the serial port to load the new value into the FIFO location. */ 751 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 752 } 753 /* 754 * Now, if we powered up the devices, then power them back down again. 755 * This is kinda ugly, but should never happen. 756 */ 757 if (!pwr) 758 csa_writeio(resp, BA0_CLKCR1, clkcr1); 759} 760 761static void 762csa_resetdsp(csa_res *resp) 763{ 764 int i; 765 766 /* 767 * Write the reset bit of the SP control register. 768 */ 769 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 770 771 /* 772 * Write the control register. 773 */ 774 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 775 776 /* 777 * Clear the trap registers. 778 */ 779 for (i = 0 ; i < 8 ; i++) { 780 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 781 csa_writemem(resp, BA1_TWPR, 0xffff); 782 } 783 csa_writemem(resp, BA1_DREG, 0); 784 785 /* 786 * Set the frame timer to reflect the number of cycles per frame. 787 */ 788 csa_writemem(resp, BA1_FRMT, 0xadf); 789} 790 791static int 792csa_downloadimage(csa_res *resp) 793{ 794 int i; 795 u_int32_t tmp, src, dst, count, data; 796 797 for (i = 0; i < CLEAR__COUNT; i++) { 798 dst = ClrStat[i].BA1__DestByteOffset; 799 count = ClrStat[i].BA1__SourceSize; 800 for (tmp = 0; tmp < count; tmp += 4) 801 csa_writemem(resp, dst + tmp, 0x00000000); 802 } 803 804 for (i = 0; i < FILL__COUNT; i++) { 805 src = 0; 806 dst = FillStat[i].Offset; 807 count = FillStat[i].Size; 808 for (tmp = 0; tmp < count; tmp += 4) { 809 data = FillStat[i].pFill[src]; 810 csa_writemem(resp, dst + tmp, data); 811 src++; 812 } 813 } 814 815 return (0); 816} 817 818int 819csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 820{ 821 int i; 822 u_int32_t acsda, acctl, acsts; 823 824 /* 825 * Make sure that there is not data sitting around from a previous 826 * uncompleted access. ACSDA = Status Data Register = 47Ch 827 */ 828 acsda = csa_readio(resp, BA0_ACSDA); 829 830 /* 831 * Setup the AC97 control registers on the CS461x to send the 832 * appropriate command to the AC97 to perform the read. 833 * ACCAD = Command Address Register = 46Ch 834 * ACCDA = Command Data Register = 470h 835 * ACCTL = Control Register = 460h 836 * set DCV - will clear when process completed 837 * set CRW - Read command 838 * set VFRM - valid frame enabled 839 * set ESYN - ASYNC generation enabled 840 * set RSTN - ARST# inactive, AC97 codec not reset 841 */ 842 843 /* 844 * Get the actual AC97 register from the offset 845 */ 846 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 847 csa_writeio(resp, BA0_ACCDA, 0); 848 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 849 850 /* 851 * Wait for the read to occur. 852 */ 853 acctl = 0; 854 for (i = 0 ; i < 10 ; i++) { 855 /* 856 * First, we want to wait for a short time. 857 */ 858 DELAY(25); 859 860 /* 861 * Now, check to see if the read has completed. 862 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 863 */ 864 acctl = csa_readio(resp, BA0_ACCTL); 865 if ((acctl & ACCTL_DCV) == 0) 866 break; 867 } 868 869 /* 870 * Make sure the read completed. 871 */ 872 if ((acctl & ACCTL_DCV) != 0) 873 return (EAGAIN); 874 875 /* 876 * Wait for the valid status bit to go active. 877 */ 878 acsts = 0; 879 for (i = 0 ; i < 10 ; i++) { 880 /* 881 * Read the AC97 status register. 882 * ACSTS = Status Register = 464h 883 */ 884 acsts = csa_readio(resp, BA0_ACSTS); 885 /* 886 * See if we have valid status. 887 * VSTS - Valid Status 888 */ 889 if ((acsts & ACSTS_VSTS) != 0) 890 break; 891 /* 892 * Wait for a short while. 893 */ 894 DELAY(25); 895 } 896 897 /* 898 * Make sure we got valid status. 899 */ 900 if ((acsts & ACSTS_VSTS) == 0) 901 return (EAGAIN); 902 903 /* 904 * Read the data returned from the AC97 register. 905 * ACSDA = Status Data Register = 474h 906 */ 907 *data = csa_readio(resp, BA0_ACSDA); 908 909 return (0); 910} 911 912int 913csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 914{ 915 int i; 916 u_int32_t acctl; 917 918 /* 919 * Setup the AC97 control registers on the CS461x to send the 920 * appropriate command to the AC97 to perform the write. 921 * ACCAD = Command Address Register = 46Ch 922 * ACCDA = Command Data Register = 470h 923 * ACCTL = Control Register = 460h 924 * set DCV - will clear when process completed 925 * set VFRM - valid frame enabled 926 * set ESYN - ASYNC generation enabled 927 * set RSTN - ARST# inactive, AC97 codec not reset 928 */ 929 930 /* 931 * Get the actual AC97 register from the offset 932 */ 933 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 934 csa_writeio(resp, BA0_ACCDA, data); 935 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 936 937 /* 938 * Wait for the write to occur. 939 */ 940 acctl = 0; 941 for (i = 0 ; i < 10 ; i++) { 942 /* 943 * First, we want to wait for a short time. 944 */ 945 DELAY(25); 946 947 /* 948 * Now, check to see if the read has completed. 949 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 950 */ 951 acctl = csa_readio(resp, BA0_ACCTL); 952 if ((acctl & ACCTL_DCV) == 0) 953 break; 954 } 955 956 /* 957 * Make sure the write completed. 958 */ 959 if ((acctl & ACCTL_DCV) != 0) 960 return (EAGAIN); 961 962 return (0); 963} 964 965u_int32_t 966csa_readio(csa_res *resp, u_long offset) 967{ 968 u_int32_t ul; 969 970 if (offset < BA0_AC97_RESET) 971 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 972 else { 973 if (csa_readcodec(resp, offset, &ul)) 974 ul = 0; 975 return (ul); 976 } 977} 978 979void 980csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 981{ 982 if (offset < BA0_AC97_RESET) 983 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 984 else 985 csa_writecodec(resp, offset, data); 986} 987 988u_int32_t 989csa_readmem(csa_res *resp, u_long offset) 990{ 991 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 992} 993 994void 995csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 996{ 997 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 998} 999 1000static device_method_t csa_methods[] = { 1001 /* Device interface */ 1002 DEVMETHOD(device_probe, csa_probe), 1003 DEVMETHOD(device_attach, csa_attach), 1004 DEVMETHOD(device_detach, csa_detach), 1005 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1006 DEVMETHOD(device_suspend, bus_generic_suspend), 1007 DEVMETHOD(device_resume, bus_generic_resume), 1008 1009 /* Bus interface */ 1010 DEVMETHOD(bus_print_child, bus_generic_print_child), 1011 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1012 DEVMETHOD(bus_release_resource, csa_release_resource), 1013 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1014 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1015 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1016 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1017 1018 { 0, 0 } 1019}; 1020 1021static driver_t csa_driver = { 1022 "csa", 1023 csa_methods, 1024 sizeof(struct csa_softc), 1025}; 1026 1027/* 1028 * csa can be attached to a pci bus. 1029 */ 1030DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1031MODULE_DEPEND(snd_csa, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1032MODULE_VERSION(snd_csa, 1); 1033