csa.c revision 78564
1/* 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/sound/pci/csa.c 78564 2001-06-21 19:45:59Z greid $ 31 */ 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/malloc.h> 38#include <sys/module.h> 39#include <machine/resource.h> 40#include <machine/bus.h> 41#include <sys/rman.h> 42#include <sys/soundcard.h> 43#include <dev/sound/pcm/sound.h> 44#include <dev/sound/chip.h> 45#include <dev/sound/pci/csareg.h> 46#include <dev/sound/pci/csavar.h> 47 48#include <pci/pcireg.h> 49#include <pci/pcivar.h> 50 51#include <gnu/dev/sound/pci/csaimg.h> 52 53/* This is the pci device id. */ 54#define CS4610_PCI_ID 0x60011013 55#define CS4614_PCI_ID 0x60031013 56#define CS4615_PCI_ID 0x60041013 57#define CS4281_PCI_ID 0x60051013 58 59/* Here is the parameter structure per a device. */ 60struct csa_softc { 61 device_t dev; /* device */ 62 csa_res res; /* resources */ 63 64 device_t pcm; /* pcm device */ 65 driver_intr_t* pcmintr; /* pcm intr */ 66 void *pcmintr_arg; /* pcm intr arg */ 67 device_t midi; /* midi device */ 68 driver_intr_t* midiintr; /* midi intr */ 69 void *midiintr_arg; /* midi intr arg */ 70 void *ih; /* cookie */ 71 72 struct csa_card *card; 73 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 74}; 75 76typedef struct csa_softc *sc_p; 77 78static int csa_probe(device_t dev); 79static int csa_attach(device_t dev); 80static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 81 u_long start, u_long end, u_long count, u_int flags); 82static int csa_release_resource(device_t bus, device_t child, int type, int rid, 83 struct resource *r); 84static int csa_setup_intr(device_t bus, device_t child, 85 struct resource *irq, int flags, 86 driver_intr_t *intr, void *arg, void **cookiep); 87static int csa_teardown_intr(device_t bus, device_t child, 88 struct resource *irq, void *cookie); 89static driver_intr_t csa_intr; 90static int csa_initialize(sc_p scp); 91static void csa_resetdsp(csa_res *resp); 92static int csa_downloadimage(csa_res *resp); 93 94static devclass_t csa_devclass; 95 96static void 97amp_none(void) 98{ 99} 100 101static void 102amp_voyetra(void) 103{ 104} 105 106static int 107clkrun_hack(int run) 108{ 109#ifdef __i386__ 110 devclass_t pci_devclass; 111 device_t *pci_devices, *pci_children, *busp, *childp; 112 int pci_count = 0, pci_childcount = 0; 113 int i, j, port; 114 u_int16_t control; 115 bus_space_tag_t btag; 116 117 if ((pci_devclass = devclass_find("pci")) == NULL) { 118 return ENXIO; 119 } 120 121 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 122 123 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 124 pci_childcount = 0; 125 device_get_children(*busp, &pci_children, &pci_childcount); 126 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 127 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 128 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 129 /* XXX */ 130 btag = I386_BUS_SPACE_IO; 131 132 control = bus_space_read_2(btag, 0x0, port); 133 control &= ~0x2000; 134 control |= run? 0 : 0x2000; 135 bus_space_write_2(btag, 0x0, port, control); 136 free(pci_devices, M_TEMP); 137 free(pci_children, M_TEMP); 138 return 0; 139 } 140 } 141 free(pci_children, M_TEMP); 142 } 143 144 free(pci_devices, M_TEMP); 145 return ENXIO; 146#else 147 return 0; 148#endif 149} 150 151static struct csa_card cards_4610[] = { 152 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL }, 153}; 154 155static struct csa_card cards_4614[] = { 156 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL}, 157 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL}, 158 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL}, 159 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL}, 160 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL}, 161 /* Not sure if the 570 needs the clkrun hack */ 162 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, clkrun_hack}, 163 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack}, 164 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL}, 165 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL }, 166}; 167 168static struct csa_card cards_4615[] = { 169 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL }, 170}; 171 172static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL }; 173 174struct card_type { 175 u_int32_t devid; 176 char *name; 177 struct csa_card *cards; 178}; 179 180static struct card_type cards[] = { 181 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 182 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 183 {CS4615_PCI_ID, "CS4615", cards_4615}, 184 {0, NULL, NULL}, 185}; 186 187static struct card_type * 188csa_findcard(device_t dev) 189{ 190 int i; 191 192 i = 0; 193 while (cards[i].devid != 0) { 194 if (pci_get_devid(dev) == cards[i].devid) 195 return &cards[i]; 196 i++; 197 } 198 return NULL; 199} 200 201struct csa_card * 202csa_findsubcard(device_t dev) 203{ 204 int i; 205 struct card_type *card; 206 struct csa_card *subcard; 207 208 card = csa_findcard(dev); 209 if (card == NULL) 210 return &nocard; 211 subcard = card->cards; 212 i = 0; 213 while (subcard[i].subvendor != 0) { 214 if (pci_get_subvendor(dev) == subcard[i].subvendor 215 && pci_get_subdevice(dev) == subcard[i].subdevice) { 216 return &subcard[i]; 217 } 218 i++; 219 } 220 return &subcard[i]; 221} 222 223static int 224csa_probe(device_t dev) 225{ 226 struct card_type *card; 227 228 card = csa_findcard(dev); 229 if (card) { 230 device_set_desc(dev, card->name); 231 return 0; 232 } 233 return ENXIO; 234} 235 236static int 237csa_attach(device_t dev) 238{ 239 u_int32_t stcmd; 240 sc_p scp; 241 csa_res *resp; 242 struct sndcard_func *func; 243 int error = ENXIO; 244 245 scp = device_get_softc(dev); 246 247 /* Fill in the softc. */ 248 bzero(scp, sizeof(*scp)); 249 scp->dev = dev; 250 251 /* Wake up the device. */ 252 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 253 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 254 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 255 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 256 } 257 258 /* Allocate the resources. */ 259 resp = &scp->res; 260 scp->card = csa_findsubcard(dev); 261 scp->binfo.card = scp->card; 262 printf("csa: card is %s\n", scp->card->name); 263 resp->io_rid = PCIR_MAPS; 264 resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, 1, RF_ACTIVE); 265 if (resp->io == NULL) 266 return (ENXIO); 267 resp->mem_rid = PCIR_MAPS + 4; 268 resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, 1, RF_ACTIVE); 269 if (resp->mem == NULL) 270 goto err_io; 271 resp->irq_rid = 0; 272 resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 273 if (resp->irq == NULL) 274 goto err_mem; 275 276 /* Enable interrupt. */ 277 if (snd_setup_intr(dev, resp->irq, INTR_MPSAFE, csa_intr, scp, &scp->ih)) 278 goto err_intr; 279#if 0 280 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 281 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 282#endif 283 284 /* Initialize the chip. */ 285 if (csa_initialize(scp)) 286 goto err_teardown; 287 288 /* Reset the Processor. */ 289 csa_resetdsp(resp); 290 291 /* Download the Processor Image to the processor. */ 292 if (csa_downloadimage(resp)) 293 goto err_teardown; 294 295 /* Attach the children. */ 296 297 /* PCM Audio */ 298 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 299 if (func == NULL) { 300 error = ENOMEM; 301 goto err_teardown; 302 } 303 func->varinfo = &scp->binfo; 304 func->func = SCF_PCM; 305 scp->pcm = device_add_child(dev, "pcm", -1); 306 device_set_ivars(scp->pcm, func); 307 308 /* Midi Interface */ 309 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 310 if (func == NULL) { 311 error = ENOMEM; 312 goto err_teardown; 313 } 314 func->varinfo = &scp->binfo; 315 func->func = SCF_MIDI; 316 scp->midi = device_add_child(dev, "midi", -1); 317 device_set_ivars(scp->midi, func); 318 319 bus_generic_attach(dev); 320 321 return (0); 322 323err_teardown: 324 bus_teardown_intr(dev, resp->irq, scp->ih); 325err_intr: 326 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 327err_mem: 328 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 329err_io: 330 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 331 return (error); 332} 333 334static int 335csa_detach(device_t dev) 336{ 337 sc_p scp; 338 339 scp = device_get_softc(dev); 340 device_delete_child(dev, scp->midi); 341 device_delete_child(dev, scp->pcm); 342 return bus_generic_detach(dev); 343} 344 345static struct resource * 346csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 347 u_long start, u_long end, u_long count, u_int flags) 348{ 349 sc_p scp; 350 csa_res *resp; 351 struct resource *res; 352 353 scp = device_get_softc(bus); 354 resp = &scp->res; 355 switch (type) { 356 case SYS_RES_IRQ: 357 if (*rid != 0) 358 return (NULL); 359 res = resp->irq; 360 break; 361 case SYS_RES_MEMORY: 362 switch (*rid) { 363 case PCIR_MAPS: 364 res = resp->io; 365 break; 366 case PCIR_MAPS + 4: 367 res = resp->mem; 368 break; 369 default: 370 return (NULL); 371 } 372 break; 373 default: 374 return (NULL); 375 } 376 377 return res; 378} 379 380static int 381csa_release_resource(device_t bus, device_t child, int type, int rid, 382 struct resource *r) 383{ 384 return (0); 385} 386 387/* 388 * The following three functions deal with interrupt handling. 389 * An interrupt is primarily handled by the bridge driver. 390 * The bridge driver then determines the child devices to pass 391 * the interrupt. Certain information of the device can be read 392 * only once(eg the value of HISR). The bridge driver is responsible 393 * to pass such the information to the children. 394 */ 395 396static int 397csa_setup_intr(device_t bus, device_t child, 398 struct resource *irq, int flags, 399 driver_intr_t *intr, void *arg, void **cookiep) 400{ 401 sc_p scp; 402 csa_res *resp; 403 struct sndcard_func *func; 404 405 scp = device_get_softc(bus); 406 resp = &scp->res; 407 408 /* 409 * Look at the function code of the child to determine 410 * the appropriate hander for it. 411 */ 412 func = device_get_ivars(child); 413 if (func == NULL || irq != resp->irq) 414 return (EINVAL); 415 416 switch (func->func) { 417 case SCF_PCM: 418 scp->pcmintr = intr; 419 scp->pcmintr_arg = arg; 420 break; 421 422 case SCF_MIDI: 423 scp->midiintr = intr; 424 scp->midiintr_arg = arg; 425 break; 426 427 default: 428 return (EINVAL); 429 } 430 *cookiep = scp; 431 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 432 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 433 434 return (0); 435} 436 437static int 438csa_teardown_intr(device_t bus, device_t child, 439 struct resource *irq, void *cookie) 440{ 441 sc_p scp; 442 csa_res *resp; 443 struct sndcard_func *func; 444 445 scp = device_get_softc(bus); 446 resp = &scp->res; 447 448 /* 449 * Look at the function code of the child to determine 450 * the appropriate hander for it. 451 */ 452 func = device_get_ivars(child); 453 if (func == NULL || irq != resp->irq || cookie != scp) 454 return (EINVAL); 455 456 switch (func->func) { 457 case SCF_PCM: 458 scp->pcmintr = NULL; 459 scp->pcmintr_arg = NULL; 460 break; 461 462 case SCF_MIDI: 463 scp->midiintr = NULL; 464 scp->midiintr_arg = NULL; 465 break; 466 467 default: 468 return (EINVAL); 469 } 470 471 return (0); 472} 473 474/* The interrupt handler */ 475static void 476csa_intr(void *arg) 477{ 478 sc_p scp = arg; 479 csa_res *resp; 480 u_int32_t hisr; 481 482 resp = &scp->res; 483 484 /* Is this interrupt for us? */ 485 hisr = csa_readio(resp, BA0_HISR); 486 if ((hisr & 0x7fffffff) == 0) { 487 /* Throw an eoi. */ 488 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 489 return; 490 } 491 492 /* 493 * Pass the value of HISR via struct csa_bridgeinfo. 494 * The children get access through their ivars. 495 */ 496 scp->binfo.hisr = hisr; 497 498 /* Invoke the handlers of the children. */ 499 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 500 scp->pcmintr(scp->pcmintr_arg); 501 hisr &= ~(HISR_VC0 | HISR_VC1); 502 } 503 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 504 scp->midiintr(scp->midiintr_arg); 505 hisr &= ~HISR_MIDI; 506 } 507 508 /* Throw an eoi. */ 509 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 510} 511 512static int 513csa_initialize(sc_p scp) 514{ 515 int i; 516 u_int32_t acsts, acisv; 517 csa_res *resp; 518 519 resp = &scp->res; 520 521 /* 522 * First, blast the clock control register to zero so that the PLL starts 523 * out in a known state, and blast the master serial port control register 524 * to zero so that the serial ports also start out in a known state. 525 */ 526 csa_writeio(resp, BA0_CLKCR1, 0); 527 csa_writeio(resp, BA0_SERMC1, 0); 528 529 /* 530 * If we are in AC97 mode, then we must set the part to a host controlled 531 * AC-link. Otherwise, we won't be able to bring up the link. 532 */ 533#if 1 534 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 535#else 536 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 537#endif /* 1 */ 538 539 /* 540 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 541 * spec) and then drive it high. This is done for non AC97 modes since 542 * there might be logic external to the CS461x that uses the ARST# line 543 * for a reset. 544 */ 545 csa_writeio(resp, BA0_ACCTL, 1); 546 DELAY(50); 547 csa_writeio(resp, BA0_ACCTL, 0); 548 DELAY(50); 549 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 550 551 /* 552 * The first thing we do here is to enable sync generation. As soon 553 * as we start receiving bit clock, we'll start producing the SYNC 554 * signal. 555 */ 556 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 557 558 /* 559 * Now wait for a short while to allow the AC97 part to start 560 * generating bit clock (so we don't try to start the PLL without an 561 * input clock). 562 */ 563 DELAY(50000); 564 565 /* 566 * Set the serial port timing configuration, so that 567 * the clock control circuit gets its clock from the correct place. 568 */ 569 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 570 DELAY(700000); 571 572 /* 573 * Write the selected clock control setup to the hardware. Do not turn on 574 * SWCE yet (if requested), so that the devices clocked by the output of 575 * PLL are not clocked until the PLL is stable. 576 */ 577 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 578 csa_writeio(resp, BA0_PLLM, 0x3a); 579 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 580 581 /* 582 * Power up the PLL. 583 */ 584 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 585 586 /* 587 * Wait until the PLL has stabilized. 588 */ 589 DELAY(5000); 590 591 /* 592 * Turn on clocking of the core so that we can setup the serial ports. 593 */ 594 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 595 596 /* 597 * Fill the serial port FIFOs with silence. 598 */ 599 csa_clearserialfifos(resp); 600 601 /* 602 * Set the serial port FIFO pointer to the first sample in the FIFO. 603 */ 604#if notdef 605 csa_writeio(resp, BA0_SERBSP, 0); 606#endif /* notdef */ 607 608 /* 609 * Write the serial port configuration to the part. The master 610 * enable bit is not set until all other values have been written. 611 */ 612 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 613 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 614 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 615 616 /* 617 * Wait for the codec ready signal from the AC97 codec. 618 */ 619 acsts = 0; 620 for (i = 0 ; i < 1000 ; i++) { 621 /* 622 * First, lets wait a short while to let things settle out a bit, 623 * and to prevent retrying the read too quickly. 624 */ 625 DELAY(125); 626 627 /* 628 * Read the AC97 status register to see if we've seen a CODEC READY 629 * signal from the AC97 codec. 630 */ 631 acsts = csa_readio(resp, BA0_ACSTS); 632 if ((acsts & ACSTS_CRDY) != 0) 633 break; 634 } 635 636 /* 637 * Make sure we sampled CODEC READY. 638 */ 639 if ((acsts & ACSTS_CRDY) == 0) 640 return (ENXIO); 641 642 /* 643 * Assert the vaid frame signal so that we can start sending commands 644 * to the AC97 codec. 645 */ 646 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 647 648 /* 649 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 650 * the codec is pumping ADC data across the AC-link. 651 */ 652 acisv = 0; 653 for (i = 0 ; i < 1000 ; i++) { 654 /* 655 * First, lets wait a short while to let things settle out a bit, 656 * and to prevent retrying the read too quickly. 657 */ 658#if notdef 659 DELAY(10000000L); /* clw */ 660#else 661 DELAY(1000); 662#endif /* notdef */ 663 /* 664 * Read the input slot valid register and see if input slots 3 and 665 * 4 are valid yet. 666 */ 667 acisv = csa_readio(resp, BA0_ACISV); 668 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 669 break; 670 } 671 /* 672 * Make sure we sampled valid input slots 3 and 4. If not, then return 673 * an error. 674 */ 675 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 676 return (ENXIO); 677 678 /* 679 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 680 * commense the transfer of digital audio data to the AC97 codec. 681 */ 682 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 683 684 /* 685 * Power down the DAC and ADC. We will power them up (if) when we need 686 * them. 687 */ 688#if notdef 689 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 690#endif /* notdef */ 691 692 /* 693 * Turn off the Processor by turning off the software clock enable flag in 694 * the clock control register. 695 */ 696#if notdef 697 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 698 csa_writeio(resp, BA0_CLKCR1, clkcr1); 699#endif /* notdef */ 700 701 /* 702 * Enable interrupts on the part. 703 */ 704#if 0 705 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 706#endif /* notdef */ 707 708 return (0); 709} 710 711void 712csa_clearserialfifos(csa_res *resp) 713{ 714 int i, j, pwr; 715 u_int8_t clkcr1, serbst; 716 717 /* 718 * See if the devices are powered down. If so, we must power them up first 719 * or they will not respond. 720 */ 721 pwr = 1; 722 clkcr1 = csa_readio(resp, BA0_CLKCR1); 723 if ((clkcr1 & CLKCR1_SWCE) == 0) { 724 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 725 pwr = 0; 726 } 727 728 /* 729 * We want to clear out the serial port FIFOs so we don't end up playing 730 * whatever random garbage happens to be in them. We fill the sample FIFOs 731 * with zero (silence). 732 */ 733 csa_writeio(resp, BA0_SERBWP, 0); 734 735 /* Fill all 256 sample FIFO locations. */ 736 serbst = 0; 737 for (i = 0 ; i < 256 ; i++) { 738 /* Make sure the previous FIFO write operation has completed. */ 739 for (j = 0 ; j < 5 ; j++) { 740 DELAY(100); 741 serbst = csa_readio(resp, BA0_SERBST); 742 if ((serbst & SERBST_WBSY) == 0) 743 break; 744 } 745 if ((serbst & SERBST_WBSY) != 0) { 746 if (!pwr) 747 csa_writeio(resp, BA0_CLKCR1, clkcr1); 748 } 749 /* Write the serial port FIFO index. */ 750 csa_writeio(resp, BA0_SERBAD, i); 751 /* Tell the serial port to load the new value into the FIFO location. */ 752 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 753 } 754 /* 755 * Now, if we powered up the devices, then power them back down again. 756 * This is kinda ugly, but should never happen. 757 */ 758 if (!pwr) 759 csa_writeio(resp, BA0_CLKCR1, clkcr1); 760} 761 762static void 763csa_resetdsp(csa_res *resp) 764{ 765 int i; 766 767 /* 768 * Write the reset bit of the SP control register. 769 */ 770 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 771 772 /* 773 * Write the control register. 774 */ 775 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 776 777 /* 778 * Clear the trap registers. 779 */ 780 for (i = 0 ; i < 8 ; i++) { 781 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 782 csa_writemem(resp, BA1_TWPR, 0xffff); 783 } 784 csa_writemem(resp, BA1_DREG, 0); 785 786 /* 787 * Set the frame timer to reflect the number of cycles per frame. 788 */ 789 csa_writemem(resp, BA1_FRMT, 0xadf); 790} 791 792static int 793csa_downloadimage(csa_res *resp) 794{ 795 int i; 796 u_int32_t tmp, src, dst, count, data; 797 798 for (i = 0; i < CLEAR__COUNT; i++) { 799 dst = ClrStat[i].BA1__DestByteOffset; 800 count = ClrStat[i].BA1__SourceSize; 801 for (tmp = 0; tmp < count; tmp += 4) 802 csa_writemem(resp, dst + tmp, 0x00000000); 803 } 804 805 for (i = 0; i < FILL__COUNT; i++) { 806 src = 0; 807 dst = FillStat[i].Offset; 808 count = FillStat[i].Size; 809 for (tmp = 0; tmp < count; tmp += 4) { 810 data = FillStat[i].pFill[src]; 811 csa_writemem(resp, dst + tmp, data); 812 src++; 813 } 814 } 815 816 return (0); 817} 818 819int 820csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 821{ 822 int i; 823 u_int32_t acsda, acctl, acsts; 824 825 /* 826 * Make sure that there is not data sitting around from a previous 827 * uncompleted access. ACSDA = Status Data Register = 47Ch 828 */ 829 acsda = csa_readio(resp, BA0_ACSDA); 830 831 /* 832 * Setup the AC97 control registers on the CS461x to send the 833 * appropriate command to the AC97 to perform the read. 834 * ACCAD = Command Address Register = 46Ch 835 * ACCDA = Command Data Register = 470h 836 * ACCTL = Control Register = 460h 837 * set DCV - will clear when process completed 838 * set CRW - Read command 839 * set VFRM - valid frame enabled 840 * set ESYN - ASYNC generation enabled 841 * set RSTN - ARST# inactive, AC97 codec not reset 842 */ 843 844 /* 845 * Get the actual AC97 register from the offset 846 */ 847 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 848 csa_writeio(resp, BA0_ACCDA, 0); 849 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 850 851 /* 852 * Wait for the read to occur. 853 */ 854 acctl = 0; 855 for (i = 0 ; i < 10 ; i++) { 856 /* 857 * First, we want to wait for a short time. 858 */ 859 DELAY(25); 860 861 /* 862 * Now, check to see if the read has completed. 863 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 864 */ 865 acctl = csa_readio(resp, BA0_ACCTL); 866 if ((acctl & ACCTL_DCV) == 0) 867 break; 868 } 869 870 /* 871 * Make sure the read completed. 872 */ 873 if ((acctl & ACCTL_DCV) != 0) 874 return (EAGAIN); 875 876 /* 877 * Wait for the valid status bit to go active. 878 */ 879 acsts = 0; 880 for (i = 0 ; i < 10 ; i++) { 881 /* 882 * Read the AC97 status register. 883 * ACSTS = Status Register = 464h 884 */ 885 acsts = csa_readio(resp, BA0_ACSTS); 886 /* 887 * See if we have valid status. 888 * VSTS - Valid Status 889 */ 890 if ((acsts & ACSTS_VSTS) != 0) 891 break; 892 /* 893 * Wait for a short while. 894 */ 895 DELAY(25); 896 } 897 898 /* 899 * Make sure we got valid status. 900 */ 901 if ((acsts & ACSTS_VSTS) == 0) 902 return (EAGAIN); 903 904 /* 905 * Read the data returned from the AC97 register. 906 * ACSDA = Status Data Register = 474h 907 */ 908 *data = csa_readio(resp, BA0_ACSDA); 909 910 return (0); 911} 912 913int 914csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 915{ 916 int i; 917 u_int32_t acctl; 918 919 /* 920 * Setup the AC97 control registers on the CS461x to send the 921 * appropriate command to the AC97 to perform the write. 922 * ACCAD = Command Address Register = 46Ch 923 * ACCDA = Command Data Register = 470h 924 * ACCTL = Control Register = 460h 925 * set DCV - will clear when process completed 926 * set VFRM - valid frame enabled 927 * set ESYN - ASYNC generation enabled 928 * set RSTN - ARST# inactive, AC97 codec not reset 929 */ 930 931 /* 932 * Get the actual AC97 register from the offset 933 */ 934 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 935 csa_writeio(resp, BA0_ACCDA, data); 936 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 937 938 /* 939 * Wait for the write to occur. 940 */ 941 acctl = 0; 942 for (i = 0 ; i < 10 ; i++) { 943 /* 944 * First, we want to wait for a short time. 945 */ 946 DELAY(25); 947 948 /* 949 * Now, check to see if the read has completed. 950 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 951 */ 952 acctl = csa_readio(resp, BA0_ACCTL); 953 if ((acctl & ACCTL_DCV) == 0) 954 break; 955 } 956 957 /* 958 * Make sure the write completed. 959 */ 960 if ((acctl & ACCTL_DCV) != 0) 961 return (EAGAIN); 962 963 return (0); 964} 965 966u_int32_t 967csa_readio(csa_res *resp, u_long offset) 968{ 969 u_int32_t ul; 970 971 if (offset < BA0_AC97_RESET) 972 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 973 else { 974 if (csa_readcodec(resp, offset, &ul)) 975 ul = 0; 976 return (ul); 977 } 978} 979 980void 981csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 982{ 983 if (offset < BA0_AC97_RESET) 984 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 985 else 986 csa_writecodec(resp, offset, data); 987} 988 989u_int32_t 990csa_readmem(csa_res *resp, u_long offset) 991{ 992 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 993} 994 995void 996csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 997{ 998 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 999} 1000 1001static device_method_t csa_methods[] = { 1002 /* Device interface */ 1003 DEVMETHOD(device_probe, csa_probe), 1004 DEVMETHOD(device_attach, csa_attach), 1005 DEVMETHOD(device_detach, csa_detach), 1006 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1007 DEVMETHOD(device_suspend, bus_generic_suspend), 1008 DEVMETHOD(device_resume, bus_generic_resume), 1009 1010 /* Bus interface */ 1011 DEVMETHOD(bus_print_child, bus_generic_print_child), 1012 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1013 DEVMETHOD(bus_release_resource, csa_release_resource), 1014 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1015 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1016 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1017 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1018 1019 { 0, 0 } 1020}; 1021 1022static driver_t csa_driver = { 1023 "csa", 1024 csa_methods, 1025 sizeof(struct csa_softc), 1026}; 1027 1028/* 1029 * csa can be attached to a pci bus. 1030 */ 1031DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1032MODULE_DEPEND(snd_csa, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1033MODULE_VERSION(snd_csa, 1); 1034