csa.c revision 78032
1/* 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/sound/pci/csa.c 78032 2001-06-11 00:29:25Z cg $ 31 */ 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/malloc.h> 38#include <sys/module.h> 39#include <machine/resource.h> 40#include <machine/bus.h> 41#include <sys/rman.h> 42#include <sys/soundcard.h> 43#include <dev/sound/pcm/sound.h> 44#include <dev/sound/chip.h> 45#include <dev/sound/pci/csareg.h> 46#include <dev/sound/pci/csavar.h> 47 48#include <pci/pcireg.h> 49#include <pci/pcivar.h> 50 51#include <gnu/dev/sound/pci/csaimg.h> 52 53/* This is the pci device id. */ 54#define CS4610_PCI_ID 0x60011013 55#define CS4614_PCI_ID 0x60031013 56#define CS4615_PCI_ID 0x60041013 57#define CS4281_PCI_ID 0x60051013 58 59/* Here is the parameter structure per a device. */ 60struct csa_softc { 61 device_t dev; /* device */ 62 csa_res res; /* resources */ 63 64 device_t pcm; /* pcm device */ 65 driver_intr_t* pcmintr; /* pcm intr */ 66 void *pcmintr_arg; /* pcm intr arg */ 67 device_t midi; /* midi device */ 68 driver_intr_t* midiintr; /* midi intr */ 69 void *midiintr_arg; /* midi intr arg */ 70 void *ih; /* cookie */ 71 72 struct csa_card *card; 73 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 74}; 75 76typedef struct csa_softc *sc_p; 77 78static int csa_probe(device_t dev); 79static int csa_attach(device_t dev); 80static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 81 u_long start, u_long end, u_long count, u_int flags); 82static int csa_release_resource(device_t bus, device_t child, int type, int rid, 83 struct resource *r); 84static int csa_setup_intr(device_t bus, device_t child, 85 struct resource *irq, int flags, 86 driver_intr_t *intr, void *arg, void **cookiep); 87static int csa_teardown_intr(device_t bus, device_t child, 88 struct resource *irq, void *cookie); 89static driver_intr_t csa_intr; 90static int csa_initialize(sc_p scp); 91static void csa_resetdsp(csa_res *resp); 92static int csa_downloadimage(csa_res *resp); 93 94static devclass_t csa_devclass; 95 96static void 97amp_none(void) 98{ 99} 100 101static void 102amp_voyetra(void) 103{ 104} 105 106static int 107clkrun_hack(int run) 108{ 109#ifdef __i386__ 110 devclass_t pci_devclass; 111 device_t *pci_devices, *pci_children, *busp, *childp; 112 int pci_count = 0, pci_childcount = 0; 113 int i, j, port; 114 u_int16_t control; 115 bus_space_tag_t btag; 116 117 if ((pci_devclass = devclass_find("pci")) == NULL) { 118 return ENXIO; 119 } 120 121 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 122 123 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 124 pci_childcount = 0; 125 device_get_children(*busp, &pci_children, &pci_childcount); 126 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 127 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 128 free(pci_devices, M_TEMP); 129 free(pci_children, M_TEMP); 130 131 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 132 /* XXX */ 133 btag = I386_BUS_SPACE_IO; 134 135 control = bus_space_read_2(btag, 0x0, port); 136 control &= ~0x2000; 137 control |= run? 0 : 0x2000; 138 bus_space_write_2(btag, 0x0, port, control); 139 return 0; 140 } 141 } 142 } 143 144 free(pci_devices, M_TEMP); 145 free(pci_children, M_TEMP); 146 return ENXIO; 147#else 148 return 0; 149#endif 150} 151 152static struct csa_card cards_4610[] = { 153 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL }, 154}; 155 156static struct csa_card cards_4614[] = { 157 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL}, 158 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL}, 159 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL}, 160 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL}, 161 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL}, 162 /* Not sure if the 570 needs the clkrun hack */ 163 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, clkrun_hack}, 164 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack}, 165 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL}, 166 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL }, 167}; 168 169static struct csa_card cards_4615[] = { 170 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL }, 171}; 172 173static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL }; 174 175struct card_type { 176 u_int32_t devid; 177 char *name; 178 struct csa_card *cards; 179}; 180 181static struct card_type cards[] = { 182 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 183 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 184 {CS4615_PCI_ID, "CS4615", cards_4615}, 185 {0, NULL, NULL}, 186}; 187 188static struct card_type * 189csa_findcard(device_t dev) 190{ 191 int i; 192 193 i = 0; 194 while (cards[i].devid != 0) { 195 if (pci_get_devid(dev) == cards[i].devid) 196 return &cards[i]; 197 i++; 198 } 199 return NULL; 200} 201 202struct csa_card * 203csa_findsubcard(device_t dev) 204{ 205 int i; 206 struct card_type *card; 207 struct csa_card *subcard; 208 209 card = csa_findcard(dev); 210 if (card == NULL) 211 return &nocard; 212 subcard = card->cards; 213 i = 0; 214 while (subcard[i].subvendor != 0) { 215 if (pci_get_subvendor(dev) == subcard[i].subvendor 216 && pci_get_subdevice(dev) == subcard[i].subdevice) { 217 return &subcard[i]; 218 } 219 i++; 220 } 221 return &subcard[i]; 222} 223 224static int 225csa_probe(device_t dev) 226{ 227 struct card_type *card; 228 229 card = csa_findcard(dev); 230 if (card) { 231 device_set_desc(dev, card->name); 232 return 0; 233 } 234 return ENXIO; 235} 236 237static int 238csa_attach(device_t dev) 239{ 240 u_int32_t stcmd; 241 sc_p scp; 242 csa_res *resp; 243 struct sndcard_func *func; 244 245 scp = device_get_softc(dev); 246 247 /* Fill in the softc. */ 248 bzero(scp, sizeof(*scp)); 249 scp->dev = dev; 250 251 /* Wake up the device. */ 252 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 253 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 254 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 255 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 256 } 257 258 /* Allocate the resources. */ 259 resp = &scp->res; 260 scp->card = csa_findsubcard(dev); 261 scp->binfo.card = scp->card; 262 printf("csa: card is %s\n", scp->card->name); 263 resp->io_rid = PCIR_MAPS; 264 resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, 1, RF_ACTIVE); 265 if (resp->io == NULL) 266 return (ENXIO); 267 resp->mem_rid = PCIR_MAPS + 4; 268 resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, 1, RF_ACTIVE); 269 if (resp->mem == NULL) { 270 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 271 return (ENXIO); 272 } 273 resp->irq_rid = 0; 274 resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 275 if (resp->irq == NULL) { 276 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 277 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 278 return (ENXIO); 279 } 280 281 /* Enable interrupt. */ 282 if (snd_setup_intr(dev, resp->irq, INTR_MPSAFE, csa_intr, scp, &scp->ih)) { 283 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 284 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 285 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 286 return (ENXIO); 287 } 288#if 0 289 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 290 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 291#endif 292 293 /* Initialize the chip. */ 294 if (csa_initialize(scp)) { 295 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 296 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 297 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 298 return (ENXIO); 299 } 300 301 /* Reset the Processor. */ 302 csa_resetdsp(resp); 303 304 /* Download the Processor Image to the processor. */ 305 if (csa_downloadimage(resp)) { 306 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 307 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 308 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 309 return (ENXIO); 310 } 311 312 /* Attach the children. */ 313 314 /* PCM Audio */ 315 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT); 316 if (func == NULL) 317 return (ENOMEM); 318 bzero(func, sizeof(*func)); 319 func->varinfo = &scp->binfo; 320 func->func = SCF_PCM; 321 scp->pcm = device_add_child(dev, "pcm", -1); 322 device_set_ivars(scp->pcm, func); 323 324 /* Midi Interface */ 325 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT); 326 if (func == NULL) 327 return (ENOMEM); 328 bzero(func, sizeof(*func)); 329 func->varinfo = &scp->binfo; 330 func->func = SCF_MIDI; 331 scp->midi = device_add_child(dev, "midi", -1); 332 device_set_ivars(scp->midi, func); 333 334 bus_generic_attach(dev); 335 336 return (0); 337} 338 339static int 340csa_detach(device_t dev) 341{ 342 sc_p scp; 343 344 scp = device_get_softc(dev); 345 device_delete_child(dev, scp->midi); 346 device_delete_child(dev, scp->pcm); 347 return bus_generic_detach(dev); 348} 349 350static struct resource * 351csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 352 u_long start, u_long end, u_long count, u_int flags) 353{ 354 sc_p scp; 355 csa_res *resp; 356 struct resource *res; 357 358 scp = device_get_softc(bus); 359 resp = &scp->res; 360 switch (type) { 361 case SYS_RES_IRQ: 362 if (*rid != 0) 363 return (NULL); 364 res = resp->irq; 365 break; 366 case SYS_RES_MEMORY: 367 switch (*rid) { 368 case PCIR_MAPS: 369 res = resp->io; 370 break; 371 case PCIR_MAPS + 4: 372 res = resp->mem; 373 break; 374 default: 375 return (NULL); 376 } 377 break; 378 default: 379 return (NULL); 380 } 381 382 return res; 383} 384 385static int 386csa_release_resource(device_t bus, device_t child, int type, int rid, 387 struct resource *r) 388{ 389 return (0); 390} 391 392/* 393 * The following three functions deal with interrupt handling. 394 * An interrupt is primarily handled by the bridge driver. 395 * The bridge driver then determines the child devices to pass 396 * the interrupt. Certain information of the device can be read 397 * only once(eg the value of HISR). The bridge driver is responsible 398 * to pass such the information to the children. 399 */ 400 401static int 402csa_setup_intr(device_t bus, device_t child, 403 struct resource *irq, int flags, 404 driver_intr_t *intr, void *arg, void **cookiep) 405{ 406 sc_p scp; 407 csa_res *resp; 408 struct sndcard_func *func; 409 410 scp = device_get_softc(bus); 411 resp = &scp->res; 412 413 /* 414 * Look at the function code of the child to determine 415 * the appropriate hander for it. 416 */ 417 func = device_get_ivars(child); 418 if (func == NULL || irq != resp->irq) 419 return (EINVAL); 420 421 switch (func->func) { 422 case SCF_PCM: 423 scp->pcmintr = intr; 424 scp->pcmintr_arg = arg; 425 break; 426 427 case SCF_MIDI: 428 scp->midiintr = intr; 429 scp->midiintr_arg = arg; 430 break; 431 432 default: 433 return (EINVAL); 434 } 435 *cookiep = scp; 436 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 437 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 438 439 return (0); 440} 441 442static int 443csa_teardown_intr(device_t bus, device_t child, 444 struct resource *irq, void *cookie) 445{ 446 sc_p scp; 447 csa_res *resp; 448 struct sndcard_func *func; 449 450 scp = device_get_softc(bus); 451 resp = &scp->res; 452 453 /* 454 * Look at the function code of the child to determine 455 * the appropriate hander for it. 456 */ 457 func = device_get_ivars(child); 458 if (func == NULL || irq != resp->irq || cookie != scp) 459 return (EINVAL); 460 461 switch (func->func) { 462 case SCF_PCM: 463 scp->pcmintr = NULL; 464 scp->pcmintr_arg = NULL; 465 break; 466 467 case SCF_MIDI: 468 scp->midiintr = NULL; 469 scp->midiintr_arg = NULL; 470 break; 471 472 default: 473 return (EINVAL); 474 } 475 476 return (0); 477} 478 479/* The interrupt handler */ 480static void 481csa_intr(void *arg) 482{ 483 sc_p scp = arg; 484 csa_res *resp; 485 u_int32_t hisr; 486 487 resp = &scp->res; 488 489 /* Is this interrupt for us? */ 490 hisr = csa_readio(resp, BA0_HISR); 491 if ((hisr & 0x7fffffff) == 0) { 492 /* Throw an eoi. */ 493 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 494 return; 495 } 496 497 /* 498 * Pass the value of HISR via struct csa_bridgeinfo. 499 * The children get access through their ivars. 500 */ 501 scp->binfo.hisr = hisr; 502 503 /* Invoke the handlers of the children. */ 504 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 505 scp->pcmintr(scp->pcmintr_arg); 506 hisr &= ~(HISR_VC0 | HISR_VC1); 507 } 508 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 509 scp->midiintr(scp->midiintr_arg); 510 hisr &= ~HISR_MIDI; 511 } 512 513 /* Throw an eoi. */ 514 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 515} 516 517static int 518csa_initialize(sc_p scp) 519{ 520 int i; 521 u_int32_t acsts, acisv; 522 csa_res *resp; 523 524 resp = &scp->res; 525 526 /* 527 * First, blast the clock control register to zero so that the PLL starts 528 * out in a known state, and blast the master serial port control register 529 * to zero so that the serial ports also start out in a known state. 530 */ 531 csa_writeio(resp, BA0_CLKCR1, 0); 532 csa_writeio(resp, BA0_SERMC1, 0); 533 534 /* 535 * If we are in AC97 mode, then we must set the part to a host controlled 536 * AC-link. Otherwise, we won't be able to bring up the link. 537 */ 538#if 1 539 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 540#else 541 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 542#endif /* 1 */ 543 544 /* 545 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 546 * spec) and then drive it high. This is done for non AC97 modes since 547 * there might be logic external to the CS461x that uses the ARST# line 548 * for a reset. 549 */ 550 csa_writeio(resp, BA0_ACCTL, 1); 551 DELAY(50); 552 csa_writeio(resp, BA0_ACCTL, 0); 553 DELAY(50); 554 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 555 556 /* 557 * The first thing we do here is to enable sync generation. As soon 558 * as we start receiving bit clock, we'll start producing the SYNC 559 * signal. 560 */ 561 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 562 563 /* 564 * Now wait for a short while to allow the AC97 part to start 565 * generating bit clock (so we don't try to start the PLL without an 566 * input clock). 567 */ 568 DELAY(50000); 569 570 /* 571 * Set the serial port timing configuration, so that 572 * the clock control circuit gets its clock from the correct place. 573 */ 574 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 575 DELAY(700000); 576 577 /* 578 * Write the selected clock control setup to the hardware. Do not turn on 579 * SWCE yet (if requested), so that the devices clocked by the output of 580 * PLL are not clocked until the PLL is stable. 581 */ 582 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 583 csa_writeio(resp, BA0_PLLM, 0x3a); 584 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 585 586 /* 587 * Power up the PLL. 588 */ 589 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 590 591 /* 592 * Wait until the PLL has stabilized. 593 */ 594 DELAY(5000); 595 596 /* 597 * Turn on clocking of the core so that we can setup the serial ports. 598 */ 599 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 600 601 /* 602 * Fill the serial port FIFOs with silence. 603 */ 604 csa_clearserialfifos(resp); 605 606 /* 607 * Set the serial port FIFO pointer to the first sample in the FIFO. 608 */ 609#if notdef 610 csa_writeio(resp, BA0_SERBSP, 0); 611#endif /* notdef */ 612 613 /* 614 * Write the serial port configuration to the part. The master 615 * enable bit is not set until all other values have been written. 616 */ 617 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 618 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 619 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 620 621 /* 622 * Wait for the codec ready signal from the AC97 codec. 623 */ 624 acsts = 0; 625 for (i = 0 ; i < 1000 ; i++) { 626 /* 627 * First, lets wait a short while to let things settle out a bit, 628 * and to prevent retrying the read too quickly. 629 */ 630 DELAY(125); 631 632 /* 633 * Read the AC97 status register to see if we've seen a CODEC READY 634 * signal from the AC97 codec. 635 */ 636 acsts = csa_readio(resp, BA0_ACSTS); 637 if ((acsts & ACSTS_CRDY) != 0) 638 break; 639 } 640 641 /* 642 * Make sure we sampled CODEC READY. 643 */ 644 if ((acsts & ACSTS_CRDY) == 0) 645 return (ENXIO); 646 647 /* 648 * Assert the vaid frame signal so that we can start sending commands 649 * to the AC97 codec. 650 */ 651 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 652 653 /* 654 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 655 * the codec is pumping ADC data across the AC-link. 656 */ 657 acisv = 0; 658 for (i = 0 ; i < 1000 ; i++) { 659 /* 660 * First, lets wait a short while to let things settle out a bit, 661 * and to prevent retrying the read too quickly. 662 */ 663#if notdef 664 DELAY(10000000L); /* clw */ 665#else 666 DELAY(1000); 667#endif /* notdef */ 668 /* 669 * Read the input slot valid register and see if input slots 3 and 670 * 4 are valid yet. 671 */ 672 acisv = csa_readio(resp, BA0_ACISV); 673 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 674 break; 675 } 676 /* 677 * Make sure we sampled valid input slots 3 and 4. If not, then return 678 * an error. 679 */ 680 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 681 return (ENXIO); 682 683 /* 684 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 685 * commense the transfer of digital audio data to the AC97 codec. 686 */ 687 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 688 689 /* 690 * Power down the DAC and ADC. We will power them up (if) when we need 691 * them. 692 */ 693#if notdef 694 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 695#endif /* notdef */ 696 697 /* 698 * Turn off the Processor by turning off the software clock enable flag in 699 * the clock control register. 700 */ 701#if notdef 702 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 703 csa_writeio(resp, BA0_CLKCR1, clkcr1); 704#endif /* notdef */ 705 706 /* 707 * Enable interrupts on the part. 708 */ 709#if 0 710 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 711#endif /* notdef */ 712 713 return (0); 714} 715 716void 717csa_clearserialfifos(csa_res *resp) 718{ 719 int i, j, pwr; 720 u_int8_t clkcr1, serbst; 721 722 /* 723 * See if the devices are powered down. If so, we must power them up first 724 * or they will not respond. 725 */ 726 pwr = 1; 727 clkcr1 = csa_readio(resp, BA0_CLKCR1); 728 if ((clkcr1 & CLKCR1_SWCE) == 0) { 729 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 730 pwr = 0; 731 } 732 733 /* 734 * We want to clear out the serial port FIFOs so we don't end up playing 735 * whatever random garbage happens to be in them. We fill the sample FIFOs 736 * with zero (silence). 737 */ 738 csa_writeio(resp, BA0_SERBWP, 0); 739 740 /* Fill all 256 sample FIFO locations. */ 741 serbst = 0; 742 for (i = 0 ; i < 256 ; i++) { 743 /* Make sure the previous FIFO write operation has completed. */ 744 for (j = 0 ; j < 5 ; j++) { 745 DELAY(100); 746 serbst = csa_readio(resp, BA0_SERBST); 747 if ((serbst & SERBST_WBSY) == 0) 748 break; 749 } 750 if ((serbst & SERBST_WBSY) != 0) { 751 if (!pwr) 752 csa_writeio(resp, BA0_CLKCR1, clkcr1); 753 } 754 /* Write the serial port FIFO index. */ 755 csa_writeio(resp, BA0_SERBAD, i); 756 /* Tell the serial port to load the new value into the FIFO location. */ 757 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 758 } 759 /* 760 * Now, if we powered up the devices, then power them back down again. 761 * This is kinda ugly, but should never happen. 762 */ 763 if (!pwr) 764 csa_writeio(resp, BA0_CLKCR1, clkcr1); 765} 766 767static void 768csa_resetdsp(csa_res *resp) 769{ 770 int i; 771 772 /* 773 * Write the reset bit of the SP control register. 774 */ 775 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 776 777 /* 778 * Write the control register. 779 */ 780 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 781 782 /* 783 * Clear the trap registers. 784 */ 785 for (i = 0 ; i < 8 ; i++) { 786 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 787 csa_writemem(resp, BA1_TWPR, 0xffff); 788 } 789 csa_writemem(resp, BA1_DREG, 0); 790 791 /* 792 * Set the frame timer to reflect the number of cycles per frame. 793 */ 794 csa_writemem(resp, BA1_FRMT, 0xadf); 795} 796 797static int 798csa_downloadimage(csa_res *resp) 799{ 800 int i; 801 u_int32_t tmp, src, dst, count, data; 802 803 for (i = 0; i < CLEAR__COUNT; i++) { 804 dst = ClrStat[i].BA1__DestByteOffset; 805 count = ClrStat[i].BA1__SourceSize; 806 for (tmp = 0; tmp < count; tmp += 4) 807 csa_writemem(resp, dst + tmp, 0x00000000); 808 } 809 810 for (i = 0; i < FILL__COUNT; i++) { 811 src = 0; 812 dst = FillStat[i].Offset; 813 count = FillStat[i].Size; 814 for (tmp = 0; tmp < count; tmp += 4) { 815 data = FillStat[i].pFill[src]; 816 csa_writemem(resp, dst + tmp, data); 817 src++; 818 } 819 } 820 821 return (0); 822} 823 824int 825csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 826{ 827 int i; 828 u_int32_t acsda, acctl, acsts; 829 830 /* 831 * Make sure that there is not data sitting around from a previous 832 * uncompleted access. ACSDA = Status Data Register = 47Ch 833 */ 834 acsda = csa_readio(resp, BA0_ACSDA); 835 836 /* 837 * Setup the AC97 control registers on the CS461x to send the 838 * appropriate command to the AC97 to perform the read. 839 * ACCAD = Command Address Register = 46Ch 840 * ACCDA = Command Data Register = 470h 841 * ACCTL = Control Register = 460h 842 * set DCV - will clear when process completed 843 * set CRW - Read command 844 * set VFRM - valid frame enabled 845 * set ESYN - ASYNC generation enabled 846 * set RSTN - ARST# inactive, AC97 codec not reset 847 */ 848 849 /* 850 * Get the actual AC97 register from the offset 851 */ 852 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 853 csa_writeio(resp, BA0_ACCDA, 0); 854 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 855 856 /* 857 * Wait for the read to occur. 858 */ 859 acctl = 0; 860 for (i = 0 ; i < 10 ; i++) { 861 /* 862 * First, we want to wait for a short time. 863 */ 864 DELAY(25); 865 866 /* 867 * Now, check to see if the read has completed. 868 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 869 */ 870 acctl = csa_readio(resp, BA0_ACCTL); 871 if ((acctl & ACCTL_DCV) == 0) 872 break; 873 } 874 875 /* 876 * Make sure the read completed. 877 */ 878 if ((acctl & ACCTL_DCV) != 0) 879 return (EAGAIN); 880 881 /* 882 * Wait for the valid status bit to go active. 883 */ 884 acsts = 0; 885 for (i = 0 ; i < 10 ; i++) { 886 /* 887 * Read the AC97 status register. 888 * ACSTS = Status Register = 464h 889 */ 890 acsts = csa_readio(resp, BA0_ACSTS); 891 /* 892 * See if we have valid status. 893 * VSTS - Valid Status 894 */ 895 if ((acsts & ACSTS_VSTS) != 0) 896 break; 897 /* 898 * Wait for a short while. 899 */ 900 DELAY(25); 901 } 902 903 /* 904 * Make sure we got valid status. 905 */ 906 if ((acsts & ACSTS_VSTS) == 0) 907 return (EAGAIN); 908 909 /* 910 * Read the data returned from the AC97 register. 911 * ACSDA = Status Data Register = 474h 912 */ 913 *data = csa_readio(resp, BA0_ACSDA); 914 915 return (0); 916} 917 918int 919csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 920{ 921 int i; 922 u_int32_t acctl; 923 924 /* 925 * Setup the AC97 control registers on the CS461x to send the 926 * appropriate command to the AC97 to perform the write. 927 * ACCAD = Command Address Register = 46Ch 928 * ACCDA = Command Data Register = 470h 929 * ACCTL = Control Register = 460h 930 * set DCV - will clear when process completed 931 * set VFRM - valid frame enabled 932 * set ESYN - ASYNC generation enabled 933 * set RSTN - ARST# inactive, AC97 codec not reset 934 */ 935 936 /* 937 * Get the actual AC97 register from the offset 938 */ 939 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 940 csa_writeio(resp, BA0_ACCDA, data); 941 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 942 943 /* 944 * Wait for the write to occur. 945 */ 946 acctl = 0; 947 for (i = 0 ; i < 10 ; i++) { 948 /* 949 * First, we want to wait for a short time. 950 */ 951 DELAY(25); 952 953 /* 954 * Now, check to see if the read has completed. 955 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 956 */ 957 acctl = csa_readio(resp, BA0_ACCTL); 958 if ((acctl & ACCTL_DCV) == 0) 959 break; 960 } 961 962 /* 963 * Make sure the write completed. 964 */ 965 if ((acctl & ACCTL_DCV) != 0) 966 return (EAGAIN); 967 968 return (0); 969} 970 971u_int32_t 972csa_readio(csa_res *resp, u_long offset) 973{ 974 u_int32_t ul; 975 976 if (offset < BA0_AC97_RESET) 977 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 978 else { 979 if (csa_readcodec(resp, offset, &ul)) 980 ul = 0; 981 return (ul); 982 } 983} 984 985void 986csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 987{ 988 if (offset < BA0_AC97_RESET) 989 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 990 else 991 csa_writecodec(resp, offset, data); 992} 993 994u_int32_t 995csa_readmem(csa_res *resp, u_long offset) 996{ 997 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 998} 999 1000void 1001csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1002{ 1003 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1004} 1005 1006static device_method_t csa_methods[] = { 1007 /* Device interface */ 1008 DEVMETHOD(device_probe, csa_probe), 1009 DEVMETHOD(device_attach, csa_attach), 1010 DEVMETHOD(device_detach, csa_detach), 1011 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1012 DEVMETHOD(device_suspend, bus_generic_suspend), 1013 DEVMETHOD(device_resume, bus_generic_resume), 1014 1015 /* Bus interface */ 1016 DEVMETHOD(bus_print_child, bus_generic_print_child), 1017 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1018 DEVMETHOD(bus_release_resource, csa_release_resource), 1019 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1020 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1021 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1022 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1023 1024 { 0, 0 } 1025}; 1026 1027static driver_t csa_driver = { 1028 "csa", 1029 csa_methods, 1030 sizeof(struct csa_softc), 1031}; 1032 1033/* 1034 * csa can be attached to a pci bus. 1035 */ 1036DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1037MODULE_DEPEND(snd_csa, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1038MODULE_VERSION(snd_csa, 1); 1039