csa.c revision 100634
1/* 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <machine/resource.h> 38#include <machine/bus.h> 39#include <sys/rman.h> 40#include <sys/soundcard.h> 41#include <dev/sound/pcm/sound.h> 42#include <dev/sound/chip.h> 43#include <dev/sound/pci/csareg.h> 44#include <dev/sound/pci/csavar.h> 45 46#include <pci/pcireg.h> 47#include <pci/pcivar.h> 48 49#include <gnu/dev/sound/pci/csaimg.h> 50 51SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/csa.c 100634 2002-07-24 21:27:22Z ambrisko $"); 52 53/* This is the pci device id. */ 54#define CS4610_PCI_ID 0x60011013 55#define CS4614_PCI_ID 0x60031013 56#define CS4615_PCI_ID 0x60041013 57 58/* Here is the parameter structure per a device. */ 59struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73}; 74 75typedef struct csa_softc *sc_p; 76 77static int csa_probe(device_t dev); 78static int csa_attach(device_t dev); 79static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 driver_intr_t *intr, void *arg, void **cookiep); 86static int csa_teardown_intr(device_t bus, device_t child, 87 struct resource *irq, void *cookie); 88static driver_intr_t csa_intr; 89static int csa_initialize(sc_p scp); 90static void csa_resetdsp(csa_res *resp); 91static int csa_downloadimage(csa_res *resp); 92 93static devclass_t csa_devclass; 94 95static void 96amp_none(void) 97{ 98} 99 100static void 101amp_voyetra(void) 102{ 103} 104 105static int 106clkrun_hack(int run) 107{ 108#ifdef __i386__ 109 devclass_t pci_devclass; 110 device_t *pci_devices, *pci_children, *busp, *childp; 111 int pci_count = 0, pci_childcount = 0; 112 int i, j, port; 113 u_int16_t control; 114 bus_space_tag_t btag; 115 116 if ((pci_devclass = devclass_find("pci")) == NULL) { 117 return ENXIO; 118 } 119 120 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 121 122 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 123 pci_childcount = 0; 124 device_get_children(*busp, &pci_children, &pci_childcount); 125 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 126 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 127 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 128 /* XXX */ 129 btag = I386_BUS_SPACE_IO; 130 131 control = bus_space_read_2(btag, 0x0, port); 132 control &= ~0x2000; 133 control |= run? 0 : 0x2000; 134 bus_space_write_2(btag, 0x0, port, control); 135 free(pci_devices, M_TEMP); 136 free(pci_children, M_TEMP); 137 return 0; 138 } 139 } 140 free(pci_children, M_TEMP); 141 } 142 143 free(pci_devices, M_TEMP); 144 return ENXIO; 145#else 146 return 0; 147#endif 148} 149 150static struct csa_card cards_4610[] = { 151 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 152}; 153 154static struct csa_card cards_4614[] = { 155 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 156 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 157 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 158 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 159 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 160 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 161 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 162 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 163 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 164}; 165 166static struct csa_card cards_4615[] = { 167 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 168}; 169 170static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 171 172struct card_type { 173 u_int32_t devid; 174 char *name; 175 struct csa_card *cards; 176}; 177 178static struct card_type cards[] = { 179 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 180 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 181 {CS4615_PCI_ID, "CS4615", cards_4615}, 182 {0, NULL, NULL}, 183}; 184 185static struct card_type * 186csa_findcard(device_t dev) 187{ 188 int i; 189 190 i = 0; 191 while (cards[i].devid != 0) { 192 if (pci_get_devid(dev) == cards[i].devid) 193 return &cards[i]; 194 i++; 195 } 196 return NULL; 197} 198 199struct csa_card * 200csa_findsubcard(device_t dev) 201{ 202 int i; 203 struct card_type *card; 204 struct csa_card *subcard; 205 206 card = csa_findcard(dev); 207 if (card == NULL) 208 return &nocard; 209 subcard = card->cards; 210 i = 0; 211 while (subcard[i].subvendor != 0) { 212 if (pci_get_subvendor(dev) == subcard[i].subvendor 213 && pci_get_subdevice(dev) == subcard[i].subdevice) { 214 return &subcard[i]; 215 } 216 i++; 217 } 218 return &subcard[i]; 219} 220 221static int 222csa_probe(device_t dev) 223{ 224 struct card_type *card; 225 226 card = csa_findcard(dev); 227 if (card) { 228 device_set_desc(dev, card->name); 229 return 0; 230 } 231 return ENXIO; 232} 233 234static int 235csa_attach(device_t dev) 236{ 237 u_int32_t stcmd; 238 sc_p scp; 239 csa_res *resp; 240 struct sndcard_func *func; 241 int error = ENXIO; 242 243 scp = device_get_softc(dev); 244 245 /* Fill in the softc. */ 246 bzero(scp, sizeof(*scp)); 247 scp->dev = dev; 248 249 /* Wake up the device. */ 250 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 251 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 252 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 253 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 254 } 255 256 /* Allocate the resources. */ 257 resp = &scp->res; 258 scp->card = csa_findsubcard(dev); 259 scp->binfo.card = scp->card; 260 printf("csa: card is %s\n", scp->card->name); 261 resp->io_rid = PCIR_MAPS; 262 resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, 1, RF_ACTIVE); 263 if (resp->io == NULL) 264 return (ENXIO); 265 resp->mem_rid = PCIR_MAPS + 4; 266 resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, 1, RF_ACTIVE); 267 if (resp->mem == NULL) 268 goto err_io; 269 resp->irq_rid = 0; 270 resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 271 if (resp->irq == NULL) 272 goto err_mem; 273 274 /* Enable interrupt. */ 275 if (snd_setup_intr(dev, resp->irq, INTR_MPSAFE, csa_intr, scp, &scp->ih)) 276 goto err_intr; 277#if 0 278 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 279 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 280#endif 281 282 /* Initialize the chip. */ 283 if (csa_initialize(scp)) 284 goto err_teardown; 285 286 /* Reset the Processor. */ 287 csa_resetdsp(resp); 288 289 /* Download the Processor Image to the processor. */ 290 if (csa_downloadimage(resp)) 291 goto err_teardown; 292 293 /* Attach the children. */ 294 295 /* PCM Audio */ 296 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 297 if (func == NULL) { 298 error = ENOMEM; 299 goto err_teardown; 300 } 301 func->varinfo = &scp->binfo; 302 func->func = SCF_PCM; 303 scp->pcm = device_add_child(dev, "pcm", -1); 304 device_set_ivars(scp->pcm, func); 305 306 /* Midi Interface */ 307 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 308 if (func == NULL) { 309 error = ENOMEM; 310 goto err_teardown; 311 } 312 func->varinfo = &scp->binfo; 313 func->func = SCF_MIDI; 314 scp->midi = device_add_child(dev, "midi", -1); 315 device_set_ivars(scp->midi, func); 316 317 bus_generic_attach(dev); 318 319 return (0); 320 321err_teardown: 322 bus_teardown_intr(dev, resp->irq, scp->ih); 323err_intr: 324 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 325err_mem: 326 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 327err_io: 328 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 329 return (error); 330} 331 332static int 333csa_detach(device_t dev) 334{ 335 csa_res *resp; 336 sc_p scp; 337 int err; 338 339 scp = device_get_softc(dev); 340 resp = &scp->res; 341 342 err = 0; 343 if (scp->midi != NULL) 344 err = device_delete_child(dev, scp->midi); 345 if (err) 346 return err; 347 scp->midi = NULL; 348 349 if (scp->pcm != NULL) 350 err = device_delete_child(dev, scp->pcm); 351 if (err) 352 return err; 353 scp->pcm = NULL; 354 355 bus_teardown_intr(dev, resp->irq, scp->ih); 356 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 357 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 358 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 359 360 return bus_generic_detach(dev); 361} 362 363static int 364csa_resume(device_t dev) 365{ 366 csa_detach(dev); 367 csa_attach(dev); 368 369 return 0; 370} 371 372static struct resource * 373csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 374 u_long start, u_long end, u_long count, u_int flags) 375{ 376 sc_p scp; 377 csa_res *resp; 378 struct resource *res; 379 380 scp = device_get_softc(bus); 381 resp = &scp->res; 382 switch (type) { 383 case SYS_RES_IRQ: 384 if (*rid != 0) 385 return (NULL); 386 res = resp->irq; 387 break; 388 case SYS_RES_MEMORY: 389 switch (*rid) { 390 case PCIR_MAPS: 391 res = resp->io; 392 break; 393 case PCIR_MAPS + 4: 394 res = resp->mem; 395 break; 396 default: 397 return (NULL); 398 } 399 break; 400 default: 401 return (NULL); 402 } 403 404 return res; 405} 406 407static int 408csa_release_resource(device_t bus, device_t child, int type, int rid, 409 struct resource *r) 410{ 411 return (0); 412} 413 414/* 415 * The following three functions deal with interrupt handling. 416 * An interrupt is primarily handled by the bridge driver. 417 * The bridge driver then determines the child devices to pass 418 * the interrupt. Certain information of the device can be read 419 * only once(eg the value of HISR). The bridge driver is responsible 420 * to pass such the information to the children. 421 */ 422 423static int 424csa_setup_intr(device_t bus, device_t child, 425 struct resource *irq, int flags, 426 driver_intr_t *intr, void *arg, void **cookiep) 427{ 428 sc_p scp; 429 csa_res *resp; 430 struct sndcard_func *func; 431 432 scp = device_get_softc(bus); 433 resp = &scp->res; 434 435 /* 436 * Look at the function code of the child to determine 437 * the appropriate hander for it. 438 */ 439 func = device_get_ivars(child); 440 if (func == NULL || irq != resp->irq) 441 return (EINVAL); 442 443 switch (func->func) { 444 case SCF_PCM: 445 scp->pcmintr = intr; 446 scp->pcmintr_arg = arg; 447 break; 448 449 case SCF_MIDI: 450 scp->midiintr = intr; 451 scp->midiintr_arg = arg; 452 break; 453 454 default: 455 return (EINVAL); 456 } 457 *cookiep = scp; 458 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 459 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 460 461 return (0); 462} 463 464static int 465csa_teardown_intr(device_t bus, device_t child, 466 struct resource *irq, void *cookie) 467{ 468 sc_p scp; 469 csa_res *resp; 470 struct sndcard_func *func; 471 472 scp = device_get_softc(bus); 473 resp = &scp->res; 474 475 /* 476 * Look at the function code of the child to determine 477 * the appropriate hander for it. 478 */ 479 func = device_get_ivars(child); 480 if (func == NULL || irq != resp->irq || cookie != scp) 481 return (EINVAL); 482 483 switch (func->func) { 484 case SCF_PCM: 485 scp->pcmintr = NULL; 486 scp->pcmintr_arg = NULL; 487 break; 488 489 case SCF_MIDI: 490 scp->midiintr = NULL; 491 scp->midiintr_arg = NULL; 492 break; 493 494 default: 495 return (EINVAL); 496 } 497 498 return (0); 499} 500 501/* The interrupt handler */ 502static void 503csa_intr(void *arg) 504{ 505 sc_p scp = arg; 506 csa_res *resp; 507 u_int32_t hisr; 508 509 resp = &scp->res; 510 511 /* Is this interrupt for us? */ 512 hisr = csa_readio(resp, BA0_HISR); 513 if ((hisr & 0x7fffffff) == 0) { 514 /* Throw an eoi. */ 515 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 516 return; 517 } 518 519 /* 520 * Pass the value of HISR via struct csa_bridgeinfo. 521 * The children get access through their ivars. 522 */ 523 scp->binfo.hisr = hisr; 524 525 /* Invoke the handlers of the children. */ 526 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 527 scp->pcmintr(scp->pcmintr_arg); 528 hisr &= ~(HISR_VC0 | HISR_VC1); 529 } 530 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 531 scp->midiintr(scp->midiintr_arg); 532 hisr &= ~HISR_MIDI; 533 } 534 535 /* Throw an eoi. */ 536 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 537} 538 539static int 540csa_initialize(sc_p scp) 541{ 542 int i; 543 u_int32_t acsts, acisv; 544 csa_res *resp; 545 546 resp = &scp->res; 547 548 /* 549 * First, blast the clock control register to zero so that the PLL starts 550 * out in a known state, and blast the master serial port control register 551 * to zero so that the serial ports also start out in a known state. 552 */ 553 csa_writeio(resp, BA0_CLKCR1, 0); 554 csa_writeio(resp, BA0_SERMC1, 0); 555 556 /* 557 * If we are in AC97 mode, then we must set the part to a host controlled 558 * AC-link. Otherwise, we won't be able to bring up the link. 559 */ 560#if 1 561 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 562#else 563 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 564#endif /* 1 */ 565 566 /* 567 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 568 * spec) and then drive it high. This is done for non AC97 modes since 569 * there might be logic external to the CS461x that uses the ARST# line 570 * for a reset. 571 */ 572 csa_writeio(resp, BA0_ACCTL, 1); 573 DELAY(50); 574 csa_writeio(resp, BA0_ACCTL, 0); 575 DELAY(50); 576 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 577 578 /* 579 * The first thing we do here is to enable sync generation. As soon 580 * as we start receiving bit clock, we'll start producing the SYNC 581 * signal. 582 */ 583 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 584 585 /* 586 * Now wait for a short while to allow the AC97 part to start 587 * generating bit clock (so we don't try to start the PLL without an 588 * input clock). 589 */ 590 DELAY(50000); 591 592 /* 593 * Set the serial port timing configuration, so that 594 * the clock control circuit gets its clock from the correct place. 595 */ 596 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 597 DELAY(700000); 598 599 /* 600 * Write the selected clock control setup to the hardware. Do not turn on 601 * SWCE yet (if requested), so that the devices clocked by the output of 602 * PLL are not clocked until the PLL is stable. 603 */ 604 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 605 csa_writeio(resp, BA0_PLLM, 0x3a); 606 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 607 608 /* 609 * Power up the PLL. 610 */ 611 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 612 613 /* 614 * Wait until the PLL has stabilized. 615 */ 616 DELAY(5000); 617 618 /* 619 * Turn on clocking of the core so that we can setup the serial ports. 620 */ 621 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 622 623 /* 624 * Fill the serial port FIFOs with silence. 625 */ 626 csa_clearserialfifos(resp); 627 628 /* 629 * Set the serial port FIFO pointer to the first sample in the FIFO. 630 */ 631#if notdef 632 csa_writeio(resp, BA0_SERBSP, 0); 633#endif /* notdef */ 634 635 /* 636 * Write the serial port configuration to the part. The master 637 * enable bit is not set until all other values have been written. 638 */ 639 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 640 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 641 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 642 643 /* 644 * Wait for the codec ready signal from the AC97 codec. 645 */ 646 acsts = 0; 647 for (i = 0 ; i < 1000 ; i++) { 648 /* 649 * First, lets wait a short while to let things settle out a bit, 650 * and to prevent retrying the read too quickly. 651 */ 652 DELAY(125); 653 654 /* 655 * Read the AC97 status register to see if we've seen a CODEC READY 656 * signal from the AC97 codec. 657 */ 658 acsts = csa_readio(resp, BA0_ACSTS); 659 if ((acsts & ACSTS_CRDY) != 0) 660 break; 661 } 662 663 /* 664 * Make sure we sampled CODEC READY. 665 */ 666 if ((acsts & ACSTS_CRDY) == 0) 667 return (ENXIO); 668 669 /* 670 * Assert the vaid frame signal so that we can start sending commands 671 * to the AC97 codec. 672 */ 673 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 674 675 /* 676 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 677 * the codec is pumping ADC data across the AC-link. 678 */ 679 acisv = 0; 680 for (i = 0 ; i < 1000 ; i++) { 681 /* 682 * First, lets wait a short while to let things settle out a bit, 683 * and to prevent retrying the read too quickly. 684 */ 685#if notdef 686 DELAY(10000000L); /* clw */ 687#else 688 DELAY(1000); 689#endif /* notdef */ 690 /* 691 * Read the input slot valid register and see if input slots 3 and 692 * 4 are valid yet. 693 */ 694 acisv = csa_readio(resp, BA0_ACISV); 695 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 696 break; 697 } 698 /* 699 * Make sure we sampled valid input slots 3 and 4. If not, then return 700 * an error. 701 */ 702 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 703 return (ENXIO); 704 705 /* 706 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 707 * commense the transfer of digital audio data to the AC97 codec. 708 */ 709 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 710 711 /* 712 * Power down the DAC and ADC. We will power them up (if) when we need 713 * them. 714 */ 715#if notdef 716 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 717#endif /* notdef */ 718 719 /* 720 * Turn off the Processor by turning off the software clock enable flag in 721 * the clock control register. 722 */ 723#if notdef 724 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 725 csa_writeio(resp, BA0_CLKCR1, clkcr1); 726#endif /* notdef */ 727 728 /* 729 * Enable interrupts on the part. 730 */ 731#if 0 732 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 733#endif /* notdef */ 734 735 return (0); 736} 737 738void 739csa_clearserialfifos(csa_res *resp) 740{ 741 int i, j, pwr; 742 u_int8_t clkcr1, serbst; 743 744 /* 745 * See if the devices are powered down. If so, we must power them up first 746 * or they will not respond. 747 */ 748 pwr = 1; 749 clkcr1 = csa_readio(resp, BA0_CLKCR1); 750 if ((clkcr1 & CLKCR1_SWCE) == 0) { 751 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 752 pwr = 0; 753 } 754 755 /* 756 * We want to clear out the serial port FIFOs so we don't end up playing 757 * whatever random garbage happens to be in them. We fill the sample FIFOs 758 * with zero (silence). 759 */ 760 csa_writeio(resp, BA0_SERBWP, 0); 761 762 /* Fill all 256 sample FIFO locations. */ 763 serbst = 0; 764 for (i = 0 ; i < 256 ; i++) { 765 /* Make sure the previous FIFO write operation has completed. */ 766 for (j = 0 ; j < 5 ; j++) { 767 DELAY(100); 768 serbst = csa_readio(resp, BA0_SERBST); 769 if ((serbst & SERBST_WBSY) == 0) 770 break; 771 } 772 if ((serbst & SERBST_WBSY) != 0) { 773 if (!pwr) 774 csa_writeio(resp, BA0_CLKCR1, clkcr1); 775 } 776 /* Write the serial port FIFO index. */ 777 csa_writeio(resp, BA0_SERBAD, i); 778 /* Tell the serial port to load the new value into the FIFO location. */ 779 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 780 } 781 /* 782 * Now, if we powered up the devices, then power them back down again. 783 * This is kinda ugly, but should never happen. 784 */ 785 if (!pwr) 786 csa_writeio(resp, BA0_CLKCR1, clkcr1); 787} 788 789static void 790csa_resetdsp(csa_res *resp) 791{ 792 int i; 793 794 /* 795 * Write the reset bit of the SP control register. 796 */ 797 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 798 799 /* 800 * Write the control register. 801 */ 802 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 803 804 /* 805 * Clear the trap registers. 806 */ 807 for (i = 0 ; i < 8 ; i++) { 808 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 809 csa_writemem(resp, BA1_TWPR, 0xffff); 810 } 811 csa_writemem(resp, BA1_DREG, 0); 812 813 /* 814 * Set the frame timer to reflect the number of cycles per frame. 815 */ 816 csa_writemem(resp, BA1_FRMT, 0xadf); 817} 818 819static int 820csa_downloadimage(csa_res *resp) 821{ 822 int i; 823 u_int32_t tmp, src, dst, count, data; 824 825 for (i = 0; i < CLEAR__COUNT; i++) { 826 dst = ClrStat[i].BA1__DestByteOffset; 827 count = ClrStat[i].BA1__SourceSize; 828 for (tmp = 0; tmp < count; tmp += 4) 829 csa_writemem(resp, dst + tmp, 0x00000000); 830 } 831 832 for (i = 0; i < FILL__COUNT; i++) { 833 src = 0; 834 dst = FillStat[i].Offset; 835 count = FillStat[i].Size; 836 for (tmp = 0; tmp < count; tmp += 4) { 837 data = FillStat[i].pFill[src]; 838 csa_writemem(resp, dst + tmp, data); 839 src++; 840 } 841 } 842 843 return (0); 844} 845 846int 847csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 848{ 849 int i; 850 u_int32_t acsda, acctl, acsts; 851 852 /* 853 * Make sure that there is not data sitting around from a previous 854 * uncompleted access. ACSDA = Status Data Register = 47Ch 855 */ 856 acsda = csa_readio(resp, BA0_ACSDA); 857 858 /* 859 * Setup the AC97 control registers on the CS461x to send the 860 * appropriate command to the AC97 to perform the read. 861 * ACCAD = Command Address Register = 46Ch 862 * ACCDA = Command Data Register = 470h 863 * ACCTL = Control Register = 460h 864 * set DCV - will clear when process completed 865 * set CRW - Read command 866 * set VFRM - valid frame enabled 867 * set ESYN - ASYNC generation enabled 868 * set RSTN - ARST# inactive, AC97 codec not reset 869 */ 870 871 /* 872 * Get the actual AC97 register from the offset 873 */ 874 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 875 csa_writeio(resp, BA0_ACCDA, 0); 876 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 877 878 /* 879 * Wait for the read to occur. 880 */ 881 acctl = 0; 882 for (i = 0 ; i < 10 ; i++) { 883 /* 884 * First, we want to wait for a short time. 885 */ 886 DELAY(25); 887 888 /* 889 * Now, check to see if the read has completed. 890 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 891 */ 892 acctl = csa_readio(resp, BA0_ACCTL); 893 if ((acctl & ACCTL_DCV) == 0) 894 break; 895 } 896 897 /* 898 * Make sure the read completed. 899 */ 900 if ((acctl & ACCTL_DCV) != 0) 901 return (EAGAIN); 902 903 /* 904 * Wait for the valid status bit to go active. 905 */ 906 acsts = 0; 907 for (i = 0 ; i < 10 ; i++) { 908 /* 909 * Read the AC97 status register. 910 * ACSTS = Status Register = 464h 911 */ 912 acsts = csa_readio(resp, BA0_ACSTS); 913 /* 914 * See if we have valid status. 915 * VSTS - Valid Status 916 */ 917 if ((acsts & ACSTS_VSTS) != 0) 918 break; 919 /* 920 * Wait for a short while. 921 */ 922 DELAY(25); 923 } 924 925 /* 926 * Make sure we got valid status. 927 */ 928 if ((acsts & ACSTS_VSTS) == 0) 929 return (EAGAIN); 930 931 /* 932 * Read the data returned from the AC97 register. 933 * ACSDA = Status Data Register = 474h 934 */ 935 *data = csa_readio(resp, BA0_ACSDA); 936 937 return (0); 938} 939 940int 941csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 942{ 943 int i; 944 u_int32_t acctl; 945 946 /* 947 * Setup the AC97 control registers on the CS461x to send the 948 * appropriate command to the AC97 to perform the write. 949 * ACCAD = Command Address Register = 46Ch 950 * ACCDA = Command Data Register = 470h 951 * ACCTL = Control Register = 460h 952 * set DCV - will clear when process completed 953 * set VFRM - valid frame enabled 954 * set ESYN - ASYNC generation enabled 955 * set RSTN - ARST# inactive, AC97 codec not reset 956 */ 957 958 /* 959 * Get the actual AC97 register from the offset 960 */ 961 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 962 csa_writeio(resp, BA0_ACCDA, data); 963 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 964 965 /* 966 * Wait for the write to occur. 967 */ 968 acctl = 0; 969 for (i = 0 ; i < 10 ; i++) { 970 /* 971 * First, we want to wait for a short time. 972 */ 973 DELAY(25); 974 975 /* 976 * Now, check to see if the read has completed. 977 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 978 */ 979 acctl = csa_readio(resp, BA0_ACCTL); 980 if ((acctl & ACCTL_DCV) == 0) 981 break; 982 } 983 984 /* 985 * Make sure the write completed. 986 */ 987 if ((acctl & ACCTL_DCV) != 0) 988 return (EAGAIN); 989 990 return (0); 991} 992 993u_int32_t 994csa_readio(csa_res *resp, u_long offset) 995{ 996 u_int32_t ul; 997 998 if (offset < BA0_AC97_RESET) 999 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1000 else { 1001 if (csa_readcodec(resp, offset, &ul)) 1002 ul = 0; 1003 return (ul); 1004 } 1005} 1006 1007void 1008csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1009{ 1010 if (offset < BA0_AC97_RESET) 1011 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1012 else 1013 csa_writecodec(resp, offset, data); 1014} 1015 1016u_int32_t 1017csa_readmem(csa_res *resp, u_long offset) 1018{ 1019 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1020} 1021 1022void 1023csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1024{ 1025 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1026} 1027 1028static device_method_t csa_methods[] = { 1029 /* Device interface */ 1030 DEVMETHOD(device_probe, csa_probe), 1031 DEVMETHOD(device_attach, csa_attach), 1032 DEVMETHOD(device_detach, csa_detach), 1033 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1034 DEVMETHOD(device_suspend, bus_generic_suspend), 1035 DEVMETHOD(device_resume, csa_resume), 1036 1037 /* Bus interface */ 1038 DEVMETHOD(bus_print_child, bus_generic_print_child), 1039 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1040 DEVMETHOD(bus_release_resource, csa_release_resource), 1041 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1042 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1043 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1044 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1045 1046 { 0, 0 } 1047}; 1048 1049static driver_t csa_driver = { 1050 "csa", 1051 csa_methods, 1052 sizeof(struct csa_softc), 1053}; 1054 1055/* 1056 * csa can be attached to a pci bus. 1057 */ 1058DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1059MODULE_DEPEND(snd_csa, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1060MODULE_VERSION(snd_csa, 1); 1061