cs4281.c revision 192919
1169695Skan/*- 2169695Skan * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3169695Skan * All rights reserved. 4169695Skan * 5169695Skan * Redistribution and use in source and binary forms, with or without 6169695Skan * modification, are permitted provided that the following conditions 7169695Skan * are met: 8169695Skan * 1. Redistributions of source code must retain the above copyright 9169695Skan * notice, this list of conditions and the following disclaimer. 10169695Skan * 2. Redistributions in binary form must reproduce the above copyright 11169695Skan * notice, this list of conditions and the following disclaimer in the 12169695Skan * documentation and/or other materials provided with the distribution. 13169695Skan * 14169695Skan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15169695Skan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16169695Skan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17169695Skan * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18169695Skan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19169695Skan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20169695Skan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21169695Skan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22169695Skan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23169695Skan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24169695Skan * SUCH DAMAGE. 25169695Skan */ 26169695Skan 27169695Skan/* 28169695Skan * The order of pokes in the initiation sequence is based on Linux 29169695Skan * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom 30169695Skan * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org) 31169695Skan * contributed towards power management. 32169695Skan */ 33169695Skan 34169695Skan#include <dev/sound/pcm/sound.h> 35169695Skan#include <dev/sound/pcm/ac97.h> 36169695Skan 37169695Skan#include <dev/pci/pcireg.h> 38169695Skan#include <dev/pci/pcivar.h> 39169695Skan 40169695Skan#include <dev/sound/pci/cs4281.h> 41169695Skan 42169695SkanSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cs4281.c 192919 2009-05-27 18:13:15Z joel $"); 43169695Skan 44169695Skan#define CS4281_DEFAULT_BUFSZ 16384 45169695Skan 46169695Skan/* Max fifo size for full duplex is 64 */ 47169695Skan#define CS4281_FIFO_SIZE 15 48169695Skan 49169695Skan/* DMA Engine Indices */ 50169695Skan#define CS4281_DMA_PLAY 0 51169695Skan#define CS4281_DMA_REC 1 52169695Skan 53169695Skan/* Misc */ 54169695Skan 55169695Skan#define inline __inline 56169695Skan 57169695Skan#ifndef DEB 58169695Skan#define DEB(x) /* x */ 59169695Skan#endif /* DEB */ 60169695Skan 61169695Skan/* ------------------------------------------------------------------------- */ 62169695Skan/* Structures */ 63169695Skan 64169695Skanstruct sc_info; 65169695Skan 66169695Skan/* channel registers */ 67169695Skanstruct sc_chinfo { 68169695Skan struct sc_info *parent; 69169695Skan 70169695Skan struct snd_dbuf *buffer; 71169695Skan struct pcm_channel *channel; 72169695Skan 73169695Skan u_int32_t spd, fmt, bps, blksz; 74169695Skan 75169695Skan int dma_setup, dma_active, dma_chan; 76169695Skan}; 77169695Skan 78169695Skan/* device private data */ 79169695Skanstruct sc_info { 80169695Skan device_t dev; 81169695Skan u_int32_t type; 82169695Skan 83169695Skan bus_space_tag_t st; 84169695Skan bus_space_handle_t sh; 85169695Skan bus_dma_tag_t parent_dmat; 86169695Skan 87169695Skan struct resource *reg, *irq, *mem; 88169695Skan int regtype, regid, irqid, memid; 89169695Skan void *ih; 90169695Skan 91169695Skan int power; 92169695Skan unsigned long bufsz; 93169695Skan struct sc_chinfo pch; 94169695Skan struct sc_chinfo rch; 95169695Skan}; 96169695Skan 97169695Skan/* -------------------------------------------------------------------- */ 98169695Skan/* prototypes */ 99169695Skan 100169695Skan/* ADC/DAC control */ 101169695Skanstatic u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go); 102169695Skanstatic void adcdac_prog(struct sc_chinfo *ch); 103169695Skan 104169695Skan/* power management and interrupt control */ 105169695Skanstatic void cs4281_intr(void *); 106169695Skanstatic int cs4281_power(struct sc_info *, int); 107169695Skanstatic int cs4281_init(struct sc_info *); 108169695Skan 109169695Skan/* talk to the card */ 110169695Skanstatic u_int32_t cs4281_rd(struct sc_info *, int); 111169695Skanstatic void cs4281_wr(struct sc_info *, int, u_int32_t); 112169695Skan 113169695Skan/* misc */ 114169695Skanstatic u_int8_t cs4281_rate_to_rv(u_int32_t); 115169695Skanstatic u_int32_t cs4281_format_to_dmr(u_int32_t); 116169695Skanstatic u_int32_t cs4281_format_to_bps(u_int32_t); 117169695Skan 118169695Skan/* -------------------------------------------------------------------- */ 119169695Skan/* formats (do not add formats without editing cs_fmt_tab) */ 120169695Skan 121169695Skanstatic u_int32_t cs4281_fmts[] = { 122169695Skan AFMT_U8, 123169695Skan AFMT_U8 | AFMT_STEREO, 124169695Skan AFMT_S8, 125169695Skan AFMT_S8 | AFMT_STEREO, 126169695Skan AFMT_S16_LE, 127169695Skan AFMT_S16_LE | AFMT_STEREO, 128169695Skan AFMT_U16_LE, 129169695Skan AFMT_U16_LE | AFMT_STEREO, 130169695Skan AFMT_S16_BE, 131169695Skan AFMT_S16_BE | AFMT_STEREO, 132169695Skan AFMT_U16_BE, 133169695Skan AFMT_U16_BE | AFMT_STEREO, 134169695Skan 0 135169695Skan}; 136169695Skan 137169695Skanstatic struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0}; 138169695Skan 139169695Skan/* -------------------------------------------------------------------- */ 140169695Skan/* Hardware */ 141169695Skan 142169695Skanstatic inline u_int32_t 143169695Skancs4281_rd(struct sc_info *sc, int regno) 144169695Skan{ 145169695Skan return bus_space_read_4(sc->st, sc->sh, regno); 146169695Skan} 147169695Skan 148169695Skanstatic inline void 149169695Skancs4281_wr(struct sc_info *sc, int regno, u_int32_t data) 150169695Skan{ 151169695Skan bus_space_write_4(sc->st, sc->sh, regno, data); 152169695Skan DELAY(100); 153169695Skan} 154169695Skan 155169695Skanstatic inline void 156169695Skancs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask) 157169695Skan{ 158169695Skan u_int32_t r; 159169695Skan r = cs4281_rd(sc, regno); 160169695Skan cs4281_wr(sc, regno, r & ~mask); 161169695Skan} 162169695Skan 163169695Skanstatic inline void 164169695Skancs4281_set4(struct sc_info *sc, int regno, u_int32_t mask) 165169695Skan{ 166169695Skan u_int32_t v; 167169695Skan v = cs4281_rd(sc, regno); 168169695Skan cs4281_wr(sc, regno, v | mask); 169169695Skan} 170169695Skan 171169695Skanstatic int 172169695Skancs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries) 173169695Skan{ 174169695Skan u_int32_t v; 175169695Skan 176169695Skan while(tries > 0) { 177169695Skan DELAY(100); 178169695Skan v = cs4281_rd(sc, regno); 179169695Skan if ((v & mask) == mask) break; 180169695Skan tries --; 181169695Skan } 182169695Skan return tries; 183169695Skan} 184169695Skan 185169695Skanstatic int 186169695Skancs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries) 187169695Skan{ 188169695Skan u_int32_t v; 189169695Skan 190169695Skan while(tries > 0) { 191169695Skan DELAY(100); 192169695Skan v = ~ cs4281_rd(sc, regno); 193169695Skan if (v & mask) break; 194169695Skan tries --; 195169695Skan } 196169695Skan return tries; 197169695Skan} 198169695Skan 199169695Skan/* ------------------------------------------------------------------------- */ 200169695Skan/* Register value mapping functions */ 201169695Skan 202169695Skanstatic u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000}; 203169695Skan#define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0]) 204169695Skan 205169695Skanstatic u_int8_t 206169695Skancs4281_rate_to_rv(u_int32_t rate) 207169695Skan{ 208169695Skan u_int32_t v; 209169695Skan 210169695Skan for (v = 0; v < CS4281_NUM_RATES; v++) { 211169695Skan if (rate == cs4281_rates[v]) return v; 212169695Skan } 213169695Skan 214169695Skan v = 1536000 / rate; 215169695Skan if (v > 255 || v < 32) v = 5; /* default to 8k */ 216169695Skan return v; 217169695Skan} 218169695Skan 219169695Skanstatic u_int32_t 220169695Skancs4281_rv_to_rate(u_int8_t rv) 221169695Skan{ 222169695Skan u_int32_t r; 223169695Skan 224169695Skan if (rv < CS4281_NUM_RATES) return cs4281_rates[rv]; 225169695Skan r = 1536000 / rv; 226169695Skan return r; 227169695Skan} 228169695Skan 229169695Skanstatic inline u_int32_t 230169695Skancs4281_format_to_dmr(u_int32_t format) 231169695Skan{ 232169695Skan u_int32_t dmr = 0; 233169695Skan if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8; 234169695Skan if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO; 235169695Skan if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND; 236169695Skan if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN; 237169695Skan return dmr; 238169695Skan} 239169695Skan 240169695Skanstatic inline u_int32_t 241169695Skancs4281_format_to_bps(u_int32_t format) 242169695Skan{ 243169695Skan return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1); 244169695Skan} 245169695Skan 246169695Skan/* -------------------------------------------------------------------- */ 247169695Skan/* ac97 codec */ 248169695Skan 249169695Skanstatic u_int32_t 250169695Skancs4281_rdcd(kobj_t obj, void *devinfo, int regno) 251169695Skan{ 252169695Skan struct sc_info *sc = (struct sc_info *)devinfo; 253169695Skan int codecno; 254169695Skan 255169695Skan codecno = regno >> 8; 256169695Skan regno &= 0xff; 257169695Skan 258169695Skan /* Remove old state */ 259169695Skan cs4281_rd(sc, CS4281PCI_ACSDA); 260169695Skan 261169695Skan /* Fill in AC97 register value request form */ 262169695Skan cs4281_wr(sc, CS4281PCI_ACCAD, regno); 263169695Skan cs4281_wr(sc, CS4281PCI_ACCDA, 0); 264169695Skan cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 265169695Skan CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV | 266169695Skan CS4281PCI_ACCTL_CRW); 267169695Skan 268169695Skan /* Wait for read to complete */ 269169695Skan if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 270169695Skan device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n"); 271169695Skan return 0xffffffff; 272169695Skan } 273169695Skan 274169695Skan /* Wait for valid status */ 275169695Skan if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) { 276169695Skan device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n"); 277169695Skan return 0xffffffff; 278169695Skan } 279169695Skan 280169695Skan return cs4281_rd(sc, CS4281PCI_ACSDA); 281169695Skan} 282169695Skan 283169695Skanstatic void 284169695Skancs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 285169695Skan{ 286169695Skan struct sc_info *sc = (struct sc_info *)devinfo; 287169695Skan int codecno; 288169695Skan 289169695Skan codecno = regno >> 8; 290169695Skan regno &= 0xff; 291169695Skan 292169695Skan cs4281_wr(sc, CS4281PCI_ACCAD, regno); 293169695Skan cs4281_wr(sc, CS4281PCI_ACCDA, data); 294169695Skan cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 295169695Skan CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV); 296169695Skan 297169695Skan if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 298169695Skan device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n"); 299169695Skan } 300169695Skan} 301169695Skan 302169695Skanstatic kobj_method_t cs4281_ac97_methods[] = { 303169695Skan KOBJMETHOD(ac97_read, cs4281_rdcd), 304169695Skan KOBJMETHOD(ac97_write, cs4281_wrcd), 305169695Skan { 0, 0 } 306169695Skan}; 307169695SkanAC97_DECLARE(cs4281_ac97); 308169695Skan 309169695Skan/* ------------------------------------------------------------------------- */ 310169695Skan/* shared rec/play channel interface */ 311169695Skan 312169695Skanstatic void * 313169695Skancs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 314169695Skan{ 315169695Skan struct sc_info *sc = devinfo; 316169695Skan struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 317169695Skan 318169695Skan ch->buffer = b; 319169695Skan if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 320169695Skan return NULL; 321169695Skan } 322169695Skan ch->parent = sc; 323169695Skan ch->channel = c; 324169695Skan 325169695Skan ch->fmt = AFMT_U8; 326169695Skan ch->spd = DSP_DEFAULT_SPEED; 327169695Skan ch->bps = 1; 328169695Skan ch->blksz = sndbuf_getsize(ch->buffer); 329169695Skan 330169695Skan ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC; 331169695Skan ch->dma_setup = 0; 332169695Skan 333169695Skan adcdac_go(ch, 0); 334169695Skan adcdac_prog(ch); 335169695Skan 336169695Skan return ch; 337169695Skan} 338169695Skan 339169695Skanstatic int 340169695Skancs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 341169695Skan{ 342169695Skan struct sc_chinfo *ch = data; 343169695Skan struct sc_info *sc = ch->parent; 344169695Skan u_int32_t go; 345169695Skan 346169695Skan go = adcdac_go(ch, 0); 347169695Skan 348169695Skan /* 2 interrupts are possible and used in buffer (half-empty,empty), 349169695Skan * hence factor of 2. */ 350169695Skan ch->blksz = MIN(blocksize, sc->bufsz / 2); 351169695Skan sndbuf_resize(ch->buffer, 2, ch->blksz); 352169695Skan ch->dma_setup = 0; 353169695Skan adcdac_prog(ch); 354169695Skan adcdac_go(ch, go); 355169695Skan 356169695Skan DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz)); 357169695Skan 358169695Skan return ch->blksz; 359169695Skan} 360169695Skan 361169695Skanstatic int 362169695Skancs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed) 363169695Skan{ 364169695Skan struct sc_chinfo *ch = data; 365169695Skan struct sc_info *sc = ch->parent; 366169695Skan u_int32_t go, v, r; 367169695Skan 368169695Skan go = adcdac_go(ch, 0); /* pause */ 369169695Skan r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR; 370169695Skan v = cs4281_rate_to_rv(speed); 371169695Skan cs4281_wr(sc, r, v); 372169695Skan adcdac_go(ch, go); /* unpause */ 373169695Skan 374169695Skan ch->spd = cs4281_rv_to_rate(v); 375169695Skan return ch->spd; 376169695Skan} 377169695Skan 378169695Skanstatic int 379169695Skancs4281chan_setformat(kobj_t obj, void *data, u_int32_t format) 380169695Skan{ 381169695Skan struct sc_chinfo *ch = data; 382169695Skan struct sc_info *sc = ch->parent; 383169695Skan u_int32_t v, go; 384169695Skan 385169695Skan go = adcdac_go(ch, 0); /* pause */ 386169695Skan 387169695Skan if (ch->dma_chan == CS4281_DMA_PLAY) 388169695Skan v = CS4281PCI_DMR_TR_PLAY; 389169695Skan else 390169695Skan v = CS4281PCI_DMR_TR_REC; 391169695Skan v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO; 392169695Skan v |= cs4281_format_to_dmr(format); 393169695Skan cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v); 394169695Skan 395169695Skan adcdac_go(ch, go); /* unpause */ 396169695Skan 397169695Skan ch->fmt = format; 398169695Skan ch->bps = cs4281_format_to_bps(format); 399169695Skan ch->dma_setup = 0; 400169695Skan 401169695Skan return 0; 402169695Skan} 403169695Skan 404169695Skanstatic int 405169695Skancs4281chan_getptr(kobj_t obj, void *data) 406169695Skan{ 407169695Skan struct sc_chinfo *ch = data; 408169695Skan struct sc_info *sc = ch->parent; 409169695Skan u_int32_t dba, dca, ptr; 410169695Skan int sz; 411169695Skan 412169695Skan sz = sndbuf_getsize(ch->buffer); 413169695Skan dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan)); 414169695Skan dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan)); 415169695Skan ptr = (dca - dba + sz) % sz; 416169695Skan 417169695Skan return ptr; 418169695Skan} 419169695Skan 420169695Skanstatic int 421169695Skancs4281chan_trigger(kobj_t obj, void *data, int go) 422169695Skan{ 423169695Skan struct sc_chinfo *ch = data; 424169695Skan 425169695Skan switch(go) { 426169695Skan case PCMTRIG_START: 427169695Skan adcdac_prog(ch); 428169695Skan adcdac_go(ch, 1); 429169695Skan break; 430169695Skan case PCMTRIG_STOP: 431169695Skan case PCMTRIG_ABORT: 432169695Skan adcdac_go(ch, 0); 433169695Skan break; 434169695Skan default: 435169695Skan break; 436169695Skan } 437169695Skan 438169695Skan /* return 0 if ok */ 439169695Skan return 0; 440169695Skan} 441169695Skan 442169695Skanstatic struct pcmchan_caps * 443169695Skancs4281chan_getcaps(kobj_t obj, void *data) 444169695Skan{ 445169695Skan return &cs4281_caps; 446169695Skan} 447169695Skan 448169695Skanstatic kobj_method_t cs4281chan_methods[] = { 449169695Skan KOBJMETHOD(channel_init, cs4281chan_init), 450169695Skan KOBJMETHOD(channel_setformat, cs4281chan_setformat), 451169695Skan KOBJMETHOD(channel_setspeed, cs4281chan_setspeed), 452169695Skan KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize), 453169695Skan KOBJMETHOD(channel_trigger, cs4281chan_trigger), 454169695Skan KOBJMETHOD(channel_getptr, cs4281chan_getptr), 455169695Skan KOBJMETHOD(channel_getcaps, cs4281chan_getcaps), 456169695Skan { 0, 0 } 457169695Skan}; 458169695SkanCHANNEL_DECLARE(cs4281chan); 459169695Skan 460169695Skan/* -------------------------------------------------------------------- */ 461169695Skan/* ADC/DAC control */ 462169695Skan 463169695Skan/* adcdac_go enables/disable DMA channel, returns non-zero if DMA was 464169695Skan * active before call */ 465169695Skan 466169695Skanstatic u_int32_t 467169695Skanadcdac_go(struct sc_chinfo *ch, u_int32_t go) 468169695Skan{ 469169695Skan struct sc_info *sc = ch->parent; 470169695Skan u_int32_t going; 471169695Skan 472169695Skan going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK); 473169695Skan 474169695Skan if (go) 475169695Skan cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 476169695Skan else 477169695Skan cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 478169695Skan 479169695Skan cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 480169695Skan 481169695Skan return going; 482169695Skan} 483169695Skan 484169695Skanstatic void 485169695Skanadcdac_prog(struct sc_chinfo *ch) 486169695Skan{ 487169695Skan struct sc_info *sc = ch->parent; 488169695Skan u_int32_t go; 489169695Skan 490169695Skan if (!ch->dma_setup) { 491169695Skan go = adcdac_go(ch, 0); 492169695Skan cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan), 493169695Skan sndbuf_getbufaddr(ch->buffer)); 494169695Skan cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan), 495169695Skan sndbuf_getsize(ch->buffer) / ch->bps - 1); 496169695Skan ch->dma_setup = 1; 497169695Skan adcdac_go(ch, go); 498169695Skan } 499169695Skan} 500169695Skan 501169695Skan/* -------------------------------------------------------------------- */ 502169695Skan/* The interrupt handler */ 503169695Skan 504169695Skanstatic void 505169695Skancs4281_intr(void *p) 506169695Skan{ 507169695Skan struct sc_info *sc = (struct sc_info *)p; 508169695Skan u_int32_t hisr; 509169695Skan 510169695Skan hisr = cs4281_rd(sc, CS4281PCI_HISR); 511169695Skan 512169695Skan if (hisr == 0) return; 513169695Skan 514169695Skan if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) { 515169695Skan chn_intr(sc->pch.channel); 516169695Skan cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */ 517169695Skan } 518169695Skan 519169695Skan if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) { 520169695Skan chn_intr(sc->rch.channel); 521169695Skan cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */ 522169695Skan } 523169695Skan 524169695Skan /* Signal End-of-Interrupt */ 525169695Skan cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 526169695Skan} 527169695Skan 528169695Skan/* -------------------------------------------------------------------- */ 529169695Skan/* power management related */ 530169695Skan 531169695Skanstatic int 532169695Skancs4281_power(struct sc_info *sc, int state) 533169695Skan{ 534169695Skan 535169695Skan switch (state) { 536169695Skan case 0: 537169695Skan /* Permit r/w access to all BA0 registers */ 538169695Skan cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC); 539169695Skan /* Power on */ 540169695Skan cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 541169695Skan break; 542169695Skan case 3: 543169695Skan /* Power off card and codec */ 544169695Skan cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 545169695Skan cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 546 break; 547 } 548 549 DEB(printf("cs4281_power %d -> %d\n", sc->power, state)); 550 sc->power = state; 551 552 return 0; 553} 554 555static int 556cs4281_init(struct sc_info *sc) 557{ 558 u_int32_t i, v; 559 560 /* (0) Blast clock register and serial port */ 561 cs4281_wr(sc, CS4281PCI_CLKCR1, 0); 562 cs4281_wr(sc, CS4281PCI_SERMC, 0); 563 564 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */ 565 cs4281_wr(sc, CS4281PCI_ACCTL, 0); 566 DELAY(50); 567 568 /* (2) Effect Reset */ 569 cs4281_wr(sc, CS4281PCI_SPMC, 0); 570 DELAY(100); 571 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 572 /* Wait 50ms for ABITCLK to become stable */ 573 DELAY(50000); 574 575 /* (3) Enable Sound System Clocks */ 576 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP); 577 DELAY(50000); /* Wait for PLL to stabilize */ 578 cs4281_wr(sc, CS4281PCI_CLKCR1, 579 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE); 580 581 /* (4) Power Up - this combination is essential. */ 582 cs4281_set4(sc, CS4281PCI_SSPM, 583 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN | 584 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN); 585 586 /* (5) Wait for clock stabilization */ 587 if (cs4281_waitset(sc, 588 CS4281PCI_CLKCR1, 589 CS4281PCI_CLKCR1_DLLRDY, 590 250) == 0) { 591 device_printf(sc->dev, "Clock stabilization failed\n"); 592 return -1; 593 } 594 595 /* (6) Enable ASYNC generation. */ 596 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN); 597 598 /* Wait to allow AC97 to start generating clock bit */ 599 DELAY(50000); 600 601 /* Set AC97 timing */ 602 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 603 604 /* (7) Wait for AC97 ready signal */ 605 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) { 606 device_printf(sc->dev, "codec did not avail\n"); 607 return -1; 608 } 609 610 /* (8) Assert valid frame signal to begin sending commands to 611 * AC97 codec */ 612 cs4281_wr(sc, 613 CS4281PCI_ACCTL, 614 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN); 615 616 /* (9) Wait for codec calibration */ 617 for(i = 0 ; i < 1000; i++) { 618 DELAY(10000); 619 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 620 if ((v & 0x0f) == 0x0f) { 621 break; 622 } 623 } 624 if (i == 1000) { 625 device_printf(sc->dev, "codec failed to calibrate\n"); 626 return -1; 627 } 628 629 /* (10) Set AC97 timing */ 630 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 631 632 /* (11) Wait for valid data to arrive */ 633 if (cs4281_waitset(sc, 634 CS4281PCI_ACISV, 635 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4), 636 10000) == 0) { 637 device_printf(sc->dev, "cs4281 never got valid data\n"); 638 return -1; 639 } 640 641 /* (12) Start digital data transfer of audio data to codec */ 642 cs4281_wr(sc, 643 CS4281PCI_ACOSV, 644 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4)); 645 646 /* Set Master and headphone to max */ 647 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0); 648 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0); 649 650 /* Power on the DAC */ 651 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff; 652 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 653 654 /* Wait until DAC state ready */ 655 for(i = 0; i < 320; i++) { 656 DELAY(100); 657 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 658 if (v & 0x02) break; 659 } 660 661 /* Power on the ADC */ 662 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff; 663 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 664 665 /* Wait until ADC state ready */ 666 for(i = 0; i < 320; i++) { 667 DELAY(100); 668 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 669 if (v & 0x01) break; 670 } 671 672 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */ 673 /* Play FIFO */ 674 675 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) | 676 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) | 677 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 678 CS4281PCI_FCR_OF(0); 679 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v); 680 681 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN); 682 683 /* Record FIFO */ 684 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) | 685 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) | 686 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 687 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1); 688 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH); 689 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN); 690 691 /* Match AC97 slots to FIFOs */ 692 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) | 693 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) | 694 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) | 695 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT); 696 cs4281_wr(sc, CS4281PCI_SRCSA, v); 697 698 /* Set Auto-Initialize and set directions */ 699 cs4281_wr(sc, 700 CS4281PCI_DMR(CS4281_DMA_PLAY), 701 CS4281PCI_DMR_DMA | 702 CS4281PCI_DMR_AUTO | 703 CS4281PCI_DMR_TR_PLAY); 704 cs4281_wr(sc, 705 CS4281PCI_DMR(CS4281_DMA_REC), 706 CS4281PCI_DMR_DMA | 707 CS4281PCI_DMR_AUTO | 708 CS4281PCI_DMR_TR_REC); 709 710 /* Enable half and empty buffer interrupts keeping DMA paused */ 711 cs4281_wr(sc, 712 CS4281PCI_DCR(CS4281_DMA_PLAY), 713 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 714 cs4281_wr(sc, 715 CS4281PCI_DCR(CS4281_DMA_REC), 716 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 717 718 /* Enable Interrupts */ 719 cs4281_clr4(sc, 720 CS4281PCI_HIMR, 721 CS4281PCI_HIMR_DMAI | 722 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) | 723 CS4281PCI_HIMR_DMA(CS4281_DMA_REC)); 724 725 /* Set playback volume */ 726 cs4281_wr(sc, CS4281PCI_PPLVC, 7); 727 cs4281_wr(sc, CS4281PCI_PPRVC, 7); 728 729 return 0; 730} 731 732/* -------------------------------------------------------------------- */ 733/* Probe and attach the card */ 734 735static int 736cs4281_pci_probe(device_t dev) 737{ 738 char *s = NULL; 739 740 switch (pci_get_devid(dev)) { 741 case CS4281_PCI_ID: 742 s = "Crystal Semiconductor CS4281"; 743 break; 744 } 745 746 if (s) 747 device_set_desc(dev, s); 748 return s ? BUS_PROBE_DEFAULT : ENXIO; 749} 750 751static int 752cs4281_pci_attach(device_t dev) 753{ 754 struct sc_info *sc; 755 struct ac97_info *codec = NULL; 756 u_int32_t data; 757 char status[SND_STATUSLEN]; 758 759 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 760 sc->dev = dev; 761 sc->type = pci_get_devid(dev); 762 763 data = pci_read_config(dev, PCIR_COMMAND, 2); 764 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 765 pci_write_config(dev, PCIR_COMMAND, data, 2); 766 767#if __FreeBSD_version > 500000 768 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 769 /* Reset the power state. */ 770 device_printf(dev, "chip is in D%d power mode " 771 "-- setting to D0\n", pci_get_powerstate(dev)); 772 773 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 774 } 775#else 776 data = pci_read_config(dev, CS4281PCI_PMCS_OFFSET, 4); 777 if (data & CS4281PCI_PMCS_PS_MASK) { 778 /* Reset the power state. */ 779 device_printf(dev, "chip is in D%d power mode " 780 "-- setting to D0\n", 781 data & CS4281PCI_PMCS_PS_MASK); 782 pci_write_config(dev, CS4281PCI_PMCS_OFFSET, 783 data & ~CS4281PCI_PMCS_PS_MASK, 4); 784 } 785#endif 786 787 sc->regid = PCIR_BAR(0); 788 sc->regtype = SYS_RES_MEMORY; 789 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 790 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE); 791 if (!sc->reg) { 792 sc->regtype = SYS_RES_IOPORT; 793 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, 794 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE); 795 if (!sc->reg) { 796 device_printf(dev, "unable to allocate register space\n"); 797 goto bad; 798 } 799 } 800 sc->st = rman_get_bustag(sc->reg); 801 sc->sh = rman_get_bushandle(sc->reg); 802 803 sc->memid = PCIR_BAR(1); 804 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0, 805 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE); 806 if (sc->mem == NULL) { 807 device_printf(dev, "unable to allocate fifo space\n"); 808 goto bad; 809 } 810 811 sc->irqid = 0; 812 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 813 RF_ACTIVE | RF_SHAREABLE); 814 if (!sc->irq) { 815 device_printf(dev, "unable to allocate interrupt\n"); 816 goto bad; 817 } 818 819 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) { 820 device_printf(dev, "unable to setup interrupt\n"); 821 goto bad; 822 } 823 824 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536); 825 826 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 827 /*boundary*/0, 828 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 829 /*highaddr*/BUS_SPACE_MAXADDR, 830 /*filter*/NULL, /*filterarg*/NULL, 831 /*maxsize*/sc->bufsz, /*nsegments*/1, 832 /*maxsegz*/0x3ffff, 833 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 834 /*lockarg*/&Giant, &sc->parent_dmat) != 0) { 835 device_printf(dev, "unable to create dma tag\n"); 836 goto bad; 837 } 838 839 /* power up */ 840 cs4281_power(sc, 0); 841 842 /* init chip */ 843 if (cs4281_init(sc) == -1) { 844 device_printf(dev, "unable to initialize the card\n"); 845 goto bad; 846 } 847 848 /* create/init mixer */ 849 codec = AC97_CREATE(dev, sc, cs4281_ac97); 850 if (codec == NULL) 851 goto bad; 852 853 mixer_init(dev, ac97_getmixerclass(), codec); 854 855 if (pcm_register(dev, sc, 1, 1)) 856 goto bad; 857 858 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc); 859 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc); 860 861 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 862 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 863 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281)); 864 pcm_setstatus(dev, status); 865 866 return 0; 867 868 bad: 869 if (codec) 870 ac97_destroy(codec); 871 if (sc->reg) 872 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 873 if (sc->mem) 874 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 875 if (sc->ih) 876 bus_teardown_intr(dev, sc->irq, sc->ih); 877 if (sc->irq) 878 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 879 if (sc->parent_dmat) 880 bus_dma_tag_destroy(sc->parent_dmat); 881 free(sc, M_DEVBUF); 882 883 return ENXIO; 884} 885 886static int 887cs4281_pci_detach(device_t dev) 888{ 889 int r; 890 struct sc_info *sc; 891 892 r = pcm_unregister(dev); 893 if (r) 894 return r; 895 896 sc = pcm_getdevinfo(dev); 897 898 /* power off */ 899 cs4281_power(sc, 3); 900 901 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 902 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 903 bus_teardown_intr(dev, sc->irq, sc->ih); 904 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 905 bus_dma_tag_destroy(sc->parent_dmat); 906 free(sc, M_DEVBUF); 907 908 return 0; 909} 910 911static int 912cs4281_pci_suspend(device_t dev) 913{ 914 struct sc_info *sc; 915 916 sc = pcm_getdevinfo(dev); 917 918 sc->rch.dma_active = adcdac_go(&sc->rch, 0); 919 sc->pch.dma_active = adcdac_go(&sc->pch, 0); 920 921 cs4281_power(sc, 3); 922 923 return 0; 924} 925 926static int 927cs4281_pci_resume(device_t dev) 928{ 929 struct sc_info *sc; 930 931 sc = pcm_getdevinfo(dev); 932 933 /* power up */ 934 cs4281_power(sc, 0); 935 936 /* initialize chip */ 937 if (cs4281_init(sc) == -1) { 938 device_printf(dev, "unable to reinitialize the card\n"); 939 return ENXIO; 940 } 941 942 /* restore mixer state */ 943 if (mixer_reinit(dev) == -1) { 944 device_printf(dev, "unable to reinitialize the mixer\n"); 945 return ENXIO; 946 } 947 948 /* restore chip state */ 949 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd); 950 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz); 951 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt); 952 adcdac_go(&sc->rch, sc->rch.dma_active); 953 954 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd); 955 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz); 956 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt); 957 adcdac_go(&sc->pch, sc->pch.dma_active); 958 959 return 0; 960} 961 962static device_method_t cs4281_methods[] = { 963 /* Device interface */ 964 DEVMETHOD(device_probe, cs4281_pci_probe), 965 DEVMETHOD(device_attach, cs4281_pci_attach), 966 DEVMETHOD(device_detach, cs4281_pci_detach), 967 DEVMETHOD(device_suspend, cs4281_pci_suspend), 968 DEVMETHOD(device_resume, cs4281_pci_resume), 969 { 0, 0 } 970}; 971 972static driver_t cs4281_driver = { 973 "pcm", 974 cs4281_methods, 975 PCM_SOFTC_SIZE, 976}; 977 978DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0); 979MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 980MODULE_VERSION(snd_cs4281, 1); 981