cmi.c revision 166904
1279377Simp/*- 2279377Simp * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3279377Simp * All rights reserved. 4279377Simp * 5279377Simp * Redistribution and use in source and binary forms, with or without 6279377Simp * modification, are permitted provided that the following conditions 7279377Simp * are met: 8279377Simp * 1. Redistributions of source code must retain the above copyright 9279377Simp * notice, this list of conditions and the following disclaimer. 10279377Simp * 2. Redistributions in binary form must reproduce the above copyright 11279377Simp * notice, this list of conditions and the following disclaimer in the 12279377Simp * documentation and/or other materials provided with the distribution. 13279377Simp * 14279377Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15279377Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16279377Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17279377Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18279377Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19279377Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20279377Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21279377Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22279377Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23279377Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24279377Simp * SUCH DAMAGE. 25279377Simp * 26279377Simp * This driver exists largely as a result of other people's efforts. 27279377Simp * Much of register handling is based on NetBSD CMI8x38 audio driver 28279377Simp * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 29279377Simp * <cltien@cmedia.com.tw> clarified points regarding the DMA related 30279377Simp * registers and the 8738 mixer devices. His Linux driver was also a 31279377Simp * useful reference point. 32279377Simp * 33279377Simp * TODO: MIDI 34279377Simp * 35279377Simp * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 36279377Simp * 37279377Simp * This card/code does not always manage to sample at 44100 - actual 38279377Simp * rate drifts slightly between recordings (usually 0-3%). No 39279377Simp * differences visible in register dumps between times that work and 40279377Simp * those that don't. 41279377Simp */ 42279377Simp 43279377Simp#include <dev/sound/pcm/sound.h> 44279377Simp#include <dev/sound/pci/cmireg.h> 45279377Simp#include <dev/sound/isa/sb.h> 46279377Simp 47279377Simp#include <dev/pci/pcireg.h> 48279377Simp#include <dev/pci/pcivar.h> 49279377Simp 50279377Simp#include <sys/sysctl.h> 51279377Simp#include <dev/sound/midi/mpu401.h> 52279377Simp 53279377Simp#include "mixer_if.h" 54279377Simp#include "mpufoi_if.h" 55279377Simp 56279377SimpSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cmi.c 166904 2007-02-23 13:47:34Z netchild $"); 57279377Simp 58279377Simp/* Supported chip ID's */ 59279377Simp#define CMI8338A_PCI_ID 0x010013f6 60279377Simp#define CMI8338B_PCI_ID 0x010113f6 61279377Simp#define CMI8738_PCI_ID 0x011113f6 62279377Simp#define CMI8738B_PCI_ID 0x011213f6 63279377Simp 64279377Simp/* Buffer size max is 64k for permitted DMA boundaries */ 65279377Simp#define CMI_DEFAULT_BUFSZ 16384 66279377Simp 67279377Simp/* Interrupts per length of buffer */ 68279377Simp#define CMI_INTR_PER_BUFFER 2 69279377Simp 70279377Simp/* Clarify meaning of named defines in cmireg.h */ 71279377Simp#define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 72279377Simp#define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 73279377Simp#define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 74279377Simp#define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 75279377Simp 76279377Simp/* Our indication of custom mixer control */ 77279377Simp#define CMPCI_NON_SB16_CONTROL 0xff 78279377Simp 79279377Simp/* Debugging macro's */ 80279377Simp#undef DEB 81279377Simp#ifndef DEB 82279377Simp#define DEB(x) /* x */ 83279377Simp#endif /* DEB */ 84279377Simp 85279377Simp#ifndef DEBMIX 86279377Simp#define DEBMIX(x) /* x */ 87279377Simp#endif /* DEBMIX */ 88279377Simp 89279377Simp/* ------------------------------------------------------------------------- */ 90279377Simp/* Structures */ 91279377Simp 92279377Simpstruct sc_info; 93279377Simp 94279377Simpstruct sc_chinfo { 95279377Simp struct sc_info *parent; 96279377Simp struct pcm_channel *channel; 97279377Simp struct snd_dbuf *buffer; 98279377Simp u_int32_t fmt, spd, phys_buf, bps; 99279377Simp u_int32_t dma_active:1, dma_was_active:1; 100279377Simp int dir; 101279377Simp}; 102279377Simp 103279377Simpstruct sc_info { 104279377Simp device_t dev; 105279377Simp 106279377Simp bus_space_tag_t st; 107279377Simp bus_space_handle_t sh; 108279377Simp bus_dma_tag_t parent_dmat; 109279377Simp struct resource *reg, *irq; 110279377Simp int regid, irqid; 111279377Simp void *ih; 112279377Simp struct mtx *lock; 113279377Simp 114279377Simp int spdif_enabled; 115279377Simp unsigned int bufsz; 116279377Simp struct sc_chinfo pch, rch; 117279377Simp 118279377Simp struct mpu401 *mpu; 119279377Simp mpu401_intr_t *mpu_intr; 120279377Simp struct resource *mpu_reg; 121279377Simp int mpu_regid; 122279377Simp bus_space_tag_t mpu_bt; 123279377Simp bus_space_handle_t mpu_bh; 124279377Simp}; 125279377Simp 126279377Simp/* Channel caps */ 127279377Simp 128279377Simpstatic u_int32_t cmi_fmt[] = { 129279377Simp AFMT_U8, 130279377Simp AFMT_STEREO | AFMT_U8, 131279377Simp AFMT_S16_LE, 132279377Simp AFMT_STEREO | AFMT_S16_LE, 133279377Simp 0 134279377Simp}; 135279377Simp 136279377Simpstatic struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 137279377Simp 138279377Simp/* ------------------------------------------------------------------------- */ 139279377Simp/* Register Utilities */ 140279377Simp 141279377Simpstatic u_int32_t 142279377Simpcmi_rd(struct sc_info *sc, int regno, int size) 143279377Simp{ 144279377Simp switch (size) { 145279377Simp case 1: 146279377Simp return bus_space_read_1(sc->st, sc->sh, regno); 147279377Simp case 2: 148279377Simp return bus_space_read_2(sc->st, sc->sh, regno); 149279377Simp case 4: 150279377Simp return bus_space_read_4(sc->st, sc->sh, regno); 151279377Simp default: 152279377Simp DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 153279377Simp return 0xFFFFFFFF; 154279377Simp } 155279377Simp} 156279377Simp 157279377Simpstatic void 158279377Simpcmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 159279377Simp{ 160279377Simp switch (size) { 161279377Simp case 1: 162279377Simp bus_space_write_1(sc->st, sc->sh, regno, data); 163279377Simp break; 164279377Simp case 2: 165279377Simp bus_space_write_2(sc->st, sc->sh, regno, data); 166279377Simp break; 167279377Simp case 4: 168279377Simp bus_space_write_4(sc->st, sc->sh, regno, data); 169279377Simp break; 170279377Simp } 171279377Simp} 172279377Simp 173279377Simpstatic void 174279377Simpcmi_partial_wr4(struct sc_info *sc, 175279377Simp int reg, int shift, u_int32_t mask, u_int32_t val) 176279377Simp{ 177279377Simp u_int32_t r; 178279377Simp 179279377Simp r = cmi_rd(sc, reg, 4); 180279377Simp r &= ~(mask << shift); 181279377Simp r |= val << shift; 182279377Simp cmi_wr(sc, reg, r, 4); 183279377Simp} 184279377Simp 185279377Simpstatic void 186279377Simpcmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 187279377Simp{ 188279377Simp u_int32_t r; 189279377Simp 190279377Simp r = cmi_rd(sc, reg, 4); 191279377Simp r &= ~mask; 192279377Simp cmi_wr(sc, reg, r, 4); 193279377Simp} 194279377Simp 195279377Simpstatic void 196279377Simpcmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 197279377Simp{ 198279377Simp u_int32_t r; 199279377Simp 200279377Simp r = cmi_rd(sc, reg, 4); 201279377Simp r |= mask; 202279377Simp cmi_wr(sc, reg, r, 4); 203279377Simp} 204279377Simp 205279377Simp/* ------------------------------------------------------------------------- */ 206279377Simp/* Rate Mapping */ 207279377Simp 208279377Simpstatic int cmi_rates[] = {5512, 8000, 11025, 16000, 209279377Simp 22050, 32000, 44100, 48000}; 210279377Simp#define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 211279377Simp 212279377Simp/* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 213279377Simp * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 214279377Simp 215279377Simpstatic u_int32_t 216279377Simpcmpci_rate_to_regvalue(int rate) 217279377Simp{ 218279377Simp int i, r; 219279377Simp 220279377Simp for(i = 0; i < NUM_CMI_RATES - 1; i++) { 221279377Simp if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 222279377Simp break; 223279377Simp } 224279377Simp } 225279377Simp 226279377Simp DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 227279377Simp 228279377Simp r = ((i >> 1) | (i << 2)) & 0x07; 229279377Simp return r; 230279377Simp} 231279377Simp 232279377Simpstatic int 233279377Simpcmpci_regvalue_to_rate(u_int32_t r) 234279377Simp{ 235279377Simp int i; 236279377Simp 237279377Simp i = ((r << 1) | (r >> 2)) & 0x07; 238279377Simp DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 239279377Simp return cmi_rates[i]; 240279377Simp} 241279377Simp 242279377Simp/* ------------------------------------------------------------------------- */ 243279377Simp/* ADC/DAC control - there are 2 dma channels on 8738, either can be 244279377Simp * playback or capture. We use ch0 for playback and ch1 for capture. */ 245279377Simp 246279377Simpstatic void 247279377Simpcmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 248279377Simp{ 249279377Simp u_int32_t s, i, sz; 250279377Simp 251279377Simp ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 252279377Simp 253279377Simp cmi_wr(sc, base, ch->phys_buf, 4); 254279377Simp sz = (u_int32_t)sndbuf_getsize(ch->buffer); 255279377Simp 256279377Simp s = sz / ch->bps - 1; 257279377Simp cmi_wr(sc, base + 4, s, 2); 258279377Simp 259279377Simp i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 260279377Simp cmi_wr(sc, base + 6, i, 2); 261279377Simp} 262279377Simp 263279377Simp 264279377Simpstatic void 265279377Simpcmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 266279377Simp{ 267279377Simp cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 268279377Simp 269279377Simp cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 270279377Simp cmi_set4(sc, CMPCI_REG_INTR_CTRL, 271279377Simp CMPCI_REG_CH0_INTR_ENABLE); 272279377Simp 273279377Simp ch->dma_active = 1; 274279377Simp} 275279377Simp 276279377Simpstatic u_int32_t 277279377Simpcmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 278279377Simp{ 279279377Simp u_int32_t r = ch->dma_active; 280279377Simp 281279377Simp cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 282279377Simp cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 283279377Simp cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 284279377Simp cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 285279377Simp ch->dma_active = 0; 286279377Simp return r; 287279377Simp} 288279377Simp 289279377Simpstatic void 290279377Simpcmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 291279377Simp{ 292279377Simp cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 293279377Simp cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 294279377Simp /* Enable Interrupts */ 295279377Simp cmi_set4(sc, CMPCI_REG_INTR_CTRL, 296279377Simp CMPCI_REG_CH1_INTR_ENABLE); 297279377Simp DEB(printf("cmi_ch1_start: dma prog\n")); 298279377Simp ch->dma_active = 1; 299279377Simp} 300279377Simp 301279377Simpstatic u_int32_t 302279377Simpcmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 303279377Simp{ 304279377Simp u_int32_t r = ch->dma_active; 305279377Simp 306279377Simp cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 307279377Simp cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 308279377Simp cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 309279377Simp cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 310279377Simp ch->dma_active = 0; 311279377Simp return r; 312279377Simp} 313279377Simp 314279377Simpstatic void 315279377Simpcmi_spdif_speed(struct sc_info *sc, int speed) { 316279377Simp u_int32_t fcr1, lcr, mcr; 317279377Simp 318279377Simp if (speed >= 44100) { 319279377Simp fcr1 = CMPCI_REG_SPDIF0_ENABLE; 320279377Simp lcr = CMPCI_REG_XSPDIF_ENABLE; 321279377Simp mcr = (speed == 48000) ? 322279377Simp CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 323279377Simp } else { 324279377Simp fcr1 = mcr = lcr = 0; 325279377Simp } 326279377Simp 327279377Simp cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 328279377Simp CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 329279377Simp cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 330279377Simp CMPCI_REG_SPDIF0_ENABLE, fcr1); 331279377Simp cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 332279377Simp CMPCI_REG_XSPDIF_ENABLE, lcr); 333279377Simp} 334279377Simp 335279377Simp/* ------------------------------------------------------------------------- */ 336279377Simp/* Channel Interface implementation */ 337279377Simp 338279377Simpstatic void * 339279377Simpcmichan_init(kobj_t obj, void *devinfo, 340279377Simp struct snd_dbuf *b, struct pcm_channel *c, int dir) 341279377Simp{ 342279377Simp struct sc_info *sc = devinfo; 343279377Simp struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 344279377Simp 345279377Simp ch->parent = sc; 346279377Simp ch->channel = c; 347279377Simp ch->bps = 1; 348279377Simp ch->fmt = AFMT_U8; 349279377Simp ch->spd = DSP_DEFAULT_SPEED; 350279377Simp ch->buffer = b; 351279377Simp ch->dma_active = 0; 352279377Simp if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) { 353279377Simp DEB(printf("cmichan_init failed\n")); 354279377Simp return NULL; 355279377Simp } 356279377Simp 357279377Simp ch->dir = dir; 358279377Simp snd_mtxlock(sc->lock); 359279377Simp if (ch->dir == PCMDIR_PLAY) { 360279377Simp cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 361279377Simp } else { 362279377Simp cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 363279377Simp } 364279377Simp snd_mtxunlock(sc->lock); 365279377Simp 366279377Simp return ch; 367279377Simp} 368279377Simp 369279377Simpstatic int 370279377Simpcmichan_setformat(kobj_t obj, void *data, u_int32_t format) 371279377Simp{ 372279377Simp struct sc_chinfo *ch = data; 373279377Simp struct sc_info *sc = ch->parent; 374279377Simp u_int32_t f; 375279377Simp 376279377Simp if (format & AFMT_S16_LE) { 377279377Simp f = CMPCI_REG_FORMAT_16BIT; 378279377Simp ch->bps = 2; 379279377Simp } else { 380279377Simp f = CMPCI_REG_FORMAT_8BIT; 381279377Simp ch->bps = 1; 382279377Simp } 383279377Simp 384279377Simp if (format & AFMT_STEREO) { 385279377Simp f |= CMPCI_REG_FORMAT_STEREO; 386279377Simp ch->bps *= 2; 387279377Simp } else { 388279377Simp f |= CMPCI_REG_FORMAT_MONO; 389279377Simp } 390279377Simp 391279377Simp snd_mtxlock(sc->lock); 392279377Simp if (ch->dir == PCMDIR_PLAY) { 393279377Simp cmi_partial_wr4(ch->parent, 394279377Simp CMPCI_REG_CHANNEL_FORMAT, 395279377Simp CMPCI_REG_CH0_FORMAT_SHIFT, 396279377Simp CMPCI_REG_CH0_FORMAT_MASK, 397279377Simp f); 398279377Simp } else { 399279377Simp cmi_partial_wr4(ch->parent, 400279377Simp CMPCI_REG_CHANNEL_FORMAT, 401279377Simp CMPCI_REG_CH1_FORMAT_SHIFT, 402279377Simp CMPCI_REG_CH1_FORMAT_MASK, 403279377Simp f); 404279377Simp } 405279377Simp snd_mtxunlock(sc->lock); 406279377Simp ch->fmt = format; 407279377Simp 408279377Simp return 0; 409279377Simp} 410279377Simp 411279377Simpstatic int 412279377Simpcmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 413279377Simp{ 414279377Simp struct sc_chinfo *ch = data; 415279377Simp struct sc_info *sc = ch->parent; 416279377Simp u_int32_t r, rsp; 417279377Simp 418279377Simp r = cmpci_rate_to_regvalue(speed); 419279377Simp snd_mtxlock(sc->lock); 420279377Simp if (ch->dir == PCMDIR_PLAY) { 421279377Simp if (speed < 44100) { 422279377Simp /* disable if req before rate change */ 423279377Simp cmi_spdif_speed(ch->parent, speed); 424279377Simp } 425279377Simp cmi_partial_wr4(ch->parent, 426279377Simp CMPCI_REG_FUNC_1, 427279377Simp CMPCI_REG_DAC_FS_SHIFT, 428279377Simp CMPCI_REG_DAC_FS_MASK, 429279377Simp r); 430279377Simp if (speed >= 44100 && ch->parent->spdif_enabled) { 431279377Simp /* enable if req after rate change */ 432279377Simp cmi_spdif_speed(ch->parent, speed); 433279377Simp } 434279377Simp rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 435279377Simp rsp >>= CMPCI_REG_DAC_FS_SHIFT; 436279377Simp rsp &= CMPCI_REG_DAC_FS_MASK; 437279377Simp } else { 438279377Simp cmi_partial_wr4(ch->parent, 439279377Simp CMPCI_REG_FUNC_1, 440279377Simp CMPCI_REG_ADC_FS_SHIFT, 441279377Simp CMPCI_REG_ADC_FS_MASK, 442279377Simp r); 443279377Simp rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 444279377Simp rsp >>= CMPCI_REG_ADC_FS_SHIFT; 445279377Simp rsp &= CMPCI_REG_ADC_FS_MASK; 446279377Simp } 447279377Simp snd_mtxunlock(sc->lock); 448279377Simp ch->spd = cmpci_regvalue_to_rate(r); 449279377Simp 450279377Simp DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 451279377Simp (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 452279377Simp speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 453279377Simp 454279377Simp return ch->spd; 455279377Simp} 456279377Simp 457279377Simpstatic int 458279377Simpcmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 459279377Simp{ 460279377Simp struct sc_chinfo *ch = data; 461279377Simp struct sc_info *sc = ch->parent; 462279377Simp 463279377Simp /* user has requested interrupts every blocksize bytes */ 464279377Simp if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 465279377Simp blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 466279377Simp } 467279377Simp sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 468279377Simp 469279377Simp return blocksize; 470279377Simp} 471279377Simp 472279377Simpstatic int 473279377Simpcmichan_trigger(kobj_t obj, void *data, int go) 474279377Simp{ 475279377Simp struct sc_chinfo *ch = data; 476279377Simp struct sc_info *sc = ch->parent; 477279377Simp 478279377Simp snd_mtxlock(sc->lock); 479279377Simp if (ch->dir == PCMDIR_PLAY) { 480279377Simp switch(go) { 481279377Simp case PCMTRIG_START: 482279377Simp cmi_ch0_start(sc, ch); 483279377Simp break; 484279377Simp case PCMTRIG_ABORT: 485279377Simp cmi_ch0_stop(sc, ch); 486279377Simp break; 487279377Simp } 488279377Simp } else { 489279377Simp switch(go) { 490279377Simp case PCMTRIG_START: 491279377Simp cmi_ch1_start(sc, ch); 492279377Simp break; 493279377Simp case PCMTRIG_ABORT: 494279377Simp cmi_ch1_stop(sc, ch); 495279377Simp break; 496279377Simp } 497279377Simp } 498279377Simp snd_mtxunlock(sc->lock); 499279377Simp return 0; 500279377Simp} 501279377Simp 502279377Simpstatic int 503279377Simpcmichan_getptr(kobj_t obj, void *data) 504279377Simp{ 505279377Simp struct sc_chinfo *ch = data; 506279377Simp struct sc_info *sc = ch->parent; 507279377Simp u_int32_t physptr, bufptr, sz; 508279377Simp 509279377Simp snd_mtxlock(sc->lock); 510279377Simp if (ch->dir == PCMDIR_PLAY) { 511279377Simp physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 512279377Simp } else { 513279377Simp physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 514279377Simp } 515279377Simp snd_mtxunlock(sc->lock); 516279377Simp 517279377Simp sz = sndbuf_getsize(ch->buffer); 518279377Simp bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 519279377Simp 520279377Simp return bufptr; 521279377Simp} 522279377Simp 523279377Simpstatic void 524279377Simpcmi_intr(void *data) 525279377Simp{ 526279377Simp struct sc_info *sc = data; 527279377Simp u_int32_t intrstat; 528279377Simp u_int32_t toclear; 529279377Simp 530279377Simp snd_mtxlock(sc->lock); 531279377Simp intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 532279377Simp if ((intrstat & CMPCI_REG_ANY_INTR) != 0) { 533279377Simp 534279377Simp toclear = 0; 535279377Simp if (intrstat & CMPCI_REG_CH0_INTR) { 536279377Simp toclear |= CMPCI_REG_CH0_INTR_ENABLE; 537279377Simp //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 538279377Simp } 539279377Simp 540279377Simp if (intrstat & CMPCI_REG_CH1_INTR) { 541279377Simp toclear |= CMPCI_REG_CH1_INTR_ENABLE; 542279377Simp //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 543279377Simp } 544279377Simp 545279377Simp if (toclear) { 546279377Simp cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear); 547279377Simp snd_mtxunlock(sc->lock); 548279377Simp 549279377Simp /* Signal interrupts to channel */ 550279377Simp if (intrstat & CMPCI_REG_CH0_INTR) { 551279377Simp chn_intr(sc->pch.channel); 552279377Simp } 553279377Simp 554279377Simp if (intrstat & CMPCI_REG_CH1_INTR) { 555279377Simp chn_intr(sc->rch.channel); 556279377Simp } 557279377Simp 558279377Simp snd_mtxlock(sc->lock); 559279377Simp cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear); 560279377Simp 561279377Simp } 562279377Simp } 563279377Simp if(sc->mpu_intr) { 564279377Simp (sc->mpu_intr)(sc->mpu); 565279377Simp } 566279377Simp snd_mtxunlock(sc->lock); 567279377Simp return; 568279377Simp} 569279377Simp 570279377Simpstatic struct pcmchan_caps * 571279377Simpcmichan_getcaps(kobj_t obj, void *data) 572279377Simp{ 573279377Simp return &cmi_caps; 574279377Simp} 575279377Simp 576279377Simpstatic kobj_method_t cmichan_methods[] = { 577279377Simp KOBJMETHOD(channel_init, cmichan_init), 578279377Simp KOBJMETHOD(channel_setformat, cmichan_setformat), 579279377Simp KOBJMETHOD(channel_setspeed, cmichan_setspeed), 580279377Simp KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 581279377Simp KOBJMETHOD(channel_trigger, cmichan_trigger), 582279377Simp KOBJMETHOD(channel_getptr, cmichan_getptr), 583279377Simp KOBJMETHOD(channel_getcaps, cmichan_getcaps), 584279377Simp { 0, 0 } 585279377Simp}; 586279377SimpCHANNEL_DECLARE(cmichan); 587279377Simp 588279377Simp/* ------------------------------------------------------------------------- */ 589279377Simp/* Mixer - sb16 with kinks */ 590279377Simp 591279377Simpstatic void 592cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 593{ 594 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 595 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 596} 597 598static u_int8_t 599cmimix_rd(struct sc_info *sc, u_int8_t port) 600{ 601 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 602 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 603} 604 605struct sb16props { 606 u_int8_t rreg; /* right reg chan register */ 607 u_int8_t stereo:1; /* (no explanation needed, honest) */ 608 u_int8_t rec:1; /* recording source */ 609 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 610 u_int8_t oselect; /* output select mask */ 611 u_int8_t iselect; /* right input select mask */ 612} static const cmt[SOUND_MIXER_NRDEVICES] = { 613 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 614 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 615 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 616 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 617 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 618 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 619 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 620 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 621 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 622 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 623 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 624 /* These controls are not implemented in CMI8738, but maybe at a 625 future date. They are not documented in C-Media documentation, 626 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 627 */ 628 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 629 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 630 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 631 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 632 /* The mic pre-amp is implemented with non-SB16 compatible 633 registers. */ 634 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 635}; 636 637#define MIXER_GAIN_REG_RTOL(r) (r - 1) 638 639static int 640cmimix_init(struct snd_mixer *m) 641{ 642 struct sc_info *sc = mix_getdevinfo(m); 643 u_int32_t i,v; 644 645 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 646 if (cmt[i].bits) v |= 1 << i; 647 } 648 mix_setdevs(m, v); 649 650 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 651 if (cmt[i].rec) v |= 1 << i; 652 } 653 mix_setrecdevs(m, v); 654 655 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 656 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 657 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 658 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 659 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 660 return 0; 661} 662 663static int 664cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 665{ 666 struct sc_info *sc = mix_getdevinfo(m); 667 u_int32_t r, l, max; 668 u_int8_t v; 669 670 max = (1 << cmt[dev].bits) - 1; 671 672 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 673 /* For time being this can only be one thing (mic in 674 * mic/aux reg) */ 675 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 676 l = left * max / 100; 677 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 678 v |= ((l << 1) | (~l >> 3)) & 0x0f; 679 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 680 return 0; 681 } 682 683 l = (left * max / 100) << (8 - cmt[dev].bits); 684 if (cmt[dev].stereo) { 685 r = (right * max / 100) << (8 - cmt[dev].bits); 686 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 687 cmimix_wr(sc, cmt[dev].rreg, r); 688 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 689 "value 0x%02x:0x%02x\n", 690 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 691 } else { 692 r = l; 693 cmimix_wr(sc, cmt[dev].rreg, l); 694 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 695 "value 0x%02x:0x%02x\n", 696 dev, cmt[dev].rreg, l, l)); 697 } 698 699 /* Zero gain does not mute channel from output, but this does... */ 700 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 701 if (l == 0 && r == 0) { 702 v &= ~cmt[dev].oselect; 703 } else { 704 v |= cmt[dev].oselect; 705 } 706 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 707 708 return 0; 709} 710 711static int 712cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 713{ 714 struct sc_info *sc = mix_getdevinfo(m); 715 u_int32_t i, ml, sl; 716 717 ml = sl = 0; 718 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 719 if ((1<<i) & src) { 720 if (cmt[i].stereo) { 721 sl |= cmt[i].iselect; 722 } else { 723 ml |= cmt[i].iselect; 724 } 725 } 726 } 727 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 728 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 729 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 730 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 731 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 732 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 733 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 734 735 return src; 736} 737 738/* Optional SPDIF support. */ 739 740static int 741cmi_initsys(struct sc_info* sc) 742{ 743#ifdef SND_DYNSYSCTL 744 /* XXX: an user should be able to set this with a control tool, 745 if not done before 7.0-RELEASE, this needs to be converted 746 to a device specific sysctl "dev.pcm.X.yyy" via 747 device_get_sysctl_*() as discussed on multimedia@ in msg-id 748 <861wujij2q.fsf@xps.des.no> */ 749 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 750 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 751 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 752 &sc->spdif_enabled, 0, 753 "enable SPDIF output at 44.1 kHz and above"); 754#endif /* SND_DYNSYSCTL */ 755 return 0; 756} 757 758/* ------------------------------------------------------------------------- */ 759static kobj_method_t cmi_mixer_methods[] = { 760 KOBJMETHOD(mixer_init, cmimix_init), 761 KOBJMETHOD(mixer_set, cmimix_set), 762 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 763 { 0, 0 } 764}; 765MIXER_DECLARE(cmi_mixer); 766 767/* 768 * mpu401 functions 769 */ 770 771static unsigned char 772cmi_mread(void *arg, struct sc_info *sc, int reg) 773{ 774 unsigned int d; 775 776 d = bus_space_read_1(0,0, 0x330 + reg); 777 /* printf("cmi_mread: reg %x %x\n",reg, d); 778 */ 779 return d; 780} 781 782static void 783cmi_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b) 784{ 785 786 bus_space_write_1(0,0,0x330 + reg , b); 787} 788 789static int 790cmi_muninit(void *arg, struct sc_info *sc) 791{ 792 793 snd_mtxlock(sc->lock); 794 sc->mpu_intr = 0; 795 sc->mpu = 0; 796 snd_mtxunlock(sc->lock); 797 798 return 0; 799} 800 801static kobj_method_t cmi_mpu_methods[] = { 802 KOBJMETHOD(mpufoi_read, cmi_mread), 803 KOBJMETHOD(mpufoi_write, cmi_mwrite), 804 KOBJMETHOD(mpufoi_uninit, cmi_muninit), 805 { 0, 0 } 806}; 807 808static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0); 809 810static void 811cmi_midiattach(struct sc_info *sc) { 812/* 813 const struct { 814 int port,bits; 815 } *p, ports[] = { 816 {0x330,0}, 817 {0x320,1}, 818 {0x310,2}, 819 {0x300,3}, 820 {0,0} } ; 821 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does 822 anyone know how to bus_space tag? 823*/ 824 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 825 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL, 826 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT); 827 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL, 828 0 << CMPCI_REG_VMPUSEL_SHIFT ); 829 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 830 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr); 831} 832 833 834 835/* ------------------------------------------------------------------------- */ 836/* Power and reset */ 837 838static void 839cmi_power(struct sc_info *sc, int state) 840{ 841 switch (state) { 842 case 0: /* full power */ 843 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 844 break; 845 default: 846 /* power off */ 847 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 848 break; 849 } 850} 851 852static int 853cmi_init(struct sc_info *sc) 854{ 855 /* Effect reset */ 856 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 857 DELAY(100); 858 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 859 860 /* Disable interrupts and channels */ 861 cmi_clr4(sc, CMPCI_REG_FUNC_0, 862 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 863 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 864 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 865 866 /* Configure DMA channels, ch0 = play, ch1 = capture */ 867 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 868 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 869 870 /* Attempt to enable 4 Channel output */ 871 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 872 873 /* Disable SPDIF1 - not compatible with config */ 874 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 875 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 876 877 return 0; 878} 879 880static void 881cmi_uninit(struct sc_info *sc) 882{ 883 /* Disable interrupts and channels */ 884 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 885 CMPCI_REG_CH0_INTR_ENABLE | 886 CMPCI_REG_CH1_INTR_ENABLE | 887 CMPCI_REG_TDMA_INTR_ENABLE); 888 cmi_clr4(sc, CMPCI_REG_FUNC_0, 889 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 890 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 891 892 if( sc->mpu ) 893 sc->mpu_intr = 0; 894} 895 896/* ------------------------------------------------------------------------- */ 897/* Bus and device registration */ 898static int 899cmi_probe(device_t dev) 900{ 901 switch(pci_get_devid(dev)) { 902 case CMI8338A_PCI_ID: 903 device_set_desc(dev, "CMedia CMI8338A"); 904 return BUS_PROBE_DEFAULT; 905 case CMI8338B_PCI_ID: 906 device_set_desc(dev, "CMedia CMI8338B"); 907 return BUS_PROBE_DEFAULT; 908 case CMI8738_PCI_ID: 909 device_set_desc(dev, "CMedia CMI8738"); 910 return BUS_PROBE_DEFAULT; 911 case CMI8738B_PCI_ID: 912 device_set_desc(dev, "CMedia CMI8738B"); 913 return BUS_PROBE_DEFAULT; 914 default: 915 return ENXIO; 916 } 917} 918 919static int 920cmi_attach(device_t dev) 921{ 922 struct sc_info *sc; 923 u_int32_t data; 924 char status[SND_STATUSLEN]; 925 926 sc = malloc(sizeof(struct sc_info), M_DEVBUF, M_NOWAIT | M_ZERO); 927 if (sc == NULL) { 928 device_printf(dev, "cannot allocate softc\n"); 929 return ENXIO; 930 } 931 932 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 933 data = pci_read_config(dev, PCIR_COMMAND, 2); 934 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 935 pci_write_config(dev, PCIR_COMMAND, data, 2); 936 data = pci_read_config(dev, PCIR_COMMAND, 2); 937 938 sc->dev = dev; 939 sc->regid = PCIR_BAR(0); 940 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid, 941 RF_ACTIVE); 942 if (!sc->reg) { 943 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 944 goto bad; 945 } 946 sc->st = rman_get_bustag(sc->reg); 947 sc->sh = rman_get_bushandle(sc->reg); 948 949 cmi_midiattach(sc); 950 951 sc->irqid = 0; 952 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 953 RF_ACTIVE | RF_SHAREABLE); 954 if (!sc->irq || 955 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 956 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 957 goto bad; 958 } 959 960 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 961 962 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 963 /*boundary*/0, 964 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 965 /*highaddr*/BUS_SPACE_MAXADDR, 966 /*filter*/NULL, /*filterarg*/NULL, 967 /*maxsize*/sc->bufsz, /*nsegments*/1, 968 /*maxsegz*/0x3ffff, /*flags*/0, 969 /*lockfunc*/NULL, 970 /*lockfunc*/NULL, 971 &sc->parent_dmat) != 0) { 972 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 973 goto bad; 974 } 975 976 cmi_power(sc, 0); 977 if (cmi_init(sc)) 978 goto bad; 979 980 if (mixer_init(dev, &cmi_mixer_class, sc)) 981 goto bad; 982 983 if (pcm_register(dev, sc, 1, 1)) 984 goto bad; 985 986 cmi_initsys(sc); 987 988 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 989 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 990 991 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 992 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi)); 993 pcm_setstatus(dev, status); 994 995 DEB(printf("cmi_attach: succeeded\n")); 996 return 0; 997 998 bad: 999 if (sc->parent_dmat) 1000 bus_dma_tag_destroy(sc->parent_dmat); 1001 if (sc->ih) 1002 bus_teardown_intr(dev, sc->irq, sc->ih); 1003 if (sc->irq) 1004 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1005 if (sc->reg) 1006 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1007 if (sc->lock) 1008 snd_mtxfree(sc->lock); 1009 if (sc) 1010 free(sc, M_DEVBUF); 1011 1012 return ENXIO; 1013} 1014 1015static int 1016cmi_detach(device_t dev) 1017{ 1018 struct sc_info *sc; 1019 int r; 1020 1021 r = pcm_unregister(dev); 1022 if (r) return r; 1023 1024 sc = pcm_getdevinfo(dev); 1025 cmi_uninit(sc); 1026 cmi_power(sc, 3); 1027 1028 bus_dma_tag_destroy(sc->parent_dmat); 1029 bus_teardown_intr(dev, sc->irq, sc->ih); 1030 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1031 if(sc->mpu) 1032 mpu401_uninit(sc->mpu); 1033 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1034 if (sc->mpu_reg) 1035 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg); 1036 1037 snd_mtxfree(sc->lock); 1038 free(sc, M_DEVBUF); 1039 1040 return 0; 1041} 1042 1043static int 1044cmi_suspend(device_t dev) 1045{ 1046 struct sc_info *sc = pcm_getdevinfo(dev); 1047 1048 snd_mtxlock(sc->lock); 1049 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 1050 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 1051 cmi_power(sc, 3); 1052 snd_mtxunlock(sc->lock); 1053 return 0; 1054} 1055 1056static int 1057cmi_resume(device_t dev) 1058{ 1059 struct sc_info *sc = pcm_getdevinfo(dev); 1060 1061 snd_mtxlock(sc->lock); 1062 cmi_power(sc, 0); 1063 if (cmi_init(sc) != 0) { 1064 device_printf(dev, "unable to reinitialize the card\n"); 1065 snd_mtxunlock(sc->lock); 1066 return ENXIO; 1067 } 1068 1069 if (mixer_reinit(dev) == -1) { 1070 device_printf(dev, "unable to reinitialize the mixer\n"); 1071 snd_mtxunlock(sc->lock); 1072 return ENXIO; 1073 } 1074 1075 if (sc->pch.dma_was_active) { 1076 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 1077 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 1078 cmi_ch0_start(sc, &sc->pch); 1079 } 1080 1081 if (sc->rch.dma_was_active) { 1082 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 1083 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 1084 cmi_ch1_start(sc, &sc->rch); 1085 } 1086 snd_mtxunlock(sc->lock); 1087 return 0; 1088} 1089 1090static device_method_t cmi_methods[] = { 1091 DEVMETHOD(device_probe, cmi_probe), 1092 DEVMETHOD(device_attach, cmi_attach), 1093 DEVMETHOD(device_detach, cmi_detach), 1094 DEVMETHOD(device_resume, cmi_resume), 1095 DEVMETHOD(device_suspend, cmi_suspend), 1096 { 0, 0 } 1097}; 1098 1099static driver_t cmi_driver = { 1100 "pcm", 1101 cmi_methods, 1102 PCM_SOFTC_SIZE 1103}; 1104 1105DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0); 1106MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1107MODULE_DEPEND(snd_cmi, midi, 1,1,1); 1108MODULE_VERSION(snd_cmi, 1); 1109