cmi.c revision 111183
175584Sru/* 275584Sru * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 375584Sru * All rights reserved. 475584Sru * 575584Sru * Redistribution and use in source and binary forms, with or without 675584Sru * modification, are permitted provided that the following conditions 775584Sru * are met: 875584Sru * 1. Redistributions of source code must retain the above copyright 975584Sru * notice, this list of conditions and the following disclaimer. 1075584Sru * 2. Redistributions in binary form must reproduce the above copyright 1175584Sru * notice, this list of conditions and the following disclaimer in the 1275584Sru * documentation and/or other materials provided with the distribution. 1375584Sru * 1475584Sru * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1575584Sru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1675584Sru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1775584Sru * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1875584Sru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1975584Sru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2075584Sru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2175584Sru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 2275584Sru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2375584Sru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 2475584Sru * SUCH DAMAGE. 2575584Sru * 2675584Sru * This driver exists largely as a result of other people's efforts. 2775584Sru * Much of register handling is based on NetBSD CMI8x38 audio driver 2875584Sru * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 2975584Sru * <cltien@cmedia.com.tw> clarified points regarding the DMA related 3075584Sru * registers and the 8738 mixer devices. His Linux driver was also a 3175584Sru * useful reference point. 3275584Sru * 3375584Sru * TODO: MIDI 3475584Sru * 3575584Sru * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 3675584Sru * 3775584Sru * This card/code does not always manage to sample at 44100 - actual 3875584Sru * rate drifts slightly between recordings (usually 0-3%). No 3975584Sru * differences visible in register dumps between times that work and 4075584Sru * those that don't. 4175584Sru */ 4275584Sru 4375584Sru#include <dev/sound/pcm/sound.h> 4475584Sru#include <dev/sound/pci/cmireg.h> 4575584Sru#include <dev/sound/isa/sb.h> 4675584Sru 4775584Sru#include <pci/pcireg.h> 4875584Sru#include <pci/pcivar.h> 4975584Sru 5075584Sru#include <sys/sysctl.h> 5175584Sru 5275584Sru#include "mixer_if.h" 5375584Sru 5475584SruSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cmi.c 111183 2003-02-20 17:31:12Z cognet $"); 5575584Sru 5675584Sru/* Supported chip ID's */ 5775584Sru#define CMI8338A_PCI_ID 0x010013f6 5875584Sru#define CMI8338B_PCI_ID 0x010113f6 5975584Sru#define CMI8738_PCI_ID 0x011113f6 6075584Sru#define CMI8738B_PCI_ID 0x011213f6 6175584Sru 6275584Sru/* Buffer size max is 64k for permitted DMA boundaries */ 6375584Sru#define CMI_DEFAULT_BUFSZ 16384 6475584Sru 6575584Sru/* Interrupts per length of buffer */ 6675584Sru#define CMI_INTR_PER_BUFFER 2 6775584Sru 6875584Sru/* Clarify meaning of named defines in cmireg.h */ 6975584Sru#define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 7075584Sru#define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 7175584Sru#define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 7275584Sru#define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 7375584Sru 7475584Sru/* Our indication of custom mixer control */ 7575584Sru#define CMPCI_NON_SB16_CONTROL 0xff 7675584Sru 7775584Sru/* Debugging macro's */ 7875584Sru#undef DEB 7975584Sru#ifndef DEB 8075584Sru#define DEB(x) /* x */ 8175584Sru#endif /* DEB */ 8275584Sru 8375584Sru#ifndef DEBMIX 8475584Sru#define DEBMIX(x) /* x */ 8575584Sru#endif /* DEBMIX */ 8675584Sru 8775584Sru/* ------------------------------------------------------------------------- */ 8875584Sru/* Structures */ 8975584Sru 9075584Srustruct sc_info; 9175584Sru 9275584Srustruct sc_chinfo { 9375584Sru struct sc_info *parent; 9475584Sru struct pcm_channel *channel; 9575584Sru struct snd_dbuf *buffer; 9675584Sru u_int32_t fmt, spd, phys_buf, bps; 9775584Sru u_int32_t dma_active:1, dma_was_active:1; 9875584Sru int dir; 9975584Sru}; 10075584Sru 10175584Srustruct sc_info { 10275584Sru device_t dev; 10375584Sru 10475584Sru bus_space_tag_t st; 10575584Sru bus_space_handle_t sh; 10675584Sru bus_dma_tag_t parent_dmat; 10775584Sru struct resource *reg, *irq; 10875584Sru int regid, irqid; 10975584Sru void *ih; 11075584Sru struct mtx *lock; 11175584Sru 11275584Sru int spdif_enabled; 11375584Sru unsigned int bufsz; 11475584Sru struct sc_chinfo pch, rch; 11575584Sru}; 11675584Sru 11775584Sru/* Channel caps */ 11875584Sru 11975584Srustatic u_int32_t cmi_fmt[] = { 12075584Sru AFMT_U8, 12175584Sru AFMT_STEREO | AFMT_U8, 12275584Sru AFMT_S16_LE, 12375584Sru AFMT_STEREO | AFMT_S16_LE, 12475584Sru 0 12575584Sru}; 12675584Sru 12775584Srustatic struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 12875584Sru 12975584Sru/* ------------------------------------------------------------------------- */ 13075584Sru/* Register Utilities */ 13175584Sru 13275584Srustatic u_int32_t 13375584Srucmi_rd(struct sc_info *sc, int regno, int size) 13475584Sru{ 13575584Sru switch (size) { 13675584Sru case 1: 13775584Sru return bus_space_read_1(sc->st, sc->sh, regno); 13875584Sru case 2: 13975584Sru return bus_space_read_2(sc->st, sc->sh, regno); 14075584Sru case 4: 14175584Sru return bus_space_read_4(sc->st, sc->sh, regno); 14275584Sru default: 14375584Sru DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 14475584Sru return 0xFFFFFFFF; 14575584Sru } 14675584Sru} 14775584Sru 14875584Srustatic void 14975584Srucmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 15075584Sru{ 15175584Sru switch (size) { 15275584Sru case 1: 15375584Sru bus_space_write_1(sc->st, sc->sh, regno, data); 15475584Sru break; 15575584Sru case 2: 15675584Sru bus_space_write_2(sc->st, sc->sh, regno, data); 15775584Sru break; 15875584Sru case 4: 15975584Sru bus_space_write_4(sc->st, sc->sh, regno, data); 16075584Sru break; 16175584Sru } 16275584Sru} 16375584Sru 16475584Srustatic void 16575584Srucmi_partial_wr4(struct sc_info *sc, 16675584Sru int reg, int shift, u_int32_t mask, u_int32_t val) 16775584Sru{ 16875584Sru u_int32_t r; 16975584Sru 17075584Sru r = cmi_rd(sc, reg, 4); 17175584Sru r &= ~(mask << shift); 17275584Sru r |= val << shift; 17375584Sru cmi_wr(sc, reg, r, 4); 17475584Sru} 17575584Sru 17675584Srustatic void 17775584Srucmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 17875584Sru{ 17975584Sru u_int32_t r; 18075584Sru 18175584Sru r = cmi_rd(sc, reg, 4); 18275584Sru r &= ~mask; 18375584Sru cmi_wr(sc, reg, r, 4); 18475584Sru} 18575584Sru 18675584Srustatic void 18775584Srucmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 18875584Sru{ 18975584Sru u_int32_t r; 19075584Sru 19175584Sru r = cmi_rd(sc, reg, 4); 19275584Sru r |= mask; 19375584Sru cmi_wr(sc, reg, r, 4); 19475584Sru} 19575584Sru 19675584Sru/* ------------------------------------------------------------------------- */ 19775584Sru/* Rate Mapping */ 19875584Sru 19975584Srustatic int cmi_rates[] = {5512, 8000, 11025, 16000, 20075584Sru 22050, 32000, 44100, 48000}; 20175584Sru#define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 20275584Sru 20375584Sru/* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 20475584Sru * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 20575584Sru 20675584Srustatic u_int32_t 207114402Srucmpci_rate_to_regvalue(int rate) 20875584Sru{ 20975584Sru int i, r; 21075584Sru 21175584Sru for(i = 0; i < NUM_CMI_RATES - 1; i++) { 21275584Sru if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 21375584Sru break; 21475584Sru } 215104862Sru } 216104862Sru 217 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 218 219 r = ((i >> 1) | (i << 2)) & 0x07; 220 return r; 221} 222 223static int 224cmpci_regvalue_to_rate(u_int32_t r) 225{ 226 int i; 227 228 i = ((r << 1) | (r >> 2)) & 0x07; 229 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 230 return cmi_rates[i]; 231} 232 233/* ------------------------------------------------------------------------- */ 234/* ADC/DAC control - there are 2 dma channels on 8738, either can be 235 * playback or capture. We use ch0 for playback and ch1 for capture. */ 236 237static void 238cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 239{ 240 u_int32_t s, i, sz; 241 242 ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 243 244 cmi_wr(sc, base, ch->phys_buf, 4); 245 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 246 247 s = sz / ch->bps - 1; 248 cmi_wr(sc, base + 4, s, 2); 249 250 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 251 cmi_wr(sc, base + 6, i, 2); 252} 253 254 255static void 256cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 257{ 258 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 259 260 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 261 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 262 CMPCI_REG_CH0_INTR_ENABLE); 263 264 ch->dma_active = 1; 265} 266 267static u_int32_t 268cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 269{ 270 u_int32_t r = ch->dma_active; 271 272 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 273 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 274 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 275 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 276 ch->dma_active = 0; 277 return r; 278} 279 280static void 281cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 282{ 283 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 284 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 285 /* Enable Interrupts */ 286 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 287 CMPCI_REG_CH1_INTR_ENABLE); 288 DEB(printf("cmi_ch1_start: dma prog\n")); 289 ch->dma_active = 1; 290} 291 292static u_int32_t 293cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 294{ 295 u_int32_t r = ch->dma_active; 296 297 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 298 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 299 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 300 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 301 ch->dma_active = 0; 302 return r; 303} 304 305static void 306cmi_spdif_speed(struct sc_info *sc, int speed) { 307 u_int32_t fcr1, lcr, mcr; 308 309 if (speed >= 44100) { 310 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 311 lcr = CMPCI_REG_XSPDIF_ENABLE; 312 mcr = (speed == 48000) ? 313 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 314 } else { 315 fcr1 = mcr = lcr = 0; 316 } 317 318 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 319 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 320 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 321 CMPCI_REG_SPDIF0_ENABLE, fcr1); 322 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 323 CMPCI_REG_XSPDIF_ENABLE, lcr); 324} 325 326/* ------------------------------------------------------------------------- */ 327/* Channel Interface implementation */ 328 329static void * 330cmichan_init(kobj_t obj, void *devinfo, 331 struct snd_dbuf *b, struct pcm_channel *c, int dir) 332{ 333 struct sc_info *sc = devinfo; 334 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 335 336 ch->parent = sc; 337 ch->channel = c; 338 ch->bps = 1; 339 ch->fmt = AFMT_U8; 340 ch->spd = DSP_DEFAULT_SPEED; 341 ch->buffer = b; 342 ch->dma_active = 0; 343 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) { 344 DEB(printf("cmichan_init failed\n")); 345 return NULL; 346 } 347 348 ch->dir = dir; 349 snd_mtxlock(sc->lock); 350 if (ch->dir == PCMDIR_PLAY) { 351 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 352 } else { 353 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 354 } 355 snd_mtxunlock(sc->lock); 356 357 return ch; 358} 359 360static int 361cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 362{ 363 struct sc_chinfo *ch = data; 364 struct sc_info *sc = ch->parent; 365 u_int32_t f; 366 367 if (format & AFMT_S16_LE) { 368 f = CMPCI_REG_FORMAT_16BIT; 369 ch->bps = 2; 370 } else { 371 f = CMPCI_REG_FORMAT_8BIT; 372 ch->bps = 1; 373 } 374 375 if (format & AFMT_STEREO) { 376 f |= CMPCI_REG_FORMAT_STEREO; 377 ch->bps *= 2; 378 } else { 379 f |= CMPCI_REG_FORMAT_MONO; 380 } 381 382 snd_mtxlock(sc->lock); 383 if (ch->dir == PCMDIR_PLAY) { 384 cmi_partial_wr4(ch->parent, 385 CMPCI_REG_CHANNEL_FORMAT, 386 CMPCI_REG_CH0_FORMAT_SHIFT, 387 CMPCI_REG_CH0_FORMAT_MASK, 388 f); 389 } else { 390 cmi_partial_wr4(ch->parent, 391 CMPCI_REG_CHANNEL_FORMAT, 392 CMPCI_REG_CH1_FORMAT_SHIFT, 393 CMPCI_REG_CH1_FORMAT_MASK, 394 f); 395 } 396 snd_mtxunlock(sc->lock); 397 ch->fmt = format; 398 399 return 0; 400} 401 402static int 403cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 404{ 405 struct sc_chinfo *ch = data; 406 struct sc_info *sc = ch->parent; 407 u_int32_t r, rsp; 408 409 r = cmpci_rate_to_regvalue(speed); 410 snd_mtxlock(sc->lock); 411 if (ch->dir == PCMDIR_PLAY) { 412 if (speed < 44100) { 413 /* disable if req before rate change */ 414 cmi_spdif_speed(ch->parent, speed); 415 } 416 cmi_partial_wr4(ch->parent, 417 CMPCI_REG_FUNC_1, 418 CMPCI_REG_DAC_FS_SHIFT, 419 CMPCI_REG_DAC_FS_MASK, 420 r); 421 if (speed >= 44100 && ch->parent->spdif_enabled) { 422 /* enable if req after rate change */ 423 cmi_spdif_speed(ch->parent, speed); 424 } 425 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 426 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 427 rsp &= CMPCI_REG_DAC_FS_MASK; 428 } else { 429 cmi_partial_wr4(ch->parent, 430 CMPCI_REG_FUNC_1, 431 CMPCI_REG_ADC_FS_SHIFT, 432 CMPCI_REG_ADC_FS_MASK, 433 r); 434 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 435 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 436 rsp &= CMPCI_REG_ADC_FS_MASK; 437 } 438 snd_mtxunlock(sc->lock); 439 ch->spd = cmpci_regvalue_to_rate(r); 440 441 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 442 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 443 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 444 445 return ch->spd; 446} 447 448static int 449cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 450{ 451 struct sc_chinfo *ch = data; 452 struct sc_info *sc = ch->parent; 453 454 /* user has requested interrupts every blocksize bytes */ 455 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 456 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 457 } 458 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 459 460 return blocksize; 461} 462 463static int 464cmichan_trigger(kobj_t obj, void *data, int go) 465{ 466 struct sc_chinfo *ch = data; 467 struct sc_info *sc = ch->parent; 468 469 snd_mtxlock(sc->lock); 470 if (ch->dir == PCMDIR_PLAY) { 471 switch(go) { 472 case PCMTRIG_START: 473 cmi_ch0_start(sc, ch); 474 break; 475 case PCMTRIG_ABORT: 476 cmi_ch0_stop(sc, ch); 477 break; 478 } 479 } else { 480 switch(go) { 481 case PCMTRIG_START: 482 cmi_ch1_start(sc, ch); 483 break; 484 case PCMTRIG_ABORT: 485 cmi_ch1_stop(sc, ch); 486 break; 487 } 488 } 489 snd_mtxunlock(sc->lock); 490 return 0; 491} 492 493static int 494cmichan_getptr(kobj_t obj, void *data) 495{ 496 struct sc_chinfo *ch = data; 497 struct sc_info *sc = ch->parent; 498 u_int32_t physptr, bufptr, sz; 499 500 snd_mtxlock(sc->lock); 501 if (ch->dir == PCMDIR_PLAY) { 502 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 503 } else { 504 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 505 } 506 snd_mtxunlock(sc->lock); 507 508 sz = sndbuf_getsize(ch->buffer); 509 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 510 511 return bufptr; 512} 513 514static void 515cmi_intr(void *data) 516{ 517 struct sc_info *sc = data; 518 u_int32_t intrstat; 519 520 snd_mtxlock(sc->lock); 521 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 522 if ((intrstat & CMPCI_REG_ANY_INTR) == 0) { 523 goto out; 524 } 525 526 /* Disable interrupts */ 527 if (intrstat & CMPCI_REG_CH0_INTR) { 528 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 529 } 530 531 if (intrstat & CMPCI_REG_CH1_INTR) { 532 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 533 } 534 535 /* Signal interrupts to channel */ 536 if (intrstat & CMPCI_REG_CH0_INTR) { 537 chn_intr(sc->pch.channel); 538 } 539 540 if (intrstat & CMPCI_REG_CH1_INTR) { 541 chn_intr(sc->rch.channel); 542 } 543 544 /* Enable interrupts */ 545 if (intrstat & CMPCI_REG_CH0_INTR) { 546 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 547 } 548 549 if (intrstat & CMPCI_REG_CH1_INTR) { 550 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 551 } 552 553out: 554 snd_mtxunlock(sc->lock); 555 return; 556} 557 558static struct pcmchan_caps * 559cmichan_getcaps(kobj_t obj, void *data) 560{ 561 return &cmi_caps; 562} 563 564static kobj_method_t cmichan_methods[] = { 565 KOBJMETHOD(channel_init, cmichan_init), 566 KOBJMETHOD(channel_setformat, cmichan_setformat), 567 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 568 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 569 KOBJMETHOD(channel_trigger, cmichan_trigger), 570 KOBJMETHOD(channel_getptr, cmichan_getptr), 571 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 572 { 0, 0 } 573}; 574CHANNEL_DECLARE(cmichan); 575 576/* ------------------------------------------------------------------------- */ 577/* Mixer - sb16 with kinks */ 578 579static void 580cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 581{ 582 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 583 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 584} 585 586static u_int8_t 587cmimix_rd(struct sc_info *sc, u_int8_t port) 588{ 589 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 590 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 591} 592 593struct sb16props { 594 u_int8_t rreg; /* right reg chan register */ 595 u_int8_t stereo:1; /* (no explanation needed, honest) */ 596 u_int8_t rec:1; /* recording source */ 597 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 598 u_int8_t oselect; /* output select mask */ 599 u_int8_t iselect; /* right input select mask */ 600} static const cmt[SOUND_MIXER_NRDEVICES] = { 601 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 602 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 603 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 604 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 605 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 606 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 607 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 608 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 609 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 610 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 611 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 612 /* These controls are not implemented in CMI8738, but maybe at a 613 future date. They are not documented in C-Media documentation, 614 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 615 */ 616 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 617 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 618 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 619 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 620 /* The mic pre-amp is implemented with non-SB16 compatible 621 registers. */ 622 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 623}; 624 625#define MIXER_GAIN_REG_RTOL(r) (r - 1) 626 627static int 628cmimix_init(struct snd_mixer *m) 629{ 630 struct sc_info *sc = mix_getdevinfo(m); 631 u_int32_t i,v; 632 633 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 634 if (cmt[i].bits) v |= 1 << i; 635 } 636 mix_setdevs(m, v); 637 638 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 639 if (cmt[i].rec) v |= 1 << i; 640 } 641 mix_setrecdevs(m, v); 642 643 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 644 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 645 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 646 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 647 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 648 return 0; 649} 650 651static int 652cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 653{ 654 struct sc_info *sc = mix_getdevinfo(m); 655 u_int32_t r, l, max; 656 u_int8_t v; 657 658 max = (1 << cmt[dev].bits) - 1; 659 660 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 661 /* For time being this can only be one thing (mic in 662 * mic/aux reg) */ 663 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 664 l = left * max / 100; 665 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 666 v |= ((l << 1) | (~l >> 3)) & 0x0f; 667 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 668 return 0; 669 } 670 671 l = (left * max / 100) << (8 - cmt[dev].bits); 672 if (cmt[dev].stereo) { 673 r = (right * max / 100) << (8 - cmt[dev].bits); 674 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 675 cmimix_wr(sc, cmt[dev].rreg, r); 676 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 677 "value 0x%02x:0x%02x\n", 678 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 679 } else { 680 r = l; 681 cmimix_wr(sc, cmt[dev].rreg, l); 682 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 683 "value 0x%02x:0x%02x\n", 684 dev, cmt[dev].rreg, l, l)); 685 } 686 687 /* Zero gain does not mute channel from output, but this does... */ 688 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 689 if (l == 0 && r == 0) { 690 v &= ~cmt[dev].oselect; 691 } else { 692 v |= cmt[dev].oselect; 693 } 694 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 695 696 return 0; 697} 698 699static int 700cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 701{ 702 struct sc_info *sc = mix_getdevinfo(m); 703 u_int32_t i, ml, sl; 704 705 ml = sl = 0; 706 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 707 if ((1<<i) & src) { 708 if (cmt[i].stereo) { 709 sl |= cmt[i].iselect; 710 } else { 711 ml |= cmt[i].iselect; 712 } 713 } 714 } 715 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 716 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 717 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 718 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 719 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 720 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 721 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 722 723 return src; 724} 725 726/* Optional SPDIF support. */ 727 728static int 729cmi_initsys(struct sc_info* sc) 730{ 731#ifdef SND_DYNSYSCTL 732 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 733 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 734 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 735 &sc->spdif_enabled, 0, 736 "enable SPDIF output at 44.1 kHz and above"); 737#endif /* SND_DYNSYSCTL */ 738 return 0; 739} 740 741/* ------------------------------------------------------------------------- */ 742static kobj_method_t cmi_mixer_methods[] = { 743 KOBJMETHOD(mixer_init, cmimix_init), 744 KOBJMETHOD(mixer_set, cmimix_set), 745 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 746 { 0, 0 } 747}; 748MIXER_DECLARE(cmi_mixer); 749 750/* ------------------------------------------------------------------------- */ 751/* Power and reset */ 752 753static void 754cmi_power(struct sc_info *sc, int state) 755{ 756 switch (state) { 757 case 0: /* full power */ 758 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 759 break; 760 default: 761 /* power off */ 762 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 763 break; 764 } 765} 766 767static int 768cmi_init(struct sc_info *sc) 769{ 770 /* Effect reset */ 771 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 772 DELAY(100); 773 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 774 775 /* Disable interrupts and channels */ 776 cmi_clr4(sc, CMPCI_REG_FUNC_0, 777 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 778 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 779 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 780 781 /* Configure DMA channels, ch0 = play, ch1 = capture */ 782 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 783 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 784 785 /* Attempt to enable 4 Channel output */ 786 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 787 788 /* Disable SPDIF1 - not compatible with config */ 789 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 790 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 791 792 return 0; 793} 794 795static void 796cmi_uninit(struct sc_info *sc) 797{ 798 /* Disable interrupts and channels */ 799 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 800 CMPCI_REG_CH0_INTR_ENABLE | 801 CMPCI_REG_CH1_INTR_ENABLE | 802 CMPCI_REG_TDMA_INTR_ENABLE); 803 cmi_clr4(sc, CMPCI_REG_FUNC_0, 804 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 805} 806 807/* ------------------------------------------------------------------------- */ 808/* Bus and device registration */ 809static int 810cmi_probe(device_t dev) 811{ 812 switch(pci_get_devid(dev)) { 813 case CMI8338A_PCI_ID: 814 device_set_desc(dev, "CMedia CMI8338A"); 815 return 0; 816 case CMI8338B_PCI_ID: 817 device_set_desc(dev, "CMedia CMI8338B"); 818 return 0; 819 case CMI8738_PCI_ID: 820 device_set_desc(dev, "CMedia CMI8738"); 821 return 0; 822 case CMI8738B_PCI_ID: 823 device_set_desc(dev, "CMedia CMI8738B"); 824 return 0; 825 default: 826 return ENXIO; 827 } 828} 829 830static int 831cmi_attach(device_t dev) 832{ 833 struct snddev_info *d; 834 struct sc_info *sc; 835 u_int32_t data; 836 char status[SND_STATUSLEN]; 837 838 d = device_get_softc(dev); 839 sc = malloc(sizeof(struct sc_info), M_DEVBUF, M_NOWAIT | M_ZERO); 840 if (sc == NULL) { 841 device_printf(dev, "cannot allocate softc\n"); 842 return ENXIO; 843 } 844 845 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 846 data = pci_read_config(dev, PCIR_COMMAND, 2); 847 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 848 pci_write_config(dev, PCIR_COMMAND, data, 2); 849 data = pci_read_config(dev, PCIR_COMMAND, 2); 850 851 sc->dev = dev; 852 sc->regid = PCIR_MAPS; 853 sc->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->regid, 854 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE); 855 if (!sc->reg) { 856 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 857 goto bad; 858 } 859 sc->st = rman_get_bustag(sc->reg); 860 sc->sh = rman_get_bushandle(sc->reg); 861 862 sc->irqid = 0; 863 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 864 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 865 if (!sc->irq || 866 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 867 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 868 goto bad; 869 } 870 871 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 872 873 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 874 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 875 /*highaddr*/BUS_SPACE_MAXADDR, 876 /*filter*/NULL, /*filterarg*/NULL, 877 /*maxsize*/sc->bufsz, /*nsegments*/1, 878 /*maxsegz*/0x3ffff, /*flags*/0, 879 &sc->parent_dmat) != 0) { 880 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 881 goto bad; 882 } 883 884 cmi_power(sc, 0); 885 if (cmi_init(sc)) 886 goto bad; 887 888 if (mixer_init(dev, &cmi_mixer_class, sc)) 889 goto bad; 890 891 if (pcm_register(dev, sc, 1, 1)) 892 goto bad; 893 894 cmi_initsys(sc); 895 896 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 897 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 898 899 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld", 900 rman_get_start(sc->reg), rman_get_start(sc->irq)); 901 pcm_setstatus(dev, status); 902 903 DEB(printf("cmi_attach: succeeded\n")); 904 return 0; 905 906 bad: 907 if (sc->parent_dmat) 908 bus_dma_tag_destroy(sc->parent_dmat); 909 if (sc->ih) 910 bus_teardown_intr(dev, sc->irq, sc->ih); 911 if (sc->irq) 912 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 913 if (sc->reg) 914 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 915 if (sc->lock) 916 snd_mtxfree(sc->lock); 917 if (sc) 918 free(sc, M_DEVBUF); 919 920 return ENXIO; 921} 922 923static int 924cmi_detach(device_t dev) 925{ 926 struct sc_info *sc; 927 int r; 928 929 r = pcm_unregister(dev); 930 if (r) return r; 931 932 sc = pcm_getdevinfo(dev); 933 cmi_uninit(sc); 934 cmi_power(sc, 3); 935 936 bus_dma_tag_destroy(sc->parent_dmat); 937 bus_teardown_intr(dev, sc->irq, sc->ih); 938 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 939 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 940 snd_mtxfree(sc->lock); 941 free(sc, M_DEVBUF); 942 943 return 0; 944} 945 946static int 947cmi_suspend(device_t dev) 948{ 949 struct sc_info *sc = pcm_getdevinfo(dev); 950 951 snd_mtxlock(sc->lock); 952 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 953 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 954 cmi_power(sc, 3); 955 snd_mtxunlock(sc->lock); 956 return 0; 957} 958 959static int 960cmi_resume(device_t dev) 961{ 962 struct sc_info *sc = pcm_getdevinfo(dev); 963 964 snd_mtxlock(sc->lock); 965 cmi_power(sc, 0); 966 if (cmi_init(sc) != 0) { 967 device_printf(dev, "unable to reinitialize the card\n"); 968 snd_mtxunlock(sc->lock); 969 return ENXIO; 970 } 971 972 if (mixer_reinit(dev) == -1) { 973 device_printf(dev, "unable to reinitialize the mixer\n"); 974 snd_mtxunlock(sc->lock); 975 return ENXIO; 976 } 977 978 if (sc->pch.dma_was_active) { 979 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 980 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 981 cmi_ch0_start(sc, &sc->pch); 982 } 983 984 if (sc->rch.dma_was_active) { 985 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 986 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 987 cmi_ch1_start(sc, &sc->rch); 988 } 989 snd_mtxunlock(sc->lock); 990 return 0; 991} 992 993static device_method_t cmi_methods[] = { 994 DEVMETHOD(device_probe, cmi_probe), 995 DEVMETHOD(device_attach, cmi_attach), 996 DEVMETHOD(device_detach, cmi_detach), 997 DEVMETHOD(device_resume, cmi_resume), 998 DEVMETHOD(device_suspend, cmi_suspend), 999 { 0, 0 } 1000}; 1001 1002static driver_t cmi_driver = { 1003 "pcm", 1004 cmi_methods, 1005 PCM_SOFTC_SIZE 1006}; 1007 1008DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0); 1009MODULE_DEPEND(snd_cmi, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1010MODULE_VERSION(snd_cmi, 1); 1011