1139749Simp/*- 254773Simp * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 354773Simp * All rights reserved. 454773Simp * 554773Simp * Redistribution and use in source and binary forms, with or without 654773Simp * modification, are permitted provided that the following conditions 754773Simp * are met: 854773Simp * 1. Redistributions of source code must retain the above copyright 954773Simp * notice, this list of conditions and the following disclaimer. 1054773Simp * 2. Redistributions in binary form must reproduce the above copyright 1154773Simp * notice, this list of conditions and the following disclaimer in the 1254773Simp * documentation and/or other materials provided with the distribution. 1354773Simp * 3. All advertising materials mentioning features or use of this software 1454773Simp * must display the following acknowledgement: 1554773Simp * This product includes software developed by Gardner Buchanan. 1654773Simp * 4. The name of Gardner Buchanan may not be used to endorse or promote 1754773Simp * products derived from this software without specific prior written 1854773Simp * permission. 1954773Simp * 2054773Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2154773Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2254773Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2354773Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2454773Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2554773Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2654773Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2754773Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2854773Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2954773Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3054773Simp * 3154773Simp * $FreeBSD: releng/10.2/sys/dev/sn/if_snreg.h 150459 2005-09-22 05:56:32Z imp $ 3254773Simp */ 3354773Simp 3454773Simp/* 3554773Simp * This file contains register information and access macros for 3654773Simp * the SMC91xxx chipset. 3754773Simp * 3854773Simp * Information contained in this file was obtained from the SMC91C92 3954773Simp * and SMC91C94 manuals from SMC. You will need one of these in order 4054773Simp * to make any meaningful changes to this driver. Information about 4154773Simp * obtaining one can be found at http://www.smc.com in the components 4254773Simp * division. 4354773Simp * 4454773Simp * This FreeBSD driver is derived in part from the smc9194 Linux driver 4554773Simp * by Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 4654773Simp * It is also derived in part from the FreeBSD ep (3C509) driver which 4754773Simp * is Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights 4854773Simp * reserved. 4954773Simp * 5054773Simp */ 5154773Simp#ifndef _IF_SNREG_H_ 5254773Simp#define _IF_SNREG_H_ 5354773Simp 5454773Simp/* 5554773Simp * Wait time for memory to be free. This probably shouldn't be 5654773Simp * tuned that much, as waiting for this means nothing else happens 5754773Simp * in the system 5854773Simp */ 5954773Simp#define MEMORY_WAIT_TIME 1000 6054773Simp 6154773Simp 6254773Simp/* The SMC91xxx uses 16 I/O ports 6354773Simp */ 6454773Simp#define SMC_IO_EXTENT 16 6554773Simp 6654773Simp 6754773Simp/* 6854773Simp * A description of the SMC registers is probably in order here, 6954773Simp * although for details, the SMC datasheet is invaluable. 7054773Simp * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet 7154773Simp * Controller With RAM", Rev. 12/0/94. Constant definitions I give 7254773Simp * here are loosely based on the mnemonic names given to them in the 7354773Simp * data sheet, but there are many exceptions. 7454773Simp * 7554773Simp * Basically, the chip has 4 banks of registers (0 to 3), which 7654773Simp * are accessed by writing a number into the BANK_SELECT register 7754773Simp * (I also use a SMC_SELECT_BANK macro for this). Registers are 7854773Simp * either Byte or Word sized. My constant definitions end in _B 7954773Simp * or _W as appropriate. 8054773Simp * 8154773Simp * The banks are arranged so that for most purposes, bank 2 is all 8254773Simp * that is needed for normal run time tasks. 8354773Simp */ 8454773Simp 8554773Simp/* 8654773Simp * Bank Select Register. This also doubles as 8754773Simp * a chip identification register. This register 8854773Simp * is mapped at the same position in all banks. 8954773Simp */ 9054773Simp#define BANK_SELECT_REG_W 0x0e 9154773Simp#define BSR_DETECT_MASK 0xff00 9254773Simp#define BSR_DETECT_VALUE 0x3300 9354773Simp 9454773Simp 9554773Simp/* BANK 0 9654773Simp */ 9754773Simp 9854773Simp/* Transmit Control Register controls some aspects of the transmit 9954773Simp * behavior of the Ethernet Protocol Handler. 10054773Simp */ 10154773Simp#define TXMIT_CONTROL_REG_W 0x00 10254773Simp 10354773Simp#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ 10454773Simp#define TCR_LOOP 0x0002 /* Enable internal analogue loopback */ 10554773Simp#define TCR_FORCOL 0x0004 /* Force Collision on next TX */ 10654773Simp#define TCR_PAD_ENABLE 0x0080 /* Pad short packets to 64 bytes */ 10754773Simp#define TCR_NOCRC 0x0100 /* Do not append CRC */ 10854773Simp#define TCR_MON_CSN 0x0400 /* monitors the carrier status */ 10954773Simp#define TCR_FDUPLX 0x0800 /* receive packets sent out */ 11054773Simp#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ 11154773Simp#define TCR_EPH_LOOP 0x2000 /* Enable internal digital loopback */ 11254773Simp 11354773Simp 11454773Simp/* Status of the last transmitted frame and instantaneous status of 11554773Simp * the Ethernet Protocol Handler jumbled together. In auto-release 11654773Simp * mode this information is simply discarded after each TX. This info 11754773Simp * is copied to the status word of in-memory packets after transmit 11854773Simp * where relevent statuses can be checked. 11954773Simp */ 12054773Simp#define EPH_STATUS_REG_W 0x02 12154773Simp 12254773Simp#define EPHSR_TX_SUC 0x0001 /* Transmit was successful */ 12354773Simp#define EPHSR_SNGLCOL 0x0002 /* Single collision occurred */ 12454773Simp#define EPHSR_MULCOL 0x0004 /* Multiple Collisions occurred */ 12554773Simp#define EPHSR_LTX_MULT 0x0008 /* Transmit was a multicast */ 12654773Simp#define EPHSR_16COL 0x0010 /* 16 Collisions occurred, TX disabled */ 12754773Simp#define EPHSR_SQET 0x0020 /* SQE Test failed, TX disabled */ 12854773Simp#define EPHSR_LTX_BRD 0x0040 /* Transmit was a broadcast */ 12954773Simp#define EPHSR_DEFR 0x0080 /* TX deferred due to carrier det. */ 13054773Simp#define EPHSR_LATCOL 0x0200 /* Late collision detected, TX disabled */ 13154773Simp#define EPHSR_LOST_CAR 0x0400 /* Lost carrier sense, TX disabled */ 13254773Simp#define EPHSR_EXC_DEF 0x0800 /* Excessive deferrals in TX >2 MAXETHER 13354773Simp * times */ 13454773Simp#define EPHSR_CTR_ROL 0x1000 /* Some ECR Counter(s) rolled over */ 13554773Simp#define EPHSR_RX_OVRN 0x2000 /* Receiver overrun, packets dropped */ 13654773Simp#define EPHSR_LINK_OK 0x4000 /* Link integrity is OK */ 13754773Simp#define EPHSR_TXUNRN 0x8000 /* Transmit underrun */ 13854773Simp 13954773Simp 14054773Simp/* Receiver Control Register controls some aspects of the receive 14154773Simp * behavior of the Ethernet Protocol Handler. 14254773Simp */ 14354773Simp#define RECV_CONTROL_REG_W 0x04 14454773Simp 14554773Simp#define RCR_RX_ABORT 0x0001 /* Received huge packet */ 14654773Simp#define RCR_PROMISC 0x0002 /* enable promiscuous mode */ 14754773Simp#define RCR_ALMUL 0x0004 /* receive all multicast packets */ 14854773Simp#define RCR_ENABLE 0x0100 /* IFF this is set, we can recieve packets */ 14954773Simp#define RCR_STRIP_CRC 0x0200 /* strips CRC */ 15054773Simp#define RCR_GAIN_BITS 0x0c00 /* PLL Gain control (for testing) */ 15154773Simp#define RCR_FILT_CAR 0x4000 /* Enable 12 bit carrier filter */ 15254773Simp#define RCR_SOFTRESET 0x8000 /* Resets the EPH logic */ 15354773Simp 15454773Simp 15554773Simp/* TX Statistics counters 15654773Simp */ 15754773Simp#define COUNTER_REG_W 0x06 15854773Simp 15954773Simp#define ECR_COLN_MASK 0x000f /* Vanilla collisions */ 16054773Simp#define ECR_MCOLN_MASK 0x00f0 /* Multiple collisions */ 16154773Simp#define ECR_DTX_MASK 0x0f00 /* Deferred transmits */ 16254773Simp#define ECR_EXDTX_MASK 0xf000 /* Excessively deferred transmits */ 16354773Simp 16454773Simp/* Memory Information 16554773Simp */ 16654773Simp#define MEM_INFO_REG_W 0x08 16754773Simp 16854773Simp#define MIR_FREE_MASK 0xff00 /* Free memory pages available */ 16954773Simp#define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */ 17054773Simp 17154773Simp/* Memory Configuration 17254773Simp */ 17354773Simp#define MEM_CFG_REG_W 0x0a 17454773Simp 17554773Simp#define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */ 17654773Simp 17754773Simp 17854773Simp/* Bank 0, Register 0x0c is unised in the SMC91C92 17954773Simp */ 18054773Simp 18154773Simp 18254773Simp/* BANK 1 18354773Simp */ 18454773Simp 18554773Simp/* Adapter configuration 18654773Simp */ 18754773Simp#define CONFIG_REG_W 0x00 18854773Simp 18954773Simp#define CR_INT_SEL0 0x0002 /* Interrupt selector */ 19054773Simp#define CR_INT_SEL1 0x0004 /* Interrupt selector */ 19154773Simp#define CR_DIS_LINK 0x0040 /* Disable 10BaseT Link Test */ 19254773Simp#define CR_16BIT 0x0080 /* Bus width */ 19354773Simp#define CR_AUI_SELECT 0x0100 /* Use external (AUI) Transceiver */ 19454773Simp#define CR_SET_SQLCH 0x0200 /* Squelch level */ 19554773Simp#define CR_FULL_STEP 0x0400 /* AUI signalling mode */ 19654773Simp#define CR_NOW_WAIT_ST 0x1000 /* Disable bus wait states */ 19754773Simp 19854773Simp/* The contents of this port are used by the adapter 19954773Simp * to decode its I/O address. We use it as a varification 20054773Simp * that the adapter is detected properly when probing. 20154773Simp */ 20254773Simp#define BASE_ADDR_REG_W 0x02 /* The select IO Base addr. */ 20354773Simp 20454773Simp/* These registers hold the Ethernet MAC address. 20554773Simp */ 20654773Simp#define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */ 20754773Simp#define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */ 20854773Simp#define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */ 20954773Simp 21054773Simp/* General purpose register used for talking to the EEPROM. 21154773Simp */ 21254773Simp#define GENERAL_REG_W 0x0a 21354773Simp 21454773Simp/* Control register used for talking to the EEPROM and 21554773Simp * setting some EPH functions. 21654773Simp */ 21754773Simp#define CONTROL_REG_W 0x0c 21854773Simp#define CTR_STORE 0x0001 /* Store something to EEPROM */ 21954773Simp#define CTR_RELOAD 0x0002 /* Read EEPROM into registers */ 22054773Simp#define CTR_EEPROM_SEL 0x0004 /* Select registers for Reload/Store */ 22154773Simp#define CTR_TE_ENABLE 0x0020 /* Enable TX Error detection via EPH_INT */ 22254773Simp#define CTR_CR_ENABLE 0x0040 /* Enable Counter Rollover via EPH_INT */ 22354773Simp#define CTR_LE_ENABLE 0x0080 /* Enable Link Error detection via EPH_INT */ 22454773Simp#define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */ 22554773Simp#define CTR_POWERDOWN 0x2000 /* Enter powerdown mode */ 22654773Simp#define CTR_RCV_BAD 0x4000 /* Enable receipt of frames with bad CRC */ 22754773Simp 22854773Simp 22954773Simp/* BANK 2 23054773Simp */ 23154773Simp 23254773Simp/* Memory Management Unit Control Register 23354773Simp * Controls allocation of memory to receive and 23454773Simp * transmit functions. 23554773Simp */ 23654773Simp#define MMU_CMD_REG_W 0x00 23754773Simp#define MMUCR_BUSY 0x0001 /* MMU busy performing a release */ 23854773Simp 23954773Simp/* MMU Commands: 24054773Simp */ 24154773Simp#define MMUCR_NOP 0x0000 /* Do nothing */ 24254773Simp#define MMUCR_ALLOC 0x0020 /* Or with number of 256 byte packets - 1 */ 24354773Simp#define MMUCR_RESET 0x0040 /* Reset MMU State */ 24454773Simp#define MMUCR_REMOVE 0x0060 /* Dequeue (but not free) current RX packet */ 24554773Simp#define MMUCR_RELEASE 0x0080 /* Dequeue and free the current RX packet */ 24654773Simp#define MMUCR_FREEPKT 0x00a0 /* Release packet in PNR register */ 24754773Simp#define MMUCR_ENQUEUE 0x00c0 /* Enqueue the packet for transmit */ 24854773Simp#define MMUCR_RESETTX 0x00e0 /* Reset transmit queues */ 24954773Simp 25054773Simp/* Packet Number at TX Area 25154773Simp */ 25254773Simp#define PACKET_NUM_REG_B 0x02 25354773Simp 25454773Simp/* Packet number resulting from MMUCR_ALLOC 25554773Simp */ 25654773Simp#define ALLOC_RESULT_REG_B 0x03 25754773Simp#define ARR_FAILED 0x80 25854773Simp 25954773Simp/* Transmit and receive queue heads 26054773Simp */ 26154773Simp#define FIFO_PORTS_REG_W 0x04 26254773Simp#define FIFO_REMPTY 0x8000 26354773Simp#define FIFO_TEMPTY 0x0080 26454773Simp#define FIFO_RX_MASK 0x7f00 26554773Simp#define FIFO_TX_MASK 0x007f 26654773Simp 26754773Simp/* The address within the packet for reading/writing. The 26854773Simp * PTR_RCV bit is tricky. When PTR_RCV==1, the packet number 26954773Simp * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK. 27054773Simp * When PTR_RCV==0, the packet number to be written is found 27154773Simp * in the PACKET_NUM_REG_B. 27254773Simp */ 27354773Simp#define POINTER_REG_W 0x06 27454773Simp#define PTR_READ 0x2000 /* Intended access mode */ 27554773Simp#define PTR_AUTOINC 0x4000 /* Do auto inc after read/write */ 27654773Simp#define PTR_RCV 0x8000 /* FIFO_RX is packet, otherwise PNR is packet */ 27754773Simp 27854773Simp/* Data I/O register to be used in conjunction with 27954773Simp * The pointer register to read and write data from the 28054773Simp * card. The same register can be used for byte and word 28154773Simp * ops. 28254773Simp */ 28354773Simp#define DATA_REG_W 0x08 28454773Simp#define DATA_REG_B 0x08 28554773Simp#define DATA_1_REG_B 0x08 28654773Simp#define DATA_2_REG_B 0x0a 28754773Simp 28854773Simp/* Sense interrupt status (READ) 28954773Simp */ 29054773Simp#define INTR_STAT_REG_B 0x0c 29154773Simp 29254773Simp/* Acknowledge interrupt sources (WRITE) 29354773Simp */ 29454773Simp#define INTR_ACK_REG_B 0x0c 29554773Simp 29654773Simp/* Interrupt mask. Bit set indicates interrupt allowed. 29754773Simp */ 29854773Simp#define INTR_MASK_REG_B 0x0d 29954773Simp 30054773Simp/* Interrupts 30154773Simp */ 30254773Simp#define IM_RCV_INT 0x01 /* A packet has been received */ 30354773Simp#define IM_TX_INT 0x02 /* Packet TX complete */ 30454773Simp#define IM_TX_EMPTY_INT 0x04 /* No packets left to TX */ 30554773Simp#define IM_ALLOC_INT 0x08 /* Memory allocation completed */ 30654773Simp#define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */ 30754773Simp#define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */ 30854773Simp#define IM_ERCV_INT 0x40 /* not on SMC9192 */ 30954773Simp 31054773Simp/* BANK 3 31154773Simp */ 31254773Simp 31354773Simp/* Multicast subscriptions. 31454773Simp * The multicast handling in the SMC90Cxx is quite complicated. A table 31554773Simp * of multicast address subscriptions is provided and a clever way of 31654773Simp * speeding the search of that table by hashing is implemented in the 31754773Simp * hardware. I have ignored this and simply subscribed to all multicasts 31854773Simp * and let the kernel deal with the results. 31954773Simp */ 32054773Simp#define MULTICAST1_REG_W 0x00 32154773Simp#define MULTICAST2_REG_W 0x02 32254773Simp#define MULTICAST3_REG_W 0x04 32354773Simp#define MULTICAST4_REG_W 0x06 32454773Simp 32554773Simp/* These registers do not exist on SMC9192, or at least 32654773Simp * are not documented in the SMC91C92 data sheet. 32754773Simp * The REVISION_REG_W register does however seem to work. 32854773Simp */ 32954773Simp#define MGMT_REG_W 0x08 33054773Simp#define REVISION_REG_W 0x0a /* (hi: chip id low: rev #) */ 33154773Simp#define ERCV_REG_W 0x0c 33254773Simp 33354773Simp/* These are constants expected to be found in the 33454773Simp * chip id register. 33554773Simp */ 33654773Simp#define CHIP_9190 3 33754773Simp#define CHIP_9194 4 33854773Simp#define CHIP_9195 5 33954773Simp#define CHIP_91100 7 34071060Stoshi#define CHIP_91100FD 8 34154773Simp 34254773Simp/* When packets are stuffed into the card or sucked out of the card 34354773Simp * they are set up more or less as follows: 34454773Simp * 34554773Simp * Addr msbyte lsbyte 34654773Simp * 00 SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status 34754773Simp * 02 RRRRR - RESERVED (unused) 34854773Simp * 02 CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored) 34954773Simp * 04 DDDDDDDD DDDDDDDD - DESTINATION ADDRESS 35054773Simp * 06 DDDDDDDD DDDDDDDD (48 bit Ethernet MAC Address) 35154773Simp * 08 DDDDDDDD DDDDDDDD 35254773Simp * 0A SSSSSSSS SSSSSSSS - SOURCE ADDRESS 35354773Simp * 0C SSSSSSSS SSSSSSSS (48 bit Ethernet MAC Address) 35454773Simp * 0E SSSSSSSS SSSSSSSS 35554773Simp * 10 PPPPPPPP PPPPPPPP 35654773Simp * .. PPPPPPPP PPPPPPPP 35754773Simp * C-2 CCCCCCCC - CONTROL BYTE 35854773Simp * C-2 PPPPPPPP - Last data byte (If odd length) 35954773Simp * 36054773Simp * The STATUS_WORD is derived from the EPH_STATUS_REG_W register 36154773Simp * during transmit and is composed of another set of bits described 36254773Simp * below during receive. 36354773Simp */ 36454773Simp 36554773Simp 36654773Simp/* Receive status bits. These values are found in the status word 36754773Simp * field of a received packet. For receive packets I use the RS_ODDFRAME 36854773Simp * to detect whether a frame has an extra byte on it. The CTLB_ODD 36954773Simp * bit of the control byte tells the same thing. 37054773Simp */ 37154773Simp#define RS_MULTICAST 0x0001 /* Packet is multicast */ 37254773Simp#define RS_HASH_MASK 0x007e /* Mask of multicast hash value */ 37354773Simp#define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */ 37454773Simp#define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */ 37554773Simp#define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */ 37654773Simp#define RS_BADCRC 0x2000 /* Frame had CRC error */ 37754773Simp#define RS_ALGNERR 0x8000 /* Frame had alignment error */ 37854773Simp#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 37954773Simp 38054773Simp#define RLEN_MASK 0x07ff /* Significant length bits in RX length */ 38154773Simp 38254773Simp/* The control byte has the following significant bits. 38354773Simp * For transmit, the CTLB_ODD bit specifies whether an extra byte 38454773Simp * is present in the frame. Bit 0 of the byte count field is 38554773Simp * ignored. I just pad every frame to even length and forget about 38654773Simp * it. 38754773Simp */ 38854773Simp#define CTLB_CRC 0x10 /* Add CRC for this packet (TX only) */ 38954773Simp#define CTLB_ODD 0x20 /* The packet length is ODD */ 39054773Simp 39154773Simp 39254773Simp/* 39354773Simp * I define some macros to make it easier to do somewhat common 39454773Simp * or slightly complicated, repeated tasks. 39554773Simp */ 39654773Simp 39754773Simp/* Select a register bank, 0 to 3 39854773Simp */ 399121514Simp#define SMC_SELECT_BANK(sc, x) { CSR_WRITE_2(sc, BANK_SELECT_REG_W, (x)); } 40054773Simp 40154773Simp/* Define a small delay for the reset 40254773Simp */ 403121514Simp#define SMC_DELAY(sc) { CSR_READ_2(sc, RECV_CONTROL_REG_W); \ 404121514Simp CSR_READ_2(sc, RECV_CONTROL_REG_W); \ 405121514Simp CSR_READ_2(sc, RECV_CONTROL_REG_W); } 40654773Simp 40754773Simp#endif /* _IF_SNREG_H_ */ 408