1120286Swilko/* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */ 2139825Simp/*- 3120286Swilko * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 4120286Swilko * 5120286Swilko * Permission to use, copy, modify, and distribute this software for any 6120286Swilko * purpose with or without fee is hereby granted, provided that the above 7120286Swilko * copyright notice and this permission notice appear in all copies. 8120286Swilko * 9120286Swilko * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10120286Swilko * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11120286Swilko * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12120286Swilko * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13120286Swilko * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14120286Swilko * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15120286Swilko * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16120286Swilko * 17120286Swilko * $FreeBSD: releng/10.2/sys/dev/sk/yukonreg.h 158070 2006-04-27 05:59:09Z yongari $ 18120286Swilko */ 19120286Swilko 20120286Swilko/* General Purpose Status Register (GPSR) */ 21120286Swilko#define YUKON_GPSR 0x0000 22120286Swilko 23120286Swilko#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */ 24120286Swilko#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */ 25158070Syongari#define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */ 26120286Swilko#define YU_GPSR_LINK 0x1000 /* link status (down/up) */ 27120286Swilko#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */ 28120286Swilko#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */ 29120286Swilko#define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */ 30120286Swilko#define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */ 31120286Swilko#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */ 32120286Swilko#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */ 33120286Swilko#define YU_GPSR_PARTITION 0x0008 /* partition mode */ 34158070Syongari#define YU_GPSR_FCTL_RX 0x0004 /* Rx flow control, 1 - disabled */ 35158070Syongari#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode, 1 - enabled */ 36120286Swilko 37120286Swilko/* General Purpose Control Register (GPCR) */ 38120286Swilko#define YUKON_GPCR 0x0004 39120286Swilko 40158070Syongari#define YU_GPCR_FCTL_TX_DIS 0x2000 /* Disable Tx flow control 802.3x */ 41120286Swilko#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */ 42120286Swilko#define YU_GPCR_RXEN 0x0800 /* Receive Enable */ 43158070Syongari#define YU_GPCR_BURSTEN 0x0400 /* Burst Mode Enable */ 44158070Syongari#define YU_GPCR_LPBK 0x0200 /* MAC Loopback Enable */ 45120286Swilko#define YU_GPCR_PAR 0x0100 /* Partition Enable */ 46158070Syongari#define YU_GPCR_GIG 0x0080 /* Gigabit Speed 1000Mbps */ 47120286Swilko#define YU_GPCR_FLP 0x0040 /* Force Link Pass */ 48120286Swilko#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */ 49158070Syongari#define YU_GPCR_FCTL_RX_DIS 0x0010 /* Disable Rx flow control 802.3x */ 50158070Syongari#define YU_GPCR_SPEED 0x0008 /* Port Speed 100Mbps */ 51158070Syongari#define YU_GPCR_DPLX_DIS 0x0004 /* Disable Auto-Update for duplex */ 52158070Syongari#define YU_GPCR_FCTL_DIS 0x0002 /* Disable Auto-Update for 802.3x */ 53158070Syongari#define YU_GPCR_SPEED_DIS 0x0001 /* Disable Auto-Update for speed */ 54120286Swilko 55120286Swilko/* Transmit Control Register (TCR) */ 56120286Swilko#define YUKON_TCR 0x0008 57120286Swilko 58120286Swilko#define YU_TCR_FJ 0x8000 /* force jam / flow control */ 59120286Swilko#define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */ 60120286Swilko#define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */ 61120286Swilko#define YU_TCR_COLTH 0x1c00 /* collision threshold */ 62120286Swilko 63120286Swilko/* Receive Control Register (RCR) */ 64120286Swilko#define YUKON_RCR 0x000c 65120286Swilko 66120286Swilko#define YU_RCR_UFLEN 0x8000 /* unicast filter enable */ 67120286Swilko#define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */ 68120286Swilko#define YU_RCR_CRCR 0x2000 /* remove CRC */ 69120286Swilko#define YU_RCR_PASSFC 0x1000 /* pass flow control packets */ 70120286Swilko 71120286Swilko/* Transmit Flow Control Register (TFCR) */ 72120286Swilko#define YUKON_TFCR 0x0010 /* Pause Time */ 73120286Swilko 74120286Swilko/* Transmit Parameter Register (TPR) */ 75120286Swilko#define YUKON_TPR 0x0014 76120286Swilko 77120286Swilko#define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14) 78120286Swilko#define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9) 79120286Swilko#define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4) 80120286Swilko 81120286Swilko/* Serial Mode Register (SMR) */ 82120286Swilko#define YUKON_SMR 0x0018 83120286Swilko 84120286Swilko#define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11) 85120286Swilko#define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */ 86120286Swilko#define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */ 87120286Swilko#define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */ 88120286Swilko#define YU_SMR_IPG_DATA(x) ((x) & 0x1f) 89120286Swilko 90120286Swilko/* Source Address Low #1 (SAL1) */ 91120286Swilko#define YUKON_SAL1 0x001c /* SA1[15:0] */ 92120286Swilko 93120286Swilko/* Source Address Middle #1 (SAM1) */ 94120286Swilko#define YUKON_SAM1 0x0020 /* SA1[31:16] */ 95120286Swilko 96120286Swilko/* Source Address High #1 (SAH1) */ 97120286Swilko#define YUKON_SAH1 0x0024 /* SA1[47:32] */ 98120286Swilko 99120286Swilko/* Source Address Low #2 (SAL2) */ 100120286Swilko#define YUKON_SAL2 0x0028 /* SA2[15:0] */ 101120286Swilko 102120286Swilko/* Source Address Middle #2 (SAM2) */ 103120286Swilko#define YUKON_SAM2 0x002c /* SA2[31:16] */ 104120286Swilko 105120286Swilko/* Source Address High #2 (SAH2) */ 106120286Swilko#define YUKON_SAH2 0x0030 /* SA2[47:32] */ 107120286Swilko 108120286Swilko/* Multicatst Address Hash Register 1 (MCAH1) */ 109120286Swilko#define YUKON_MCAH1 0x0034 110120286Swilko 111120286Swilko/* Multicatst Address Hash Register 2 (MCAH2) */ 112120286Swilko#define YUKON_MCAH2 0x0038 113120286Swilko 114120286Swilko/* Multicatst Address Hash Register 3 (MCAH3) */ 115120286Swilko#define YUKON_MCAH3 0x003c 116120286Swilko 117120286Swilko/* Multicatst Address Hash Register 4 (MCAH4) */ 118120286Swilko#define YUKON_MCAH4 0x0040 119120286Swilko 120120286Swilko/* Transmit Interrupt Register (TIR) */ 121120286Swilko#define YUKON_TIR 0x0044 122120286Swilko 123120286Swilko#define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */ 124120286Swilko#define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */ 125120286Swilko#define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */ 126120286Swilko#define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */ 127120286Swilko#define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */ 128120286Swilko#define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */ 129120286Swilko#define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */ 130120286Swilko#define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */ 131120286Swilko#define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */ 132120286Swilko#define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */ 133120286Swilko#define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */ 134120286Swilko#define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */ 135120286Swilko#define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */ 136120286Swilko#define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */ 137120286Swilko#define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */ 138120286Swilko 139120286Swilko/* Receive Interrupt Register (RIR) */ 140120286Swilko#define YUKON_RIR 0x0048 141120286Swilko 142120286Swilko/* Transmit and Receive Interrupt Register (TRIR) */ 143120286Swilko#define YUKON_TRIR 0x004c 144120286Swilko 145120286Swilko/* Transmit Interrupt Mask Register (TIMR) */ 146120286Swilko#define YUKON_TIMR 0x0050 147120286Swilko 148120286Swilko/* Receive Interrupt Mask Register (RIMR) */ 149120286Swilko#define YUKON_RIMR 0x0054 150120286Swilko 151120286Swilko/* Transmit and Receive Interrupt Mask Register (TRIMR) */ 152120286Swilko#define YUKON_TRIMR 0x0058 153120286Swilko 154120286Swilko/* SMI Control Register (SMICR) */ 155120286Swilko#define YUKON_SMICR 0x0080 156120286Swilko 157120286Swilko#define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11) 158120286Swilko#define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6) 159120286Swilko#define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */ 160120286Swilko#define YU_SMICR_OP_READ 0x0020 /* opcode read */ 161120286Swilko#define YU_SMICR_OP_WRITE 0x0000 /* opcode write */ 162120286Swilko#define YU_SMICR_READ_VALID 0x0010 /* read valid */ 163120286Swilko#define YU_SMICR_BUSY 0x0008 /* busy (writing) */ 164120286Swilko 165120286Swilko/* SMI Data Register (SMIDR) */ 166120286Swilko#define YUKON_SMIDR 0x0084 167120286Swilko 168120286Swilko/* PHY Addres Register (PAR) */ 169120286Swilko#define YUKON_PAR 0x0088 170120286Swilko 171120286Swilko#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */ 172120286Swilko#define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */ 173158070Syongari 174158070Syongari/* Receive status */ 175158070Syongari#define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */ 176158070Syongari#define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */ 177158070Syongari#define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */ 178158070Syongari#define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */ 179158070Syongari#define YU_RXSTAT_MIIERR 0x00000020 /* MII error */ 180158070Syongari#define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */ 181158070Syongari#define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */ 182158070Syongari#define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */ 183158070Syongari#define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */ 184158070Syongari#define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */ 185158070Syongari#define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */ 186158070Syongari#define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */ 187158070Syongari#define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */ 188158070Syongari#define YU_RXSTAT_LENSHIFT 16 189158070Syongari 190158070Syongari#define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT) 191