if_sisreg.h revision 72813
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sisreg.h 72813 2001-02-21 20:54:22Z wpaul $ 33 */ 34 35/* 36 * Register definitions for the SiS 900 and SiS 7016 chipsets. The 37 * 7016 is actually an older chip and some of its registers differ 38 * from the 900, however the core operational registers are the same: 39 * the differences lie in the OnNow/Wake on LAN stuff which we don't 40 * use anyway. The 7016 needs an external MII compliant PHY while the 41 * SiS 900 has one built in. All registers are 32-bits wide. 42 */ 43 44/* Registers common to SiS 900 and SiS 7016 */ 45#define SIS_CSR 0x00 46#define SIS_CFG 0x04 47#define SIS_EECTL 0x08 48#define SIS_PCICTL 0x0C 49#define SIS_ISR 0x10 50#define SIS_IMR 0x14 51#define SIS_IER 0x18 52#define SIS_PHYCTL 0x1C 53#define SIS_TX_LISTPTR 0x20 54#define SIS_TX_CFG 0x24 55#define SIS_RX_LISTPTR 0x30 56#define SIS_RX_CFG 0x34 57#define SIS_FLOWCTL 0x38 58#define SIS_RXFILT_CTL 0x48 59#define SIS_RXFILT_DATA 0x4C 60#define SIS_PWRMAN_CTL 0xB0 61#define SIS_PWERMAN_WKUP_EVENT 0xB4 62#define SIS_WKUP_FRAME_CRC 0xBC 63#define SIS_WKUP_FRAME_MASK0 0xC0 64#define SIS_WKUP_FRAME_MASKXX 0xEC 65 66/* SiS 7016 specific registers */ 67#define SIS_SILICON_REV 0x5C 68#define SIS_MIB_CTL0 0x60 69#define SIS_MIB_CTL1 0x64 70#define SIS_MIB_CTL2 0x68 71#define SIS_MIB_CTL3 0x6C 72#define SIS_MIB 0x80 73#define SIS_LINKSTS 0xA0 74#define SIS_TIMEUNIT 0xA4 75#define SIS_GPIO 0xB8 76 77/* NS DP83815 registers */ 78#define NS_CLKRUN 0x3C 79#define NS_BMCR 0x80 80#define NS_BMSR 0x84 81#define NS_PHYIDR1 0x88 82#define NS_PHYIDR2 0x8C 83#define NS_ANAR 0x90 84#define NS_ANLPAR 0x94 85#define NS_ANER 0x98 86#define NS_ANNPTR 0x9C 87 88#define NS_PHY_CR 0xE4 89#define NS_PHY_10BTSCR 0xE8 90#define NS_PHY_PAGE 0xCC 91#define NS_PHY_EXTCFG 0xF0 92#define NS_PHY_DSPCFG 0xF4 93#define NS_PHY_SDCFG 0xF8 94#define NS_PHY_TDATA 0xFC 95 96#define NS_CLKRUN_PMESTS 0x00008000 97#define NS_CLKRUN_PMEENB 0x00000100 98#define NS_CLNRUN_CLKRUN_ENB 0x00000001 99 100#define SIS_CSR_TX_ENABLE 0x00000001 101#define SIS_CSR_TX_DISABLE 0x00000002 102#define SIS_CSR_RX_ENABLE 0x00000004 103#define SIS_CSR_RX_DISABLE 0x00000008 104#define SIS_CSR_TX_RESET 0x00000010 105#define SIS_CSR_RX_RESET 0x00000020 106#define SIS_CSR_SOFTINTR 0x00000080 107#define SIS_CSR_RESET 0x00000100 108 109#define SIS_CFG_BIGENDIAN 0x00000001 110#define SIS_CFG_PERR_DETECT 0x00000008 111#define SIS_CFG_DEFER_DISABLE 0x00000010 112#define SIS_CFG_OUTOFWIN_TIMER 0x00000020 113#define SIS_CFG_SINGLE_BACKOFF 0x00000040 114#define SIS_CFG_PCIREQ_ALG 0x00000080 115 116#define SIS_EECTL_DIN 0x00000001 117#define SIS_EECTL_DOUT 0x00000002 118#define SIS_EECTL_CLK 0x00000004 119#define SIS_EECTL_CSEL 0x00000008 120 121#define SIS_EECMD_WRITE 0x140 122#define SIS_EECMD_READ 0x180 123#define SIS_EECMD_ERASE 0x1c0 124 125#define SIS_EE_NODEADDR 0x8 126#define NS_EE_NODEADDR 0x6 127 128#define SIS_PCICTL_SRAMADDR 0x0000001F 129#define SIS_PCICTL_RAMTSTENB 0x00000020 130#define SIS_PCICTL_TXTSTENB 0x00000040 131#define SIS_PCICTL_RXTSTENB 0x00000080 132#define SIS_PCICTL_BMTSTENB 0x00000200 133#define SIS_PCICTL_RAMADDR 0x001F0000 134#define SIS_PCICTL_ROMTIME 0x0F000000 135#define SIS_PCICTL_DISCTEST 0x40000000 136 137#define SIS_ISR_RX_OK 0x00000001 138#define SIS_ISR_RX_DESC_OK 0x00000002 139#define SIS_ISR_RX_ERR 0x00000004 140#define SIS_ISR_RX_EARLY 0x00000008 141#define SIS_ISR_RX_IDLE 0x00000010 142#define SIS_ISR_RX_OFLOW 0x00000020 143#define SIS_ISR_TX_OK 0x00000040 144#define SIS_ISR_TX_DESC_OK 0x00000080 145#define SIS_ISR_TX_ERR 0x00000100 146#define SIS_ISR_TX_IDLE 0x00000200 147#define SIS_ISR_TX_UFLOW 0x00000400 148#define SIS_ISR_SOFTINTR 0x00000800 149#define SIS_ISR_HIBITS 0x00008000 150#define SIS_ISR_RX_FIFO_OFLOW 0x00010000 151#define SIS_ISR_TGT_ABRT 0x00100000 152#define SIS_ISR_BM_ABRT 0x00200000 153#define SIS_ISR_SYSERR 0x00400000 154#define SIS_ISR_PARITY_ERR 0x00800000 155#define SIS_ISR_RX_RESET_DONE 0x01000000 156#define SIS_ISR_TX_RESET_DONE 0x02000000 157#define SIS_ISR_TX_PAUSE_START 0x04000000 158#define SIS_ISR_TX_PAUSE_DONE 0x08000000 159#define SIS_ISR_WAKE_EVENT 0x10000000 160 161#define SIS_IMR_RX_OK 0x00000001 162#define SIS_IMR_RX_DESC_OK 0x00000002 163#define SIS_IMR_RX_ERR 0x00000004 164#define SIS_IMR_RX_EARLY 0x00000008 165#define SIS_IMR_RX_IDLE 0x00000010 166#define SIS_IMR_RX_OFLOW 0x00000020 167#define SIS_IMR_TX_OK 0x00000040 168#define SIS_IMR_TX_DESC_OK 0x00000080 169#define SIS_IMR_TX_ERR 0x00000100 170#define SIS_IMR_TX_IDLE 0x00000200 171#define SIS_IMR_TX_UFLOW 0x00000400 172#define SIS_IMR_SOFTINTR 0x00000800 173#define SIS_IMR_HIBITS 0x00008000 174#define SIS_IMR_RX_FIFO_OFLOW 0x00010000 175#define SIS_IMR_TGT_ABRT 0x00100000 176#define SIS_IMR_BM_ABRT 0x00200000 177#define SIS_IMR_SYSERR 0x00400000 178#define SIS_IMR_PARITY_ERR 0x00800000 179#define SIS_IMR_RX_RESET_DONE 0x01000000 180#define SIS_IMR_TX_RESET_DONE 0x02000000 181#define SIS_IMR_TX_PAUSE_START 0x04000000 182#define SIS_IMR_TX_PAUSE_DONE 0x08000000 183#define SIS_IMR_WAKE_EVENT 0x10000000 184 185#define SIS_INTRS \ 186 (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ 187 SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ 188 SIS_IMR_SYSERR) 189 190#define SIS_IER_INTRENB 0x00000001 191 192#define SIS_PHYCTL_ACCESS 0x00000010 193#define SIS_PHYCTL_OP 0x00000020 194#define SIS_PHYCTL_REGADDR 0x000007C0 195#define SIS_PHYCTL_PHYADDR 0x0000F800 196#define SIS_PHYCTL_PHYDATA 0xFFFF0000 197 198#define SIS_PHYOP_READ 0x00000020 199#define SIS_PHYOP_WRITE 0x00000000 200 201#define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ 202#define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ 203#define SIS_TXCFG_DMABURST 0x00700000 204#define SIS_TXCFG_AUTOPAD 0x10000000 205#define SIS_TXCFG_LOOPBK 0x20000000 206#define SIS_TXCFG_IGN_HBEAT 0x40000000 207#define SIS_TXCFG_IGN_CARR 0x80000000 208 209#define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) 210#define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) 211 212#define SIS_TXDMA_512BYTES 0x00000000 213#define SIS_TXDMA_4BYTES 0x00100000 214#define SIS_TXDMA_8BYTES 0x00200000 215#define SIS_TXDMA_16BYTES 0x00300000 216#define SIS_TXDMA_32BYTES 0x00400000 217#define SIS_TXDMA_64BYTES 0x00500000 218#define SIS_TXDMA_128BYTES 0x00600000 219#define SIS_TXDMA_256BYTES 0x00700000 220 221#define SIS_TXCFG_100 \ 222 (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ 223 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 224 225#define SIS_TXCFG_10 \ 226 (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\ 227 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 228 229#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 230#define SIS_RXCFG_DMABURST 0x00700000 231#define SIS_RXCFG_RX_JABBER 0x08000000 232#define SIS_RXCFG_RX_TXPKTS 0x10000000 233#define SIS_RXCFG_RX_RUNTS 0x40000000 234#define SIS_RXCFG_RX_GIANTS 0x80000000 235 236#define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) 237 238#define SIS_RXDMA_512BYTES 0x00000000 239#define SIS_RXDMA_4BYTES 0x00100000 240#define SIS_RXDMA_8BYTES 0x00200000 241#define SIS_RXDMA_16BYTES 0x00300000 242#define SIS_RXDMA_32BYTES 0x00400000 243#define SIS_RXDMA_64BYTES 0x00500000 244#define SIS_RXDMA_128BYTES 0x00600000 245#define SIS_RXDMA_256BYTES 0x00700000 246 247#define SIS_RXCFG \ 248 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES) 249 250#define SIS_RXFILTCTL_ADDR 0x000F0000 251#define NS_RXFILTCTL_MCHASH 0x00200000 252#define NS_RXFILTCTL_ARP 0x00400000 253#define NS_RXFILTCTL_PERFECT 0x08000000 254#define SIS_RXFILTCTL_ALLPHYS 0x10000000 255#define SIS_RXFILTCTL_ALLMULTI 0x20000000 256#define SIS_RXFILTCTL_BROAD 0x40000000 257#define SIS_RXFILTCTL_ENABLE 0x80000000 258 259#define SIS_FILTADDR_PAR0 0x00000000 260#define SIS_FILTADDR_PAR1 0x00010000 261#define SIS_FILTADDR_PAR2 0x00020000 262#define SIS_FILTADDR_MAR0 0x00040000 263#define SIS_FILTADDR_MAR1 0x00050000 264#define SIS_FILTADDR_MAR2 0x00060000 265#define SIS_FILTADDR_MAR3 0x00070000 266#define SIS_FILTADDR_MAR4 0x00080000 267#define SIS_FILTADDR_MAR5 0x00090000 268#define SIS_FILTADDR_MAR6 0x000A0000 269#define SIS_FILTADDR_MAR7 0x000B0000 270 271#define NS_FILTADDR_PAR0 0x00000000 272#define NS_FILTADDR_PAR1 0x00000002 273#define NS_FILTADDR_PAR2 0x00000004 274 275#define NS_FILTADDR_FMEM_LO 0x00000200 276#define NS_FILTADDR_FMEM_HI 0x000003FE 277 278/* 279 * DMA descriptor structures. The first part of the descriptor 280 * is the hardware descriptor format, which is just three longwords. 281 * After this, we include some additional structure members for 282 * use by the driver. Note that for this structure will be a different 283 * size on the alpha, but that's okay as long as it's a multiple of 4 284 * bytes in size. 285 */ 286struct sis_desc { 287 /* SiS hardware descriptor section */ 288 u_int32_t sis_next; 289 u_int32_t sis_cmdsts; 290#define sis_rxstat sis_cmdsts 291#define sis_txstat sis_cmdsts 292#define sis_ctl sis_cmdsts 293 u_int32_t sis_ptr; 294 /* Driver software section */ 295 struct mbuf *sis_mbuf; 296 struct sis_desc *sis_nextdesc; 297}; 298 299#define SIS_CMDSTS_BUFLEN 0x00000FFF 300#define SIS_CMDSTS_PKT_OK 0x08000000 301#define SIS_CMDSTS_CRC 0x10000000 302#define SIS_CMDSTS_INTR 0x20000000 303#define SIS_CMDSTS_MORE 0x40000000 304#define SIS_CMDSTS_OWN 0x80000000 305 306#define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE))) 307#define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN) 308#define SIS_INC(x, y) (x) = (x + 1) % y 309#define SIS_RXBYTES(x) ((x)->sis_ctl & SIS_CMDSTS_BUFLEN) 310 311#define SIS_RXSTAT_COLL 0x00010000 312#define SIS_RXSTAT_LOOPBK 0x00020000 313#define SIS_RXSTAT_ALIGNERR 0x00040000 314#define SIS_RXSTAT_CRCERR 0x00080000 315#define SIS_RXSTAT_SYMBOLERR 0x00100000 316#define SIS_RXSTAT_RUNT 0x00200000 317#define SIS_RXSTAT_GIANT 0x00400000 318#define SIS_RXSTAT_DSTCLASS 0x01800000 319#define SIS_RXSTAT_OVERRUN 0x02000000 320#define SIS_RXSTAT_RX_ABORT 0x04000000 321 322#define SIS_DSTCLASS_REJECT 0x00000000 323#define SIS_DSTCLASS_UNICAST 0x00800000 324#define SIS_DSTCLASS_MULTICAST 0x01000000 325#define SIS_DSTCLASS_BROADCAST 0x02000000 326 327#define SIS_TXSTAT_COLLCNT 0x000F0000 328#define SIS_TXSTAT_EXCESSCOLLS 0x00100000 329#define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 330#define SIS_TXSTAT_EXCESS_DEFER 0x00400000 331#define SIS_TXSTAT_DEFERED 0x00800000 332#define SIS_TXSTAT_CARR_LOST 0x01000000 333#define SIS_TXSTAT_UNDERRUN 0x02000000 334#define SIS_TXSTAT_TX_ABORT 0x04000000 335 336#define SIS_RX_LIST_CNT 64 337#define SIS_TX_LIST_CNT 128 338 339struct sis_list_data { 340 struct sis_desc sis_rx_list[SIS_RX_LIST_CNT]; 341 struct sis_desc sis_tx_list[SIS_TX_LIST_CNT]; 342}; 343 344struct sis_ring_data { 345 int sis_rx_prod; 346 int sis_tx_prod; 347 int sis_tx_cons; 348 int sis_tx_cnt; 349}; 350 351 352/* 353 * SiS PCI vendor ID. 354 */ 355#define SIS_VENDORID 0x1039 356 357/* 358 * SiS PCI device IDs 359 */ 360#define SIS_DEVICEID_900 0x0900 361#define SIS_DEVICEID_7016 0x7016 362 363/* 364 * SiS 900 PCI revision codes. 365 */ 366#define SIS_REV_630E 0x0081 367#define SIS_REV_630S 0x0082 368#define SIS_REV_630EA1 0x0083 369 370/* 371 * NatSemi vendor ID 372 */ 373#define NS_VENDORID 0x100B 374 375/* 376 * DP83815 device ID 377 */ 378#define NS_DEVICEID_DP83815 0x0020 379 380struct sis_type { 381 u_int16_t sis_vid; 382 u_int16_t sis_did; 383 char *sis_name; 384}; 385 386#define SIS_TYPE_900 1 387#define SIS_TYPE_7016 2 388#define SIS_TYPE_83815 3 389 390struct sis_softc { 391 struct arpcom arpcom; /* interface info */ 392 bus_space_handle_t sis_bhandle; 393 bus_space_tag_t sis_btag; 394 struct resource *sis_res; 395 struct resource *sis_irq; 396 void *sis_intrhand; 397 device_t sis_miibus; 398 u_int8_t sis_unit; 399 u_int8_t sis_type; 400 u_int8_t sis_link; 401 struct sis_list_data *sis_ldata; 402 struct sis_ring_data sis_cdata; 403 struct callout_handle sis_stat_ch; 404 struct mtx sis_mtx; 405}; 406 407#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 408#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 409 410/* 411 * register space access macros 412 */ 413#define CSR_WRITE_4(sc, reg, val) \ 414 bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val) 415 416#define CSR_READ_4(sc, reg) \ 417 bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg) 418 419#define SIS_TIMEOUT 1000 420#define ETHER_ALIGN 2 421#define SIS_RXLEN 1536 422#define SIS_MIN_FRAMELEN 60 423 424/* 425 * PCI low memory base and low I/O base register, and 426 * other PCI registers. 427 */ 428 429#define SIS_PCI_VENDOR_ID 0x00 430#define SIS_PCI_DEVICE_ID 0x02 431#define SIS_PCI_COMMAND 0x04 432#define SIS_PCI_STATUS 0x06 433#define SIS_PCI_REVID 0x08 434#define SIS_PCI_CLASSCODE 0x09 435#define SIS_PCI_CACHELEN 0x0C 436#define SIS_PCI_LATENCY_TIMER 0x0D 437#define SIS_PCI_HEADER_TYPE 0x0E 438#define SIS_PCI_LOIO 0x10 439#define SIS_PCI_LOMEM 0x14 440#define SIS_PCI_BIOSROM 0x30 441#define SIS_PCI_INTLINE 0x3C 442#define SIS_PCI_INTPIN 0x3D 443#define SIS_PCI_MINGNT 0x3E 444#define SIS_PCI_MINLAT 0x0F 445#define SIS_PCI_RESETOPT 0x48 446#define SIS_PCI_EEPROM_DATA 0x4C 447 448/* power management registers */ 449#define SIS_PCI_CAPID 0x50 /* 8 bits */ 450#define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ 451#define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 452#define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 453 454#define SIS_PSTATE_MASK 0x0003 455#define SIS_PSTATE_D0 0x0000 456#define SIS_PSTATE_D1 0x0001 457#define SIS_PSTATE_D2 0x0002 458#define SIS_PSTATE_D3 0x0003 459#define SIS_PME_EN 0x0010 460#define SIS_PME_STATUS 0x8000 461 462#ifdef __alpha__ 463#undef vtophys 464#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 465#endif 466