if_sisreg.h revision 62672
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sisreg.h 62672 2000-07-06 06:02:04Z wpaul $ 33 */ 34 35/* 36 * Register definitions for the SiS 900 and SiS 7016 chipsets. The 37 * 7016 is actually an older chip and some of its registers differ 38 * from the 900, however the core operational registers are the same: 39 * the differences lie in the OnNow/Wake on LAN stuff which we don't 40 * use anyway. The 7016 needs an external MII compliant PHY while the 41 * SiS 900 has one built in. All registers are 32-bits wide. 42 */ 43 44/* Registers common to SiS 900 and SiS 7016 */ 45#define SIS_CSR 0x00 46#define SIS_CFG 0x04 47#define SIS_EECTL 0x08 48#define SIS_PCICTL 0x0C 49#define SIS_ISR 0x10 50#define SIS_IMR 0x14 51#define SIS_IER 0x18 52#define SIS_PHYCTL 0x1C 53#define SIS_TX_LISTPTR 0x20 54#define SIS_TX_CFG 0x24 55#define SIS_RX_LISTPTR 0x30 56#define SIS_RX_CFG 0x34 57#define SIS_FLOWCTL 0x38 58#define SIS_RXFILT_CTL 0x48 59#define SIS_RXFILT_DATA 0x4C 60#define SIS_PWRMAN_CTL 0xB0 61#define SIS_PWERMAN_WKUP_EVENT 0xB4 62#define SIS_WKUP_FRAME_CRC 0xBC 63#define SIS_WKUP_FRAME_MASK0 0xC0 64#define SIS_WKUP_FRAME_MASKXX 0xEC 65 66/* SiS 7016 specific registers */ 67#define SIS_SILICON_REV 0x5C 68#define SIS_MIB_CTL0 0x60 69#define SIS_MIB_CTL1 0x64 70#define SIS_MIB_CTL2 0x68 71#define SIS_MIB_CTL3 0x6C 72#define SIS_MIB 0x80 73#define SIS_LINKSTS 0xA0 74#define SIS_TIMEUNIT 0xA4 75#define SIS_GPIO 0xB8 76 77/* NS DP83815 registers */ 78#define NS_BMCR 0x80 79#define NS_BMSR 0x84 80#define NS_PHYIDR1 0x88 81#define NS_PHYIDR2 0x8C 82#define NS_ANAR 0x90 83#define NS_ANLPAR 0x94 84#define NS_ANER 0x98 85#define NS_ANNPTR 0x9C 86 87#define SIS_CSR_TX_ENABLE 0x00000001 88#define SIS_CSR_TX_DISABLE 0x00000002 89#define SIS_CSR_RX_ENABLE 0x00000004 90#define SIS_CSR_RX_DISABLE 0x00000008 91#define SIS_CSR_TX_RESET 0x00000010 92#define SIS_CSR_RX_RESET 0x00000020 93#define SIS_CSR_SOFTINTR 0x00000080 94#define SIS_CSR_RESET 0x00000100 95 96#define SIS_CFG_BIGENDIAN 0x00000001 97#define SIS_CFG_PERR_DETECT 0x00000008 98#define SIS_CFG_DEFER_DISABLE 0x00000010 99#define SIS_CFG_OUTOFWIN_TIMER 0x00000020 100#define SIS_CFG_SINGLE_BACKOFF 0x00000040 101#define SIS_CFG_PCIREQ_ALG 0x00000080 102 103#define SIS_EECTL_DIN 0x00000001 104#define SIS_EECTL_DOUT 0x00000002 105#define SIS_EECTL_CLK 0x00000004 106#define SIS_EECTL_CSEL 0x00000008 107 108#define SIS_EECMD_WRITE 0x140 109#define SIS_EECMD_READ 0x180 110#define SIS_EECMD_ERASE 0x1c0 111 112#define SIS_EE_NODEADDR 0x8 113#define NS_EE_NODEADDR 0x6 114 115#define SIS_PCICTL_SRAMADDR 0x0000001F 116#define SIS_PCICTL_RAMTSTENB 0x00000020 117#define SIS_PCICTL_TXTSTENB 0x00000040 118#define SIS_PCICTL_RXTSTENB 0x00000080 119#define SIS_PCICTL_BMTSTENB 0x00000200 120#define SIS_PCICTL_RAMADDR 0x001F0000 121#define SIS_PCICTL_ROMTIME 0x0F000000 122#define SIS_PCICTL_DISCTEST 0x40000000 123 124#define SIS_ISR_RX_OK 0x00000001 125#define SIS_ISR_RX_DESC_OK 0x00000002 126#define SIS_ISR_RX_ERR 0x00000004 127#define SIS_ISR_RX_EARLY 0x00000008 128#define SIS_ISR_RX_IDLE 0x00000010 129#define SIS_ISR_RX_OFLOW 0x00000020 130#define SIS_ISR_TX_OK 0x00000040 131#define SIS_ISR_TX_DESC_OK 0x00000080 132#define SIS_ISR_TX_ERR 0x00000100 133#define SIS_ISR_TX_IDLE 0x00000200 134#define SIS_ISR_TX_UFLOW 0x00000400 135#define SIS_ISR_SOFTINTR 0x00000800 136#define SIS_ISR_HIBITS 0x00008000 137#define SIS_ISR_RX_FIFO_OFLOW 0x00010000 138#define SIS_ISR_TGT_ABRT 0x00100000 139#define SIS_ISR_BM_ABRT 0x00200000 140#define SIS_ISR_SYSERR 0x00400000 141#define SIS_ISR_PARITY_ERR 0x00800000 142#define SIS_ISR_RX_RESET_DONE 0x01000000 143#define SIS_ISR_TX_RESET_DONE 0x02000000 144#define SIS_ISR_TX_PAUSE_START 0x04000000 145#define SIS_ISR_TX_PAUSE_DONE 0x08000000 146#define SIS_ISR_WAKE_EVENT 0x10000000 147 148#define SIS_IMR_RX_OK 0x00000001 149#define SIS_IMR_RX_DESC_OK 0x00000002 150#define SIS_IMR_RX_ERR 0x00000004 151#define SIS_IMR_RX_EARLY 0x00000008 152#define SIS_IMR_RX_IDLE 0x00000010 153#define SIS_IMR_RX_OFLOW 0x00000020 154#define SIS_IMR_TX_OK 0x00000040 155#define SIS_IMR_TX_DESC_OK 0x00000080 156#define SIS_IMR_TX_ERR 0x00000100 157#define SIS_IMR_TX_IDLE 0x00000200 158#define SIS_IMR_TX_UFLOW 0x00000400 159#define SIS_IMR_SOFTINTR 0x00000800 160#define SIS_IMR_HIBITS 0x00008000 161#define SIS_IMR_RX_FIFO_OFLOW 0x00010000 162#define SIS_IMR_TGT_ABRT 0x00100000 163#define SIS_IMR_BM_ABRT 0x00200000 164#define SIS_IMR_SYSERR 0x00400000 165#define SIS_IMR_PARITY_ERR 0x00800000 166#define SIS_IMR_RX_RESET_DONE 0x01000000 167#define SIS_IMR_TX_RESET_DONE 0x02000000 168#define SIS_IMR_TX_PAUSE_START 0x04000000 169#define SIS_IMR_TX_PAUSE_DONE 0x08000000 170#define SIS_IMR_WAKE_EVENT 0x10000000 171 172#define SIS_INTRS \ 173 (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ 174 SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ 175 SIS_IMR_SYSERR) 176 177#define SIS_IER_INTRENB 0x00000001 178 179#define SIS_PHYCTL_ACCESS 0x00000010 180#define SIS_PHYCTL_OP 0x00000020 181#define SIS_PHYCTL_REGADDR 0x000007C0 182#define SIS_PHYCTL_PHYADDR 0x0000F800 183#define SIS_PHYCTL_PHYDATA 0xFFFF0000 184 185#define SIS_PHYOP_READ 0x00000020 186#define SIS_PHYOP_WRITE 0x00000000 187 188#define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ 189#define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ 190#define SIS_TXCFG_DMABURST 0x00700000 191#define SIS_TXCFG_AUTOPAD 0x10000000 192#define SIS_TXCFG_LOOPBK 0x20000000 193#define SIS_TXCFG_IGN_HBEAT 0x40000000 194#define SIS_TXCFG_IGN_CARR 0x80000000 195 196#define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) 197#define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) 198 199#define SIS_TXDMA_512BYTES 0x00000000 200#define SIS_TXDMA_4BYTES 0x00100000 201#define SIS_TXDMA_8BYTES 0x00200000 202#define SIS_TXDMA_16BYTES 0x00300000 203#define SIS_TXDMA_32BYTES 0x00400000 204#define SIS_TXDMA_64BYTES 0x00500000 205#define SIS_TXDMA_128BYTES 0x00600000 206#define SIS_TXDMA_256BYTES 0x00700000 207 208#define SIS_TXCFG \ 209 (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ 210 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1500)) 211 212#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 213#define SIS_RXCFG_DMABURST 0x00700000 214#define SIS_RXCFG_RX_JABBER 0x08000000 215#define SIS_RXCFG_RX_TXPKTS 0x10000000 216#define SIS_RXCFG_RX_RUNTS 0x40000000 217#define SIS_RXCFG_RX_GIANTS 0x80000000 218 219#define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) 220 221#define SIS_RXDMA_512BYTES 0x00000000 222#define SIS_RXDMA_4BYTES 0x00100000 223#define SIS_RXDMA_8BYTES 0x00200000 224#define SIS_RXDMA_16BYTES 0x00300000 225#define SIS_RXDMA_32BYTES 0x00400000 226#define SIS_RXDMA_64BYTES 0x00500000 227#define SIS_RXDMA_128BYTES 0x00600000 228#define SIS_RXDMA_256BYTES 0x00700000 229 230#define SIS_RXCFG \ 231 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES) 232 233#define SIS_RXFILTCTL_ADDR 0x000F0000 234#define NS_RXFILTCTL_MCHASH 0x00200000 235#define NS_RXFILTCTL_ARP 0x00400000 236#define NS_RXFILTCTL_PERFECT 0x08000000 237#define SIS_RXFILTCTL_ALLPHYS 0x10000000 238#define SIS_RXFILTCTL_ALLMULTI 0x20000000 239#define SIS_RXFILTCTL_BROAD 0x40000000 240#define SIS_RXFILTCTL_ENABLE 0x80000000 241 242#define SIS_FILTADDR_PAR0 0x00000000 243#define SIS_FILTADDR_PAR1 0x00010000 244#define SIS_FILTADDR_PAR2 0x00020000 245#define SIS_FILTADDR_MAR0 0x00040000 246#define SIS_FILTADDR_MAR1 0x00050000 247#define SIS_FILTADDR_MAR2 0x00060000 248#define SIS_FILTADDR_MAR3 0x00070000 249#define SIS_FILTADDR_MAR4 0x00080000 250#define SIS_FILTADDR_MAR5 0x00090000 251#define SIS_FILTADDR_MAR6 0x000A0000 252#define SIS_FILTADDR_MAR7 0x000B0000 253 254#define NS_FILTADDR_PAR0 0x00000000 255#define NS_FILTADDR_PAR1 0x00000002 256#define NS_FILTADDR_PAR2 0x00000004 257 258#define NS_FILTADDR_FMEM_LO 0x00000200 259#define NS_FILTADDR_FMEM_HI 0x000003FE 260 261/* 262 * DMA descriptor structures. The first part of the descriptor 263 * is the hardware descriptor format, which is just three longwords. 264 * After this, we include some additional structure members for 265 * use by the driver. Note that for this structure will be a different 266 * size on the alpha, but that's okay as long as it's a multiple of 4 267 * bytes in size. 268 */ 269struct sis_desc { 270 /* SiS hardware descriptor section */ 271 u_int32_t sis_next; 272 u_int32_t sis_cmdsts; 273#define sis_rxstat sis_cmdsts 274#define sis_txstat sis_cmdsts 275#define sis_ctl sis_cmdsts 276 u_int32_t sis_ptr; 277 /* Driver software section */ 278 struct mbuf *sis_mbuf; 279 struct sis_desc *sis_nextdesc; 280}; 281 282#define SIS_CMDSTS_BUFLEN 0x00000FFF 283#define SIS_CMDSTS_PKT_OK 0x08000000 284#define SIS_CMDSTS_CRC 0x10000000 285#define SIS_CMDSTS_INTR 0x20000000 286#define SIS_CMDSTS_MORE 0x40000000 287#define SIS_CMDSTS_OWN 0x80000000 288 289#define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE))) 290#define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN) 291#define SIS_INC(x, y) (x) = (x + 1) % y 292#define SIS_RXBYTES(x) ((x)->sis_ctl & SIS_CMDSTS_BUFLEN) 293 294#define SIS_RXSTAT_COLL 0x00010000 295#define SIS_RXSTAT_LOOPBK 0x00020000 296#define SIS_RXSTAT_ALIGNERR 0x00040000 297#define SIS_RXSTAT_CRCERR 0x00080000 298#define SIS_RXSTAT_SYMBOLERR 0x00100000 299#define SIS_RXSTAT_RUNT 0x00200000 300#define SIS_RXSTAT_GIANT 0x00400000 301#define SIS_RXSTAT_DSTCLASS 0x01800000 302#define SIS_RXSTAT_OVERRUN 0x02000000 303#define SIS_RXSTAT_RX_ABORT 0x04000000 304 305#define SIS_DSTCLASS_REJECT 0x00000000 306#define SIS_DSTCLASS_UNICAST 0x00800000 307#define SIS_DSTCLASS_MULTICAST 0x01000000 308#define SIS_DSTCLASS_BROADCAST 0x02000000 309 310#define SIS_TXSTAT_COLLCNT 0x000F0000 311#define SIS_TXSTAT_EXCESSCOLLS 0x00100000 312#define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 313#define SIS_TXSTAT_EXCESS_DEFER 0x00400000 314#define SIS_TXSTAT_DEFERED 0x00800000 315#define SIS_TXSTAT_CARR_LOST 0x01000000 316#define SIS_TXSTAT_UNDERRUN 0x02000000 317#define SIS_TXSTAT_TX_ABORT 0x04000000 318 319#define SIS_RX_LIST_CNT 64 320#define SIS_TX_LIST_CNT 128 321 322struct sis_list_data { 323 struct sis_desc sis_rx_list[SIS_RX_LIST_CNT]; 324 struct sis_desc sis_tx_list[SIS_TX_LIST_CNT]; 325}; 326 327struct sis_ring_data { 328 int sis_rx_prod; 329 int sis_tx_prod; 330 int sis_tx_cons; 331 int sis_tx_cnt; 332}; 333 334 335/* 336 * SiS PCI vendor ID. 337 */ 338#define SIS_VENDORID 0x1039 339 340/* 341 * SiS PCI device IDs 342 */ 343#define SIS_DEVICEID_900 0x0900 344#define SIS_DEVICEID_7016 0x7016 345 346/* 347 * NatSemi vendor ID 348 */ 349#define NS_VENDORID 0x100B 350 351/* 352 * DP83815 device ID 353 */ 354#define NS_DEVICEID_DP83815 0x0020 355 356struct sis_type { 357 u_int16_t sis_vid; 358 u_int16_t sis_did; 359 char *sis_name; 360}; 361 362#define SIS_TYPE_900 1 363#define SIS_TYPE_7016 2 364#define SIS_TYPE_83815 3 365 366struct sis_softc { 367 struct arpcom arpcom; /* interface info */ 368 bus_space_handle_t sis_bhandle; 369 bus_space_tag_t sis_btag; 370 struct resource *sis_res; 371 struct resource *sis_irq; 372 void *sis_intrhand; 373 device_t sis_miibus; 374 u_int8_t sis_unit; 375 u_int8_t sis_type; 376 struct sis_list_data *sis_ldata; 377 struct sis_ring_data sis_cdata; 378 struct callout_handle sis_stat_ch; 379}; 380 381/* 382 * register space access macros 383 */ 384#define CSR_WRITE_4(sc, reg, val) \ 385 bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val) 386 387#define CSR_READ_4(sc, reg) \ 388 bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg) 389 390#define SIS_TIMEOUT 1000 391#define ETHER_ALIGN 2 392#define SIS_RXLEN 1536 393#define SIS_MIN_FRAMELEN 60 394 395/* 396 * PCI low memory base and low I/O base register, and 397 * other PCI registers. 398 */ 399 400#define SIS_PCI_VENDOR_ID 0x00 401#define SIS_PCI_DEVICE_ID 0x02 402#define SIS_PCI_COMMAND 0x04 403#define SIS_PCI_STATUS 0x06 404#define SIS_PCI_REVID 0x08 405#define SIS_PCI_CLASSCODE 0x09 406#define SIS_PCI_CACHELEN 0x0C 407#define SIS_PCI_LATENCY_TIMER 0x0D 408#define SIS_PCI_HEADER_TYPE 0x0E 409#define SIS_PCI_LOIO 0x10 410#define SIS_PCI_LOMEM 0x14 411#define SIS_PCI_BIOSROM 0x30 412#define SIS_PCI_INTLINE 0x3C 413#define SIS_PCI_INTPIN 0x3D 414#define SIS_PCI_MINGNT 0x3E 415#define SIS_PCI_MINLAT 0x0F 416#define SIS_PCI_RESETOPT 0x48 417#define SIS_PCI_EEPROM_DATA 0x4C 418 419/* power management registers */ 420#define SIS_PCI_CAPID 0x50 /* 8 bits */ 421#define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ 422#define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 423#define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 424 425#define SIS_PSTATE_MASK 0x0003 426#define SIS_PSTATE_D0 0x0000 427#define SIS_PSTATE_D1 0x0001 428#define SIS_PSTATE_D2 0x0002 429#define SIS_PSTATE_D3 0x0003 430#define SIS_PME_EN 0x0010 431#define SIS_PME_STATUS 0x8000 432 433#ifdef __alpha__ 434#undef vtophys 435#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 436#endif 437