if_sisreg.h revision 123833
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sisreg.h 123833 2003-12-25 22:14:25Z phk $ 33 */ 34 35/* 36 * Register definitions for the SiS 900 and SiS 7016 chipsets. The 37 * 7016 is actually an older chip and some of its registers differ 38 * from the 900, however the core operational registers are the same: 39 * the differences lie in the OnNow/Wake on LAN stuff which we don't 40 * use anyway. The 7016 needs an external MII compliant PHY while the 41 * SiS 900 has one built in. All registers are 32-bits wide. 42 */ 43 44/* Registers common to SiS 900 and SiS 7016 */ 45#define SIS_CSR 0x00 46#define SIS_CFG 0x04 47#define SIS_EECTL 0x08 48#define SIS_PCICTL 0x0C 49#define SIS_ISR 0x10 50#define SIS_IMR 0x14 51#define SIS_IER 0x18 52#define SIS_PHYCTL 0x1C 53#define SIS_TX_LISTPTR 0x20 54#define SIS_TX_CFG 0x24 55#define SIS_RX_LISTPTR 0x30 56#define SIS_RX_CFG 0x34 57#define SIS_FLOWCTL 0x38 58#define SIS_RXFILT_CTL 0x48 59#define SIS_RXFILT_DATA 0x4C 60#define SIS_PWRMAN_CTL 0xB0 61#define SIS_PWERMAN_WKUP_EVENT 0xB4 62#define SIS_WKUP_FRAME_CRC 0xBC 63#define SIS_WKUP_FRAME_MASK0 0xC0 64#define SIS_WKUP_FRAME_MASKXX 0xEC 65 66/* SiS 7016 specific registers */ 67#define SIS_SILICON_REV 0x5C 68#define SIS_MIB_CTL0 0x60 69#define SIS_MIB_CTL1 0x64 70#define SIS_MIB_CTL2 0x68 71#define SIS_MIB_CTL3 0x6C 72#define SIS_MIB 0x80 73#define SIS_LINKSTS 0xA0 74#define SIS_TIMEUNIT 0xA4 75#define SIS_GPIO 0xB8 76 77/* NS DP83815/6 registers */ 78#define NS_IHR 0x1C 79#define NS_CLKRUN 0x3C 80#define NS_SRR 0x58 81#define NS_BMCR 0x80 82#define NS_BMSR 0x84 83#define NS_PHYIDR1 0x88 84#define NS_PHYIDR2 0x8C 85#define NS_ANAR 0x90 86#define NS_ANLPAR 0x94 87#define NS_ANER 0x98 88#define NS_ANNPTR 0x9C 89 90#define NS_PHY_CR 0xE4 91#define NS_PHY_10BTSCR 0xE8 92#define NS_PHY_PAGE 0xCC 93#define NS_PHY_EXTCFG 0xF0 94#define NS_PHY_DSPCFG 0xF4 95#define NS_PHY_SDCFG 0xF8 96#define NS_PHY_TDATA 0xFC 97 98#define NS_CLKRUN_PMESTS 0x00008000 99#define NS_CLKRUN_PMEENB 0x00000100 100#define NS_CLNRUN_CLKRUN_ENB 0x00000001 101 102/* NS silicon revisions */ 103#define NS_SRR_15C 0x302 104#define NS_SRR_15D 0x403 105#define NS_SRR_16A 0x505 106 107#define SIS_CSR_TX_ENABLE 0x00000001 108#define SIS_CSR_TX_DISABLE 0x00000002 109#define SIS_CSR_RX_ENABLE 0x00000004 110#define SIS_CSR_RX_DISABLE 0x00000008 111#define SIS_CSR_TX_RESET 0x00000010 112#define SIS_CSR_RX_RESET 0x00000020 113#define SIS_CSR_SOFTINTR 0x00000080 114#define SIS_CSR_RESET 0x00000100 115#define SIS_CSR_ACCESS_MODE 0x00000200 116#define SIS_CSR_RELOAD 0x00000400 117 118#define SIS_CFG_BIGENDIAN 0x00000001 119#define SIS_CFG_PERR_DETECT 0x00000008 120#define SIS_CFG_DEFER_DISABLE 0x00000010 121#define SIS_CFG_OUTOFWIN_TIMER 0x00000020 122#define SIS_CFG_SINGLE_BACKOFF 0x00000040 123#define SIS_CFG_PCIREQ_ALG 0x00000080 124#define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */ 125#define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */ 126#define SIS_CFG_EDB_MASTER_EN 0x00002000 127 128#define SIS_EECTL_DIN 0x00000001 129#define SIS_EECTL_DOUT 0x00000002 130#define SIS_EECTL_CLK 0x00000004 131#define SIS_EECTL_CSEL 0x00000008 132 133#define SIS_MII_CLK 0x00000040 134#define SIS_MII_DIR 0x00000020 135#define SIS_MII_DATA 0x00000010 136 137#define SIS_EECMD_WRITE 0x140 138#define SIS_EECMD_READ 0x180 139#define SIS_EECMD_ERASE 0x1c0 140 141/* 142 * EEPROM Commands for SiS96x 143 * chipsets. 144 */ 145#define SIS_EECMD_REQ 0x00000400 146#define SIS_EECMD_DONE 0x00000200 147#define SIS_EECMD_GNT 0x00000100 148 149#define SIS_EE_NODEADDR 0x8 150#define NS_EE_NODEADDR 0x6 151 152#define SIS_PCICTL_SRAMADDR 0x0000001F 153#define SIS_PCICTL_RAMTSTENB 0x00000020 154#define SIS_PCICTL_TXTSTENB 0x00000040 155#define SIS_PCICTL_RXTSTENB 0x00000080 156#define SIS_PCICTL_BMTSTENB 0x00000200 157#define SIS_PCICTL_RAMADDR 0x001F0000 158#define SIS_PCICTL_ROMTIME 0x0F000000 159#define SIS_PCICTL_DISCTEST 0x40000000 160 161#define SIS_ISR_RX_OK 0x00000001 162#define SIS_ISR_RX_DESC_OK 0x00000002 163#define SIS_ISR_RX_ERR 0x00000004 164#define SIS_ISR_RX_EARLY 0x00000008 165#define SIS_ISR_RX_IDLE 0x00000010 166#define SIS_ISR_RX_OFLOW 0x00000020 167#define SIS_ISR_TX_OK 0x00000040 168#define SIS_ISR_TX_DESC_OK 0x00000080 169#define SIS_ISR_TX_ERR 0x00000100 170#define SIS_ISR_TX_IDLE 0x00000200 171#define SIS_ISR_TX_UFLOW 0x00000400 172#define SIS_ISR_SOFTINTR 0x00000800 173#define SIS_ISR_HIBITS 0x00008000 174#define SIS_ISR_RX_FIFO_OFLOW 0x00010000 175#define SIS_ISR_TGT_ABRT 0x00100000 176#define SIS_ISR_BM_ABRT 0x00200000 177#define SIS_ISR_SYSERR 0x00400000 178#define SIS_ISR_PARITY_ERR 0x00800000 179#define SIS_ISR_RX_RESET_DONE 0x01000000 180#define SIS_ISR_TX_RESET_DONE 0x02000000 181#define SIS_ISR_TX_PAUSE_START 0x04000000 182#define SIS_ISR_TX_PAUSE_DONE 0x08000000 183#define SIS_ISR_WAKE_EVENT 0x10000000 184 185#define SIS_IMR_RX_OK 0x00000001 186#define SIS_IMR_RX_DESC_OK 0x00000002 187#define SIS_IMR_RX_ERR 0x00000004 188#define SIS_IMR_RX_EARLY 0x00000008 189#define SIS_IMR_RX_IDLE 0x00000010 190#define SIS_IMR_RX_OFLOW 0x00000020 191#define SIS_IMR_TX_OK 0x00000040 192#define SIS_IMR_TX_DESC_OK 0x00000080 193#define SIS_IMR_TX_ERR 0x00000100 194#define SIS_IMR_TX_IDLE 0x00000200 195#define SIS_IMR_TX_UFLOW 0x00000400 196#define SIS_IMR_SOFTINTR 0x00000800 197#define SIS_IMR_HIBITS 0x00008000 198#define SIS_IMR_RX_FIFO_OFLOW 0x00010000 199#define SIS_IMR_TGT_ABRT 0x00100000 200#define SIS_IMR_BM_ABRT 0x00200000 201#define SIS_IMR_SYSERR 0x00400000 202#define SIS_IMR_PARITY_ERR 0x00800000 203#define SIS_IMR_RX_RESET_DONE 0x01000000 204#define SIS_IMR_TX_RESET_DONE 0x02000000 205#define SIS_IMR_TX_PAUSE_START 0x04000000 206#define SIS_IMR_TX_PAUSE_DONE 0x08000000 207#define SIS_IMR_WAKE_EVENT 0x10000000 208 209#define SIS_INTRS \ 210 (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ 211 SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ 212 SIS_IMR_RX_IDLE|\ 213 SIS_IMR_SYSERR) 214 215#define SIS_IER_INTRENB 0x00000001 216 217#define SIS_PHYCTL_ACCESS 0x00000010 218#define SIS_PHYCTL_OP 0x00000020 219#define SIS_PHYCTL_REGADDR 0x000007C0 220#define SIS_PHYCTL_PHYADDR 0x0000F800 221#define SIS_PHYCTL_PHYDATA 0xFFFF0000 222 223#define SIS_PHYOP_READ 0x00000020 224#define SIS_PHYOP_WRITE 0x00000000 225 226#define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ 227#define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ 228#define SIS_TXCFG_DMABURST 0x00700000 229#define SIS_TXCFG_AUTOPAD 0x10000000 230#define SIS_TXCFG_LOOPBK 0x20000000 231#define SIS_TXCFG_IGN_HBEAT 0x40000000 232#define SIS_TXCFG_IGN_CARR 0x80000000 233 234#define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) 235#define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) 236 237#define SIS_TXDMA_512BYTES 0x00000000 238#define SIS_TXDMA_4BYTES 0x00100000 239#define SIS_TXDMA_8BYTES 0x00200000 240#define SIS_TXDMA_16BYTES 0x00300000 241#define SIS_TXDMA_32BYTES 0x00400000 242#define SIS_TXDMA_64BYTES 0x00500000 243#define SIS_TXDMA_128BYTES 0x00600000 244#define SIS_TXDMA_256BYTES 0x00700000 245 246#define SIS_TXCFG_100 \ 247 (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ 248 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 249 250#define SIS_TXCFG_10 \ 251 (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\ 252 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 253 254#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 255#define SIS_RXCFG_DMABURST 0x00700000 256#define SIS_RXCFG_RX_JABBER 0x08000000 257#define SIS_RXCFG_RX_TXPKTS 0x10000000 258#define SIS_RXCFG_RX_RUNTS 0x40000000 259#define SIS_RXCFG_RX_GIANTS 0x80000000 260 261#define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) 262 263#define SIS_RXDMA_512BYTES 0x00000000 264#define SIS_RXDMA_4BYTES 0x00100000 265#define SIS_RXDMA_8BYTES 0x00200000 266#define SIS_RXDMA_16BYTES 0x00300000 267#define SIS_RXDMA_32BYTES 0x00400000 268#define SIS_RXDMA_64BYTES 0x00500000 269#define SIS_RXDMA_128BYTES 0x00600000 270#define SIS_RXDMA_256BYTES 0x00700000 271 272#define SIS_RXCFG256 \ 273 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES) 274#define SIS_RXCFG64 \ 275 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES) 276 277#define SIS_RXFILTCTL_ADDR 0x000F0000 278#define NS_RXFILTCTL_MCHASH 0x00200000 279#define NS_RXFILTCTL_ARP 0x00400000 280#define NS_RXFILTCTL_PERFECT 0x08000000 281#define SIS_RXFILTCTL_ALLPHYS 0x10000000 282#define SIS_RXFILTCTL_ALLMULTI 0x20000000 283#define SIS_RXFILTCTL_BROAD 0x40000000 284#define SIS_RXFILTCTL_ENABLE 0x80000000 285 286#define SIS_FILTADDR_PAR0 0x00000000 287#define SIS_FILTADDR_PAR1 0x00010000 288#define SIS_FILTADDR_PAR2 0x00020000 289#define SIS_FILTADDR_MAR0 0x00040000 290#define SIS_FILTADDR_MAR1 0x00050000 291#define SIS_FILTADDR_MAR2 0x00060000 292#define SIS_FILTADDR_MAR3 0x00070000 293#define SIS_FILTADDR_MAR4 0x00080000 294#define SIS_FILTADDR_MAR5 0x00090000 295#define SIS_FILTADDR_MAR6 0x000A0000 296#define SIS_FILTADDR_MAR7 0x000B0000 297 298#define NS_FILTADDR_PAR0 0x00000000 299#define NS_FILTADDR_PAR1 0x00000002 300#define NS_FILTADDR_PAR2 0x00000004 301 302#define NS_FILTADDR_FMEM_LO 0x00000200 303#define NS_FILTADDR_FMEM_HI 0x000003FE 304 305/* 306 * DMA descriptor structures. The first part of the descriptor 307 * is the hardware descriptor format, which is just three longwords. 308 * After this, we include some additional structure members for 309 * use by the driver. Note that for this structure will be a different 310 * size on the alpha, but that's okay as long as it's a multiple of 4 311 * bytes in size. 312 */ 313struct sis_desc { 314 /* SiS hardware descriptor section */ 315 u_int32_t sis_next; 316 u_int32_t sis_cmdsts; 317#define sis_rxstat sis_cmdsts 318#define sis_txstat sis_cmdsts 319#define sis_ctl sis_cmdsts 320 u_int32_t sis_ptr; 321 /* Driver software section */ 322 struct mbuf *sis_mbuf; 323 struct sis_desc *sis_nextdesc; 324 bus_dmamap_t sis_map; 325}; 326 327#define SIS_CMDSTS_BUFLEN 0x00000FFF 328#define SIS_CMDSTS_PKT_OK 0x08000000 329#define SIS_CMDSTS_CRC 0x10000000 330#define SIS_CMDSTS_INTR 0x20000000 331#define SIS_CMDSTS_MORE 0x40000000 332#define SIS_CMDSTS_OWN 0x80000000 333 334#define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE)) 335#define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN) 336#define SIS_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 337#define SIS_RXBYTES(x) (((x)->sis_ctl & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN) 338 339#define SIS_RXSTAT_COLL 0x00010000 340#define SIS_RXSTAT_LOOPBK 0x00020000 341#define SIS_RXSTAT_ALIGNERR 0x00040000 342#define SIS_RXSTAT_CRCERR 0x00080000 343#define SIS_RXSTAT_SYMBOLERR 0x00100000 344#define SIS_RXSTAT_RUNT 0x00200000 345#define SIS_RXSTAT_GIANT 0x00400000 346#define SIS_RXSTAT_DSTCLASS 0x01800000 347#define SIS_RXSTAT_OVERRUN 0x02000000 348#define SIS_RXSTAT_RX_ABORT 0x04000000 349 350#define SIS_DSTCLASS_REJECT 0x00000000 351#define SIS_DSTCLASS_UNICAST 0x00800000 352#define SIS_DSTCLASS_MULTICAST 0x01000000 353#define SIS_DSTCLASS_BROADCAST 0x02000000 354 355#define SIS_TXSTAT_COLLCNT 0x000F0000 356#define SIS_TXSTAT_EXCESSCOLLS 0x00100000 357#define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 358#define SIS_TXSTAT_EXCESS_DEFER 0x00400000 359#define SIS_TXSTAT_DEFERED 0x00800000 360#define SIS_TXSTAT_CARR_LOST 0x01000000 361#define SIS_TXSTAT_UNDERRUN 0x02000000 362#define SIS_TXSTAT_TX_ABORT 0x04000000 363 364#define SIS_RX_LIST_CNT 64 365#define SIS_TX_LIST_CNT 128 366 367#define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc) 368#define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc) 369 370struct sis_list_data { 371#ifdef foo 372 struct sis_desc sis_rx_list[SIS_RX_LIST_CNT]; 373 struct sis_desc sis_tx_list[SIS_TX_LIST_CNT]; 374#endif 375 struct sis_desc *sis_rx_list; 376 struct sis_desc *sis_tx_list; 377 bus_dma_tag_t sis_rx_tag; 378 bus_dmamap_t sis_rx_dmamap; 379 bus_dma_tag_t sis_tx_tag; 380 bus_dmamap_t sis_tx_dmamap; 381}; 382 383struct sis_ring_data { 384 int sis_rx_prod; 385 int sis_tx_prod; 386 int sis_tx_cons; 387 int sis_tx_cnt; 388 u_int32_t sis_rx_paddr; 389 u_int32_t sis_tx_paddr; 390}; 391 392 393/* 394 * SiS PCI vendor ID. 395 */ 396#define SIS_VENDORID 0x1039 397 398/* 399 * SiS PCI device IDs 400 */ 401#define SIS_DEVICEID_900 0x0900 402#define SIS_DEVICEID_7016 0x7016 403 404/* 405 * SiS 900 PCI revision codes. 406 */ 407#define SIS_REV_900B 0x0003 408#define SIS_REV_630A 0x0080 409#define SIS_REV_630E 0x0081 410#define SIS_REV_630S 0x0082 411#define SIS_REV_630EA1 0x0083 412#define SIS_REV_630ET 0x0084 413#define SIS_REV_635 0x0090 414#define SIS_REV_96x 0x0091 415 416/* 417 * NatSemi vendor ID 418 */ 419#define NS_VENDORID 0x100B 420 421/* 422 * DP83815 device ID 423 */ 424#define NS_DEVICEID_DP83815 0x0020 425 426struct sis_type { 427 u_int16_t sis_vid; 428 u_int16_t sis_did; 429 char *sis_name; 430}; 431 432struct sis_mii_frame { 433 u_int8_t mii_stdelim; 434 u_int8_t mii_opcode; 435 u_int8_t mii_phyaddr; 436 u_int8_t mii_regaddr; 437 u_int8_t mii_turnaround; 438 u_int16_t mii_data; 439}; 440 441/* 442 * MII constants 443 */ 444#define SIS_MII_STARTDELIM 0x01 445#define SIS_MII_READOP 0x02 446#define SIS_MII_WRITEOP 0x01 447#define SIS_MII_TURNAROUND 0x02 448 449#define SIS_TYPE_900 1 450#define SIS_TYPE_7016 2 451#define SIS_TYPE_83815 3 452#define SIS_TYPE_83816 4 453 454struct sis_softc { 455 struct arpcom arpcom; /* interface info */ 456 bus_space_handle_t sis_bhandle; 457 bus_space_tag_t sis_btag; 458 struct resource *sis_res; 459 struct resource *sis_irq; 460 void *sis_intrhand; 461 device_t sis_self; 462 device_t sis_miibus; 463 u_int8_t sis_unit; 464 u_int8_t sis_type; 465 u_int8_t sis_rev; 466 u_int8_t sis_link; 467 u_int sis_srr; 468 struct sis_list_data sis_ldata; 469 bus_dma_tag_t sis_parent_tag; 470 bus_dma_tag_t sis_tag; 471 struct sis_ring_data sis_cdata; 472 struct callout sis_stat_ch; 473 int sis_stopped; 474#ifdef DEVICE_POLLING 475 int rxcycles; 476#endif 477 int in_tick; 478 struct mtx sis_mtx; 479}; 480 481#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 482#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 483#define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 484 485/* 486 * register space access macros 487 */ 488#define CSR_WRITE_4(sc, reg, val) \ 489 bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val) 490 491#define CSR_READ_4(sc, reg) \ 492 bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg) 493 494#define CSR_READ_2(sc, reg) \ 495 bus_space_read_2(sc->sis_btag, sc->sis_bhandle, reg) 496 497#define SIS_TIMEOUT 1000 498#define ETHER_ALIGN 2 499#define SIS_RXLEN 1536 500#define SIS_MIN_FRAMELEN 60 501 502/* 503 * PCI low memory base and low I/O base register, and 504 * other PCI registers. 505 */ 506 507#define SIS_PCI_VENDOR_ID 0x00 508#define SIS_PCI_DEVICE_ID 0x02 509#define SIS_PCI_COMMAND 0x04 510#define SIS_PCI_STATUS 0x06 511#define SIS_PCI_REVID 0x08 512#define SIS_PCI_CLASSCODE 0x09 513#define SIS_PCI_CACHELEN 0x0C 514#define SIS_PCI_LATENCY_TIMER 0x0D 515#define SIS_PCI_HEADER_TYPE 0x0E 516#define SIS_PCI_LOIO 0x10 517#define SIS_PCI_LOMEM 0x14 518#define SIS_PCI_BIOSROM 0x30 519#define SIS_PCI_INTLINE 0x3C 520#define SIS_PCI_INTPIN 0x3D 521#define SIS_PCI_MINGNT 0x3E 522#define SIS_PCI_MINLAT 0x0F 523#define SIS_PCI_RESETOPT 0x48 524#define SIS_PCI_EEPROM_DATA 0x4C 525 526/* power management registers */ 527#define SIS_PCI_CAPID 0x50 /* 8 bits */ 528#define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ 529#define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 530#define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 531 532#define SIS_PSTATE_MASK 0x0003 533#define SIS_PSTATE_D0 0x0000 534#define SIS_PSTATE_D1 0x0001 535#define SIS_PSTATE_D2 0x0002 536#define SIS_PSTATE_D3 0x0003 537#define SIS_PME_EN 0x0010 538#define SIS_PME_STATUS 0x8000 539