sio.c revision 59888
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/sio/sio.c 59888 2000-05-02 05:54:11Z tanimura $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42#include "card.h" 43#include "pci.h" 44#include "sio.h" 45 46/* 47 * Serial driver, based on 386BSD-0.1 com driver. 48 * Mostly rewritten to use pseudo-DMA. 49 * Works for National Semiconductor NS8250-NS16550AF UARTs. 50 * COM driver, based on HP dca driver. 51 * 52 * Changes for PC-Card integration: 53 * - Added PC-Card driver table and handlers 54 */ 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/reboot.h> 58#include <sys/malloc.h> 59#include <sys/tty.h> 60#include <sys/proc.h> 61#include <sys/module.h> 62#include <sys/conf.h> 63#include <sys/dkstat.h> 64#include <sys/fcntl.h> 65#include <sys/interrupt.h> 66#include <sys/kernel.h> 67#include <sys/syslog.h> 68#include <sys/sysctl.h> 69#include <sys/bus.h> 70#include <machine/bus.h> 71#include <sys/rman.h> 72#include <sys/timetc.h> 73#include <sys/timepps.h> 74 75#include <isa/isareg.h> 76#include <isa/isavar.h> 77#if NPCI > 0 78#include <pci/pcireg.h> 79#include <pci/pcivar.h> 80#endif 81#include <machine/lock.h> 82 83#include <machine/clock.h> 84#include <machine/ipl.h> 85#ifndef SMP 86#include <machine/lock.h> 87#endif 88#include <machine/resource.h> 89 90#include <isa/sioreg.h> 91 92#ifdef COM_ESP 93#include <isa/ic/esp.h> 94#endif 95#include <isa/ic/ns16550.h> 96 97#ifndef __i386__ 98#define disable_intr() 99#define enable_intr() 100#endif 101 102#ifdef SMP 103#define disable_intr() COM_DISABLE_INTR() 104#define enable_intr() COM_ENABLE_INTR() 105#endif /* SMP */ 106 107#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 108 109#define CALLOUT_MASK 0x80 110#define CONTROL_MASK 0x60 111#define CONTROL_INIT_STATE 0x20 112#define CONTROL_LOCK_STATE 0x40 113#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 114#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 115#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 116 117#ifdef COM_MULTIPORT 118/* checks in flags for multiport and which is multiport "master chip" 119 * for a given card 120 */ 121#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 122#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 123#define COM_NOTAST4(flags) ((flags) & 0x04) 124#endif /* COM_MULTIPORT */ 125 126#define COM_CONSOLE(flags) ((flags) & 0x10) 127#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 128#define COM_LLCONSOLE(flags) ((flags) & 0x40) 129#define COM_DEBUGGER(flags) ((flags) & 0x80) 130#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 131#define COM_NOFIFO(flags) ((flags) & 0x02) 132#define COM_ST16650A(flags) ((flags) & 0x20000) 133#define COM_C_NOPROBE (0x40000) 134#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 135#define COM_C_IIR_TXRDYBUG (0x80000) 136#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 137#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 138 139#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 140 141/* 142 * com state bits. 143 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 144 * than the other bits so that they can be tested as a group without masking 145 * off the low bits. 146 * 147 * The following com and tty flags correspond closely: 148 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 149 * comstop()) 150 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 151 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 152 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 153 * TS_FLUSH is not used. 154 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 155 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 156 */ 157#define CS_BUSY 0x80 /* output in progress */ 158#define CS_TTGO 0x40 /* output not stopped by XOFF */ 159#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 160#define CS_CHECKMSR 1 /* check of MSR scheduled */ 161#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 162#define CS_DTR_OFF 0x10 /* DTR held off */ 163#define CS_ODONE 4 /* output completed */ 164#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 165#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 166 167static char const * const error_desc[] = { 168#define CE_OVERRUN 0 169 "silo overflow", 170#define CE_INTERRUPT_BUF_OVERFLOW 1 171 "interrupt-level buffer overflow", 172#define CE_TTY_BUF_OVERFLOW 2 173 "tty-level buffer overflow", 174}; 175 176#define CE_NTYPES 3 177#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 178 179/* types. XXX - should be elsewhere */ 180typedef u_int Port_t; /* hardware port */ 181typedef u_char bool_t; /* boolean */ 182 183/* queue of linear buffers */ 184struct lbq { 185 u_char *l_head; /* next char to process */ 186 u_char *l_tail; /* one past the last char to process */ 187 struct lbq *l_next; /* next in queue */ 188 bool_t l_queued; /* nonzero if queued */ 189}; 190 191/* com device structure */ 192struct com_s { 193 u_int flags; /* Copy isa device flags */ 194 u_char state; /* miscellaneous flag bits */ 195 bool_t active_out; /* nonzero if the callout device is open */ 196 u_char cfcr_image; /* copy of value written to CFCR */ 197#ifdef COM_ESP 198 bool_t esp; /* is this unit a hayes esp board? */ 199#endif 200 u_char extra_state; /* more flag bits, separate for order trick */ 201 u_char fifo_image; /* copy of value written to FIFO */ 202 bool_t hasfifo; /* nonzero for 16550 UARTs */ 203 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 204 bool_t loses_outints; /* nonzero if device loses output interrupts */ 205 u_char mcr_image; /* copy of value written to MCR */ 206#ifdef COM_MULTIPORT 207 bool_t multiport; /* is this unit part of a multiport device? */ 208#endif /* COM_MULTIPORT */ 209 bool_t no_irq; /* nonzero if irq is not attached */ 210 bool_t gone; /* hardware disappeared */ 211 bool_t poll; /* nonzero if polling is required */ 212 bool_t poll_output; /* nonzero if polling for output is required */ 213 int unit; /* unit number */ 214 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 215 u_int tx_fifo_size; 216 u_int wopeners; /* # processes waiting for DCD in open() */ 217 218 /* 219 * The high level of the driver never reads status registers directly 220 * because there would be too many side effects to handle conveniently. 221 * Instead, it reads copies of the registers stored here by the 222 * interrupt handler. 223 */ 224 u_char last_modem_status; /* last MSR read by intr handler */ 225 u_char prev_modem_status; /* last MSR handled by high level */ 226 227 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 228 u_char *ibuf; /* start of input buffer */ 229 u_char *ibufend; /* end of input buffer */ 230 u_char *ibufold; /* old input buffer, to be freed */ 231 u_char *ihighwater; /* threshold in input buffer */ 232 u_char *iptr; /* next free spot in input buffer */ 233 int ibufsize; /* size of ibuf (not include error bytes) */ 234 int ierroff; /* offset of error bytes in ibuf */ 235 236 struct lbq obufq; /* head of queue of output buffers */ 237 struct lbq obufs[2]; /* output buffers */ 238 239 Port_t data_port; /* i/o ports */ 240#ifdef COM_ESP 241 Port_t esp_port; 242#endif 243 Port_t int_id_port; 244 Port_t iobase; 245 Port_t modem_ctl_port; 246 Port_t line_status_port; 247 Port_t modem_status_port; 248 Port_t intr_ctl_port; /* Ports of IIR register */ 249 250 struct tty *tp; /* cross reference */ 251 252 /* Initial state. */ 253 struct termios it_in; /* should be in struct tty */ 254 struct termios it_out; 255 256 /* Lock state. */ 257 struct termios lt_in; /* should be in struct tty */ 258 struct termios lt_out; 259 260 bool_t do_timestamp; 261 bool_t do_dcd_timestamp; 262 struct timeval timestamp; 263 struct timeval dcd_timestamp; 264 struct pps_state pps; 265 266 u_long bytes_in; /* statistics */ 267 u_long bytes_out; 268 u_int delta_error_counts[CE_NTYPES]; 269 u_long error_counts[CE_NTYPES]; 270 271 struct resource *irqres; 272 struct resource *ioportres; 273 void *cookie; 274 275 /* 276 * Data area for output buffers. Someday we should build the output 277 * buffer queue without copying data. 278 */ 279 u_char obuf1[256]; 280 u_char obuf2[256]; 281}; 282 283#ifdef COM_ESP 284static int espattach __P((struct com_s *com, Port_t esp_port)); 285#endif 286static int sioattach __P((device_t dev, int rid)); 287static int sio_isa_attach __P((device_t dev)); 288 289static timeout_t siobusycheck; 290static timeout_t siodtrwakeup; 291static void comhardclose __P((struct com_s *com)); 292static void sioinput __P((struct com_s *com)); 293static void siointr1 __P((struct com_s *com)); 294static void siointr __P((void *arg)); 295static int commctl __P((struct com_s *com, int bits, int how)); 296static int comparam __P((struct tty *tp, struct termios *t)); 297static swihand_t siopoll; 298static int sioprobe __P((device_t dev, int xrid)); 299static int sio_isa_probe __P((device_t dev)); 300static void siosettimeout __P((void)); 301static int siosetwater __P((struct com_s *com, speed_t speed)); 302static void comstart __P((struct tty *tp)); 303static void comstop __P((struct tty *tp, int rw)); 304static timeout_t comwakeup; 305static void disc_optim __P((struct tty *tp, struct termios *t, 306 struct com_s *com)); 307 308#if NCARD > 0 309static int sio_pccard_attach __P((device_t dev)); 310static int sio_pccard_detach __P((device_t dev)); 311static int sio_pccard_probe __P((device_t dev)); 312#endif /* NCARD > 0 */ 313 314#if NPCI > 0 315static int sio_pci_attach __P((device_t dev)); 316static void sio_pci_kludge_unit __P((device_t dev)); 317static int sio_pci_probe __P((device_t dev)); 318#endif /* NPCI > 0 */ 319 320static char driver_name[] = "sio"; 321 322/* table and macro for fast conversion from a unit number to its com struct */ 323static devclass_t sio_devclass; 324#define com_addr(unit) ((struct com_s *) \ 325 devclass_get_softc(sio_devclass, unit)) 326 327static device_method_t sio_isa_methods[] = { 328 /* Device interface */ 329 DEVMETHOD(device_probe, sio_isa_probe), 330 DEVMETHOD(device_attach, sio_isa_attach), 331 332 { 0, 0 } 333}; 334 335static driver_t sio_isa_driver = { 336 driver_name, 337 sio_isa_methods, 338 sizeof(struct com_s), 339}; 340 341#if NCARD > 0 342static device_method_t sio_pccard_methods[] = { 343 /* Device interface */ 344 DEVMETHOD(device_probe, sio_pccard_probe), 345 DEVMETHOD(device_attach, sio_pccard_attach), 346 DEVMETHOD(device_detach, sio_pccard_detach), 347 348 { 0, 0 } 349}; 350 351static driver_t sio_pccard_driver = { 352 driver_name, 353 sio_pccard_methods, 354 sizeof(struct com_s), 355}; 356#endif /* NCARD > 0 */ 357 358#if NPCI > 0 359static device_method_t sio_pci_methods[] = { 360 /* Device interface */ 361 DEVMETHOD(device_probe, sio_pci_probe), 362 DEVMETHOD(device_attach, sio_pci_attach), 363 364 { 0, 0 } 365}; 366 367static driver_t sio_pci_driver = { 368 driver_name, 369 sio_pci_methods, 370 sizeof(struct com_s), 371}; 372#endif /* NPCI > 0 */ 373 374static d_open_t sioopen; 375static d_close_t sioclose; 376static d_read_t sioread; 377static d_write_t siowrite; 378static d_ioctl_t sioioctl; 379 380#define CDEV_MAJOR 28 381static struct cdevsw sio_cdevsw = { 382 /* open */ sioopen, 383 /* close */ sioclose, 384 /* read */ sioread, 385 /* write */ siowrite, 386 /* ioctl */ sioioctl, 387 /* poll */ ttypoll, 388 /* mmap */ nommap, 389 /* strategy */ nostrategy, 390 /* name */ driver_name, 391 /* maj */ CDEV_MAJOR, 392 /* dump */ nodump, 393 /* psize */ nopsize, 394 /* flags */ D_TTY, 395 /* bmaj */ -1 396}; 397 398int comconsole = -1; 399static volatile speed_t comdefaultrate = CONSPEED; 400#ifdef __alpha__ 401static volatile speed_t gdbdefaultrate = CONSPEED; 402#endif 403static u_int com_events; /* input chars + weighted output completions */ 404static Port_t siocniobase; 405static int siocnunit; 406static Port_t siogdbiobase; 407static int siogdbunit = -1; 408static bool_t sio_registered; 409static int sio_timeout; 410static int sio_timeouts_until_log; 411static struct callout_handle sio_timeout_handle 412 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 413static int sio_numunits; 414 415static struct speedtab comspeedtab[] = { 416 { 0, 0 }, 417 { 50, COMBRD(50) }, 418 { 75, COMBRD(75) }, 419 { 110, COMBRD(110) }, 420 { 134, COMBRD(134) }, 421 { 150, COMBRD(150) }, 422 { 200, COMBRD(200) }, 423 { 300, COMBRD(300) }, 424 { 600, COMBRD(600) }, 425 { 1200, COMBRD(1200) }, 426 { 1800, COMBRD(1800) }, 427 { 2400, COMBRD(2400) }, 428 { 4800, COMBRD(4800) }, 429 { 9600, COMBRD(9600) }, 430 { 19200, COMBRD(19200) }, 431 { 38400, COMBRD(38400) }, 432 { 57600, COMBRD(57600) }, 433 { 115200, COMBRD(115200) }, 434 { -1, -1 } 435}; 436 437#ifdef COM_ESP 438/* XXX configure this properly. */ 439static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 440static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 441#endif 442 443/* 444 * handle sysctl read/write requests for console speed 445 * 446 * In addition to setting comdefaultrate for I/O through /dev/console, 447 * also set the initial and lock values for the /dev/ttyXX device 448 * if there is one associated with the console. Finally, if the /dev/tty 449 * device has already been open, change the speed on the open running port 450 * itself. 451 */ 452 453static int 454sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS 455{ 456 int error, s; 457 speed_t newspeed; 458 struct com_s *com; 459 struct tty *tp; 460 461 newspeed = comdefaultrate; 462 463 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 464 if (error || !req->newptr) 465 return (error); 466 467 comdefaultrate = newspeed; 468 469 if (comconsole < 0) /* serial console not selected? */ 470 return (0); 471 472 com = com_addr(comconsole); 473 if (com == NULL) 474 return (ENXIO); 475 476 /* 477 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 478 * (note, the lock rates really are boolean -- if non-zero, disallow 479 * speed changes) 480 */ 481 com->it_in.c_ispeed = com->it_in.c_ospeed = 482 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 483 com->it_out.c_ispeed = com->it_out.c_ospeed = 484 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 485 486 /* 487 * if we're open, change the running rate too 488 */ 489 tp = com->tp; 490 if (tp && (tp->t_state & TS_ISOPEN)) { 491 tp->t_termios.c_ispeed = 492 tp->t_termios.c_ospeed = comdefaultrate; 493 s = spltty(); 494 error = comparam(tp, &tp->t_termios); 495 splx(s); 496 } 497 return error; 498} 499 500SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 501 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 502 503#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 504#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 505 506#if NCARD > 0 507static int 508sio_pccard_probe(dev) 509 device_t dev; 510{ 511 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */ 512 /* until bus_setup_intr */ 513 SET_FLAG(dev, COM_C_NOPROBE); 514 515 return (sioprobe(dev, 0)); 516} 517 518static int 519sio_pccard_attach(dev) 520 device_t dev; 521{ 522 return (sioattach(dev, 0)); 523} 524 525/* 526 * sio_detach - unload the driver and clear the table. 527 * XXX TODO: 528 * This is usually called when the card is ejected, but 529 * can be caused by a modunload of a controller driver. 530 * The idea is to reset the driver's view of the device 531 * and ensure that any driver entry points such as 532 * read and write do not hang. 533 */ 534static int 535sio_pccard_detach(dev) 536 device_t dev; 537{ 538 struct com_s *com; 539 540 com = (struct com_s *) device_get_softc(dev); 541 if (com == NULL) { 542 device_printf(dev, "NULL com in siounload\n"); 543 return (0); 544 } 545 if (com->iobase == 0) { 546 device_printf(dev, "already unloaded!\n"); 547 return (0); 548 } 549 com->gone = 1; 550 if (com->irqres) { 551 bus_teardown_intr(dev, com->irqres, com->cookie); 552 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 553 } 554 if (com->ioportres) 555 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 556 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 557 device_printf(dev, "still open, forcing close\n"); 558 com->tp->t_gen++; 559 ttyclose(com->tp); 560 ttwakeup(com->tp); 561 ttwwakeup(com->tp); 562 } else { 563 if (com->ibuf != NULL) 564 free(com->ibuf, M_DEVBUF); 565 } 566 device_printf(dev, "unloaded\n"); 567 return (0); 568} 569#endif /* NCARD > 0 */ 570 571#if NPCI > 0 572struct pci_ids { 573 u_int32_t type; 574 const char *desc; 575 int rid; 576}; 577 578static struct pci_ids pci_ids[] = { 579 { 0x100812b9, "3COM PCI FaxModem", 0x10 }, 580 { 0x048011c1, "ActionTec 56k FAX PCI Modem", 0x14 }, 581 { 0x00000000, NULL, 0 } 582}; 583 584static int 585sio_pci_attach(dev) 586 device_t dev; 587{ 588 u_int32_t type; 589 struct pci_ids *id; 590 591 type = pci_get_devid(dev); 592 id = pci_ids; 593 while (id->type && id->type != type) 594 id++; 595 if (id->desc == NULL) 596 return (ENXIO); 597 sio_pci_kludge_unit(dev); 598 return (sioattach(dev, id->rid)); 599} 600 601/* 602 * Don't cut and paste this to other drivers. It is a horrible kludge 603 * which will fail to work and also be unnecessary in future versions. 604 */ 605static void 606sio_pci_kludge_unit(dev) 607 device_t dev; 608{ 609 devclass_t dc; 610 int err; 611 int start; 612 int unit; 613 614 unit = 0; 615 start = 0; 616 while (resource_int_value("sio", unit, "port", &start) == 0 && 617 start > 0) 618 unit++; 619 if (device_get_unit(dev) < unit) { 620 dc = device_get_devclass(dev); 621 while (devclass_get_device(dc, unit)) 622 unit++; 623 device_printf(dev, "moving to sio%d\n", unit); 624 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */ 625 if (err) 626 device_printf(dev, "error moving device %d\n", err); 627 } 628} 629 630static int 631sio_pci_probe(dev) 632 device_t dev; 633{ 634 u_int32_t type; 635 struct pci_ids *id; 636 637 type = pci_get_devid(dev); 638 id = pci_ids; 639 while (id->type && id->type != type) 640 id++; 641 if (id->desc == NULL) 642 return (ENXIO); 643 device_set_desc(dev, id->desc); 644 return (sioprobe(dev, id->rid)); 645} 646#endif /* NPCI > 0 */ 647 648static struct isa_pnp_id sio_ids[] = { 649 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */ 650 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */ 651 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */ 652 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */ 653 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */ 654 /* Devices that do not have a compatid */ 655 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */ 656 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */ 657 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */ 658 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */ 659 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */ 660 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */ 661 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */ 662 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */ 663 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */ 664 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */ 665 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */ 666 {0x0000aa1a, NULL}, /* FUJ0000 - FUJITSU Modem 33600 PNP/I2 */ 667 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */ 668 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */ 669 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */ 670 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */ 671 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */ 672 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */ 673 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */ 674 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */ 675 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */ 676 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */ 677 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */ 678 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */ 679 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */ 680 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */ 681 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */ 682 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */ 683 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */ 684 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */ 685 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */ 686 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */ 687 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */ 688 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */ 689 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */ 690 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */ 691 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */ 692 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */ 693 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */ 694 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */ 695 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */ 696 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */ 697 {0x11007256, NULL}, /* USR0011 - USR ? */ 698 {0x01017256, NULL}, /* USR0101 - USR ? */ 699 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */ 700 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */ 701 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */ 702 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */ 703 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */ 704 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */ 705 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */ 706 {0x90307256, NULL}, /* USR3090 - USR ? */ 707 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */ 708 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */ 709 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */ 710 {0} 711}; 712 713 714 715static int 716sio_isa_probe(dev) 717 device_t dev; 718{ 719 /* Check isapnp ids */ 720 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO) 721 return (ENXIO); 722 return (sioprobe(dev, 0)); 723} 724 725static int 726sioprobe(dev, xrid) 727 device_t dev; 728 int xrid; 729{ 730#if 0 731 static bool_t already_init; 732 device_t xdev; 733#endif 734 bool_t failures[10]; 735 int fn; 736 device_t idev; 737 Port_t iobase; 738 intrmask_t irqmap[4]; 739 intrmask_t irqs; 740 u_char mcr_image; 741 int result; 742 u_long xirq; 743 u_int flags = device_get_flags(dev); 744 int rid; 745 struct resource *port; 746 747 rid = xrid; 748 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 749 0, ~0, IO_COMSIZE, RF_ACTIVE); 750 if (!port) 751 return (ENXIO); 752 753#if 0 754 /* 755 * XXX this is broken - when we are first called, there are no 756 * previously configured IO ports. We could hard code 757 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 758 * This code has been doing nothing since the conversion since 759 * "count" is zero the first time around. 760 */ 761 if (!already_init) { 762 /* 763 * Turn off MCR_IENABLE for all likely serial ports. An unused 764 * port with its MCR_IENABLE gate open will inhibit interrupts 765 * from any used port that shares the interrupt vector. 766 * XXX the gate enable is elsewhere for some multiports. 767 */ 768 device_t *devs; 769 int count, i, xioport; 770 771 devclass_get_devices(sio_devclass, &devs, &count); 772 for (i = 0; i < count; i++) { 773 xdev = devs[i]; 774 if (device_is_enabled(xdev) && 775 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 776 NULL) == 0) 777 outb(xioport + com_mcr, 0); 778 } 779 free(devs, M_TEMP); 780 already_init = TRUE; 781 } 782#endif 783 784 if (COM_LLCONSOLE(flags)) { 785 printf("sio%d: reserved for low-level i/o\n", 786 device_get_unit(dev)); 787 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 788 return (ENXIO); 789 } 790 791 /* 792 * If the device is on a multiport card and has an AST/4 793 * compatible interrupt control register, initialize this 794 * register and prepare to leave MCR_IENABLE clear in the mcr. 795 * Otherwise, prepare to set MCR_IENABLE in the mcr. 796 * Point idev to the device struct giving the correct id_irq. 797 * This is the struct for the master device if there is one. 798 */ 799 idev = dev; 800 mcr_image = MCR_IENABLE; 801#ifdef COM_MULTIPORT 802 if (COM_ISMULTIPORT(flags)) { 803 Port_t xiobase; 804 u_long io; 805 806 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 807 if (idev == NULL) { 808 printf("sio%d: master device %d not configured\n", 809 device_get_unit(dev), COM_MPMASTER(flags)); 810 idev = dev; 811 } 812 if (!COM_NOTAST4(flags)) { 813 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 814 NULL) == 0) { 815 xiobase = io; 816 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 817 NULL, NULL) == 0) 818 outb(xiobase + com_scr, 0x80); 819 else 820 outb(xiobase + com_scr, 0); 821 } 822 mcr_image = 0; 823 } 824 } 825#endif /* COM_MULTIPORT */ 826 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 827 mcr_image = 0; 828 829 bzero(failures, sizeof failures); 830 iobase = rman_get_start(port); 831 832 /* 833 * We don't want to get actual interrupts, just masked ones. 834 * Interrupts from this line should already be masked in the ICU, 835 * but mask them in the processor as well in case there are some 836 * (misconfigured) shared interrupts. 837 */ 838 disable_intr(); 839/* EXTRA DELAY? */ 840 841 /* 842 * Initialize the speed and the word size and wait long enough to 843 * drain the maximum of 16 bytes of junk in device output queues. 844 * The speed is undefined after a master reset and must be set 845 * before relying on anything related to output. There may be 846 * junk after a (very fast) soft reboot and (apparently) after 847 * master reset. 848 * XXX what about the UART bug avoided by waiting in comparam()? 849 * We don't want to to wait long enough to drain at 2 bps. 850 */ 851 if (iobase == siocniobase) 852 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 853 else { 854 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 855 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 856 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 857 outb(iobase + com_cfcr, CFCR_8BITS); 858 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 859 } 860 861 /* 862 * Enable the interrupt gate and disable device interupts. This 863 * should leave the device driving the interrupt line low and 864 * guarantee an edge trigger if an interrupt can be generated. 865 */ 866/* EXTRA DELAY? */ 867 outb(iobase + com_mcr, mcr_image); 868 outb(iobase + com_ier, 0); 869 DELAY(1000); /* XXX */ 870 irqmap[0] = isa_irq_pending(); 871 872 /* 873 * Attempt to set loopback mode so that we can send a null byte 874 * without annoying any external device. 875 */ 876/* EXTRA DELAY? */ 877 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK); 878 879 /* 880 * Attempt to generate an output interrupt. On 8250's, setting 881 * IER_ETXRDY generates an interrupt independent of the current 882 * setting and independent of whether the THR is empty. On 16450's, 883 * setting IER_ETXRDY generates an interrupt independent of the 884 * current setting. On 16550A's, setting IER_ETXRDY only 885 * generates an interrupt when IER_ETXRDY is not already set. 886 */ 887 outb(iobase + com_ier, IER_ETXRDY); 888 889 /* 890 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 891 * an interrupt. They'd better generate one for actually doing 892 * output. Loopback may be broken on the same incompatibles but 893 * it's unlikely to do more than allow the null byte out. 894 */ 895 outb(iobase + com_data, 0); 896 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 897 898 /* 899 * Turn off loopback mode so that the interrupt gate works again 900 * (MCR_IENABLE was hidden). This should leave the device driving 901 * an interrupt line high. It doesn't matter if the interrupt 902 * line oscillates while we are not looking at it, since interrupts 903 * are disabled. 904 */ 905/* EXTRA DELAY? */ 906 outb(iobase + com_mcr, mcr_image); 907 908 /* 909 * Some pcmcia cards have the "TXRDY bug", so we check everyone 910 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 911 */ 912 if (COM_NOPROBE(flags)) { 913 /* Reading IIR register twice */ 914 for (fn = 0; fn < 2; fn ++) { 915 DELAY(10000); 916 failures[6] = inb(iobase + com_iir); 917 } 918 /* Check IIR_TXRDY clear ? */ 919 result = 0; 920 if (failures[6] & IIR_TXRDY) { 921 /* Nop, Double check with clearing IER */ 922 outb(iobase + com_ier, 0); 923 if (inb(iobase + com_iir) & IIR_NOPEND) { 924 /* Ok. we're familia this gang */ 925 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 926 } else { 927 /* Unknown, Just omit this chip.. XXX */ 928 result = ENXIO; 929 } 930 } else { 931 /* OK. this is well-known guys */ 932 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 933 } 934 outb(iobase + com_cfcr, CFCR_8BITS); 935 enable_intr(); 936 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 937 return (iobase == siocniobase ? 0 : result); 938 } 939 940 /* 941 * Check that 942 * o the CFCR, IER and MCR in UART hold the values written to them 943 * (the values happen to be all distinct - this is good for 944 * avoiding false positive tests from bus echoes). 945 * o an output interrupt is generated and its vector is correct. 946 * o the interrupt goes away when the IIR in the UART is read. 947 */ 948/* EXTRA DELAY? */ 949 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS; 950 failures[1] = inb(iobase + com_ier) - IER_ETXRDY; 951 failures[2] = inb(iobase + com_mcr) - mcr_image; 952 DELAY(10000); /* Some internal modems need this time */ 953 irqmap[1] = isa_irq_pending(); 954 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY; 955 DELAY(1000); /* XXX */ 956 irqmap[2] = isa_irq_pending(); 957 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 958 959 /* 960 * Turn off all device interrupts and check that they go off properly. 961 * Leave MCR_IENABLE alone. For ports without a master port, it gates 962 * the OUT2 output of the UART to 963 * the ICU input. Closing the gate would give a floating ICU input 964 * (unless there is another device driving it) and spurious interrupts. 965 * (On the system that this was first tested on, the input floats high 966 * and gives a (masked) interrupt as soon as the gate is closed.) 967 */ 968 outb(iobase + com_ier, 0); 969 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 970 failures[7] = inb(iobase + com_ier); 971 DELAY(1000); /* XXX */ 972 irqmap[3] = isa_irq_pending(); 973 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 974 975 enable_intr(); 976 977 irqs = irqmap[1] & ~irqmap[0]; 978 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 979 ((1 << xirq) & irqs) == 0) 980 printf( 981 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 982 device_get_unit(dev), xirq, irqs); 983 if (bootverbose) 984 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 985 device_get_unit(dev), 986 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 987 988 result = 0; 989 for (fn = 0; fn < sizeof failures; ++fn) 990 if (failures[fn]) { 991 outb(iobase + com_mcr, 0); 992 result = ENXIO; 993 if (bootverbose) { 994 printf("sio%d: probe failed test(s):", 995 device_get_unit(dev)); 996 for (fn = 0; fn < sizeof failures; ++fn) 997 if (failures[fn]) 998 printf(" %d", fn); 999 printf("\n"); 1000 } 1001 break; 1002 } 1003 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1004 return (iobase == siocniobase ? 0 : result); 1005} 1006 1007#ifdef COM_ESP 1008static int 1009espattach(com, esp_port) 1010 struct com_s *com; 1011 Port_t esp_port; 1012{ 1013 u_char dips; 1014 u_char val; 1015 1016 /* 1017 * Check the ESP-specific I/O port to see if we're an ESP 1018 * card. If not, return failure immediately. 1019 */ 1020 if ((inb(esp_port) & 0xf3) == 0) { 1021 printf(" port 0x%x is not an ESP board?\n", esp_port); 1022 return (0); 1023 } 1024 1025 /* 1026 * We've got something that claims to be a Hayes ESP card. 1027 * Let's hope so. 1028 */ 1029 1030 /* Get the dip-switch configuration */ 1031 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1032 dips = inb(esp_port + ESP_STATUS1); 1033 1034 /* 1035 * Bits 0,1 of dips say which COM port we are. 1036 */ 1037 if (com->iobase == likely_com_ports[dips & 0x03]) 1038 printf(" : ESP"); 1039 else { 1040 printf(" esp_port has com %d\n", dips & 0x03); 1041 return (0); 1042 } 1043 1044 /* 1045 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1046 */ 1047 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1048 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1049 val = inb(esp_port + ESP_STATUS2); 1050 if ((val & 0x70) < 0x20) { 1051 printf("-old (%o)", val & 0x70); 1052 return (0); 1053 } 1054 1055 /* 1056 * Check for ability to emulate 16550: bit 7 == 1 1057 */ 1058 if ((dips & 0x80) == 0) { 1059 printf(" slave"); 1060 return (0); 1061 } 1062 1063 /* 1064 * Okay, we seem to be a Hayes ESP card. Whee. 1065 */ 1066 com->esp = TRUE; 1067 com->esp_port = esp_port; 1068 return (1); 1069} 1070#endif /* COM_ESP */ 1071 1072static int 1073sio_isa_attach(dev) 1074 device_t dev; 1075{ 1076 return (sioattach(dev, 0)); 1077} 1078 1079static int 1080sioattach(dev, xrid) 1081 device_t dev; 1082 int xrid; 1083{ 1084 struct com_s *com; 1085#ifdef COM_ESP 1086 Port_t *espp; 1087#endif 1088 Port_t iobase; 1089 int unit; 1090 u_int flags; 1091 int rid; 1092 struct resource *port; 1093 int ret; 1094 1095 rid = xrid; 1096 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1097 0, ~0, IO_COMSIZE, RF_ACTIVE); 1098 if (!port) 1099 return (ENXIO); 1100 1101 iobase = rman_get_start(port); 1102 unit = device_get_unit(dev); 1103 com = device_get_softc(dev); 1104 flags = device_get_flags(dev); 1105 1106 if (unit >= sio_numunits) 1107 sio_numunits = unit + 1; 1108 /* 1109 * sioprobe() has initialized the device registers as follows: 1110 * o cfcr = CFCR_8BITS. 1111 * It is most important that CFCR_DLAB is off, so that the 1112 * data port is not hidden when we enable interrupts. 1113 * o ier = 0. 1114 * Interrupts are only enabled when the line is open. 1115 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1116 * interrupt control register or the config specifies no irq. 1117 * Keeping MCR_DTR and MCR_RTS off might stop the external 1118 * device from sending before we are ready. 1119 */ 1120 bzero(com, sizeof *com); 1121 com->unit = unit; 1122 com->ioportres = port; 1123 com->cfcr_image = CFCR_8BITS; 1124 com->dtr_wait = 3 * hz; 1125 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1126 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1127 com->tx_fifo_size = 1; 1128 com->obufs[0].l_head = com->obuf1; 1129 com->obufs[1].l_head = com->obuf2; 1130 1131 com->iobase = iobase; 1132 com->data_port = iobase + com_data; 1133 com->int_id_port = iobase + com_iir; 1134 com->modem_ctl_port = iobase + com_mcr; 1135 com->mcr_image = inb(com->modem_ctl_port); 1136 com->line_status_port = iobase + com_lsr; 1137 com->modem_status_port = iobase + com_msr; 1138 com->intr_ctl_port = iobase + com_ier; 1139 1140 /* 1141 * We don't use all the flags from <sys/ttydefaults.h> since they 1142 * are only relevant for logins. It's important to have echo off 1143 * initially so that the line doesn't start blathering before the 1144 * echo flag can be turned off. 1145 */ 1146 com->it_in.c_iflag = 0; 1147 com->it_in.c_oflag = 0; 1148 com->it_in.c_cflag = TTYDEF_CFLAG; 1149 com->it_in.c_lflag = 0; 1150 if (unit == comconsole) { 1151 com->it_in.c_iflag = TTYDEF_IFLAG; 1152 com->it_in.c_oflag = TTYDEF_OFLAG; 1153 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1154 com->it_in.c_lflag = TTYDEF_LFLAG; 1155 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1156 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1157 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1158 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1159 } else 1160 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1161 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1162 enable_intr(); 1163 /* 1164 * Leave i/o resources allocated if this is a `cn'-level 1165 * console, so that other devices can't snarf them. 1166 */ 1167 if (iobase != siocniobase) 1168 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1169 return (ENOMEM); 1170 } 1171 enable_intr(); 1172 termioschars(&com->it_in); 1173 com->it_out = com->it_in; 1174 1175 /* attempt to determine UART type */ 1176 printf("sio%d: type", unit); 1177 1178 1179#ifdef COM_MULTIPORT 1180 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1181#else 1182 if (!COM_IIR_TXRDYBUG(flags)) 1183#endif 1184 { 1185 u_char scr; 1186 u_char scr1; 1187 u_char scr2; 1188 1189 scr = inb(iobase + com_scr); 1190 outb(iobase + com_scr, 0xa5); 1191 scr1 = inb(iobase + com_scr); 1192 outb(iobase + com_scr, 0x5a); 1193 scr2 = inb(iobase + com_scr); 1194 outb(iobase + com_scr, scr); 1195 if (scr1 != 0xa5 || scr2 != 0x5a) { 1196 printf(" 8250"); 1197 goto determined_type; 1198 } 1199 } 1200 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1201 DELAY(100); 1202 com->st16650a = 0; 1203 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1204 case FIFO_RX_LOW: 1205 printf(" 16450"); 1206 break; 1207 case FIFO_RX_MEDL: 1208 printf(" 16450?"); 1209 break; 1210 case FIFO_RX_MEDH: 1211 printf(" 16550?"); 1212 break; 1213 case FIFO_RX_HIGH: 1214 if (COM_NOFIFO(flags)) { 1215 printf(" 16550A fifo disabled"); 1216 } else { 1217 com->hasfifo = TRUE; 1218 if (COM_ST16650A(flags)) { 1219 com->st16650a = 1; 1220 com->tx_fifo_size = 32; 1221 printf(" ST16650A"); 1222 } else { 1223 com->tx_fifo_size = COM_FIFOSIZE(flags); 1224 printf(" 16550A"); 1225 } 1226 } 1227#ifdef COM_ESP 1228 for (espp = likely_esp_ports; *espp != 0; espp++) 1229 if (espattach(com, *espp)) { 1230 com->tx_fifo_size = 1024; 1231 break; 1232 } 1233#endif 1234 if (!com->st16650a) { 1235 if (!com->tx_fifo_size) 1236 com->tx_fifo_size = 16; 1237 else 1238 printf(" lookalike with %d bytes FIFO", 1239 com->tx_fifo_size); 1240 } 1241 1242 break; 1243 } 1244 1245#ifdef COM_ESP 1246 if (com->esp) { 1247 /* 1248 * Set 16550 compatibility mode. 1249 * We don't use the ESP_MODE_SCALE bit to increase the 1250 * fifo trigger levels because we can't handle large 1251 * bursts of input. 1252 * XXX flow control should be set in comparam(), not here. 1253 */ 1254 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1255 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1256 1257 /* Set RTS/CTS flow control. */ 1258 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1259 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1260 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1261 1262 /* Set flow-control levels. */ 1263 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1264 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1265 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1266 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1267 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1268 } 1269#endif /* COM_ESP */ 1270 outb(iobase + com_fifo, 0); 1271determined_type: ; 1272 1273#ifdef COM_MULTIPORT 1274 if (COM_ISMULTIPORT(flags)) { 1275 device_t masterdev; 1276 1277 com->multiport = TRUE; 1278 printf(" (multiport"); 1279 if (unit == COM_MPMASTER(flags)) 1280 printf(" master"); 1281 printf(")"); 1282 masterdev = devclass_get_device(sio_devclass, 1283 COM_MPMASTER(flags)); 1284 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1285 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1286 } 1287#endif /* COM_MULTIPORT */ 1288 if (unit == comconsole) 1289 printf(", console"); 1290 if (COM_IIR_TXRDYBUG(flags)) 1291 printf(" with a bogus IIR_TXRDY register"); 1292 printf("\n"); 1293 1294 if (!sio_registered) { 1295 register_swi(SWI_TTY, siopoll); 1296 sio_registered = TRUE; 1297 } 1298 make_dev(&sio_cdevsw, unit, 1299 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1300 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 1301 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1302 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 1303 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1304 make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 1305 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1306 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE, 1307 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1308 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 1309 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1310 com->flags = flags; 1311 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1312 pps_init(&com->pps); 1313 1314 rid = 0; 1315 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1316 RF_ACTIVE); 1317 if (com->irqres) { 1318 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1319 INTR_TYPE_TTY | INTR_TYPE_FAST, 1320 siointr, com, &com->cookie); 1321 if (ret) { 1322 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1323 com->irqres, INTR_TYPE_TTY, 1324 siointr, com, &com->cookie); 1325 if (ret == 0) 1326 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode"); 1327 } 1328 if (ret) 1329 device_printf(dev, "could not activate interrupt\n"); 1330 } 1331 1332 return (0); 1333} 1334 1335static int 1336sioopen(dev, flag, mode, p) 1337 dev_t dev; 1338 int flag; 1339 int mode; 1340 struct proc *p; 1341{ 1342 struct com_s *com; 1343 int error; 1344 Port_t iobase; 1345 int mynor; 1346 int s; 1347 struct tty *tp; 1348 int unit; 1349 1350 mynor = minor(dev); 1351 unit = MINOR_TO_UNIT(mynor); 1352 com = com_addr(unit); 1353 if (com == NULL) 1354 return (ENXIO); 1355 if (com->gone) 1356 return (ENXIO); 1357 if (mynor & CONTROL_MASK) 1358 return (0); 1359 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1360 s = spltty(); 1361 /* 1362 * We jump to this label after all non-interrupted sleeps to pick 1363 * up any changes of the device state. 1364 */ 1365open_top: 1366 while (com->state & CS_DTR_OFF) { 1367 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1368 if (com_addr(unit) == NULL) 1369 return (ENXIO); 1370 if (error != 0 || com->gone) 1371 goto out; 1372 } 1373 if (tp->t_state & TS_ISOPEN) { 1374 /* 1375 * The device is open, so everything has been initialized. 1376 * Handle conflicts. 1377 */ 1378 if (mynor & CALLOUT_MASK) { 1379 if (!com->active_out) { 1380 error = EBUSY; 1381 goto out; 1382 } 1383 } else { 1384 if (com->active_out) { 1385 if (flag & O_NONBLOCK) { 1386 error = EBUSY; 1387 goto out; 1388 } 1389 error = tsleep(&com->active_out, 1390 TTIPRI | PCATCH, "siobi", 0); 1391 if (com_addr(unit) == NULL) 1392 return (ENXIO); 1393 if (error != 0 || com->gone) 1394 goto out; 1395 goto open_top; 1396 } 1397 } 1398 if (tp->t_state & TS_XCLUDE && 1399 suser(p)) { 1400 error = EBUSY; 1401 goto out; 1402 } 1403 } else { 1404 /* 1405 * The device isn't open, so there are no conflicts. 1406 * Initialize it. Initialization is done twice in many 1407 * cases: to preempt sleeping callin opens if we are 1408 * callout, and to complete a callin open after DCD rises. 1409 */ 1410 tp->t_oproc = comstart; 1411 tp->t_param = comparam; 1412 tp->t_stop = comstop; 1413 tp->t_dev = dev; 1414 tp->t_termios = mynor & CALLOUT_MASK 1415 ? com->it_out : com->it_in; 1416 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1417 com->poll = com->no_irq; 1418 com->poll_output = com->loses_outints; 1419 ++com->wopeners; 1420 error = comparam(tp, &tp->t_termios); 1421 --com->wopeners; 1422 if (error != 0) 1423 goto out; 1424 /* 1425 * XXX we should goto open_top if comparam() slept. 1426 */ 1427 iobase = com->iobase; 1428 if (com->hasfifo) { 1429 /* 1430 * (Re)enable and drain fifos. 1431 * 1432 * Certain SMC chips cause problems if the fifos 1433 * are enabled while input is ready. Turn off the 1434 * fifo if necessary to clear the input. We test 1435 * the input ready bit after enabling the fifos 1436 * since we've already enabled them in comparam() 1437 * and to handle races between enabling and fresh 1438 * input. 1439 */ 1440 while (TRUE) { 1441 outb(iobase + com_fifo, 1442 FIFO_RCV_RST | FIFO_XMT_RST 1443 | com->fifo_image); 1444 /* 1445 * XXX the delays are for superstitious 1446 * historical reasons. It must be less than 1447 * the character time at the maximum 1448 * supported speed (87 usec at 115200 bps 1449 * 8N1). Otherwise we might loop endlessly 1450 * if data is streaming in. We used to use 1451 * delays of 100. That usually worked 1452 * because DELAY(100) used to usually delay 1453 * for about 85 usec instead of 100. 1454 */ 1455 DELAY(50); 1456 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1457 break; 1458 outb(iobase + com_fifo, 0); 1459 DELAY(50); 1460 (void) inb(com->data_port); 1461 } 1462 } 1463 1464 disable_intr(); 1465 (void) inb(com->line_status_port); 1466 (void) inb(com->data_port); 1467 com->prev_modem_status = com->last_modem_status 1468 = inb(com->modem_status_port); 1469 if (COM_IIR_TXRDYBUG(com->flags)) { 1470 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 1471 | IER_EMSC); 1472 } else { 1473 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 1474 | IER_ERLS | IER_EMSC); 1475 } 1476 enable_intr(); 1477 /* 1478 * Handle initial DCD. Callout devices get a fake initial 1479 * DCD (trapdoor DCD). If we are callout, then any sleeping 1480 * callin opens get woken up and resume sleeping on "siobi" 1481 * instead of "siodcd". 1482 */ 1483 /* 1484 * XXX `mynor & CALLOUT_MASK' should be 1485 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 1486 * TRAPDOOR_CARRIER is the default initial state for callout 1487 * devices and SOFT_CARRIER is like CLOCAL except it hides 1488 * the true carrier. 1489 */ 1490 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 1491 (*linesw[tp->t_line].l_modem)(tp, 1); 1492 } 1493 /* 1494 * Wait for DCD if necessary. 1495 */ 1496 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 1497 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 1498 ++com->wopeners; 1499 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 1500 if (com_addr(unit) == NULL) 1501 return (ENXIO); 1502 --com->wopeners; 1503 if (error != 0 || com->gone) 1504 goto out; 1505 goto open_top; 1506 } 1507 error = (*linesw[tp->t_line].l_open)(dev, tp); 1508 disc_optim(tp, &tp->t_termios, com); 1509 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 1510 com->active_out = TRUE; 1511 siosettimeout(); 1512out: 1513 splx(s); 1514 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 1515 comhardclose(com); 1516 return (error); 1517} 1518 1519static int 1520sioclose(dev, flag, mode, p) 1521 dev_t dev; 1522 int flag; 1523 int mode; 1524 struct proc *p; 1525{ 1526 struct com_s *com; 1527 int mynor; 1528 int s; 1529 struct tty *tp; 1530 1531 mynor = minor(dev); 1532 if (mynor & CONTROL_MASK) 1533 return (0); 1534 com = com_addr(MINOR_TO_UNIT(mynor)); 1535 if (com == NULL) 1536 return (ENODEV); 1537 tp = com->tp; 1538 s = spltty(); 1539 (*linesw[tp->t_line].l_close)(tp, flag); 1540 disc_optim(tp, &tp->t_termios, com); 1541 comstop(tp, FREAD | FWRITE); 1542 comhardclose(com); 1543 ttyclose(tp); 1544 siosettimeout(); 1545 splx(s); 1546 if (com->gone) { 1547 printf("sio%d: gone\n", com->unit); 1548 s = spltty(); 1549 if (com->ibuf != NULL) 1550 free(com->ibuf, M_DEVBUF); 1551 bzero(tp, sizeof *tp); 1552 splx(s); 1553 } 1554 return (0); 1555} 1556 1557static void 1558comhardclose(com) 1559 struct com_s *com; 1560{ 1561 Port_t iobase; 1562 int s; 1563 struct tty *tp; 1564 int unit; 1565 1566 unit = com->unit; 1567 iobase = com->iobase; 1568 s = spltty(); 1569 com->poll = FALSE; 1570 com->poll_output = FALSE; 1571 com->do_timestamp = FALSE; 1572 com->do_dcd_timestamp = FALSE; 1573 com->pps.ppsparam.mode = 0; 1574 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1575 { 1576 outb(iobase + com_ier, 0); 1577 tp = com->tp; 1578 if (tp->t_cflag & HUPCL 1579 /* 1580 * XXX we will miss any carrier drop between here and the 1581 * next open. Perhaps we should watch DCD even when the 1582 * port is closed; it is not sufficient to check it at 1583 * the next open because it might go up and down while 1584 * we're not watching. 1585 */ 1586 || (!com->active_out 1587 && !(com->prev_modem_status & MSR_DCD) 1588 && !(com->it_in.c_cflag & CLOCAL)) 1589 || !(tp->t_state & TS_ISOPEN)) { 1590 (void)commctl(com, TIOCM_DTR, DMBIC); 1591 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 1592 timeout(siodtrwakeup, com, com->dtr_wait); 1593 com->state |= CS_DTR_OFF; 1594 } 1595 } 1596 } 1597 if (com->hasfifo) { 1598 /* 1599 * Disable fifos so that they are off after controlled 1600 * reboots. Some BIOSes fail to detect 16550s when the 1601 * fifos are enabled. 1602 */ 1603 outb(iobase + com_fifo, 0); 1604 } 1605 com->active_out = FALSE; 1606 wakeup(&com->active_out); 1607 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1608 splx(s); 1609} 1610 1611static int 1612sioread(dev, uio, flag) 1613 dev_t dev; 1614 struct uio *uio; 1615 int flag; 1616{ 1617 int mynor; 1618 struct com_s *com; 1619 1620 mynor = minor(dev); 1621 if (mynor & CONTROL_MASK) 1622 return (ENODEV); 1623 com = com_addr(MINOR_TO_UNIT(mynor)); 1624 if (com == NULL || com->gone) 1625 return (ENODEV); 1626 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 1627} 1628 1629static int 1630siowrite(dev, uio, flag) 1631 dev_t dev; 1632 struct uio *uio; 1633 int flag; 1634{ 1635 int mynor; 1636 struct com_s *com; 1637 int unit; 1638 1639 mynor = minor(dev); 1640 if (mynor & CONTROL_MASK) 1641 return (ENODEV); 1642 1643 unit = MINOR_TO_UNIT(mynor); 1644 com = com_addr(unit); 1645 if (com == NULL || com->gone) 1646 return (ENODEV); 1647 /* 1648 * (XXX) We disallow virtual consoles if the physical console is 1649 * a serial port. This is in case there is a display attached that 1650 * is not the console. In that situation we don't need/want the X 1651 * server taking over the console. 1652 */ 1653 if (constty != NULL && unit == comconsole) 1654 constty = NULL; 1655 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 1656} 1657 1658static void 1659siobusycheck(chan) 1660 void *chan; 1661{ 1662 struct com_s *com; 1663 int s; 1664 1665 com = (struct com_s *)chan; 1666 1667 /* 1668 * Clear TS_BUSY if low-level output is complete. 1669 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1670 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1671 * called again. Reading the line status port outside of siointr1() 1672 * is safe because CS_BUSY is clear so there are no output interrupts 1673 * to lose. 1674 */ 1675 s = spltty(); 1676 if (com->state & CS_BUSY) 1677 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1678 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1679 == (LSR_TSRE | LSR_TXRDY)) { 1680 com->tp->t_state &= ~TS_BUSY; 1681 ttwwakeup(com->tp); 1682 com->extra_state &= ~CSE_BUSYCHECK; 1683 } else 1684 timeout(siobusycheck, com, hz / 100); 1685 splx(s); 1686} 1687 1688static void 1689siodtrwakeup(chan) 1690 void *chan; 1691{ 1692 struct com_s *com; 1693 1694 com = (struct com_s *)chan; 1695 com->state &= ~CS_DTR_OFF; 1696 wakeup(&com->dtr_wait); 1697} 1698 1699static void 1700sioinput(com) 1701 struct com_s *com; 1702{ 1703 u_char *buf; 1704 int incc; 1705 u_char line_status; 1706 int recv_data; 1707 struct tty *tp; 1708 1709 buf = com->ibuf; 1710 tp = com->tp; 1711 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1712 com_events -= (com->iptr - com->ibuf); 1713 com->iptr = com->ibuf; 1714 return; 1715 } 1716 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1717 /* 1718 * Avoid the grotesquely inefficient lineswitch routine 1719 * (ttyinput) in "raw" mode. It usually takes about 450 1720 * instructions (that's without canonical processing or echo!). 1721 * slinput is reasonably fast (usually 40 instructions plus 1722 * call overhead). 1723 */ 1724 do { 1725 enable_intr(); 1726 incc = com->iptr - buf; 1727 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1728 && (com->state & CS_RTS_IFLOW 1729 || tp->t_iflag & IXOFF) 1730 && !(tp->t_state & TS_TBLOCK)) 1731 ttyblock(tp); 1732 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1733 += b_to_q((char *)buf, incc, &tp->t_rawq); 1734 buf += incc; 1735 tk_nin += incc; 1736 tk_rawcc += incc; 1737 tp->t_rawcc += incc; 1738 ttwakeup(tp); 1739 if (tp->t_state & TS_TTSTOP 1740 && (tp->t_iflag & IXANY 1741 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1742 tp->t_state &= ~TS_TTSTOP; 1743 tp->t_lflag &= ~FLUSHO; 1744 comstart(tp); 1745 } 1746 disable_intr(); 1747 } while (buf < com->iptr); 1748 } else { 1749 do { 1750 enable_intr(); 1751 line_status = buf[com->ierroff]; 1752 recv_data = *buf++; 1753 if (line_status 1754 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1755 if (line_status & LSR_BI) 1756 recv_data |= TTY_BI; 1757 if (line_status & LSR_FE) 1758 recv_data |= TTY_FE; 1759 if (line_status & LSR_OE) 1760 recv_data |= TTY_OE; 1761 if (line_status & LSR_PE) 1762 recv_data |= TTY_PE; 1763 } 1764 (*linesw[tp->t_line].l_rint)(recv_data, tp); 1765 disable_intr(); 1766 } while (buf < com->iptr); 1767 } 1768 com_events -= (com->iptr - com->ibuf); 1769 com->iptr = com->ibuf; 1770 1771 /* 1772 * There is now room for another low-level buffer full of input, 1773 * so enable RTS if it is now disabled and there is room in the 1774 * high-level buffer. 1775 */ 1776 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1777 !(tp->t_state & TS_TBLOCK)) 1778 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1779} 1780 1781void 1782siointr(arg) 1783 void *arg; 1784{ 1785#ifndef COM_MULTIPORT 1786 COM_LOCK(); 1787 siointr1((struct com_s *) arg); 1788 COM_UNLOCK(); 1789#else /* COM_MULTIPORT */ 1790 bool_t possibly_more_intrs; 1791 int unit; 1792 struct com_s *com; 1793 1794 /* 1795 * Loop until there is no activity on any port. This is necessary 1796 * to get an interrupt edge more than to avoid another interrupt. 1797 * If the IRQ signal is just an OR of the IRQ signals from several 1798 * devices, then the edge from one may be lost because another is 1799 * on. 1800 */ 1801 COM_LOCK(); 1802 do { 1803 possibly_more_intrs = FALSE; 1804 for (unit = 0; unit < sio_numunits; ++unit) { 1805 com = com_addr(unit); 1806 /* 1807 * XXX COM_LOCK(); 1808 * would it work here, or be counter-productive? 1809 */ 1810 if (com != NULL 1811 && !com->gone 1812 && (inb(com->int_id_port) & IIR_IMASK) 1813 != IIR_NOPEND) { 1814 siointr1(com); 1815 possibly_more_intrs = TRUE; 1816 } 1817 /* XXX COM_UNLOCK(); */ 1818 } 1819 } while (possibly_more_intrs); 1820 COM_UNLOCK(); 1821#endif /* COM_MULTIPORT */ 1822} 1823 1824static void 1825siointr1(com) 1826 struct com_s *com; 1827{ 1828 u_char line_status; 1829 u_char modem_status; 1830 u_char *ioptr; 1831 u_char recv_data; 1832 u_char int_ctl; 1833 u_char int_ctl_new; 1834 struct timecounter *tc; 1835 u_int count; 1836 1837 int_ctl = inb(com->intr_ctl_port); 1838 int_ctl_new = int_ctl; 1839 1840 while (!com->gone) { 1841 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1842 modem_status = inb(com->modem_status_port); 1843 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 1844 tc = timecounter; 1845 count = tc->tc_get_timecount(tc); 1846 pps_event(&com->pps, tc, count, 1847 (modem_status & MSR_DCD) ? 1848 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1849 } 1850 } 1851 line_status = inb(com->line_status_port); 1852 1853 /* input event? (check first to help avoid overruns) */ 1854 while (line_status & LSR_RCV_MASK) { 1855 /* break/unnattached error bits or real input? */ 1856 if (!(line_status & LSR_RXRDY)) 1857 recv_data = 0; 1858 else 1859 recv_data = inb(com->data_port); 1860 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1861 /* 1862 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1863 * Otherwise, push the work to a higher level 1864 * (to handle PARMRK) if we're bypassing. 1865 * Otherwise, convert BI/FE and PE+INPCK to 0. 1866 * 1867 * This makes bypassing work right in the 1868 * usual "raw" case (IGNBRK set, and IGNPAR 1869 * and INPCK clear). 1870 * 1871 * Note: BI together with FE/PE means just BI. 1872 */ 1873 if (line_status & LSR_BI) { 1874#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 1875 if (com->unit == comconsole) { 1876 breakpoint(); 1877 goto cont; 1878 } 1879#endif 1880 if (com->tp == NULL 1881 || com->tp->t_iflag & IGNBRK) 1882 goto cont; 1883 } else { 1884 if (com->tp == NULL 1885 || com->tp->t_iflag & IGNPAR) 1886 goto cont; 1887 } 1888 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1889 && (line_status & (LSR_BI | LSR_FE) 1890 || com->tp->t_iflag & INPCK)) 1891 recv_data = 0; 1892 } 1893 ++com->bytes_in; 1894 if (com->hotchar != 0 && recv_data == com->hotchar) 1895 setsofttty(); 1896 ioptr = com->iptr; 1897 if (ioptr >= com->ibufend) 1898 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1899 else { 1900 if (com->do_timestamp) 1901 microtime(&com->timestamp); 1902 ++com_events; 1903 schedsofttty(); 1904#if 0 /* for testing input latency vs efficiency */ 1905if (com->iptr - com->ibuf == 8) 1906 setsofttty(); 1907#endif 1908 ioptr[0] = recv_data; 1909 ioptr[com->ierroff] = line_status; 1910 com->iptr = ++ioptr; 1911 if (ioptr == com->ihighwater 1912 && com->state & CS_RTS_IFLOW) 1913 outb(com->modem_ctl_port, 1914 com->mcr_image &= ~MCR_RTS); 1915 if (line_status & LSR_OE) 1916 CE_RECORD(com, CE_OVERRUN); 1917 } 1918cont: 1919 /* 1920 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1921 * jump from the top of the loop to here 1922 */ 1923 line_status = inb(com->line_status_port) & 0x7F; 1924 } 1925 1926 /* modem status change? (always check before doing output) */ 1927 modem_status = inb(com->modem_status_port); 1928 if (modem_status != com->last_modem_status) { 1929 if (com->do_dcd_timestamp 1930 && !(com->last_modem_status & MSR_DCD) 1931 && modem_status & MSR_DCD) 1932 microtime(&com->dcd_timestamp); 1933 1934 /* 1935 * Schedule high level to handle DCD changes. Note 1936 * that we don't use the delta bits anywhere. Some 1937 * UARTs mess them up, and it's easy to remember the 1938 * previous bits and calculate the delta. 1939 */ 1940 com->last_modem_status = modem_status; 1941 if (!(com->state & CS_CHECKMSR)) { 1942 com_events += LOTS_OF_EVENTS; 1943 com->state |= CS_CHECKMSR; 1944 setsofttty(); 1945 } 1946 1947 /* handle CTS change immediately for crisp flow ctl */ 1948 if (com->state & CS_CTS_OFLOW) { 1949 if (modem_status & MSR_CTS) 1950 com->state |= CS_ODEVREADY; 1951 else 1952 com->state &= ~CS_ODEVREADY; 1953 } 1954 } 1955 1956 /* output queued and everything ready? */ 1957 if (line_status & LSR_TXRDY 1958 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1959 ioptr = com->obufq.l_head; 1960 if (com->tx_fifo_size > 1) { 1961 u_int ocount; 1962 1963 ocount = com->obufq.l_tail - ioptr; 1964 if (ocount > com->tx_fifo_size) 1965 ocount = com->tx_fifo_size; 1966 com->bytes_out += ocount; 1967 do 1968 outb(com->data_port, *ioptr++); 1969 while (--ocount != 0); 1970 } else { 1971 outb(com->data_port, *ioptr++); 1972 ++com->bytes_out; 1973 } 1974 com->obufq.l_head = ioptr; 1975 if (COM_IIR_TXRDYBUG(com->flags)) { 1976 int_ctl_new = int_ctl | IER_ETXRDY; 1977 } 1978 if (ioptr >= com->obufq.l_tail) { 1979 struct lbq *qp; 1980 1981 qp = com->obufq.l_next; 1982 qp->l_queued = FALSE; 1983 qp = qp->l_next; 1984 if (qp != NULL) { 1985 com->obufq.l_head = qp->l_head; 1986 com->obufq.l_tail = qp->l_tail; 1987 com->obufq.l_next = qp; 1988 } else { 1989 /* output just completed */ 1990 if (COM_IIR_TXRDYBUG(com->flags)) { 1991 int_ctl_new = int_ctl & ~IER_ETXRDY; 1992 } 1993 com->state &= ~CS_BUSY; 1994 } 1995 if (!(com->state & CS_ODONE)) { 1996 com_events += LOTS_OF_EVENTS; 1997 com->state |= CS_ODONE; 1998 setsofttty(); /* handle at high level ASAP */ 1999 } 2000 } 2001 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 2002 outb(com->intr_ctl_port, int_ctl_new); 2003 } 2004 } 2005 2006 /* finished? */ 2007#ifndef COM_MULTIPORT 2008 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2009#endif /* COM_MULTIPORT */ 2010 return; 2011 } 2012} 2013 2014static int 2015sioioctl(dev, cmd, data, flag, p) 2016 dev_t dev; 2017 u_long cmd; 2018 caddr_t data; 2019 int flag; 2020 struct proc *p; 2021{ 2022 struct com_s *com; 2023 int error; 2024 Port_t iobase; 2025 int mynor; 2026 int s; 2027 struct tty *tp; 2028#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2029 u_long oldcmd; 2030 struct termios term; 2031#endif 2032 2033 mynor = minor(dev); 2034 com = com_addr(MINOR_TO_UNIT(mynor)); 2035 if (com == NULL || com->gone) 2036 return (ENODEV); 2037 iobase = com->iobase; 2038 if (mynor & CONTROL_MASK) { 2039 struct termios *ct; 2040 2041 switch (mynor & CONTROL_MASK) { 2042 case CONTROL_INIT_STATE: 2043 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2044 break; 2045 case CONTROL_LOCK_STATE: 2046 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2047 break; 2048 default: 2049 return (ENODEV); /* /dev/nodev */ 2050 } 2051 switch (cmd) { 2052 case TIOCSETA: 2053 error = suser(p); 2054 if (error != 0) 2055 return (error); 2056 *ct = *(struct termios *)data; 2057 return (0); 2058 case TIOCGETA: 2059 *(struct termios *)data = *ct; 2060 return (0); 2061 case TIOCGETD: 2062 *(int *)data = TTYDISC; 2063 return (0); 2064 case TIOCGWINSZ: 2065 bzero(data, sizeof(struct winsize)); 2066 return (0); 2067 default: 2068 return (ENOTTY); 2069 } 2070 } 2071 tp = com->tp; 2072#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2073 term = tp->t_termios; 2074 oldcmd = cmd; 2075 error = ttsetcompat(tp, &cmd, data, &term); 2076 if (error != 0) 2077 return (error); 2078 if (cmd != oldcmd) 2079 data = (caddr_t)&term; 2080#endif 2081 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2082 int cc; 2083 struct termios *dt = (struct termios *)data; 2084 struct termios *lt = mynor & CALLOUT_MASK 2085 ? &com->lt_out : &com->lt_in; 2086 2087 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2088 | (dt->c_iflag & ~lt->c_iflag); 2089 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2090 | (dt->c_oflag & ~lt->c_oflag); 2091 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2092 | (dt->c_cflag & ~lt->c_cflag); 2093 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2094 | (dt->c_lflag & ~lt->c_lflag); 2095 for (cc = 0; cc < NCCS; ++cc) 2096 if (lt->c_cc[cc] != 0) 2097 dt->c_cc[cc] = tp->t_cc[cc]; 2098 if (lt->c_ispeed != 0) 2099 dt->c_ispeed = tp->t_ispeed; 2100 if (lt->c_ospeed != 0) 2101 dt->c_ospeed = tp->t_ospeed; 2102 } 2103 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 2104 if (error != ENOIOCTL) 2105 return (error); 2106 s = spltty(); 2107 error = ttioctl(tp, cmd, data, flag); 2108 disc_optim(tp, &tp->t_termios, com); 2109 if (error != ENOIOCTL) { 2110 splx(s); 2111 return (error); 2112 } 2113 switch (cmd) { 2114 case TIOCSBRK: 2115 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2116 break; 2117 case TIOCCBRK: 2118 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2119 break; 2120 case TIOCSDTR: 2121 (void)commctl(com, TIOCM_DTR, DMBIS); 2122 break; 2123 case TIOCCDTR: 2124 (void)commctl(com, TIOCM_DTR, DMBIC); 2125 break; 2126 /* 2127 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 2128 * changes get undone on the next call to comparam(). 2129 */ 2130 case TIOCMSET: 2131 (void)commctl(com, *(int *)data, DMSET); 2132 break; 2133 case TIOCMBIS: 2134 (void)commctl(com, *(int *)data, DMBIS); 2135 break; 2136 case TIOCMBIC: 2137 (void)commctl(com, *(int *)data, DMBIC); 2138 break; 2139 case TIOCMGET: 2140 *(int *)data = commctl(com, 0, DMGET); 2141 break; 2142 case TIOCMSDTRWAIT: 2143 /* must be root since the wait applies to following logins */ 2144 error = suser(p); 2145 if (error != 0) { 2146 splx(s); 2147 return (error); 2148 } 2149 com->dtr_wait = *(int *)data * hz / 100; 2150 break; 2151 case TIOCMGDTRWAIT: 2152 *(int *)data = com->dtr_wait * 100 / hz; 2153 break; 2154 case TIOCTIMESTAMP: 2155 com->do_timestamp = TRUE; 2156 *(struct timeval *)data = com->timestamp; 2157 break; 2158 case TIOCDCDTIMESTAMP: 2159 com->do_dcd_timestamp = TRUE; 2160 *(struct timeval *)data = com->dcd_timestamp; 2161 break; 2162 default: 2163 splx(s); 2164 error = pps_ioctl(cmd, data, &com->pps); 2165 if (error == ENODEV) 2166 error = ENOTTY; 2167 return (error); 2168 } 2169 splx(s); 2170 return (0); 2171} 2172 2173static void 2174siopoll() 2175{ 2176 int unit; 2177 2178 if (com_events == 0) 2179 return; 2180repeat: 2181 for (unit = 0; unit < sio_numunits; ++unit) { 2182 struct com_s *com; 2183 int incc; 2184 struct tty *tp; 2185 2186 com = com_addr(unit); 2187 if (com == NULL) 2188 continue; 2189 tp = com->tp; 2190 if (tp == NULL || com->gone) { 2191 /* 2192 * Discard any events related to never-opened or 2193 * going-away devices. 2194 */ 2195 disable_intr(); 2196 incc = com->iptr - com->ibuf; 2197 com->iptr = com->ibuf; 2198 if (com->state & CS_CHECKMSR) { 2199 incc += LOTS_OF_EVENTS; 2200 com->state &= ~CS_CHECKMSR; 2201 } 2202 com_events -= incc; 2203 enable_intr(); 2204 continue; 2205 } 2206 if (com->iptr != com->ibuf) { 2207 disable_intr(); 2208 sioinput(com); 2209 enable_intr(); 2210 } 2211 if (com->state & CS_CHECKMSR) { 2212 u_char delta_modem_status; 2213 2214 disable_intr(); 2215 delta_modem_status = com->last_modem_status 2216 ^ com->prev_modem_status; 2217 com->prev_modem_status = com->last_modem_status; 2218 com_events -= LOTS_OF_EVENTS; 2219 com->state &= ~CS_CHECKMSR; 2220 enable_intr(); 2221 if (delta_modem_status & MSR_DCD) 2222 (*linesw[tp->t_line].l_modem) 2223 (tp, com->prev_modem_status & MSR_DCD); 2224 } 2225 if (com->state & CS_ODONE) { 2226 disable_intr(); 2227 com_events -= LOTS_OF_EVENTS; 2228 com->state &= ~CS_ODONE; 2229 enable_intr(); 2230 if (!(com->state & CS_BUSY) 2231 && !(com->extra_state & CSE_BUSYCHECK)) { 2232 timeout(siobusycheck, com, hz / 100); 2233 com->extra_state |= CSE_BUSYCHECK; 2234 } 2235 (*linesw[tp->t_line].l_start)(tp); 2236 } 2237 if (com_events == 0) 2238 break; 2239 } 2240 if (com_events >= LOTS_OF_EVENTS) 2241 goto repeat; 2242} 2243 2244static int 2245comparam(tp, t) 2246 struct tty *tp; 2247 struct termios *t; 2248{ 2249 u_int cfcr; 2250 int cflag; 2251 struct com_s *com; 2252 int divisor; 2253 u_char dlbh; 2254 u_char dlbl; 2255 Port_t iobase; 2256 int s; 2257 int unit; 2258 2259 /* do historical conversions */ 2260 if (t->c_ispeed == 0) 2261 t->c_ispeed = t->c_ospeed; 2262 2263 /* check requested parameters */ 2264 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 2265 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 2266 return (EINVAL); 2267 2268 /* parameters are OK, convert them to the com struct and the device */ 2269 unit = DEV_TO_UNIT(tp->t_dev); 2270 com = com_addr(unit); 2271 if (com == NULL) 2272 return (ENODEV); 2273 iobase = com->iobase; 2274 s = spltty(); 2275 if (divisor == 0) 2276 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 2277 else 2278 (void)commctl(com, TIOCM_DTR, DMBIS); 2279 cflag = t->c_cflag; 2280 switch (cflag & CSIZE) { 2281 case CS5: 2282 cfcr = CFCR_5BITS; 2283 break; 2284 case CS6: 2285 cfcr = CFCR_6BITS; 2286 break; 2287 case CS7: 2288 cfcr = CFCR_7BITS; 2289 break; 2290 default: 2291 cfcr = CFCR_8BITS; 2292 break; 2293 } 2294 if (cflag & PARENB) { 2295 cfcr |= CFCR_PENAB; 2296 if (!(cflag & PARODD)) 2297 cfcr |= CFCR_PEVEN; 2298 } 2299 if (cflag & CSTOPB) 2300 cfcr |= CFCR_STOPB; 2301 2302 if (com->hasfifo && divisor != 0) { 2303 /* 2304 * Use a fifo trigger level low enough so that the input 2305 * latency from the fifo is less than about 16 msec and 2306 * the total latency is less than about 30 msec. These 2307 * latencies are reasonable for humans. Serial comms 2308 * protocols shouldn't expect anything better since modem 2309 * latencies are larger. 2310 */ 2311 com->fifo_image = t->c_ospeed <= 4800 2312 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 2313#ifdef COM_ESP 2314 /* 2315 * The Hayes ESP card needs the fifo DMA mode bit set 2316 * in compatibility mode. If not, it will interrupt 2317 * for each character received. 2318 */ 2319 if (com->esp) 2320 com->fifo_image |= FIFO_DMA_MODE; 2321#endif 2322 outb(iobase + com_fifo, com->fifo_image); 2323 } 2324 2325 /* 2326 * This returns with interrupts disabled so that we can complete 2327 * the speed change atomically. Keeping interrupts disabled is 2328 * especially important while com_data is hidden. 2329 */ 2330 (void) siosetwater(com, t->c_ispeed); 2331 2332 if (divisor != 0) { 2333 outb(iobase + com_cfcr, cfcr | CFCR_DLAB); 2334 /* 2335 * Only set the divisor registers if they would change, 2336 * since on some 16550 incompatibles (UMC8669F), setting 2337 * them while input is arriving them loses sync until 2338 * data stops arriving. 2339 */ 2340 dlbl = divisor & 0xFF; 2341 if (inb(iobase + com_dlbl) != dlbl) 2342 outb(iobase + com_dlbl, dlbl); 2343 dlbh = (u_int) divisor >> 8; 2344 if (inb(iobase + com_dlbh) != dlbh) 2345 outb(iobase + com_dlbh, dlbh); 2346 } 2347 2348 2349 outb(iobase + com_cfcr, com->cfcr_image = cfcr); 2350 2351 if (!(tp->t_state & TS_TTSTOP)) 2352 com->state |= CS_TTGO; 2353 2354 if (cflag & CRTS_IFLOW) { 2355 if (com->st16650a) { 2356 outb(iobase + com_cfcr, 0xbf); 2357 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40); 2358 } 2359 com->state |= CS_RTS_IFLOW; 2360 /* 2361 * If CS_RTS_IFLOW just changed from off to on, the change 2362 * needs to be propagated to MCR_RTS. This isn't urgent, 2363 * so do it later by calling comstart() instead of repeating 2364 * a lot of code from comstart() here. 2365 */ 2366 } else if (com->state & CS_RTS_IFLOW) { 2367 com->state &= ~CS_RTS_IFLOW; 2368 /* 2369 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2370 * on here, since comstart() won't do it later. 2371 */ 2372 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2373 if (com->st16650a) { 2374 outb(iobase + com_cfcr, 0xbf); 2375 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40); 2376 } 2377 } 2378 2379 2380 /* 2381 * Set up state to handle output flow control. 2382 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2383 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2384 */ 2385 com->state |= CS_ODEVREADY; 2386 com->state &= ~CS_CTS_OFLOW; 2387 if (cflag & CCTS_OFLOW) { 2388 com->state |= CS_CTS_OFLOW; 2389 if (!(com->last_modem_status & MSR_CTS)) 2390 com->state &= ~CS_ODEVREADY; 2391 if (com->st16650a) { 2392 outb(iobase + com_cfcr, 0xbf); 2393 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80); 2394 } 2395 } else { 2396 if (com->st16650a) { 2397 outb(iobase + com_cfcr, 0xbf); 2398 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80); 2399 } 2400 } 2401 2402 2403 outb(iobase + com_cfcr, com->cfcr_image); 2404 2405 2406 /* XXX shouldn't call functions while intrs are disabled. */ 2407 disc_optim(tp, t, com); 2408 /* 2409 * Recover from fiddling with CS_TTGO. We used to call siointr1() 2410 * unconditionally, but that defeated the careful discarding of 2411 * stale input in sioopen(). 2412 */ 2413 if (com->state >= (CS_BUSY | CS_TTGO)) 2414 siointr1(com); 2415 2416 enable_intr(); 2417 splx(s); 2418 comstart(tp); 2419 if (com->ibufold != NULL) { 2420 free(com->ibufold, M_DEVBUF); 2421 com->ibufold = NULL; 2422 } 2423 return (0); 2424} 2425 2426static int 2427siosetwater(com, speed) 2428 struct com_s *com; 2429 speed_t speed; 2430{ 2431 int cp4ticks; 2432 u_char *ibuf; 2433 int ibufsize; 2434 struct tty *tp; 2435 2436 /* 2437 * Make the buffer size large enough to handle a softtty interrupt 2438 * latency of about 2 ticks without loss of throughput or data 2439 * (about 3 ticks if input flow control is not used or not honoured, 2440 * but a bit less for CS5-CS7 modes). 2441 */ 2442 cp4ticks = speed / 10 / hz * 4; 2443 for (ibufsize = 128; ibufsize < cp4ticks;) 2444 ibufsize <<= 1; 2445 if (ibufsize == com->ibufsize) { 2446 disable_intr(); 2447 return (0); 2448 } 2449 2450 /* 2451 * Allocate input buffer. The extra factor of 2 in the size is 2452 * to allow for an error byte for each input byte. 2453 */ 2454 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2455 if (ibuf == NULL) { 2456 disable_intr(); 2457 return (ENOMEM); 2458 } 2459 2460 /* Initialize non-critical variables. */ 2461 com->ibufold = com->ibuf; 2462 com->ibufsize = ibufsize; 2463 tp = com->tp; 2464 if (tp != NULL) { 2465 tp->t_ififosize = 2 * ibufsize; 2466 tp->t_ispeedwat = (speed_t)-1; 2467 tp->t_ospeedwat = (speed_t)-1; 2468 } 2469 2470 /* 2471 * Read current input buffer, if any. Continue with interrupts 2472 * disabled. 2473 */ 2474 disable_intr(); 2475 if (com->iptr != com->ibuf) 2476 sioinput(com); 2477 2478 /*- 2479 * Initialize critical variables, including input buffer watermarks. 2480 * The external device is asked to stop sending when the buffer 2481 * exactly reaches high water, or when the high level requests it. 2482 * The high level is notified immediately (rather than at a later 2483 * clock tick) when this watermark is reached. 2484 * The buffer size is chosen so the watermark should almost never 2485 * be reached. 2486 * The low watermark is invisibly 0 since the buffer is always 2487 * emptied all at once. 2488 */ 2489 com->iptr = com->ibuf = ibuf; 2490 com->ibufend = ibuf + ibufsize; 2491 com->ierroff = ibufsize; 2492 com->ihighwater = ibuf + 3 * ibufsize / 4; 2493 return (0); 2494} 2495 2496static void 2497comstart(tp) 2498 struct tty *tp; 2499{ 2500 struct com_s *com; 2501 int s; 2502 int unit; 2503 2504 unit = DEV_TO_UNIT(tp->t_dev); 2505 com = com_addr(unit); 2506 if (com == NULL) 2507 return; 2508 s = spltty(); 2509 disable_intr(); 2510 if (tp->t_state & TS_TTSTOP) 2511 com->state &= ~CS_TTGO; 2512 else 2513 com->state |= CS_TTGO; 2514 if (tp->t_state & TS_TBLOCK) { 2515 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2516 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2517 } else { 2518 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2519 && com->state & CS_RTS_IFLOW) 2520 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2521 } 2522 enable_intr(); 2523 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2524 ttwwakeup(tp); 2525 splx(s); 2526 return; 2527 } 2528 if (tp->t_outq.c_cc != 0) { 2529 struct lbq *qp; 2530 struct lbq *next; 2531 2532 if (!com->obufs[0].l_queued) { 2533 com->obufs[0].l_tail 2534 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2535 sizeof com->obuf1); 2536 com->obufs[0].l_next = NULL; 2537 com->obufs[0].l_queued = TRUE; 2538 disable_intr(); 2539 if (com->state & CS_BUSY) { 2540 qp = com->obufq.l_next; 2541 while ((next = qp->l_next) != NULL) 2542 qp = next; 2543 qp->l_next = &com->obufs[0]; 2544 } else { 2545 com->obufq.l_head = com->obufs[0].l_head; 2546 com->obufq.l_tail = com->obufs[0].l_tail; 2547 com->obufq.l_next = &com->obufs[0]; 2548 com->state |= CS_BUSY; 2549 } 2550 enable_intr(); 2551 } 2552 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2553 com->obufs[1].l_tail 2554 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2555 sizeof com->obuf2); 2556 com->obufs[1].l_next = NULL; 2557 com->obufs[1].l_queued = TRUE; 2558 disable_intr(); 2559 if (com->state & CS_BUSY) { 2560 qp = com->obufq.l_next; 2561 while ((next = qp->l_next) != NULL) 2562 qp = next; 2563 qp->l_next = &com->obufs[1]; 2564 } else { 2565 com->obufq.l_head = com->obufs[1].l_head; 2566 com->obufq.l_tail = com->obufs[1].l_tail; 2567 com->obufq.l_next = &com->obufs[1]; 2568 com->state |= CS_BUSY; 2569 } 2570 enable_intr(); 2571 } 2572 tp->t_state |= TS_BUSY; 2573 } 2574 disable_intr(); 2575 if (com->state >= (CS_BUSY | CS_TTGO)) 2576 siointr1(com); /* fake interrupt to start output */ 2577 enable_intr(); 2578 ttwwakeup(tp); 2579 splx(s); 2580} 2581 2582static void 2583comstop(tp, rw) 2584 struct tty *tp; 2585 int rw; 2586{ 2587 struct com_s *com; 2588 2589 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 2590 if (com == NULL || com->gone) 2591 return; 2592 disable_intr(); 2593 if (rw & FWRITE) { 2594 if (com->hasfifo) 2595#ifdef COM_ESP 2596 /* XXX avoid h/w bug. */ 2597 if (!com->esp) 2598#endif 2599 outb(com->iobase + com_fifo, 2600 FIFO_XMT_RST | com->fifo_image); 2601 com->obufs[0].l_queued = FALSE; 2602 com->obufs[1].l_queued = FALSE; 2603 if (com->state & CS_ODONE) 2604 com_events -= LOTS_OF_EVENTS; 2605 com->state &= ~(CS_ODONE | CS_BUSY); 2606 com->tp->t_state &= ~TS_BUSY; 2607 } 2608 if (rw & FREAD) { 2609 if (com->hasfifo) 2610#ifdef COM_ESP 2611 /* XXX avoid h/w bug. */ 2612 if (!com->esp) 2613#endif 2614 outb(com->iobase + com_fifo, 2615 FIFO_RCV_RST | com->fifo_image); 2616 com_events -= (com->iptr - com->ibuf); 2617 com->iptr = com->ibuf; 2618 } 2619 enable_intr(); 2620 comstart(tp); 2621} 2622 2623static int 2624commctl(com, bits, how) 2625 struct com_s *com; 2626 int bits; 2627 int how; 2628{ 2629 int mcr; 2630 int msr; 2631 2632 if (how == DMGET) { 2633 bits = TIOCM_LE; /* XXX - always enabled while open */ 2634 mcr = com->mcr_image; 2635 if (mcr & MCR_DTR) 2636 bits |= TIOCM_DTR; 2637 if (mcr & MCR_RTS) 2638 bits |= TIOCM_RTS; 2639 msr = com->prev_modem_status; 2640 if (msr & MSR_CTS) 2641 bits |= TIOCM_CTS; 2642 if (msr & MSR_DCD) 2643 bits |= TIOCM_CD; 2644 if (msr & MSR_DSR) 2645 bits |= TIOCM_DSR; 2646 /* 2647 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 2648 * more volatile by reading the modem status a lot. Perhaps 2649 * we should latch both bits until the status is read here. 2650 */ 2651 if (msr & (MSR_RI | MSR_TERI)) 2652 bits |= TIOCM_RI; 2653 return (bits); 2654 } 2655 mcr = 0; 2656 if (bits & TIOCM_DTR) 2657 mcr |= MCR_DTR; 2658 if (bits & TIOCM_RTS) 2659 mcr |= MCR_RTS; 2660 if (com->gone) 2661 return(0); 2662 disable_intr(); 2663 switch (how) { 2664 case DMSET: 2665 outb(com->modem_ctl_port, 2666 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 2667 break; 2668 case DMBIS: 2669 outb(com->modem_ctl_port, com->mcr_image |= mcr); 2670 break; 2671 case DMBIC: 2672 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 2673 break; 2674 } 2675 enable_intr(); 2676 return (0); 2677} 2678 2679static void 2680siosettimeout() 2681{ 2682 struct com_s *com; 2683 bool_t someopen; 2684 int unit; 2685 2686 /* 2687 * Set our timeout period to 1 second if no polled devices are open. 2688 * Otherwise set it to max(1/200, 1/hz). 2689 * Enable timeouts iff some device is open. 2690 */ 2691 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2692 sio_timeout = hz; 2693 someopen = FALSE; 2694 for (unit = 0; unit < sio_numunits; ++unit) { 2695 com = com_addr(unit); 2696 if (com != NULL && com->tp != NULL 2697 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2698 someopen = TRUE; 2699 if (com->poll || com->poll_output) { 2700 sio_timeout = hz > 200 ? hz / 200 : 1; 2701 break; 2702 } 2703 } 2704 } 2705 if (someopen) { 2706 sio_timeouts_until_log = hz / sio_timeout; 2707 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2708 sio_timeout); 2709 } else { 2710 /* Flush error messages, if any. */ 2711 sio_timeouts_until_log = 1; 2712 comwakeup((void *)NULL); 2713 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2714 } 2715} 2716 2717static void 2718comwakeup(chan) 2719 void *chan; 2720{ 2721 struct com_s *com; 2722 int unit; 2723 2724 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2725 2726 /* 2727 * Recover from lost output interrupts. 2728 * Poll any lines that don't use interrupts. 2729 */ 2730 for (unit = 0; unit < sio_numunits; ++unit) { 2731 com = com_addr(unit); 2732 if (com != NULL && !com->gone 2733 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2734 disable_intr(); 2735 siointr1(com); 2736 enable_intr(); 2737 } 2738 } 2739 2740 /* 2741 * Check for and log errors, but not too often. 2742 */ 2743 if (--sio_timeouts_until_log > 0) 2744 return; 2745 sio_timeouts_until_log = hz / sio_timeout; 2746 for (unit = 0; unit < sio_numunits; ++unit) { 2747 int errnum; 2748 2749 com = com_addr(unit); 2750 if (com == NULL) 2751 continue; 2752 if (com->gone) 2753 continue; 2754 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2755 u_int delta; 2756 u_long total; 2757 2758 disable_intr(); 2759 delta = com->delta_error_counts[errnum]; 2760 com->delta_error_counts[errnum] = 0; 2761 enable_intr(); 2762 if (delta == 0) 2763 continue; 2764 total = com->error_counts[errnum] += delta; 2765 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2766 unit, delta, error_desc[errnum], 2767 delta == 1 ? "" : "s", total); 2768 } 2769 } 2770} 2771 2772static void 2773disc_optim(tp, t, com) 2774 struct tty *tp; 2775 struct termios *t; 2776 struct com_s *com; 2777{ 2778 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 2779 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 2780 && (!(t->c_iflag & PARMRK) 2781 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 2782 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 2783 && linesw[tp->t_line].l_rint == ttyinput) 2784 tp->t_state |= TS_CAN_BYPASS_L_RINT; 2785 else 2786 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 2787 com->hotchar = linesw[tp->t_line].l_hotchar; 2788} 2789 2790/* 2791 * Following are all routines needed for SIO to act as console 2792 */ 2793#include <sys/cons.h> 2794 2795struct siocnstate { 2796 u_char dlbl; 2797 u_char dlbh; 2798 u_char ier; 2799 u_char cfcr; 2800 u_char mcr; 2801}; 2802 2803static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 2804static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 2805static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 2806static void siocntxwait __P((Port_t iobase)); 2807 2808static cn_probe_t siocnprobe; 2809static cn_init_t siocninit; 2810static cn_checkc_t siocncheckc; 2811static cn_getc_t siocngetc; 2812static cn_putc_t siocnputc; 2813 2814#ifdef __i386__ 2815CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, 2816 siocnputc, NULL); 2817#endif 2818 2819/* To get the GDB related variables */ 2820#if DDB > 0 2821#include <ddb/ddb.h> 2822#endif 2823 2824static void 2825siocntxwait(iobase) 2826 Port_t iobase; 2827{ 2828 int timo; 2829 2830 /* 2831 * Wait for any pending transmission to finish. Required to avoid 2832 * the UART lockup bug when the speed is changed, and for normal 2833 * transmits. 2834 */ 2835 timo = 100000; 2836 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2837 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2838 ; 2839} 2840 2841/* 2842 * Read the serial port specified and try to figure out what speed 2843 * it's currently running at. We're assuming the serial port has 2844 * been initialized and is basicly idle. This routine is only intended 2845 * to be run at system startup. 2846 * 2847 * If the value read from the serial port doesn't make sense, return 0. 2848 */ 2849 2850static speed_t 2851siocngetspeed(iobase, table) 2852 Port_t iobase; 2853 struct speedtab *table; 2854{ 2855 int code; 2856 u_char dlbh; 2857 u_char dlbl; 2858 u_char cfcr; 2859 2860 cfcr = inb(iobase + com_cfcr); 2861 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2862 2863 dlbl = inb(iobase + com_dlbl); 2864 dlbh = inb(iobase + com_dlbh); 2865 2866 outb(iobase + com_cfcr, cfcr); 2867 2868 code = dlbh << 8 | dlbl; 2869 2870 for (; table->sp_speed != -1; table++) 2871 if (table->sp_code == code) 2872 return (table->sp_speed); 2873 2874 return (0); /* didn't match anything sane */ 2875} 2876 2877static void 2878siocnopen(sp, iobase, speed) 2879 struct siocnstate *sp; 2880 Port_t iobase; 2881 int speed; 2882{ 2883 int divisor; 2884 u_char dlbh; 2885 u_char dlbl; 2886 2887 /* 2888 * Save all the device control registers except the fifo register 2889 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2890 * We can't save the fifo register since it is read-only. 2891 */ 2892 sp->ier = inb(iobase + com_ier); 2893 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2894 siocntxwait(iobase); 2895 sp->cfcr = inb(iobase + com_cfcr); 2896 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2897 sp->dlbl = inb(iobase + com_dlbl); 2898 sp->dlbh = inb(iobase + com_dlbh); 2899 /* 2900 * Only set the divisor registers if they would change, since on 2901 * some 16550 incompatibles (Startech), setting them clears the 2902 * data input register. This also reduces the effects of the 2903 * UMC8669F bug. 2904 */ 2905 divisor = ttspeedtab(speed, comspeedtab); 2906 dlbl = divisor & 0xFF; 2907 if (sp->dlbl != dlbl) 2908 outb(iobase + com_dlbl, dlbl); 2909 dlbh = (u_int) divisor >> 8; 2910 if (sp->dlbh != dlbh) 2911 outb(iobase + com_dlbh, dlbh); 2912 outb(iobase + com_cfcr, CFCR_8BITS); 2913 sp->mcr = inb(iobase + com_mcr); 2914 /* 2915 * We don't want interrupts, but must be careful not to "disable" 2916 * them by clearing the MCR_IENABLE bit, since that might cause 2917 * an interrupt by floating the IRQ line. 2918 */ 2919 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2920} 2921 2922static void 2923siocnclose(sp, iobase) 2924 struct siocnstate *sp; 2925 Port_t iobase; 2926{ 2927 /* 2928 * Restore the device control registers. 2929 */ 2930 siocntxwait(iobase); 2931 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2932 if (sp->dlbl != inb(iobase + com_dlbl)) 2933 outb(iobase + com_dlbl, sp->dlbl); 2934 if (sp->dlbh != inb(iobase + com_dlbh)) 2935 outb(iobase + com_dlbh, sp->dlbh); 2936 outb(iobase + com_cfcr, sp->cfcr); 2937 /* 2938 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2939 */ 2940 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2941 outb(iobase + com_ier, sp->ier); 2942} 2943 2944static void 2945siocnprobe(cp) 2946 struct consdev *cp; 2947{ 2948 speed_t boot_speed; 2949 u_char cfcr; 2950 int s, unit; 2951 struct siocnstate sp; 2952 2953 /* 2954 * Find our first enabled console, if any. If it is a high-level 2955 * console device, then initialize it and return successfully. 2956 * If it is a low-level console device, then initialize it and 2957 * return unsuccessfully. It must be initialized in both cases 2958 * for early use by console drivers and debuggers. Initializing 2959 * the hardware is not necessary in all cases, since the i/o 2960 * routines initialize it on the fly, but it is necessary if 2961 * input might arrive while the hardware is switched back to an 2962 * uninitialized state. We can't handle multiple console devices 2963 * yet because our low-level routines don't take a device arg. 2964 * We trust the user to set the console flags properly so that we 2965 * don't need to probe. 2966 */ 2967 cp->cn_pri = CN_DEAD; 2968 2969 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2970 int flags; 2971 int disabled; 2972 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 2973 if (disabled) 2974 continue; 2975 } 2976 if (resource_int_value("sio", unit, "flags", &flags)) 2977 continue; 2978 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2979 int port; 2980 Port_t iobase; 2981 2982 if (resource_int_value("sio", unit, "port", &port)) 2983 continue; 2984 iobase = port; 2985 s = spltty(); 2986 if (boothowto & RB_SERIAL) { 2987 boot_speed = siocngetspeed(iobase, comspeedtab); 2988 if (boot_speed) 2989 comdefaultrate = boot_speed; 2990 } 2991 2992 /* 2993 * Initialize the divisor latch. We can't rely on 2994 * siocnopen() to do this the first time, since it 2995 * avoids writing to the latch if the latch appears 2996 * to have the correct value. Also, if we didn't 2997 * just read the speed from the hardware, then we 2998 * need to set the speed in hardware so that 2999 * switching it later is null. 3000 */ 3001 cfcr = inb(iobase + com_cfcr); 3002 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3003 outb(iobase + com_dlbl, 3004 COMBRD(comdefaultrate) & 0xff); 3005 outb(iobase + com_dlbh, 3006 (u_int) COMBRD(comdefaultrate) >> 8); 3007 outb(iobase + com_cfcr, cfcr); 3008 3009 siocnopen(&sp, iobase, comdefaultrate); 3010 3011 splx(s); 3012 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 3013 cp->cn_dev = makedev(CDEV_MAJOR, unit); 3014 cp->cn_pri = COM_FORCECONSOLE(flags) 3015 || boothowto & RB_SERIAL 3016 ? CN_REMOTE : CN_NORMAL; 3017 siocniobase = iobase; 3018 siocnunit = unit; 3019 } 3020 if (COM_DEBUGGER(flags)) { 3021 printf("sio%d: gdb debugging port\n", unit); 3022 siogdbiobase = iobase; 3023 siogdbunit = unit; 3024#if DDB > 0 3025 gdbdev = makedev(CDEV_MAJOR, unit); 3026 gdb_getc = siocngetc; 3027 gdb_putc = siocnputc; 3028#endif 3029 } 3030 } 3031 } 3032#ifdef __i386__ 3033#if DDB > 0 3034 /* 3035 * XXX Ugly Compatability. 3036 * If no gdb port has been specified, set it to be the console 3037 * as some configuration files don't specify the gdb port. 3038 */ 3039 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 3040 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 3041 siocnunit); 3042 printf("Set flag 0x80 on desired GDB port in your\n"); 3043 printf("configuration file (currently sio only).\n"); 3044 siogdbiobase = siocniobase; 3045 siogdbunit = siocnunit; 3046 gdbdev = makedev(CDEV_MAJOR, siocnunit); 3047 gdb_getc = siocngetc; 3048 gdb_putc = siocnputc; 3049 } 3050#endif 3051#endif 3052} 3053 3054#ifdef __alpha__ 3055 3056CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 3057 3058int 3059siocnattach(port, speed) 3060 int port; 3061 int speed; 3062{ 3063 int s; 3064 u_char cfcr; 3065 struct siocnstate sp; 3066 3067 siocniobase = port; 3068 comdefaultrate = speed; 3069 sio_consdev.cn_pri = CN_NORMAL; 3070 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 3071 3072 s = spltty(); 3073 3074 /* 3075 * Initialize the divisor latch. We can't rely on 3076 * siocnopen() to do this the first time, since it 3077 * avoids writing to the latch if the latch appears 3078 * to have the correct value. Also, if we didn't 3079 * just read the speed from the hardware, then we 3080 * need to set the speed in hardware so that 3081 * switching it later is null. 3082 */ 3083 cfcr = inb(siocniobase + com_cfcr); 3084 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 3085 outb(siocniobase + com_dlbl, 3086 COMBRD(comdefaultrate) & 0xff); 3087 outb(siocniobase + com_dlbh, 3088 (u_int) COMBRD(comdefaultrate) >> 8); 3089 outb(siocniobase + com_cfcr, cfcr); 3090 3091 siocnopen(&sp, siocniobase, comdefaultrate); 3092 splx(s); 3093 3094 cn_tab = &sio_consdev; 3095 return (0); 3096} 3097 3098int 3099siogdbattach(port, speed) 3100 int port; 3101 int speed; 3102{ 3103 int s; 3104 u_char cfcr; 3105 struct siocnstate sp; 3106 3107 siogdbiobase = port; 3108 gdbdefaultrate = speed; 3109 3110 s = spltty(); 3111 3112 /* 3113 * Initialize the divisor latch. We can't rely on 3114 * siocnopen() to do this the first time, since it 3115 * avoids writing to the latch if the latch appears 3116 * to have the correct value. Also, if we didn't 3117 * just read the speed from the hardware, then we 3118 * need to set the speed in hardware so that 3119 * switching it later is null. 3120 */ 3121 cfcr = inb(siogdbiobase + com_cfcr); 3122 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 3123 outb(siogdbiobase + com_dlbl, 3124 COMBRD(gdbdefaultrate) & 0xff); 3125 outb(siogdbiobase + com_dlbh, 3126 (u_int) COMBRD(gdbdefaultrate) >> 8); 3127 outb(siogdbiobase + com_cfcr, cfcr); 3128 3129 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 3130 splx(s); 3131 3132 return (0); 3133} 3134 3135#endif 3136 3137static void 3138siocninit(cp) 3139 struct consdev *cp; 3140{ 3141 comconsole = DEV_TO_UNIT(cp->cn_dev); 3142} 3143 3144static int 3145siocncheckc(dev) 3146 dev_t dev; 3147{ 3148 int c; 3149 Port_t iobase; 3150 int s; 3151 struct siocnstate sp; 3152 3153 if (minor(dev) == siogdbunit) 3154 iobase = siogdbiobase; 3155 else 3156 iobase = siocniobase; 3157 s = spltty(); 3158 siocnopen(&sp, iobase, comdefaultrate); 3159 if (inb(iobase + com_lsr) & LSR_RXRDY) 3160 c = inb(iobase + com_data); 3161 else 3162 c = -1; 3163 siocnclose(&sp, iobase); 3164 splx(s); 3165 return (c); 3166} 3167 3168 3169int 3170siocngetc(dev) 3171 dev_t dev; 3172{ 3173 int c; 3174 Port_t iobase; 3175 int s; 3176 struct siocnstate sp; 3177 3178 if (minor(dev) == siogdbunit) 3179 iobase = siogdbiobase; 3180 else 3181 iobase = siocniobase; 3182 s = spltty(); 3183 siocnopen(&sp, iobase, comdefaultrate); 3184 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3185 ; 3186 c = inb(iobase + com_data); 3187 siocnclose(&sp, iobase); 3188 splx(s); 3189 return (c); 3190} 3191 3192void 3193siocnputc(dev, c) 3194 dev_t dev; 3195 int c; 3196{ 3197 int s; 3198 struct siocnstate sp; 3199 Port_t iobase; 3200 3201 if (minor(dev) == siogdbunit) 3202 iobase = siogdbiobase; 3203 else 3204 iobase = siocniobase; 3205 s = spltty(); 3206 siocnopen(&sp, iobase, comdefaultrate); 3207 siocntxwait(iobase); 3208 outb(iobase + com_data, c); 3209 siocnclose(&sp, iobase); 3210 splx(s); 3211} 3212 3213#ifdef __alpha__ 3214int 3215siogdbgetc() 3216{ 3217 int c; 3218 Port_t iobase; 3219 int s; 3220 struct siocnstate sp; 3221 3222 iobase = siogdbiobase; 3223 s = spltty(); 3224 siocnopen(&sp, iobase, gdbdefaultrate); 3225 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3226 ; 3227 c = inb(iobase + com_data); 3228 siocnclose(&sp, iobase); 3229 splx(s); 3230 return (c); 3231} 3232 3233void 3234siogdbputc(c) 3235 int c; 3236{ 3237 int s; 3238 struct siocnstate sp; 3239 3240 s = spltty(); 3241 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 3242 siocntxwait(siogdbiobase); 3243 outb(siogdbiobase + com_data, c); 3244 siocnclose(&sp, siogdbiobase); 3245 splx(s); 3246} 3247#endif 3248 3249DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0); 3250#if NCARD > 0 3251DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0); 3252#endif 3253#if NPCI > 0 3254DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0); 3255#endif 3256