sio.c revision 122844
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 34 * from: i386/isa sio.c,v 1.234 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/sio/sio.c 122844 2003-11-17 07:21:19Z bde $"); 39 40#include "opt_comconsole.h" 41#include "opt_compat.h" 42#include "opt_ddb.h" 43#include "opt_sio.h" 44 45/* 46 * Serial driver, based on 386BSD-0.1 com driver. 47 * Mostly rewritten to use pseudo-DMA. 48 * Works for National Semiconductor NS8250-NS16550AF UARTs. 49 * COM driver, based on HP dca driver. 50 * 51 * Changes for PC-Card integration: 52 * - Added PC-Card driver table and handlers 53 */ 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/bus.h> 57#include <sys/conf.h> 58#include <sys/fcntl.h> 59#include <sys/interrupt.h> 60#include <sys/kernel.h> 61#include <sys/limits.h> 62#include <sys/lock.h> 63#include <sys/malloc.h> 64#include <sys/module.h> 65#include <sys/mutex.h> 66#include <sys/proc.h> 67#include <sys/reboot.h> 68#include <sys/sysctl.h> 69#include <sys/syslog.h> 70#include <sys/tty.h> 71#include <machine/bus_pio.h> 72#include <machine/bus.h> 73#include <sys/rman.h> 74#include <sys/timepps.h> 75#include <sys/uio.h> 76#include <sys/cons.h> 77#if DDB > 0 78#include <ddb/ddb.h> 79#endif 80 81#include <isa/isavar.h> 82 83#include <machine/resource.h> 84 85#include <dev/sio/sioreg.h> 86#include <dev/sio/siovar.h> 87 88#ifdef COM_ESP 89#include <dev/ic/esp.h> 90#endif 91#include <dev/ic/ns16550.h> 92 93#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 94 95#define CALLOUT_MASK 0x80 96#define CONTROL_MASK 0x60 97#define CONTROL_INIT_STATE 0x20 98#define CONTROL_LOCK_STATE 0x40 99#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 100#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \ 101 | ((mynor) & 0x1f)) 102#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \ 103 | ((unit) & 0x1f)) 104 105#ifdef COM_MULTIPORT 106/* checks in flags for multiport and which is multiport "master chip" 107 * for a given card 108 */ 109#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 110#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 111#define COM_NOTAST4(flags) ((flags) & 0x04) 112#else 113#define COM_ISMULTIPORT(flags) (0) 114#endif /* COM_MULTIPORT */ 115 116#define COM_C_IIR_TXRDYBUG 0x80000 117#define COM_CONSOLE(flags) ((flags) & 0x10) 118#define COM_DEBUGGER(flags) ((flags) & 0x80) 119#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 120#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 121#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 122#define COM_LLCONSOLE(flags) ((flags) & 0x40) 123#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 124#define COM_NOFIFO(flags) ((flags) & 0x02) 125#define COM_NOPROBE(flags) ((flags) & 0x40000) 126#define COM_NOSCR(flags) ((flags) & 0x100000) 127#define COM_PPSCTS(flags) ((flags) & 0x10000) 128#define COM_ST16650A(flags) ((flags) & 0x20000) 129#define COM_TI16754(flags) ((flags) & 0x200000) 130 131#define sio_getreg(com, off) \ 132 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 133#define sio_setreg(com, off, value) \ 134 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 135 136/* 137 * com state bits. 138 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 139 * than the other bits so that they can be tested as a group without masking 140 * off the low bits. 141 * 142 * The following com and tty flags correspond closely: 143 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 144 * comstop()) 145 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 146 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 147 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 148 * TS_FLUSH is not used. 149 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 150 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 151 */ 152#define CS_BUSY 0x80 /* output in progress */ 153#define CS_TTGO 0x40 /* output not stopped by XOFF */ 154#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 155#define CS_CHECKMSR 1 /* check of MSR scheduled */ 156#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 157#define CS_DTR_OFF 0x10 /* DTR held off */ 158#define CS_ODONE 4 /* output completed */ 159#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 160#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 161 162static char const * const error_desc[] = { 163#define CE_OVERRUN 0 164 "silo overflow", 165#define CE_INTERRUPT_BUF_OVERFLOW 1 166 "interrupt-level buffer overflow", 167#define CE_TTY_BUF_OVERFLOW 2 168 "tty-level buffer overflow", 169}; 170 171#define CE_NTYPES 3 172#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 173 174/* types. XXX - should be elsewhere */ 175typedef u_int Port_t; /* hardware port */ 176typedef u_char bool_t; /* boolean */ 177 178/* queue of linear buffers */ 179struct lbq { 180 u_char *l_head; /* next char to process */ 181 u_char *l_tail; /* one past the last char to process */ 182 struct lbq *l_next; /* next in queue */ 183 bool_t l_queued; /* nonzero if queued */ 184}; 185 186/* com device structure */ 187struct com_s { 188 u_char state; /* miscellaneous flag bits */ 189 bool_t active_out; /* nonzero if the callout device is open */ 190 u_char cfcr_image; /* copy of value written to CFCR */ 191#ifdef COM_ESP 192 bool_t esp; /* is this unit a hayes esp board? */ 193#endif 194 u_char extra_state; /* more flag bits, separate for order trick */ 195 u_char fifo_image; /* copy of value written to FIFO */ 196 bool_t hasfifo; /* nonzero for 16550 UARTs */ 197 bool_t loses_outints; /* nonzero if device loses output interrupts */ 198 u_char mcr_image; /* copy of value written to MCR */ 199#ifdef COM_MULTIPORT 200 bool_t multiport; /* is this unit part of a multiport device? */ 201#endif /* COM_MULTIPORT */ 202 bool_t no_irq; /* nonzero if irq is not attached */ 203 bool_t gone; /* hardware disappeared */ 204 bool_t poll; /* nonzero if polling is required */ 205 bool_t poll_output; /* nonzero if polling for output is required */ 206 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 207 int unit; /* unit number */ 208 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 209 u_int flags; /* copy of device flags */ 210 u_int tx_fifo_size; 211 u_int wopeners; /* # processes waiting for DCD in open() */ 212 213 /* 214 * The high level of the driver never reads status registers directly 215 * because there would be too many side effects to handle conveniently. 216 * Instead, it reads copies of the registers stored here by the 217 * interrupt handler. 218 */ 219 u_char last_modem_status; /* last MSR read by intr handler */ 220 u_char prev_modem_status; /* last MSR handled by high level */ 221 222 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 223 u_char *ibuf; /* start of input buffer */ 224 u_char *ibufend; /* end of input buffer */ 225 u_char *ibufold; /* old input buffer, to be freed */ 226 u_char *ihighwater; /* threshold in input buffer */ 227 u_char *iptr; /* next free spot in input buffer */ 228 int ibufsize; /* size of ibuf (not include error bytes) */ 229 int ierroff; /* offset of error bytes in ibuf */ 230 231 struct lbq obufq; /* head of queue of output buffers */ 232 struct lbq obufs[2]; /* output buffers */ 233 234 bus_space_tag_t bst; 235 bus_space_handle_t bsh; 236 237 Port_t data_port; /* i/o ports */ 238#ifdef COM_ESP 239 Port_t esp_port; 240#endif 241 Port_t int_ctl_port; 242 Port_t int_id_port; 243 Port_t modem_ctl_port; 244 Port_t line_status_port; 245 Port_t modem_status_port; 246 247 struct tty *tp; /* cross reference */ 248 249 /* Initial state. */ 250 struct termios it_in; /* should be in struct tty */ 251 struct termios it_out; 252 253 /* Lock state. */ 254 struct termios lt_in; /* should be in struct tty */ 255 struct termios lt_out; 256 257 bool_t do_timestamp; 258 bool_t do_dcd_timestamp; 259 struct timeval timestamp; 260 struct timeval dcd_timestamp; 261 struct pps_state pps; 262 int pps_bit; 263#ifdef ALT_BREAK_TO_DEBUGGER 264 int alt_brk_state; 265#endif 266 267 u_long bytes_in; /* statistics */ 268 u_long bytes_out; 269 u_int delta_error_counts[CE_NTYPES]; 270 u_long error_counts[CE_NTYPES]; 271 272 u_long rclk; 273 274 struct resource *irqres; 275 struct resource *ioportres; 276 int ioportrid; 277 void *cookie; 278 dev_t devs[6]; 279 280 /* 281 * Data area for output buffers. Someday we should build the output 282 * buffer queue without copying data. 283 */ 284 u_char obuf1[256]; 285 u_char obuf2[256]; 286}; 287 288#ifdef COM_ESP 289static int espattach(struct com_s *com, Port_t esp_port); 290#endif 291 292static timeout_t siobusycheck; 293static u_int siodivisor(u_long rclk, speed_t speed); 294static timeout_t siodtrwakeup; 295static void comhardclose(struct com_s *com); 296static void sioinput(struct com_s *com); 297static void siointr1(struct com_s *com); 298static void siointr(void *arg); 299static int commctl(struct com_s *com, int bits, int how); 300static int comparam(struct tty *tp, struct termios *t); 301static void siopoll(void *); 302static void siosettimeout(void); 303static int siosetwater(struct com_s *com, speed_t speed); 304static void comstart(struct tty *tp); 305static void comstop(struct tty *tp, int rw); 306static timeout_t comwakeup; 307static void disc_optim(struct tty *tp, struct termios *t, 308 struct com_s *com); 309 310char sio_driver_name[] = "sio"; 311static struct mtx sio_lock; 312static int sio_inited; 313 314/* table and macro for fast conversion from a unit number to its com struct */ 315devclass_t sio_devclass; 316#define com_addr(unit) ((struct com_s *) \ 317 devclass_get_softc(sio_devclass, unit)) /* XXX */ 318 319static d_open_t sioopen; 320static d_close_t sioclose; 321static d_read_t sioread; 322static d_write_t siowrite; 323static d_ioctl_t sioioctl; 324 325#define CDEV_MAJOR 28 326static struct cdevsw sio_cdevsw = { 327 .d_open = sioopen, 328 .d_close = sioclose, 329 .d_read = sioread, 330 .d_write = siowrite, 331 .d_ioctl = sioioctl, 332 .d_poll = ttypoll, 333 .d_name = sio_driver_name, 334 .d_maj = CDEV_MAJOR, 335 .d_flags = D_TTY, 336 .d_kqfilter = ttykqfilter, 337}; 338 339int comconsole = -1; 340static volatile speed_t comdefaultrate = CONSPEED; 341static u_long comdefaultrclk = DEFAULT_RCLK; 342SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 343static speed_t gdbdefaultrate = GDBSPEED; 344SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 345 &gdbdefaultrate, GDBSPEED, ""); 346static u_int com_events; /* input chars + weighted output completions */ 347static Port_t siocniobase; 348static int siocnunit = -1; 349static Port_t siogdbiobase; 350static int siogdbunit = -1; 351static void *sio_slow_ih; 352static void *sio_fast_ih; 353static int sio_timeout; 354static int sio_timeouts_until_log; 355static struct callout_handle sio_timeout_handle 356 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 357static int sio_numunits; 358 359#ifdef COM_ESP 360/* XXX configure this properly. */ 361/* XXX quite broken for new-bus. */ 362static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 363static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 364#endif 365 366/* 367 * handle sysctl read/write requests for console speed 368 * 369 * In addition to setting comdefaultrate for I/O through /dev/console, 370 * also set the initial and lock values for the /dev/ttyXX device 371 * if there is one associated with the console. Finally, if the /dev/tty 372 * device has already been open, change the speed on the open running port 373 * itself. 374 */ 375 376static int 377sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 378{ 379 int error, s; 380 speed_t newspeed; 381 struct com_s *com; 382 struct tty *tp; 383 384 newspeed = comdefaultrate; 385 386 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 387 if (error || !req->newptr) 388 return (error); 389 390 comdefaultrate = newspeed; 391 392 if (comconsole < 0) /* serial console not selected? */ 393 return (0); 394 395 com = com_addr(comconsole); 396 if (com == NULL) 397 return (ENXIO); 398 399 /* 400 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 401 * (note, the lock rates really are boolean -- if non-zero, disallow 402 * speed changes) 403 */ 404 com->it_in.c_ispeed = com->it_in.c_ospeed = 405 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 406 com->it_out.c_ispeed = com->it_out.c_ospeed = 407 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 408 409 /* 410 * if we're open, change the running rate too 411 */ 412 tp = com->tp; 413 if (tp && (tp->t_state & TS_ISOPEN)) { 414 tp->t_termios.c_ispeed = 415 tp->t_termios.c_ospeed = comdefaultrate; 416 s = spltty(); 417 error = comparam(tp, &tp->t_termios); 418 splx(s); 419 } 420 return error; 421} 422 423SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 424 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 425/* TUNABLE_INT("machdep.conspeed", &comdefaultrate); */ 426 427#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 428#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 429 430/* 431 * Unload the driver and clear the table. 432 * XXX this is mostly wrong. 433 * XXX TODO: 434 * This is usually called when the card is ejected, but 435 * can be caused by a kldunload of a controller driver. 436 * The idea is to reset the driver's view of the device 437 * and ensure that any driver entry points such as 438 * read and write do not hang. 439 */ 440int 441siodetach(dev) 442 device_t dev; 443{ 444 struct com_s *com; 445 int i; 446 447 com = (struct com_s *) device_get_softc(dev); 448 if (com == NULL) { 449 device_printf(dev, "NULL com in siounload\n"); 450 return (0); 451 } 452 com->gone = TRUE; 453 for (i = 0 ; i < 6; i++) 454 destroy_dev(com->devs[i]); 455 if (com->irqres) { 456 bus_teardown_intr(dev, com->irqres, com->cookie); 457 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 458 } 459 if (com->ioportres) 460 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 461 com->ioportres); 462 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 463 device_printf(dev, "still open, forcing close\n"); 464 (*linesw[com->tp->t_line].l_close)(com->tp, 0); 465 com->tp->t_gen++; 466 ttyclose(com->tp); 467 ttwakeup(com->tp); 468 ttwwakeup(com->tp); 469 } else { 470 if (com->ibuf != NULL) 471 free(com->ibuf, M_DEVBUF); 472 device_set_softc(dev, NULL); 473 free(com, M_DEVBUF); 474 } 475 return (0); 476} 477 478int 479sioprobe(dev, xrid, rclk, noprobe) 480 device_t dev; 481 int xrid; 482 u_long rclk; 483 int noprobe; 484{ 485#if 0 486 static bool_t already_init; 487 device_t xdev; 488#endif 489 struct com_s *com; 490 u_int divisor; 491 bool_t failures[10]; 492 int fn; 493 device_t idev; 494 Port_t iobase; 495 intrmask_t irqmap[4]; 496 intrmask_t irqs; 497 u_char mcr_image; 498 int result; 499 u_long xirq; 500 u_int flags = device_get_flags(dev); 501 int rid; 502 struct resource *port; 503 504 rid = xrid; 505 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 506 0, ~0, IO_COMSIZE, RF_ACTIVE); 507 if (!port) 508 return (ENXIO); 509 510 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 511 if (com == NULL) 512 return (ENOMEM); 513 device_set_softc(dev, com); 514 com->bst = rman_get_bustag(port); 515 com->bsh = rman_get_bushandle(port); 516 if (rclk == 0) 517 rclk = DEFAULT_RCLK; 518 com->rclk = rclk; 519 520 while (sio_inited != 2) 521 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 522 mtx_init(&sio_lock, sio_driver_name, NULL, 523 (comconsole != -1) ? 524 MTX_SPIN | MTX_QUIET : MTX_SPIN); 525 atomic_store_rel_int(&sio_inited, 2); 526 } 527 528#if 0 529 /* 530 * XXX this is broken - when we are first called, there are no 531 * previously configured IO ports. We could hard code 532 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 533 * This code has been doing nothing since the conversion since 534 * "count" is zero the first time around. 535 */ 536 if (!already_init) { 537 /* 538 * Turn off MCR_IENABLE for all likely serial ports. An unused 539 * port with its MCR_IENABLE gate open will inhibit interrupts 540 * from any used port that shares the interrupt vector. 541 * XXX the gate enable is elsewhere for some multiports. 542 */ 543 device_t *devs; 544 int count, i, xioport; 545 546 devclass_get_devices(sio_devclass, &devs, &count); 547 for (i = 0; i < count; i++) { 548 xdev = devs[i]; 549 if (device_is_enabled(xdev) && 550 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 551 NULL) == 0) 552 outb(xioport + com_mcr, 0); 553 } 554 free(devs, M_TEMP); 555 already_init = TRUE; 556 } 557#endif 558 559 if (COM_LLCONSOLE(flags)) { 560 printf("sio%d: reserved for low-level i/o\n", 561 device_get_unit(dev)); 562 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 563 device_set_softc(dev, NULL); 564 free(com, M_DEVBUF); 565 return (ENXIO); 566 } 567 568 /* 569 * If the device is on a multiport card and has an AST/4 570 * compatible interrupt control register, initialize this 571 * register and prepare to leave MCR_IENABLE clear in the mcr. 572 * Otherwise, prepare to set MCR_IENABLE in the mcr. 573 * Point idev to the device struct giving the correct id_irq. 574 * This is the struct for the master device if there is one. 575 */ 576 idev = dev; 577 mcr_image = MCR_IENABLE; 578#ifdef COM_MULTIPORT 579 if (COM_ISMULTIPORT(flags)) { 580 Port_t xiobase; 581 u_long io; 582 583 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 584 if (idev == NULL) { 585 printf("sio%d: master device %d not configured\n", 586 device_get_unit(dev), COM_MPMASTER(flags)); 587 idev = dev; 588 } 589 if (!COM_NOTAST4(flags)) { 590 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 591 NULL) == 0) { 592 xiobase = io; 593 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 594 NULL, NULL) == 0) 595 outb(xiobase + com_scr, 0x80); 596 else 597 outb(xiobase + com_scr, 0); 598 } 599 mcr_image = 0; 600 } 601 } 602#endif /* COM_MULTIPORT */ 603 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 604 mcr_image = 0; 605 606 bzero(failures, sizeof failures); 607 iobase = rman_get_start(port); 608 609 /* 610 * We don't want to get actual interrupts, just masked ones. 611 * Interrupts from this line should already be masked in the ICU, 612 * but mask them in the processor as well in case there are some 613 * (misconfigured) shared interrupts. 614 */ 615 mtx_lock_spin(&sio_lock); 616/* EXTRA DELAY? */ 617 618 /* 619 * For the TI16754 chips, set prescaler to 1 (4 is often the 620 * default after-reset value) as otherwise it's impossible to 621 * get highest baudrates. 622 */ 623 if (COM_TI16754(flags)) { 624 u_char cfcr, efr; 625 626 cfcr = sio_getreg(com, com_cfcr); 627 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 628 efr = sio_getreg(com, com_efr); 629 /* Unlock extended features to turn off prescaler. */ 630 sio_setreg(com, com_efr, efr | EFR_EFE); 631 /* Disable EFR. */ 632 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0); 633 /* Turn off prescaler. */ 634 sio_setreg(com, com_mcr, 635 sio_getreg(com, com_mcr) & ~MCR_PRESCALE); 636 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 637 sio_setreg(com, com_efr, efr); 638 sio_setreg(com, com_cfcr, cfcr); 639 } 640 641 /* 642 * Initialize the speed and the word size and wait long enough to 643 * drain the maximum of 16 bytes of junk in device output queues. 644 * The speed is undefined after a master reset and must be set 645 * before relying on anything related to output. There may be 646 * junk after a (very fast) soft reboot and (apparently) after 647 * master reset. 648 * XXX what about the UART bug avoided by waiting in comparam()? 649 * We don't want to to wait long enough to drain at 2 bps. 650 */ 651 if (iobase == siocniobase) 652 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 653 else { 654 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 655 divisor = siodivisor(rclk, SIO_TEST_SPEED); 656 sio_setreg(com, com_dlbl, divisor & 0xff); 657 sio_setreg(com, com_dlbh, divisor >> 8); 658 sio_setreg(com, com_cfcr, CFCR_8BITS); 659 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 660 } 661 662 /* 663 * Enable the interrupt gate and disable device interupts. This 664 * should leave the device driving the interrupt line low and 665 * guarantee an edge trigger if an interrupt can be generated. 666 */ 667/* EXTRA DELAY? */ 668 sio_setreg(com, com_mcr, mcr_image); 669 sio_setreg(com, com_ier, 0); 670 DELAY(1000); /* XXX */ 671 irqmap[0] = isa_irq_pending(); 672 673 /* 674 * Attempt to set loopback mode so that we can send a null byte 675 * without annoying any external device. 676 */ 677/* EXTRA DELAY? */ 678 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 679 680 /* 681 * Attempt to generate an output interrupt. On 8250's, setting 682 * IER_ETXRDY generates an interrupt independent of the current 683 * setting and independent of whether the THR is empty. On 16450's, 684 * setting IER_ETXRDY generates an interrupt independent of the 685 * current setting. On 16550A's, setting IER_ETXRDY only 686 * generates an interrupt when IER_ETXRDY is not already set. 687 */ 688 sio_setreg(com, com_ier, IER_ETXRDY); 689 690 /* 691 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 692 * an interrupt. They'd better generate one for actually doing 693 * output. Loopback may be broken on the same incompatibles but 694 * it's unlikely to do more than allow the null byte out. 695 */ 696 sio_setreg(com, com_data, 0); 697 if (iobase == siocniobase) 698 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 699 else 700 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 701 702 /* 703 * Turn off loopback mode so that the interrupt gate works again 704 * (MCR_IENABLE was hidden). This should leave the device driving 705 * an interrupt line high. It doesn't matter if the interrupt 706 * line oscillates while we are not looking at it, since interrupts 707 * are disabled. 708 */ 709/* EXTRA DELAY? */ 710 sio_setreg(com, com_mcr, mcr_image); 711 712 /* 713 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 714 * to 8 bits *again*, or else probe test 0 will fail. 715 * gwk@sgi.com, 4/19/2001 716 */ 717 sio_setreg(com, com_cfcr, CFCR_8BITS); 718 719 /* 720 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 721 * so we probe for a buggy IIR_TXRDY implementation even in the 722 * noprobe case. We don't probe for it in the !noprobe case because 723 * noprobe is always set for PCMCIA cards and the problem is not 724 * known to affect any other cards. 725 */ 726 if (noprobe) { 727 /* Read IIR a few times. */ 728 for (fn = 0; fn < 2; fn ++) { 729 DELAY(10000); 730 failures[6] = sio_getreg(com, com_iir); 731 } 732 733 /* IIR_TXRDY should be clear. Is it? */ 734 result = 0; 735 if (failures[6] & IIR_TXRDY) { 736 /* 737 * No. We seem to have the bug. Does our fix for 738 * it work? 739 */ 740 sio_setreg(com, com_ier, 0); 741 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 742 /* Yes. We discovered the TXRDY bug! */ 743 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 744 } else { 745 /* No. Just fail. XXX */ 746 result = ENXIO; 747 sio_setreg(com, com_mcr, 0); 748 } 749 } else { 750 /* Yes. No bug. */ 751 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 752 } 753 sio_setreg(com, com_ier, 0); 754 sio_setreg(com, com_cfcr, CFCR_8BITS); 755 mtx_unlock_spin(&sio_lock); 756 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 757 if (iobase == siocniobase) 758 result = 0; 759 if (result != 0) { 760 device_set_softc(dev, NULL); 761 free(com, M_DEVBUF); 762 } 763 return (result); 764 } 765 766 /* 767 * Check that 768 * o the CFCR, IER and MCR in UART hold the values written to them 769 * (the values happen to be all distinct - this is good for 770 * avoiding false positive tests from bus echoes). 771 * o an output interrupt is generated and its vector is correct. 772 * o the interrupt goes away when the IIR in the UART is read. 773 */ 774/* EXTRA DELAY? */ 775 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 776 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 777 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 778 DELAY(10000); /* Some internal modems need this time */ 779 irqmap[1] = isa_irq_pending(); 780 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 781 DELAY(1000); /* XXX */ 782 irqmap[2] = isa_irq_pending(); 783 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 784 785 /* 786 * Turn off all device interrupts and check that they go off properly. 787 * Leave MCR_IENABLE alone. For ports without a master port, it gates 788 * the OUT2 output of the UART to 789 * the ICU input. Closing the gate would give a floating ICU input 790 * (unless there is another device driving it) and spurious interrupts. 791 * (On the system that this was first tested on, the input floats high 792 * and gives a (masked) interrupt as soon as the gate is closed.) 793 */ 794 sio_setreg(com, com_ier, 0); 795 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 796 failures[7] = sio_getreg(com, com_ier); 797 DELAY(1000); /* XXX */ 798 irqmap[3] = isa_irq_pending(); 799 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 800 801 mtx_unlock_spin(&sio_lock); 802 803 irqs = irqmap[1] & ~irqmap[0]; 804 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 805 ((1 << xirq) & irqs) == 0) { 806 printf( 807 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 808 device_get_unit(dev), xirq, irqs); 809 printf( 810 "sio%d: port may not be enabled\n", 811 device_get_unit(dev)); 812 } 813 if (bootverbose) 814 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 815 device_get_unit(dev), 816 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 817 818 result = 0; 819 for (fn = 0; fn < sizeof failures; ++fn) 820 if (failures[fn]) { 821 sio_setreg(com, com_mcr, 0); 822 result = ENXIO; 823 if (bootverbose) { 824 printf("sio%d: probe failed test(s):", 825 device_get_unit(dev)); 826 for (fn = 0; fn < sizeof failures; ++fn) 827 if (failures[fn]) 828 printf(" %d", fn); 829 printf("\n"); 830 } 831 break; 832 } 833 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 834 if (iobase == siocniobase) 835 result = 0; 836 if (result != 0) { 837 device_set_softc(dev, NULL); 838 free(com, M_DEVBUF); 839 } 840 return (result); 841} 842 843#ifdef COM_ESP 844static int 845espattach(com, esp_port) 846 struct com_s *com; 847 Port_t esp_port; 848{ 849 u_char dips; 850 u_char val; 851 852 /* 853 * Check the ESP-specific I/O port to see if we're an ESP 854 * card. If not, return failure immediately. 855 */ 856 if ((inb(esp_port) & 0xf3) == 0) { 857 printf(" port 0x%x is not an ESP board?\n", esp_port); 858 return (0); 859 } 860 861 /* 862 * We've got something that claims to be a Hayes ESP card. 863 * Let's hope so. 864 */ 865 866 /* Get the dip-switch configuration */ 867 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 868 dips = inb(esp_port + ESP_STATUS1); 869 870 /* 871 * Bits 0,1 of dips say which COM port we are. 872 */ 873 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 874 printf(" : ESP"); 875 else { 876 printf(" esp_port has com %d\n", dips & 0x03); 877 return (0); 878 } 879 880 /* 881 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 882 */ 883 outb(esp_port + ESP_CMD1, ESP_GETTEST); 884 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 885 val = inb(esp_port + ESP_STATUS2); 886 if ((val & 0x70) < 0x20) { 887 printf("-old (%o)", val & 0x70); 888 return (0); 889 } 890 891 /* 892 * Check for ability to emulate 16550: bit 7 == 1 893 */ 894 if ((dips & 0x80) == 0) { 895 printf(" slave"); 896 return (0); 897 } 898 899 /* 900 * Okay, we seem to be a Hayes ESP card. Whee. 901 */ 902 com->esp = TRUE; 903 com->esp_port = esp_port; 904 return (1); 905} 906#endif /* COM_ESP */ 907 908int 909sioattach(dev, xrid, rclk) 910 device_t dev; 911 int xrid; 912 u_long rclk; 913{ 914 struct com_s *com; 915#ifdef COM_ESP 916 Port_t *espp; 917#endif 918 Port_t iobase; 919 int minorbase; 920 int unit; 921 u_int flags; 922 int rid; 923 struct resource *port; 924 int ret; 925 926 rid = xrid; 927 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 928 0, ~0, IO_COMSIZE, RF_ACTIVE); 929 if (!port) 930 return (ENXIO); 931 932 iobase = rman_get_start(port); 933 unit = device_get_unit(dev); 934 com = device_get_softc(dev); 935 flags = device_get_flags(dev); 936 937 if (unit >= sio_numunits) 938 sio_numunits = unit + 1; 939 /* 940 * sioprobe() has initialized the device registers as follows: 941 * o cfcr = CFCR_8BITS. 942 * It is most important that CFCR_DLAB is off, so that the 943 * data port is not hidden when we enable interrupts. 944 * o ier = 0. 945 * Interrupts are only enabled when the line is open. 946 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 947 * interrupt control register or the config specifies no irq. 948 * Keeping MCR_DTR and MCR_RTS off might stop the external 949 * device from sending before we are ready. 950 */ 951 bzero(com, sizeof *com); 952 com->unit = unit; 953 com->ioportres = port; 954 com->ioportrid = rid; 955 com->bst = rman_get_bustag(port); 956 com->bsh = rman_get_bushandle(port); 957 com->cfcr_image = CFCR_8BITS; 958 com->dtr_wait = 3 * hz; 959 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 960 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 961 com->tx_fifo_size = 1; 962 com->obufs[0].l_head = com->obuf1; 963 com->obufs[1].l_head = com->obuf2; 964 965 com->data_port = iobase + com_data; 966 com->int_ctl_port = iobase + com_ier; 967 com->int_id_port = iobase + com_iir; 968 com->modem_ctl_port = iobase + com_mcr; 969 com->mcr_image = inb(com->modem_ctl_port); 970 com->line_status_port = iobase + com_lsr; 971 com->modem_status_port = iobase + com_msr; 972 973 if (rclk == 0) 974 rclk = DEFAULT_RCLK; 975 com->rclk = rclk; 976 977 /* 978 * We don't use all the flags from <sys/ttydefaults.h> since they 979 * are only relevant for logins. It's important to have echo off 980 * initially so that the line doesn't start blathering before the 981 * echo flag can be turned off. 982 */ 983 com->it_in.c_iflag = 0; 984 com->it_in.c_oflag = 0; 985 com->it_in.c_cflag = TTYDEF_CFLAG; 986 com->it_in.c_lflag = 0; 987 if (unit == comconsole) { 988 com->it_in.c_iflag = TTYDEF_IFLAG; 989 com->it_in.c_oflag = TTYDEF_OFLAG; 990 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 991 com->it_in.c_lflag = TTYDEF_LFLAG; 992 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 993 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 994 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 995 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 996 } else 997 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 998 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 999 mtx_unlock_spin(&sio_lock); 1000 /* 1001 * Leave i/o resources allocated if this is a `cn'-level 1002 * console, so that other devices can't snarf them. 1003 */ 1004 if (iobase != siocniobase) 1005 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1006 return (ENOMEM); 1007 } 1008 mtx_unlock_spin(&sio_lock); 1009 termioschars(&com->it_in); 1010 com->it_out = com->it_in; 1011 1012 /* attempt to determine UART type */ 1013 printf("sio%d: type", unit); 1014 1015 1016 if (!COM_ISMULTIPORT(flags) && 1017 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1018 u_char scr; 1019 u_char scr1; 1020 u_char scr2; 1021 1022 scr = sio_getreg(com, com_scr); 1023 sio_setreg(com, com_scr, 0xa5); 1024 scr1 = sio_getreg(com, com_scr); 1025 sio_setreg(com, com_scr, 0x5a); 1026 scr2 = sio_getreg(com, com_scr); 1027 sio_setreg(com, com_scr, scr); 1028 if (scr1 != 0xa5 || scr2 != 0x5a) { 1029 printf(" 8250 or not responding"); 1030 goto determined_type; 1031 } 1032 } 1033 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1034 DELAY(100); 1035 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1036 case FIFO_RX_LOW: 1037 printf(" 16450"); 1038 break; 1039 case FIFO_RX_MEDL: 1040 printf(" 16450?"); 1041 break; 1042 case FIFO_RX_MEDH: 1043 printf(" 16550?"); 1044 break; 1045 case FIFO_RX_HIGH: 1046 if (COM_NOFIFO(flags)) { 1047 printf(" 16550A fifo disabled"); 1048 break; 1049 } 1050 com->hasfifo = TRUE; 1051 if (COM_ST16650A(flags)) { 1052 printf(" ST16650A"); 1053 com->st16650a = TRUE; 1054 com->tx_fifo_size = 32; 1055 break; 1056 } 1057 if (COM_TI16754(flags)) { 1058 printf(" TI16754"); 1059 com->tx_fifo_size = 64; 1060 break; 1061 } 1062 printf(" 16550A"); 1063#ifdef COM_ESP 1064 for (espp = likely_esp_ports; *espp != 0; espp++) 1065 if (espattach(com, *espp)) { 1066 com->tx_fifo_size = 1024; 1067 break; 1068 } 1069 if (com->esp != NULL) 1070 break; 1071#endif 1072 com->tx_fifo_size = COM_FIFOSIZE(flags); 1073 if (com->tx_fifo_size == 0) 1074 com->tx_fifo_size = 16; 1075 else 1076 printf(" lookalike with %u bytes FIFO", 1077 com->tx_fifo_size); 1078 break; 1079 } 1080#ifdef COM_ESP 1081 if (com->esp != NULL) { 1082 /* 1083 * Set 16550 compatibility mode. 1084 * We don't use the ESP_MODE_SCALE bit to increase the 1085 * fifo trigger levels because we can't handle large 1086 * bursts of input. 1087 * XXX flow control should be set in comparam(), not here. 1088 */ 1089 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1090 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1091 1092 /* Set RTS/CTS flow control. */ 1093 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1094 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1095 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1096 1097 /* Set flow-control levels. */ 1098 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1099 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1100 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1101 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1102 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1103 } 1104#endif /* COM_ESP */ 1105 sio_setreg(com, com_fifo, 0); 1106determined_type: ; 1107 1108#ifdef COM_MULTIPORT 1109 if (COM_ISMULTIPORT(flags)) { 1110 device_t masterdev; 1111 1112 com->multiport = TRUE; 1113 printf(" (multiport"); 1114 if (unit == COM_MPMASTER(flags)) 1115 printf(" master"); 1116 printf(")"); 1117 masterdev = devclass_get_device(sio_devclass, 1118 COM_MPMASTER(flags)); 1119 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1120 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1121 } 1122#endif /* COM_MULTIPORT */ 1123 if (unit == comconsole) 1124 printf(", console"); 1125 if (COM_IIR_TXRDYBUG(flags)) 1126 printf(" with a buggy IIR_TXRDY implementation"); 1127 printf("\n"); 1128 1129 if (sio_fast_ih == NULL) { 1130 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1131 &sio_fast_ih); 1132 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1133 &sio_slow_ih); 1134 } 1135 minorbase = UNIT_TO_MINOR(unit); 1136 com->devs[0] = make_dev(&sio_cdevsw, minorbase, 1137 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1138 com->devs[1] = make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE, 1139 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1140 com->devs[2] = make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE, 1141 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1142 com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK, 1143 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1144 com->devs[4] = make_dev(&sio_cdevsw, 1145 minorbase | CALLOUT_MASK | CONTROL_INIT_STATE, 1146 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1147 com->devs[5] = make_dev(&sio_cdevsw, 1148 minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE, 1149 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1150 for (rid = 0; rid < 6; rid++) 1151 com->devs[rid]->si_drv1 = com; 1152 com->flags = flags; 1153 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1154 1155 if (COM_PPSCTS(flags)) 1156 com->pps_bit = MSR_CTS; 1157 else 1158 com->pps_bit = MSR_DCD; 1159 pps_init(&com->pps); 1160 1161 rid = 0; 1162 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1163 RF_ACTIVE); 1164 if (com->irqres) { 1165 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1166 INTR_TYPE_TTY | INTR_FAST, 1167 siointr, com, &com->cookie); 1168 if (ret) { 1169 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1170 com->irqres, INTR_TYPE_TTY, 1171 siointr, com, &com->cookie); 1172 if (ret == 0) 1173 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1174 } 1175 if (ret) 1176 device_printf(dev, "could not activate interrupt\n"); 1177#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1178 defined(ALT_BREAK_TO_DEBUGGER)) 1179 /* 1180 * Enable interrupts for early break-to-debugger support 1181 * on the console. 1182 */ 1183 if (ret == 0 && unit == comconsole) 1184 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1185 IER_EMSC); 1186#endif 1187 } 1188 1189 return (0); 1190} 1191 1192static int 1193sioopen(dev, flag, mode, td) 1194 dev_t dev; 1195 int flag; 1196 int mode; 1197 struct thread *td; 1198{ 1199 struct com_s *com; 1200 int error; 1201 int mynor; 1202 int s; 1203 struct tty *tp; 1204 int unit; 1205 1206 mynor = minor(dev); 1207 unit = MINOR_TO_UNIT(mynor); 1208 com = com_addr(unit); 1209 if (com == NULL) 1210 return (ENXIO); 1211 if (com->gone) 1212 return (ENXIO); 1213 if (mynor & CONTROL_MASK) 1214 return (0); 1215 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1216 s = spltty(); 1217 /* 1218 * We jump to this label after all non-interrupted sleeps to pick 1219 * up any changes of the device state. 1220 */ 1221open_top: 1222 while (com->state & CS_DTR_OFF) { 1223 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1224 if (com_addr(unit) == NULL) 1225 return (ENXIO); 1226 if (error != 0 || com->gone) 1227 goto out; 1228 } 1229 if (tp->t_state & TS_ISOPEN) { 1230 /* 1231 * The device is open, so everything has been initialized. 1232 * Handle conflicts. 1233 */ 1234 if (mynor & CALLOUT_MASK) { 1235 if (!com->active_out) { 1236 error = EBUSY; 1237 goto out; 1238 } 1239 } else { 1240 if (com->active_out) { 1241 if (flag & O_NONBLOCK) { 1242 error = EBUSY; 1243 goto out; 1244 } 1245 error = tsleep(&com->active_out, 1246 TTIPRI | PCATCH, "siobi", 0); 1247 if (com_addr(unit) == NULL) 1248 return (ENXIO); 1249 if (error != 0 || com->gone) 1250 goto out; 1251 goto open_top; 1252 } 1253 } 1254 if (tp->t_state & TS_XCLUDE && 1255 suser(td)) { 1256 error = EBUSY; 1257 goto out; 1258 } 1259 } else { 1260 /* 1261 * The device isn't open, so there are no conflicts. 1262 * Initialize it. Initialization is done twice in many 1263 * cases: to preempt sleeping callin opens if we are 1264 * callout, and to complete a callin open after DCD rises. 1265 */ 1266 tp->t_oproc = comstart; 1267 tp->t_param = comparam; 1268 tp->t_stop = comstop; 1269 tp->t_dev = dev; 1270 tp->t_termios = mynor & CALLOUT_MASK 1271 ? com->it_out : com->it_in; 1272 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1273 com->poll = com->no_irq; 1274 com->poll_output = com->loses_outints; 1275 ++com->wopeners; 1276 error = comparam(tp, &tp->t_termios); 1277 --com->wopeners; 1278 if (error != 0) 1279 goto out; 1280 /* 1281 * XXX we should goto open_top if comparam() slept. 1282 */ 1283 if (com->hasfifo) { 1284 int i; 1285 /* 1286 * (Re)enable and drain fifos. 1287 * 1288 * Certain SMC chips cause problems if the fifos 1289 * are enabled while input is ready. Turn off the 1290 * fifo if necessary to clear the input. We test 1291 * the input ready bit after enabling the fifos 1292 * since we've already enabled them in comparam() 1293 * and to handle races between enabling and fresh 1294 * input. 1295 */ 1296 for (i = 0; i < 500; i++) { 1297 sio_setreg(com, com_fifo, 1298 FIFO_RCV_RST | FIFO_XMT_RST 1299 | com->fifo_image); 1300 /* 1301 * XXX the delays are for superstitious 1302 * historical reasons. It must be less than 1303 * the character time at the maximum 1304 * supported speed (87 usec at 115200 bps 1305 * 8N1). Otherwise we might loop endlessly 1306 * if data is streaming in. We used to use 1307 * delays of 100. That usually worked 1308 * because DELAY(100) used to usually delay 1309 * for about 85 usec instead of 100. 1310 */ 1311 DELAY(50); 1312 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1313 break; 1314 sio_setreg(com, com_fifo, 0); 1315 DELAY(50); 1316 (void) inb(com->data_port); 1317 } 1318 if (i == 500) { 1319 error = EIO; 1320 goto out; 1321 } 1322 } 1323 1324 mtx_lock_spin(&sio_lock); 1325 (void) inb(com->line_status_port); 1326 (void) inb(com->data_port); 1327 com->prev_modem_status = com->last_modem_status 1328 = inb(com->modem_status_port); 1329 outb(com->int_ctl_port, 1330 IER_ERXRDY | IER_ERLS | IER_EMSC 1331 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 1332 mtx_unlock_spin(&sio_lock); 1333 /* 1334 * Handle initial DCD. Callout devices get a fake initial 1335 * DCD (trapdoor DCD). If we are callout, then any sleeping 1336 * callin opens get woken up and resume sleeping on "siobi" 1337 * instead of "siodcd". 1338 */ 1339 /* 1340 * XXX `mynor & CALLOUT_MASK' should be 1341 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 1342 * TRAPDOOR_CARRIER is the default initial state for callout 1343 * devices and SOFT_CARRIER is like CLOCAL except it hides 1344 * the true carrier. 1345 */ 1346 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 1347 (*linesw[tp->t_line].l_modem)(tp, 1); 1348 } 1349 /* 1350 * Wait for DCD if necessary. 1351 */ 1352 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 1353 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 1354 ++com->wopeners; 1355 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 1356 if (com_addr(unit) == NULL) 1357 return (ENXIO); 1358 --com->wopeners; 1359 if (error != 0 || com->gone) 1360 goto out; 1361 goto open_top; 1362 } 1363 error = (*linesw[tp->t_line].l_open)(dev, tp); 1364 disc_optim(tp, &tp->t_termios, com); 1365 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 1366 com->active_out = TRUE; 1367 siosettimeout(); 1368out: 1369 splx(s); 1370 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 1371 comhardclose(com); 1372 return (error); 1373} 1374 1375static int 1376sioclose(dev, flag, mode, td) 1377 dev_t dev; 1378 int flag; 1379 int mode; 1380 struct thread *td; 1381{ 1382 struct com_s *com; 1383 int mynor; 1384 int s; 1385 struct tty *tp; 1386 1387 mynor = minor(dev); 1388 if (mynor & CONTROL_MASK) 1389 return (0); 1390 com = com_addr(MINOR_TO_UNIT(mynor)); 1391 if (com == NULL) 1392 return (ENODEV); 1393 tp = com->tp; 1394 s = spltty(); 1395 (*linesw[tp->t_line].l_close)(tp, flag); 1396 disc_optim(tp, &tp->t_termios, com); 1397 comstop(tp, FREAD | FWRITE); 1398 comhardclose(com); 1399 ttyclose(tp); 1400 siosettimeout(); 1401 splx(s); 1402 if (com->gone) { 1403 printf("sio%d: gone\n", com->unit); 1404 s = spltty(); 1405 if (com->ibuf != NULL) 1406 free(com->ibuf, M_DEVBUF); 1407 bzero(tp, sizeof *tp); 1408 splx(s); 1409 } 1410 return (0); 1411} 1412 1413static void 1414comhardclose(com) 1415 struct com_s *com; 1416{ 1417 int s; 1418 struct tty *tp; 1419 1420 s = spltty(); 1421 com->poll = FALSE; 1422 com->poll_output = FALSE; 1423 com->do_timestamp = FALSE; 1424 com->do_dcd_timestamp = FALSE; 1425 com->pps.ppsparam.mode = 0; 1426 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1427 tp = com->tp; 1428 1429#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1430 defined(ALT_BREAK_TO_DEBUGGER)) 1431 /* 1432 * Leave interrupts enabled and don't clear DTR if this is the 1433 * console. This allows us to detect break-to-debugger events 1434 * while the console device is closed. 1435 */ 1436 if (com->unit != comconsole) 1437#endif 1438 { 1439 sio_setreg(com, com_ier, 0); 1440 if (tp->t_cflag & HUPCL 1441 /* 1442 * XXX we will miss any carrier drop between here and the 1443 * next open. Perhaps we should watch DCD even when the 1444 * port is closed; it is not sufficient to check it at 1445 * the next open because it might go up and down while 1446 * we're not watching. 1447 */ 1448 || (!com->active_out 1449 && !(com->prev_modem_status & MSR_DCD) 1450 && !(com->it_in.c_cflag & CLOCAL)) 1451 || !(tp->t_state & TS_ISOPEN)) { 1452 (void)commctl(com, TIOCM_DTR, DMBIC); 1453 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 1454 timeout(siodtrwakeup, com, com->dtr_wait); 1455 com->state |= CS_DTR_OFF; 1456 } 1457 } 1458 } 1459 if (com->hasfifo) { 1460 /* 1461 * Disable fifos so that they are off after controlled 1462 * reboots. Some BIOSes fail to detect 16550s when the 1463 * fifos are enabled. 1464 */ 1465 sio_setreg(com, com_fifo, 0); 1466 } 1467 com->active_out = FALSE; 1468 wakeup(&com->active_out); 1469 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1470 splx(s); 1471} 1472 1473static int 1474sioread(dev, uio, flag) 1475 dev_t dev; 1476 struct uio *uio; 1477 int flag; 1478{ 1479 int mynor; 1480 struct com_s *com; 1481 1482 mynor = minor(dev); 1483 if (mynor & CONTROL_MASK) 1484 return (ENODEV); 1485 com = com_addr(MINOR_TO_UNIT(mynor)); 1486 if (com == NULL || com->gone) 1487 return (ENODEV); 1488 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 1489} 1490 1491static int 1492siowrite(dev, uio, flag) 1493 dev_t dev; 1494 struct uio *uio; 1495 int flag; 1496{ 1497 int mynor; 1498 struct com_s *com; 1499 int unit; 1500 1501 mynor = minor(dev); 1502 if (mynor & CONTROL_MASK) 1503 return (ENODEV); 1504 1505 unit = MINOR_TO_UNIT(mynor); 1506 com = com_addr(unit); 1507 if (com == NULL || com->gone) 1508 return (ENODEV); 1509 /* 1510 * (XXX) We disallow virtual consoles if the physical console is 1511 * a serial port. This is in case there is a display attached that 1512 * is not the console. In that situation we don't need/want the X 1513 * server taking over the console. 1514 */ 1515 if (constty != NULL && unit == comconsole) 1516 constty = NULL; 1517 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 1518} 1519 1520static void 1521siobusycheck(chan) 1522 void *chan; 1523{ 1524 struct com_s *com; 1525 int s; 1526 1527 com = (struct com_s *)chan; 1528 1529 /* 1530 * Clear TS_BUSY if low-level output is complete. 1531 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1532 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1533 * called again. Reading the line status port outside of siointr1() 1534 * is safe because CS_BUSY is clear so there are no output interrupts 1535 * to lose. 1536 */ 1537 s = spltty(); 1538 if (com->state & CS_BUSY) 1539 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1540 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1541 == (LSR_TSRE | LSR_TXRDY)) { 1542 com->tp->t_state &= ~TS_BUSY; 1543 ttwwakeup(com->tp); 1544 com->extra_state &= ~CSE_BUSYCHECK; 1545 } else 1546 timeout(siobusycheck, com, hz / 100); 1547 splx(s); 1548} 1549 1550static u_int 1551siodivisor(rclk, speed) 1552 u_long rclk; 1553 speed_t speed; 1554{ 1555 long actual_speed; 1556 u_int divisor; 1557 int error; 1558 1559 if (speed == 0) 1560 return (0); 1561#if UINT_MAX > (ULONG_MAX - 1) / 8 1562 if (speed > (ULONG_MAX - 1) / 8) 1563 return (0); 1564#endif 1565 divisor = (rclk / (8UL * speed) + 1) / 2; 1566 if (divisor == 0 || divisor >= 65536) 1567 return (0); 1568 actual_speed = rclk / (16UL * divisor); 1569 1570 /* 10 times error in percent: */ 1571 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 1572 1573 /* 3.0% maximum error tolerance: */ 1574 if (error < -30 || error > 30) 1575 return (0); 1576 1577 return (divisor); 1578} 1579 1580static void 1581siodtrwakeup(chan) 1582 void *chan; 1583{ 1584 struct com_s *com; 1585 1586 com = (struct com_s *)chan; 1587 com->state &= ~CS_DTR_OFF; 1588 wakeup(&com->dtr_wait); 1589} 1590 1591/* 1592 * Call this function with the sio_lock mutex held. It will return with the 1593 * lock still held. 1594 */ 1595static void 1596sioinput(com) 1597 struct com_s *com; 1598{ 1599 u_char *buf; 1600 int incc; 1601 u_char line_status; 1602 int recv_data; 1603 struct tty *tp; 1604 1605 buf = com->ibuf; 1606 tp = com->tp; 1607 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1608 com_events -= (com->iptr - com->ibuf); 1609 com->iptr = com->ibuf; 1610 return; 1611 } 1612 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1613 /* 1614 * Avoid the grotesquely inefficient lineswitch routine 1615 * (ttyinput) in "raw" mode. It usually takes about 450 1616 * instructions (that's without canonical processing or echo!). 1617 * slinput is reasonably fast (usually 40 instructions plus 1618 * call overhead). 1619 */ 1620 do { 1621 /* 1622 * This may look odd, but it is using save-and-enable 1623 * semantics instead of the save-and-disable semantics 1624 * that are used everywhere else. 1625 */ 1626 mtx_unlock_spin(&sio_lock); 1627 incc = com->iptr - buf; 1628 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1629 && (com->state & CS_RTS_IFLOW 1630 || tp->t_iflag & IXOFF) 1631 && !(tp->t_state & TS_TBLOCK)) 1632 ttyblock(tp); 1633 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1634 += b_to_q((char *)buf, incc, &tp->t_rawq); 1635 buf += incc; 1636 tk_nin += incc; 1637 tk_rawcc += incc; 1638 tp->t_rawcc += incc; 1639 ttwakeup(tp); 1640 if (tp->t_state & TS_TTSTOP 1641 && (tp->t_iflag & IXANY 1642 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1643 tp->t_state &= ~TS_TTSTOP; 1644 tp->t_lflag &= ~FLUSHO; 1645 comstart(tp); 1646 } 1647 mtx_lock_spin(&sio_lock); 1648 } while (buf < com->iptr); 1649 } else { 1650 do { 1651 /* 1652 * This may look odd, but it is using save-and-enable 1653 * semantics instead of the save-and-disable semantics 1654 * that are used everywhere else. 1655 */ 1656 mtx_unlock_spin(&sio_lock); 1657 line_status = buf[com->ierroff]; 1658 recv_data = *buf++; 1659 if (line_status 1660 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1661 if (line_status & LSR_BI) 1662 recv_data |= TTY_BI; 1663 if (line_status & LSR_FE) 1664 recv_data |= TTY_FE; 1665 if (line_status & LSR_OE) 1666 recv_data |= TTY_OE; 1667 if (line_status & LSR_PE) 1668 recv_data |= TTY_PE; 1669 } 1670 (*linesw[tp->t_line].l_rint)(recv_data, tp); 1671 mtx_lock_spin(&sio_lock); 1672 } while (buf < com->iptr); 1673 } 1674 com_events -= (com->iptr - com->ibuf); 1675 com->iptr = com->ibuf; 1676 1677 /* 1678 * There is now room for another low-level buffer full of input, 1679 * so enable RTS if it is now disabled and there is room in the 1680 * high-level buffer. 1681 */ 1682 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1683 !(tp->t_state & TS_TBLOCK)) 1684 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1685} 1686 1687static void 1688siointr(arg) 1689 void *arg; 1690{ 1691 struct com_s *com; 1692 1693#ifndef COM_MULTIPORT 1694 com = (struct com_s *)arg; 1695 1696 mtx_lock_spin(&sio_lock); 1697 siointr1(com); 1698 mtx_unlock_spin(&sio_lock); 1699#else /* COM_MULTIPORT */ 1700 bool_t possibly_more_intrs; 1701 int unit; 1702 1703 /* 1704 * Loop until there is no activity on any port. This is necessary 1705 * to get an interrupt edge more than to avoid another interrupt. 1706 * If the IRQ signal is just an OR of the IRQ signals from several 1707 * devices, then the edge from one may be lost because another is 1708 * on. 1709 */ 1710 mtx_lock_spin(&sio_lock); 1711 do { 1712 possibly_more_intrs = FALSE; 1713 for (unit = 0; unit < sio_numunits; ++unit) { 1714 com = com_addr(unit); 1715 /* 1716 * XXX COM_LOCK(); 1717 * would it work here, or be counter-productive? 1718 */ 1719 if (com != NULL 1720 && !com->gone 1721 && (inb(com->int_id_port) & IIR_IMASK) 1722 != IIR_NOPEND) { 1723 siointr1(com); 1724 possibly_more_intrs = TRUE; 1725 } 1726 /* XXX COM_UNLOCK(); */ 1727 } 1728 } while (possibly_more_intrs); 1729 mtx_unlock_spin(&sio_lock); 1730#endif /* COM_MULTIPORT */ 1731} 1732 1733static struct timespec siots[8]; 1734static int siotso; 1735static int volatile siotsunit = -1; 1736 1737static int 1738sysctl_siots(SYSCTL_HANDLER_ARGS) 1739{ 1740 char buf[128]; 1741 long long delta; 1742 size_t len; 1743 int error, i, tso; 1744 1745 for (i = 1, tso = siotso; i < tso; i++) { 1746 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 1747 1000000000 + 1748 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 1749 len = sprintf(buf, "%lld\n", delta); 1750 if (delta >= 110000) 1751 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 1752 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 1753 if (i == tso - 1) 1754 buf[len - 1] = '\0'; 1755 error = SYSCTL_OUT(req, buf, len); 1756 if (error != 0) 1757 return (error); 1758 uio_yield(); 1759 } 1760 return (0); 1761} 1762 1763SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 1764 0, 0, sysctl_siots, "A", "sio timestamps"); 1765 1766static void 1767siointr1(com) 1768 struct com_s *com; 1769{ 1770 u_char int_ctl; 1771 u_char int_ctl_new; 1772 u_char line_status; 1773 u_char modem_status; 1774 u_char *ioptr; 1775 u_char recv_data; 1776 1777 if (COM_IIR_TXRDYBUG(com->flags)) { 1778 int_ctl = inb(com->int_ctl_port); 1779 int_ctl_new = int_ctl; 1780 } else { 1781 int_ctl = 0; 1782 int_ctl_new = 0; 1783 } 1784 1785 while (!com->gone) { 1786 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1787 modem_status = inb(com->modem_status_port); 1788 if ((modem_status ^ com->last_modem_status) & 1789 com->pps_bit) { 1790 pps_capture(&com->pps); 1791 pps_event(&com->pps, 1792 (modem_status & com->pps_bit) ? 1793 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1794 } 1795 } 1796 line_status = inb(com->line_status_port); 1797 1798 /* input event? (check first to help avoid overruns) */ 1799 while (line_status & LSR_RCV_MASK) { 1800 /* break/unnattached error bits or real input? */ 1801 if (!(line_status & LSR_RXRDY)) 1802 recv_data = 0; 1803 else 1804 recv_data = inb(com->data_port); 1805#ifdef DDB 1806#ifdef ALT_BREAK_TO_DEBUGGER 1807 if (com->unit == comconsole && 1808 db_alt_break(recv_data, &com->alt_brk_state) != 0) 1809 breakpoint(); 1810#endif /* ALT_BREAK_TO_DEBUGGER */ 1811#endif /* DDB */ 1812 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1813 /* 1814 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1815 * Otherwise, push the work to a higher level 1816 * (to handle PARMRK) if we're bypassing. 1817 * Otherwise, convert BI/FE and PE+INPCK to 0. 1818 * 1819 * This makes bypassing work right in the 1820 * usual "raw" case (IGNBRK set, and IGNPAR 1821 * and INPCK clear). 1822 * 1823 * Note: BI together with FE/PE means just BI. 1824 */ 1825 if (line_status & LSR_BI) { 1826#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 1827 if (com->unit == comconsole) { 1828 breakpoint(); 1829 goto cont; 1830 } 1831#endif 1832 if (com->tp == NULL 1833 || com->tp->t_iflag & IGNBRK) 1834 goto cont; 1835 } else { 1836 if (com->tp == NULL 1837 || com->tp->t_iflag & IGNPAR) 1838 goto cont; 1839 } 1840 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1841 && (line_status & (LSR_BI | LSR_FE) 1842 || com->tp->t_iflag & INPCK)) 1843 recv_data = 0; 1844 } 1845 ++com->bytes_in; 1846 if (com->hotchar != 0 && recv_data == com->hotchar) 1847 swi_sched(sio_fast_ih, 0); 1848 ioptr = com->iptr; 1849 if (ioptr >= com->ibufend) 1850 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1851 else { 1852 if (com->do_timestamp) 1853 microtime(&com->timestamp); 1854 ++com_events; 1855 swi_sched(sio_slow_ih, SWI_DELAY); 1856#if 0 /* for testing input latency vs efficiency */ 1857if (com->iptr - com->ibuf == 8) 1858 swi_sched(sio_fast_ih, 0); 1859#endif 1860 ioptr[0] = recv_data; 1861 ioptr[com->ierroff] = line_status; 1862 com->iptr = ++ioptr; 1863 if (ioptr == com->ihighwater 1864 && com->state & CS_RTS_IFLOW) 1865 outb(com->modem_ctl_port, 1866 com->mcr_image &= ~MCR_RTS); 1867 if (line_status & LSR_OE) 1868 CE_RECORD(com, CE_OVERRUN); 1869 } 1870cont: 1871 if (line_status & LSR_TXRDY 1872 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 1873 goto txrdy; 1874 1875 /* 1876 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1877 * jump from the top of the loop to here 1878 */ 1879 line_status = inb(com->line_status_port) & 0x7F; 1880 } 1881 1882 /* modem status change? (always check before doing output) */ 1883 modem_status = inb(com->modem_status_port); 1884 if (modem_status != com->last_modem_status) { 1885 if (com->do_dcd_timestamp 1886 && !(com->last_modem_status & MSR_DCD) 1887 && modem_status & MSR_DCD) 1888 microtime(&com->dcd_timestamp); 1889 1890 /* 1891 * Schedule high level to handle DCD changes. Note 1892 * that we don't use the delta bits anywhere. Some 1893 * UARTs mess them up, and it's easy to remember the 1894 * previous bits and calculate the delta. 1895 */ 1896 com->last_modem_status = modem_status; 1897 if (!(com->state & CS_CHECKMSR)) { 1898 com_events += LOTS_OF_EVENTS; 1899 com->state |= CS_CHECKMSR; 1900 swi_sched(sio_fast_ih, 0); 1901 } 1902 1903 /* handle CTS change immediately for crisp flow ctl */ 1904 if (com->state & CS_CTS_OFLOW) { 1905 if (modem_status & MSR_CTS) 1906 com->state |= CS_ODEVREADY; 1907 else 1908 com->state &= ~CS_ODEVREADY; 1909 } 1910 } 1911 1912txrdy: 1913 /* output queued and everything ready? */ 1914 if (line_status & LSR_TXRDY 1915 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1916 ioptr = com->obufq.l_head; 1917 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 1918 u_int ocount; 1919 1920 ocount = com->obufq.l_tail - ioptr; 1921 if (ocount > com->tx_fifo_size) 1922 ocount = com->tx_fifo_size; 1923 com->bytes_out += ocount; 1924 do 1925 outb(com->data_port, *ioptr++); 1926 while (--ocount != 0); 1927 } else { 1928 outb(com->data_port, *ioptr++); 1929 ++com->bytes_out; 1930 if (com->unit == siotsunit 1931 && siotso < sizeof siots / sizeof siots[0]) 1932 nanouptime(&siots[siotso++]); 1933 } 1934 com->obufq.l_head = ioptr; 1935 if (COM_IIR_TXRDYBUG(com->flags)) 1936 int_ctl_new = int_ctl | IER_ETXRDY; 1937 if (ioptr >= com->obufq.l_tail) { 1938 struct lbq *qp; 1939 1940 qp = com->obufq.l_next; 1941 qp->l_queued = FALSE; 1942 qp = qp->l_next; 1943 if (qp != NULL) { 1944 com->obufq.l_head = qp->l_head; 1945 com->obufq.l_tail = qp->l_tail; 1946 com->obufq.l_next = qp; 1947 } else { 1948 /* output just completed */ 1949 if (COM_IIR_TXRDYBUG(com->flags)) 1950 int_ctl_new = int_ctl 1951 & ~IER_ETXRDY; 1952 com->state &= ~CS_BUSY; 1953 } 1954 if (!(com->state & CS_ODONE)) { 1955 com_events += LOTS_OF_EVENTS; 1956 com->state |= CS_ODONE; 1957 /* handle at high level ASAP */ 1958 swi_sched(sio_fast_ih, 0); 1959 } 1960 } 1961 if (COM_IIR_TXRDYBUG(com->flags) 1962 && int_ctl != int_ctl_new) 1963 outb(com->int_ctl_port, int_ctl_new); 1964 } 1965 1966 /* finished? */ 1967#ifndef COM_MULTIPORT 1968 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 1969#endif /* COM_MULTIPORT */ 1970 return; 1971 } 1972} 1973 1974static int 1975sioioctl(dev, cmd, data, flag, td) 1976 dev_t dev; 1977 u_long cmd; 1978 caddr_t data; 1979 int flag; 1980 struct thread *td; 1981{ 1982 struct com_s *com; 1983 int error; 1984 int mynor; 1985 int s; 1986 struct tty *tp; 1987#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 1988 u_long oldcmd; 1989 struct termios term; 1990#endif 1991 1992 mynor = minor(dev); 1993 com = com_addr(MINOR_TO_UNIT(mynor)); 1994 if (com == NULL || com->gone) 1995 return (ENODEV); 1996 if (mynor & CONTROL_MASK) { 1997 struct termios *ct; 1998 1999 switch (mynor & CONTROL_MASK) { 2000 case CONTROL_INIT_STATE: 2001 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2002 break; 2003 case CONTROL_LOCK_STATE: 2004 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2005 break; 2006 default: 2007 return (ENODEV); /* /dev/nodev */ 2008 } 2009 switch (cmd) { 2010 case TIOCSETA: 2011 error = suser(td); 2012 if (error != 0) 2013 return (error); 2014 *ct = *(struct termios *)data; 2015 return (0); 2016 case TIOCGETA: 2017 *(struct termios *)data = *ct; 2018 return (0); 2019 case TIOCGETD: 2020 *(int *)data = TTYDISC; 2021 return (0); 2022 case TIOCGWINSZ: 2023 bzero(data, sizeof(struct winsize)); 2024 return (0); 2025 default: 2026 return (ENOTTY); 2027 } 2028 } 2029 tp = com->tp; 2030#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2031 term = tp->t_termios; 2032 oldcmd = cmd; 2033 error = ttsetcompat(tp, &cmd, data, &term); 2034 if (error != 0) 2035 return (error); 2036 if (cmd != oldcmd) 2037 data = (caddr_t)&term; 2038#endif 2039 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2040 int cc; 2041 struct termios *dt = (struct termios *)data; 2042 struct termios *lt = mynor & CALLOUT_MASK 2043 ? &com->lt_out : &com->lt_in; 2044 2045 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2046 | (dt->c_iflag & ~lt->c_iflag); 2047 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2048 | (dt->c_oflag & ~lt->c_oflag); 2049 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2050 | (dt->c_cflag & ~lt->c_cflag); 2051 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2052 | (dt->c_lflag & ~lt->c_lflag); 2053 for (cc = 0; cc < NCCS; ++cc) 2054 if (lt->c_cc[cc] != 0) 2055 dt->c_cc[cc] = tp->t_cc[cc]; 2056 if (lt->c_ispeed != 0) 2057 dt->c_ispeed = tp->t_ispeed; 2058 if (lt->c_ospeed != 0) 2059 dt->c_ospeed = tp->t_ospeed; 2060 } 2061 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 2062 if (error != ENOIOCTL) 2063 return (error); 2064 s = spltty(); 2065 error = ttioctl(tp, cmd, data, flag); 2066 disc_optim(tp, &tp->t_termios, com); 2067 if (error != ENOIOCTL) { 2068 splx(s); 2069 return (error); 2070 } 2071 switch (cmd) { 2072 case TIOCSBRK: 2073 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2074 break; 2075 case TIOCCBRK: 2076 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2077 break; 2078 case TIOCSDTR: 2079 (void)commctl(com, TIOCM_DTR, DMBIS); 2080 break; 2081 case TIOCCDTR: 2082 (void)commctl(com, TIOCM_DTR, DMBIC); 2083 break; 2084 /* 2085 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 2086 * changes get undone on the next call to comparam(). 2087 */ 2088 case TIOCMSET: 2089 (void)commctl(com, *(int *)data, DMSET); 2090 break; 2091 case TIOCMBIS: 2092 (void)commctl(com, *(int *)data, DMBIS); 2093 break; 2094 case TIOCMBIC: 2095 (void)commctl(com, *(int *)data, DMBIC); 2096 break; 2097 case TIOCMGET: 2098 *(int *)data = commctl(com, 0, DMGET); 2099 break; 2100 case TIOCMSDTRWAIT: 2101 /* must be root since the wait applies to following logins */ 2102 error = suser(td); 2103 if (error != 0) { 2104 splx(s); 2105 return (error); 2106 } 2107 com->dtr_wait = *(int *)data * hz / 100; 2108 break; 2109 case TIOCMGDTRWAIT: 2110 *(int *)data = com->dtr_wait * 100 / hz; 2111 break; 2112 case TIOCTIMESTAMP: 2113 com->do_timestamp = TRUE; 2114 *(struct timeval *)data = com->timestamp; 2115 break; 2116 case TIOCDCDTIMESTAMP: 2117 com->do_dcd_timestamp = TRUE; 2118 *(struct timeval *)data = com->dcd_timestamp; 2119 break; 2120 default: 2121 splx(s); 2122 error = pps_ioctl(cmd, data, &com->pps); 2123 if (error == ENODEV) 2124 error = ENOTTY; 2125 return (error); 2126 } 2127 splx(s); 2128 return (0); 2129} 2130 2131/* software interrupt handler for SWI_TTY */ 2132static void 2133siopoll(void *dummy) 2134{ 2135 int unit; 2136 2137 if (com_events == 0) 2138 return; 2139repeat: 2140 for (unit = 0; unit < sio_numunits; ++unit) { 2141 struct com_s *com; 2142 int incc; 2143 struct tty *tp; 2144 2145 com = com_addr(unit); 2146 if (com == NULL) 2147 continue; 2148 tp = com->tp; 2149 if (tp == NULL || com->gone) { 2150 /* 2151 * Discard any events related to never-opened or 2152 * going-away devices. 2153 */ 2154 mtx_lock_spin(&sio_lock); 2155 incc = com->iptr - com->ibuf; 2156 com->iptr = com->ibuf; 2157 if (com->state & CS_CHECKMSR) { 2158 incc += LOTS_OF_EVENTS; 2159 com->state &= ~CS_CHECKMSR; 2160 } 2161 com_events -= incc; 2162 mtx_unlock_spin(&sio_lock); 2163 continue; 2164 } 2165 if (com->iptr != com->ibuf) { 2166 mtx_lock_spin(&sio_lock); 2167 sioinput(com); 2168 mtx_unlock_spin(&sio_lock); 2169 } 2170 if (com->state & CS_CHECKMSR) { 2171 u_char delta_modem_status; 2172 2173 mtx_lock_spin(&sio_lock); 2174 delta_modem_status = com->last_modem_status 2175 ^ com->prev_modem_status; 2176 com->prev_modem_status = com->last_modem_status; 2177 com_events -= LOTS_OF_EVENTS; 2178 com->state &= ~CS_CHECKMSR; 2179 mtx_unlock_spin(&sio_lock); 2180 if (delta_modem_status & MSR_DCD) 2181 (*linesw[tp->t_line].l_modem) 2182 (tp, com->prev_modem_status & MSR_DCD); 2183 } 2184 if (com->state & CS_ODONE) { 2185 mtx_lock_spin(&sio_lock); 2186 com_events -= LOTS_OF_EVENTS; 2187 com->state &= ~CS_ODONE; 2188 mtx_unlock_spin(&sio_lock); 2189 if (!(com->state & CS_BUSY) 2190 && !(com->extra_state & CSE_BUSYCHECK)) { 2191 timeout(siobusycheck, com, hz / 100); 2192 com->extra_state |= CSE_BUSYCHECK; 2193 } 2194 (*linesw[tp->t_line].l_start)(tp); 2195 } 2196 if (com_events == 0) 2197 break; 2198 } 2199 if (com_events >= LOTS_OF_EVENTS) 2200 goto repeat; 2201} 2202 2203static int 2204comparam(tp, t) 2205 struct tty *tp; 2206 struct termios *t; 2207{ 2208 u_int cfcr; 2209 int cflag; 2210 struct com_s *com; 2211 u_int divisor; 2212 u_char dlbh; 2213 u_char dlbl; 2214 u_char efr_flowbits; 2215 int s; 2216 int unit; 2217 2218 unit = DEV_TO_UNIT(tp->t_dev); 2219 com = com_addr(unit); 2220 if (com == NULL) 2221 return (ENODEV); 2222 2223 /* check requested parameters */ 2224 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 2225 return (EINVAL); 2226 divisor = siodivisor(com->rclk, t->c_ispeed); 2227 if (divisor == 0) 2228 return (EINVAL); 2229 2230 /* parameters are OK, convert them to the com struct and the device */ 2231 s = spltty(); 2232 if (t->c_ospeed == 0) 2233 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 2234 else 2235 (void)commctl(com, TIOCM_DTR, DMBIS); 2236 cflag = t->c_cflag; 2237 switch (cflag & CSIZE) { 2238 case CS5: 2239 cfcr = CFCR_5BITS; 2240 break; 2241 case CS6: 2242 cfcr = CFCR_6BITS; 2243 break; 2244 case CS7: 2245 cfcr = CFCR_7BITS; 2246 break; 2247 default: 2248 cfcr = CFCR_8BITS; 2249 break; 2250 } 2251 if (cflag & PARENB) { 2252 cfcr |= CFCR_PENAB; 2253 if (!(cflag & PARODD)) 2254 cfcr |= CFCR_PEVEN; 2255 } 2256 if (cflag & CSTOPB) 2257 cfcr |= CFCR_STOPB; 2258 2259 if (com->hasfifo) { 2260 /* 2261 * Use a fifo trigger level low enough so that the input 2262 * latency from the fifo is less than about 16 msec and 2263 * the total latency is less than about 30 msec. These 2264 * latencies are reasonable for humans. Serial comms 2265 * protocols shouldn't expect anything better since modem 2266 * latencies are larger. 2267 * 2268 * The fifo trigger level cannot be set at RX_HIGH for high 2269 * speed connections without further work on reducing 2270 * interrupt disablement times in other parts of the system, 2271 * without producing silo overflow errors. 2272 */ 2273 com->fifo_image = com->unit == siotsunit ? 0 2274 : t->c_ispeed <= 4800 2275 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 2276#ifdef COM_ESP 2277 /* 2278 * The Hayes ESP card needs the fifo DMA mode bit set 2279 * in compatibility mode. If not, it will interrupt 2280 * for each character received. 2281 */ 2282 if (com->esp) 2283 com->fifo_image |= FIFO_DMA_MODE; 2284#endif 2285 sio_setreg(com, com_fifo, com->fifo_image); 2286 } 2287 2288 /* 2289 * This returns with interrupts disabled so that we can complete 2290 * the speed change atomically. Keeping interrupts disabled is 2291 * especially important while com_data is hidden. 2292 */ 2293 (void) siosetwater(com, t->c_ispeed); 2294 2295 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 2296 /* 2297 * Only set the divisor registers if they would change, since on 2298 * some 16550 incompatibles (UMC8669F), setting them while input 2299 * is arriving loses sync until data stops arriving. 2300 */ 2301 dlbl = divisor & 0xFF; 2302 if (sio_getreg(com, com_dlbl) != dlbl) 2303 sio_setreg(com, com_dlbl, dlbl); 2304 dlbh = divisor >> 8; 2305 if (sio_getreg(com, com_dlbh) != dlbh) 2306 sio_setreg(com, com_dlbh, dlbh); 2307 2308 efr_flowbits = 0; 2309 2310 if (cflag & CRTS_IFLOW) { 2311 com->state |= CS_RTS_IFLOW; 2312 efr_flowbits |= EFR_AUTORTS; 2313 /* 2314 * If CS_RTS_IFLOW just changed from off to on, the change 2315 * needs to be propagated to MCR_RTS. This isn't urgent, 2316 * so do it later by calling comstart() instead of repeating 2317 * a lot of code from comstart() here. 2318 */ 2319 } else if (com->state & CS_RTS_IFLOW) { 2320 com->state &= ~CS_RTS_IFLOW; 2321 /* 2322 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2323 * on here, since comstart() won't do it later. 2324 */ 2325 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2326 } 2327 2328 /* 2329 * Set up state to handle output flow control. 2330 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2331 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2332 */ 2333 com->state |= CS_ODEVREADY; 2334 com->state &= ~CS_CTS_OFLOW; 2335 if (cflag & CCTS_OFLOW) { 2336 com->state |= CS_CTS_OFLOW; 2337 efr_flowbits |= EFR_AUTOCTS; 2338 if (!(com->last_modem_status & MSR_CTS)) 2339 com->state &= ~CS_ODEVREADY; 2340 } 2341 2342 if (com->st16650a) { 2343 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 2344 sio_setreg(com, com_efr, 2345 (sio_getreg(com, com_efr) 2346 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 2347 } 2348 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2349 2350 /* XXX shouldn't call functions while intrs are disabled. */ 2351 disc_optim(tp, t, com); 2352 2353 mtx_unlock_spin(&sio_lock); 2354 splx(s); 2355 comstart(tp); 2356 if (com->ibufold != NULL) { 2357 free(com->ibufold, M_DEVBUF); 2358 com->ibufold = NULL; 2359 } 2360 return (0); 2361} 2362 2363/* 2364 * This function must be called with the sio_lock mutex released and will 2365 * return with it obtained. 2366 */ 2367static int 2368siosetwater(com, speed) 2369 struct com_s *com; 2370 speed_t speed; 2371{ 2372 int cp4ticks; 2373 u_char *ibuf; 2374 int ibufsize; 2375 struct tty *tp; 2376 2377 /* 2378 * Make the buffer size large enough to handle a softtty interrupt 2379 * latency of about 2 ticks without loss of throughput or data 2380 * (about 3 ticks if input flow control is not used or not honoured, 2381 * but a bit less for CS5-CS7 modes). 2382 */ 2383 cp4ticks = speed / 10 / hz * 4; 2384 for (ibufsize = 128; ibufsize < cp4ticks;) 2385 ibufsize <<= 1; 2386 if (ibufsize == com->ibufsize) { 2387 mtx_lock_spin(&sio_lock); 2388 return (0); 2389 } 2390 2391 /* 2392 * Allocate input buffer. The extra factor of 2 in the size is 2393 * to allow for an error byte for each input byte. 2394 */ 2395 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2396 if (ibuf == NULL) { 2397 mtx_lock_spin(&sio_lock); 2398 return (ENOMEM); 2399 } 2400 2401 /* Initialize non-critical variables. */ 2402 com->ibufold = com->ibuf; 2403 com->ibufsize = ibufsize; 2404 tp = com->tp; 2405 if (tp != NULL) { 2406 tp->t_ififosize = 2 * ibufsize; 2407 tp->t_ispeedwat = (speed_t)-1; 2408 tp->t_ospeedwat = (speed_t)-1; 2409 } 2410 2411 /* 2412 * Read current input buffer, if any. Continue with interrupts 2413 * disabled. 2414 */ 2415 mtx_lock_spin(&sio_lock); 2416 if (com->iptr != com->ibuf) 2417 sioinput(com); 2418 2419 /*- 2420 * Initialize critical variables, including input buffer watermarks. 2421 * The external device is asked to stop sending when the buffer 2422 * exactly reaches high water, or when the high level requests it. 2423 * The high level is notified immediately (rather than at a later 2424 * clock tick) when this watermark is reached. 2425 * The buffer size is chosen so the watermark should almost never 2426 * be reached. 2427 * The low watermark is invisibly 0 since the buffer is always 2428 * emptied all at once. 2429 */ 2430 com->iptr = com->ibuf = ibuf; 2431 com->ibufend = ibuf + ibufsize; 2432 com->ierroff = ibufsize; 2433 com->ihighwater = ibuf + 3 * ibufsize / 4; 2434 return (0); 2435} 2436 2437static void 2438comstart(tp) 2439 struct tty *tp; 2440{ 2441 struct com_s *com; 2442 int s; 2443 int unit; 2444 2445 unit = DEV_TO_UNIT(tp->t_dev); 2446 com = com_addr(unit); 2447 if (com == NULL) 2448 return; 2449 s = spltty(); 2450 mtx_lock_spin(&sio_lock); 2451 if (tp->t_state & TS_TTSTOP) 2452 com->state &= ~CS_TTGO; 2453 else 2454 com->state |= CS_TTGO; 2455 if (tp->t_state & TS_TBLOCK) { 2456 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2457 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2458 } else { 2459 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2460 && com->state & CS_RTS_IFLOW) 2461 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2462 } 2463 mtx_unlock_spin(&sio_lock); 2464 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2465 ttwwakeup(tp); 2466 splx(s); 2467 return; 2468 } 2469 if (tp->t_outq.c_cc != 0) { 2470 struct lbq *qp; 2471 struct lbq *next; 2472 2473 if (!com->obufs[0].l_queued) { 2474 com->obufs[0].l_tail 2475 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2476 sizeof com->obuf1); 2477 com->obufs[0].l_next = NULL; 2478 com->obufs[0].l_queued = TRUE; 2479 mtx_lock_spin(&sio_lock); 2480 if (com->state & CS_BUSY) { 2481 qp = com->obufq.l_next; 2482 while ((next = qp->l_next) != NULL) 2483 qp = next; 2484 qp->l_next = &com->obufs[0]; 2485 } else { 2486 com->obufq.l_head = com->obufs[0].l_head; 2487 com->obufq.l_tail = com->obufs[0].l_tail; 2488 com->obufq.l_next = &com->obufs[0]; 2489 com->state |= CS_BUSY; 2490 } 2491 mtx_unlock_spin(&sio_lock); 2492 } 2493 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2494 com->obufs[1].l_tail 2495 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2496 sizeof com->obuf2); 2497 com->obufs[1].l_next = NULL; 2498 com->obufs[1].l_queued = TRUE; 2499 mtx_lock_spin(&sio_lock); 2500 if (com->state & CS_BUSY) { 2501 qp = com->obufq.l_next; 2502 while ((next = qp->l_next) != NULL) 2503 qp = next; 2504 qp->l_next = &com->obufs[1]; 2505 } else { 2506 com->obufq.l_head = com->obufs[1].l_head; 2507 com->obufq.l_tail = com->obufs[1].l_tail; 2508 com->obufq.l_next = &com->obufs[1]; 2509 com->state |= CS_BUSY; 2510 } 2511 mtx_unlock_spin(&sio_lock); 2512 } 2513 tp->t_state |= TS_BUSY; 2514 } 2515 mtx_lock_spin(&sio_lock); 2516 if (com->state >= (CS_BUSY | CS_TTGO)) 2517 siointr1(com); /* fake interrupt to start output */ 2518 mtx_unlock_spin(&sio_lock); 2519 ttwwakeup(tp); 2520 splx(s); 2521} 2522 2523static void 2524comstop(tp, rw) 2525 struct tty *tp; 2526 int rw; 2527{ 2528 struct com_s *com; 2529 2530 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 2531 if (com == NULL || com->gone) 2532 return; 2533 mtx_lock_spin(&sio_lock); 2534 if (rw & FWRITE) { 2535 if (com->hasfifo) 2536#ifdef COM_ESP 2537 /* XXX avoid h/w bug. */ 2538 if (!com->esp) 2539#endif 2540 sio_setreg(com, com_fifo, 2541 FIFO_XMT_RST | com->fifo_image); 2542 com->obufs[0].l_queued = FALSE; 2543 com->obufs[1].l_queued = FALSE; 2544 if (com->state & CS_ODONE) 2545 com_events -= LOTS_OF_EVENTS; 2546 com->state &= ~(CS_ODONE | CS_BUSY); 2547 com->tp->t_state &= ~TS_BUSY; 2548 } 2549 if (rw & FREAD) { 2550 if (com->hasfifo) 2551#ifdef COM_ESP 2552 /* XXX avoid h/w bug. */ 2553 if (!com->esp) 2554#endif 2555 sio_setreg(com, com_fifo, 2556 FIFO_RCV_RST | com->fifo_image); 2557 com_events -= (com->iptr - com->ibuf); 2558 com->iptr = com->ibuf; 2559 } 2560 mtx_unlock_spin(&sio_lock); 2561 comstart(tp); 2562} 2563 2564static int 2565commctl(com, bits, how) 2566 struct com_s *com; 2567 int bits; 2568 int how; 2569{ 2570 int mcr; 2571 int msr; 2572 2573 if (how == DMGET) { 2574 bits = TIOCM_LE; /* XXX - always enabled while open */ 2575 mcr = com->mcr_image; 2576 if (mcr & MCR_DTR) 2577 bits |= TIOCM_DTR; 2578 if (mcr & MCR_RTS) 2579 bits |= TIOCM_RTS; 2580 msr = com->prev_modem_status; 2581 if (msr & MSR_CTS) 2582 bits |= TIOCM_CTS; 2583 if (msr & MSR_DCD) 2584 bits |= TIOCM_CD; 2585 if (msr & MSR_DSR) 2586 bits |= TIOCM_DSR; 2587 /* 2588 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 2589 * more volatile by reading the modem status a lot. Perhaps 2590 * we should latch both bits until the status is read here. 2591 */ 2592 if (msr & (MSR_RI | MSR_TERI)) 2593 bits |= TIOCM_RI; 2594 return (bits); 2595 } 2596 mcr = 0; 2597 if (bits & TIOCM_DTR) 2598 mcr |= MCR_DTR; 2599 if (bits & TIOCM_RTS) 2600 mcr |= MCR_RTS; 2601 if (com->gone) 2602 return(0); 2603 mtx_lock_spin(&sio_lock); 2604 switch (how) { 2605 case DMSET: 2606 outb(com->modem_ctl_port, 2607 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 2608 break; 2609 case DMBIS: 2610 outb(com->modem_ctl_port, com->mcr_image |= mcr); 2611 break; 2612 case DMBIC: 2613 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 2614 break; 2615 } 2616 mtx_unlock_spin(&sio_lock); 2617 return (0); 2618} 2619 2620static void 2621siosettimeout() 2622{ 2623 struct com_s *com; 2624 bool_t someopen; 2625 int unit; 2626 2627 /* 2628 * Set our timeout period to 1 second if no polled devices are open. 2629 * Otherwise set it to max(1/200, 1/hz). 2630 * Enable timeouts iff some device is open. 2631 */ 2632 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2633 sio_timeout = hz; 2634 someopen = FALSE; 2635 for (unit = 0; unit < sio_numunits; ++unit) { 2636 com = com_addr(unit); 2637 if (com != NULL && com->tp != NULL 2638 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2639 someopen = TRUE; 2640 if (com->poll || com->poll_output) { 2641 sio_timeout = hz > 200 ? hz / 200 : 1; 2642 break; 2643 } 2644 } 2645 } 2646 if (someopen) { 2647 sio_timeouts_until_log = hz / sio_timeout; 2648 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2649 sio_timeout); 2650 } else { 2651 /* Flush error messages, if any. */ 2652 sio_timeouts_until_log = 1; 2653 comwakeup((void *)NULL); 2654 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2655 } 2656} 2657 2658static void 2659comwakeup(chan) 2660 void *chan; 2661{ 2662 struct com_s *com; 2663 int unit; 2664 2665 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2666 2667 /* 2668 * Recover from lost output interrupts. 2669 * Poll any lines that don't use interrupts. 2670 */ 2671 for (unit = 0; unit < sio_numunits; ++unit) { 2672 com = com_addr(unit); 2673 if (com != NULL && !com->gone 2674 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2675 mtx_lock_spin(&sio_lock); 2676 siointr1(com); 2677 mtx_unlock_spin(&sio_lock); 2678 } 2679 } 2680 2681 /* 2682 * Check for and log errors, but not too often. 2683 */ 2684 if (--sio_timeouts_until_log > 0) 2685 return; 2686 sio_timeouts_until_log = hz / sio_timeout; 2687 for (unit = 0; unit < sio_numunits; ++unit) { 2688 int errnum; 2689 2690 com = com_addr(unit); 2691 if (com == NULL) 2692 continue; 2693 if (com->gone) 2694 continue; 2695 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2696 u_int delta; 2697 u_long total; 2698 2699 mtx_lock_spin(&sio_lock); 2700 delta = com->delta_error_counts[errnum]; 2701 com->delta_error_counts[errnum] = 0; 2702 mtx_unlock_spin(&sio_lock); 2703 if (delta == 0) 2704 continue; 2705 total = com->error_counts[errnum] += delta; 2706 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2707 unit, delta, error_desc[errnum], 2708 delta == 1 ? "" : "s", total); 2709 } 2710 } 2711} 2712 2713static void 2714disc_optim(tp, t, com) 2715 struct tty *tp; 2716 struct termios *t; 2717 struct com_s *com; 2718{ 2719 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 2720 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 2721 && (!(t->c_iflag & PARMRK) 2722 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 2723 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 2724 && linesw[tp->t_line].l_rint == ttyinput) 2725 tp->t_state |= TS_CAN_BYPASS_L_RINT; 2726 else 2727 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 2728 com->hotchar = linesw[tp->t_line].l_hotchar; 2729} 2730 2731/* 2732 * Following are all routines needed for SIO to act as console 2733 */ 2734struct siocnstate { 2735 u_char dlbl; 2736 u_char dlbh; 2737 u_char ier; 2738 u_char cfcr; 2739 u_char mcr; 2740}; 2741 2742/* 2743 * This is a function in order to not replicate "ttyd%d" more 2744 * places than absolutely necessary. 2745 */ 2746static void 2747siocnset(struct consdev *cd, int unit) 2748{ 2749 2750 cd->cn_unit = unit; 2751 sprintf(cd->cn_name, "ttyd%d", unit); 2752} 2753 2754#ifndef __alpha__ 2755static speed_t siocngetspeed(Port_t, u_long rclk); 2756#endif 2757static void siocnclose(struct siocnstate *sp, Port_t iobase); 2758static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 2759static void siocntxwait(Port_t iobase); 2760 2761#ifdef __alpha__ 2762int siocnattach(int port, int speed); 2763int siogdbattach(int port, int speed); 2764int siogdbgetc(void); 2765void siogdbputc(int c); 2766#else 2767static cn_probe_t siocnprobe; 2768static cn_init_t siocninit; 2769static cn_term_t siocnterm; 2770#endif 2771static cn_checkc_t siocncheckc; 2772static cn_getc_t siocngetc; 2773static cn_putc_t siocnputc; 2774 2775#ifndef __alpha__ 2776CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 2777 siocnputc, NULL); 2778#endif 2779 2780#if DDB > 0 2781static struct consdev gdbconsdev; 2782#endif 2783 2784static void 2785siocntxwait(iobase) 2786 Port_t iobase; 2787{ 2788 int timo; 2789 2790 /* 2791 * Wait for any pending transmission to finish. Required to avoid 2792 * the UART lockup bug when the speed is changed, and for normal 2793 * transmits. 2794 */ 2795 timo = 100000; 2796 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2797 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2798 ; 2799} 2800 2801#ifndef __alpha__ 2802 2803/* 2804 * Read the serial port specified and try to figure out what speed 2805 * it's currently running at. We're assuming the serial port has 2806 * been initialized and is basicly idle. This routine is only intended 2807 * to be run at system startup. 2808 * 2809 * If the value read from the serial port doesn't make sense, return 0. 2810 */ 2811 2812static speed_t 2813siocngetspeed(iobase, rclk) 2814 Port_t iobase; 2815 u_long rclk; 2816{ 2817 u_int divisor; 2818 u_char dlbh; 2819 u_char dlbl; 2820 u_char cfcr; 2821 2822 cfcr = inb(iobase + com_cfcr); 2823 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2824 2825 dlbl = inb(iobase + com_dlbl); 2826 dlbh = inb(iobase + com_dlbh); 2827 2828 outb(iobase + com_cfcr, cfcr); 2829 2830 divisor = dlbh << 8 | dlbl; 2831 2832 /* XXX there should be more sanity checking. */ 2833 if (divisor == 0) 2834 return (CONSPEED); 2835 return (rclk / (16UL * divisor)); 2836} 2837 2838#endif 2839 2840static void 2841siocnopen(sp, iobase, speed) 2842 struct siocnstate *sp; 2843 Port_t iobase; 2844 int speed; 2845{ 2846 u_int divisor; 2847 u_char dlbh; 2848 u_char dlbl; 2849 2850 /* 2851 * Save all the device control registers except the fifo register 2852 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2853 * We can't save the fifo register since it is read-only. 2854 */ 2855 sp->ier = inb(iobase + com_ier); 2856 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2857 siocntxwait(iobase); 2858 sp->cfcr = inb(iobase + com_cfcr); 2859 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2860 sp->dlbl = inb(iobase + com_dlbl); 2861 sp->dlbh = inb(iobase + com_dlbh); 2862 /* 2863 * Only set the divisor registers if they would change, since on 2864 * some 16550 incompatibles (Startech), setting them clears the 2865 * data input register. This also reduces the effects of the 2866 * UMC8669F bug. 2867 */ 2868 divisor = siodivisor(comdefaultrclk, speed); 2869 dlbl = divisor & 0xFF; 2870 if (sp->dlbl != dlbl) 2871 outb(iobase + com_dlbl, dlbl); 2872 dlbh = divisor >> 8; 2873 if (sp->dlbh != dlbh) 2874 outb(iobase + com_dlbh, dlbh); 2875 outb(iobase + com_cfcr, CFCR_8BITS); 2876 sp->mcr = inb(iobase + com_mcr); 2877 /* 2878 * We don't want interrupts, but must be careful not to "disable" 2879 * them by clearing the MCR_IENABLE bit, since that might cause 2880 * an interrupt by floating the IRQ line. 2881 */ 2882 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2883} 2884 2885static void 2886siocnclose(sp, iobase) 2887 struct siocnstate *sp; 2888 Port_t iobase; 2889{ 2890 /* 2891 * Restore the device control registers. 2892 */ 2893 siocntxwait(iobase); 2894 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2895 if (sp->dlbl != inb(iobase + com_dlbl)) 2896 outb(iobase + com_dlbl, sp->dlbl); 2897 if (sp->dlbh != inb(iobase + com_dlbh)) 2898 outb(iobase + com_dlbh, sp->dlbh); 2899 outb(iobase + com_cfcr, sp->cfcr); 2900 /* 2901 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2902 */ 2903 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2904 outb(iobase + com_ier, sp->ier); 2905} 2906 2907#ifndef __alpha__ 2908 2909static void 2910siocnprobe(cp) 2911 struct consdev *cp; 2912{ 2913 speed_t boot_speed; 2914 u_char cfcr; 2915 u_int divisor; 2916 int s, unit; 2917 struct siocnstate sp; 2918 2919 /* 2920 * Find our first enabled console, if any. If it is a high-level 2921 * console device, then initialize it and return successfully. 2922 * If it is a low-level console device, then initialize it and 2923 * return unsuccessfully. It must be initialized in both cases 2924 * for early use by console drivers and debuggers. Initializing 2925 * the hardware is not necessary in all cases, since the i/o 2926 * routines initialize it on the fly, but it is necessary if 2927 * input might arrive while the hardware is switched back to an 2928 * uninitialized state. We can't handle multiple console devices 2929 * yet because our low-level routines don't take a device arg. 2930 * We trust the user to set the console flags properly so that we 2931 * don't need to probe. 2932 */ 2933 cp->cn_pri = CN_DEAD; 2934 2935 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2936 int flags; 2937 2938 if (resource_disabled("sio", unit)) 2939 continue; 2940 if (resource_int_value("sio", unit, "flags", &flags)) 2941 continue; 2942 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2943 int port; 2944 Port_t iobase; 2945 2946 if (resource_int_value("sio", unit, "port", &port)) 2947 continue; 2948 iobase = port; 2949 s = spltty(); 2950 if (boothowto & RB_SERIAL) { 2951 boot_speed = 2952 siocngetspeed(iobase, comdefaultrclk); 2953 if (boot_speed) 2954 comdefaultrate = boot_speed; 2955 } 2956 2957 /* 2958 * Initialize the divisor latch. We can't rely on 2959 * siocnopen() to do this the first time, since it 2960 * avoids writing to the latch if the latch appears 2961 * to have the correct value. Also, if we didn't 2962 * just read the speed from the hardware, then we 2963 * need to set the speed in hardware so that 2964 * switching it later is null. 2965 */ 2966 cfcr = inb(iobase + com_cfcr); 2967 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2968 divisor = siodivisor(comdefaultrclk, comdefaultrate); 2969 outb(iobase + com_dlbl, divisor & 0xff); 2970 outb(iobase + com_dlbh, divisor >> 8); 2971 outb(iobase + com_cfcr, cfcr); 2972 2973 siocnopen(&sp, iobase, comdefaultrate); 2974 2975 splx(s); 2976 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 2977 siocnset(cp, unit); 2978 cp->cn_pri = COM_FORCECONSOLE(flags) 2979 || boothowto & RB_SERIAL 2980 ? CN_REMOTE : CN_NORMAL; 2981 siocniobase = iobase; 2982 siocnunit = unit; 2983 } 2984 if (COM_DEBUGGER(flags)) { 2985 printf("sio%d: gdb debugging port\n", unit); 2986 siogdbiobase = iobase; 2987 siogdbunit = unit; 2988#if DDB > 0 2989 siocnset(&gdbconsdev, unit); 2990 gdb_arg = &gdbconsdev; 2991 gdb_getc = siocngetc; 2992 gdb_putc = siocnputc; 2993#endif 2994 } 2995 } 2996 } 2997#ifdef __i386__ 2998#if DDB > 0 2999 /* 3000 * XXX Ugly Compatability. 3001 * If no gdb port has been specified, set it to be the console 3002 * as some configuration files don't specify the gdb port. 3003 */ 3004 if (gdb_arg == NULL && (boothowto & RB_GDB)) { 3005 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 3006 siocnunit); 3007 printf("Set flag 0x80 on desired GDB port in your\n"); 3008 printf("configuration file (currently sio only).\n"); 3009 siogdbiobase = siocniobase; 3010 siogdbunit = siocnunit; 3011 siocnset(&gdbconsdev, siocnunit); 3012 gdb_arg = &gdbconsdev; 3013 gdb_getc = siocngetc; 3014 gdb_putc = siocnputc; 3015 } 3016#endif 3017#endif 3018} 3019 3020static void 3021siocninit(cp) 3022 struct consdev *cp; 3023{ 3024 comconsole = cp->cn_unit; 3025} 3026 3027static void 3028siocnterm(cp) 3029 struct consdev *cp; 3030{ 3031 comconsole = -1; 3032} 3033 3034#endif 3035 3036#ifdef __alpha__ 3037 3038CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 3039 3040int 3041siocnattach(port, speed) 3042 int port; 3043 int speed; 3044{ 3045 int s; 3046 u_char cfcr; 3047 u_int divisor; 3048 struct siocnstate sp; 3049 int unit = 0; /* XXX random value! */ 3050 3051 siocniobase = port; 3052 siocnunit = unit; 3053 comdefaultrate = speed; 3054 sio_consdev.cn_pri = CN_NORMAL; 3055 siocnset(&sio_consdev, unit); 3056 3057 s = spltty(); 3058 3059 /* 3060 * Initialize the divisor latch. We can't rely on 3061 * siocnopen() to do this the first time, since it 3062 * avoids writing to the latch if the latch appears 3063 * to have the correct value. Also, if we didn't 3064 * just read the speed from the hardware, then we 3065 * need to set the speed in hardware so that 3066 * switching it later is null. 3067 */ 3068 cfcr = inb(siocniobase + com_cfcr); 3069 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 3070 divisor = siodivisor(comdefaultrclk, comdefaultrate); 3071 outb(siocniobase + com_dlbl, divisor & 0xff); 3072 outb(siocniobase + com_dlbh, divisor >> 8); 3073 outb(siocniobase + com_cfcr, cfcr); 3074 3075 siocnopen(&sp, siocniobase, comdefaultrate); 3076 splx(s); 3077 3078 cnadd(&sio_consdev); 3079 return (0); 3080} 3081 3082int 3083siogdbattach(port, speed) 3084 int port; 3085 int speed; 3086{ 3087 int s; 3088 u_char cfcr; 3089 u_int divisor; 3090 struct siocnstate sp; 3091 int unit = 1; /* XXX random value! */ 3092 3093 siogdbiobase = port; 3094 gdbdefaultrate = speed; 3095 3096 printf("sio%d: gdb debugging port\n", unit); 3097 siogdbunit = unit; 3098#if DDB > 0 3099 siocnset(&gdbconsdev, unit); 3100 gdb_arg = &gdbconsdev; 3101 gdb_getc = siocngetc; 3102 gdb_putc = siocnputc; 3103#endif 3104 3105 s = spltty(); 3106 3107 /* 3108 * Initialize the divisor latch. We can't rely on 3109 * siocnopen() to do this the first time, since it 3110 * avoids writing to the latch if the latch appears 3111 * to have the correct value. Also, if we didn't 3112 * just read the speed from the hardware, then we 3113 * need to set the speed in hardware so that 3114 * switching it later is null. 3115 */ 3116 cfcr = inb(siogdbiobase + com_cfcr); 3117 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 3118 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 3119 outb(siogdbiobase + com_dlbl, divisor & 0xff); 3120 outb(siogdbiobase + com_dlbh, divisor >> 8); 3121 outb(siogdbiobase + com_cfcr, cfcr); 3122 3123 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 3124 splx(s); 3125 3126 return (0); 3127} 3128 3129#endif 3130 3131static int 3132siocncheckc(struct consdev *cd) 3133{ 3134 int c; 3135 Port_t iobase; 3136 int s; 3137 struct siocnstate sp; 3138 speed_t speed; 3139 3140 if (cd->cn_unit == siocnunit) { 3141 iobase = siocniobase; 3142 speed = comdefaultrate; 3143 } else { 3144 iobase = siogdbiobase; 3145 speed = gdbdefaultrate; 3146 } 3147 s = spltty(); 3148 siocnopen(&sp, iobase, speed); 3149 if (inb(iobase + com_lsr) & LSR_RXRDY) 3150 c = inb(iobase + com_data); 3151 else 3152 c = -1; 3153 siocnclose(&sp, iobase); 3154 splx(s); 3155 return (c); 3156} 3157 3158static int 3159siocngetc(struct consdev *cd) 3160{ 3161 int c; 3162 Port_t iobase; 3163 int s; 3164 struct siocnstate sp; 3165 speed_t speed; 3166 3167 if (cd->cn_unit == siocnunit) { 3168 iobase = siocniobase; 3169 speed = comdefaultrate; 3170 } else { 3171 iobase = siogdbiobase; 3172 speed = gdbdefaultrate; 3173 } 3174 s = spltty(); 3175 siocnopen(&sp, iobase, speed); 3176 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3177 ; 3178 c = inb(iobase + com_data); 3179 siocnclose(&sp, iobase); 3180 splx(s); 3181 return (c); 3182} 3183 3184static void 3185siocnputc(struct consdev *cd, int c) 3186{ 3187 int need_unlock; 3188 int s; 3189 struct siocnstate sp; 3190 Port_t iobase; 3191 speed_t speed; 3192 3193 if (cd->cn_unit == siocnunit) { 3194 iobase = siocniobase; 3195 speed = comdefaultrate; 3196 } else { 3197 iobase = siogdbiobase; 3198 speed = gdbdefaultrate; 3199 } 3200 s = spltty(); 3201 need_unlock = 0; 3202 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 3203 mtx_lock_spin(&sio_lock); 3204 need_unlock = 1; 3205 } 3206 siocnopen(&sp, iobase, speed); 3207 siocntxwait(iobase); 3208 outb(iobase + com_data, c); 3209 siocnclose(&sp, iobase); 3210 if (need_unlock) 3211 mtx_unlock_spin(&sio_lock); 3212 splx(s); 3213} 3214 3215#ifdef __alpha__ 3216int 3217siogdbgetc() 3218{ 3219 int c; 3220 Port_t iobase; 3221 speed_t speed; 3222 int s; 3223 struct siocnstate sp; 3224 3225 if (siogdbunit == siocnunit) { 3226 iobase = siocniobase; 3227 speed = comdefaultrate; 3228 } else { 3229 iobase = siogdbiobase; 3230 speed = gdbdefaultrate; 3231 } 3232 3233 s = spltty(); 3234 siocnopen(&sp, iobase, speed); 3235 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3236 ; 3237 c = inb(iobase + com_data); 3238 siocnclose(&sp, iobase); 3239 splx(s); 3240 return (c); 3241} 3242 3243void 3244siogdbputc(c) 3245 int c; 3246{ 3247 Port_t iobase; 3248 speed_t speed; 3249 int s; 3250 struct siocnstate sp; 3251 3252 if (siogdbunit == siocnunit) { 3253 iobase = siocniobase; 3254 speed = comdefaultrate; 3255 } else { 3256 iobase = siogdbiobase; 3257 speed = gdbdefaultrate; 3258 } 3259 3260 s = spltty(); 3261 siocnopen(&sp, iobase, speed); 3262 siocntxwait(siogdbiobase); 3263 outb(siogdbiobase + com_data, c); 3264 siocnclose(&sp, siogdbiobase); 3265 splx(s); 3266} 3267#endif 3268