sio.c revision 51088
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by the University of
16 *	California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 *    may be used to endorse or promote products derived from this software
19 *    without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/sio/sio.c 51088 1999-09-08 13:46:54Z peter $
34 *	from: @(#)com.c	7.5 (Berkeley) 5/16/91
35 *	from: i386/isa sio.c,v 1.234
36 */
37
38#include "opt_comconsole.h"
39#include "opt_compat.h"
40#include "opt_ddb.h"
41#include "opt_sio.h"
42#include "sio.h"
43
44/*
45 * Serial driver, based on 386BSD-0.1 com driver.
46 * Mostly rewritten to use pseudo-DMA.
47 * Works for National Semiconductor NS8250-NS16550AF UARTs.
48 * COM driver, based on HP dca driver.
49 *
50 * Changes for PC-Card integration:
51 *	- Added PC-Card driver table and handlers
52 */
53#include <sys/param.h>
54#include <sys/systm.h>
55#include <sys/reboot.h>
56#include <sys/malloc.h>
57#include <sys/tty.h>
58#include <sys/proc.h>
59#include <sys/module.h>
60#include <sys/conf.h>
61#include <sys/dkstat.h>
62#include <sys/fcntl.h>
63#include <sys/interrupt.h>
64#include <sys/kernel.h>
65#include <sys/syslog.h>
66#include <sys/sysctl.h>
67#include <sys/bus.h>
68#include <machine/bus.h>
69#include <sys/rman.h>
70#include <sys/timepps.h>
71
72#include <isa/isareg.h>
73#include <isa/isavar.h>
74#include <machine/lock.h>
75
76#include <machine/clock.h>
77#include <machine/ipl.h>
78#ifndef SMP
79#include <machine/lock.h>
80#endif
81#include <machine/resource.h>
82
83#include <isa/sioreg.h>
84
85#ifdef COM_ESP
86#include <isa/ic/esp.h>
87#endif
88#include <isa/ic/ns16550.h>
89
90#if 0
91#include "card.h"
92#if NCARD > 0
93#include <sys/module.h>
94#include <pccard/cardinfo.h>
95#include <pccard/slot.h>
96#endif
97#else
98#define NCARD 0
99#endif
100
101#ifndef __i386__
102#define disable_intr()
103#define enable_intr()
104#endif
105
106#ifdef SMP
107#define disable_intr()	COM_DISABLE_INTR()
108#define enable_intr()	COM_ENABLE_INTR()
109#endif /* SMP */
110
111#ifndef EXTRA_SIO
112#define EXTRA_SIO 4		/* XXX shouldn't need NSIO */
113#endif
114
115#define NSIOTOT (NSIO + EXTRA_SIO)
116
117#define	LOTS_OF_EVENTS	64	/* helps separate urgent events from input */
118
119#define	CALLOUT_MASK		0x80
120#define	CONTROL_MASK		0x60
121#define	CONTROL_INIT_STATE	0x20
122#define	CONTROL_LOCK_STATE	0x40
123#define	DEV_TO_UNIT(dev)	(MINOR_TO_UNIT(minor(dev)))
124#define	MINOR_MAGIC_MASK	(CALLOUT_MASK | CONTROL_MASK)
125#define	MINOR_TO_UNIT(mynor)	((mynor) & ~MINOR_MAGIC_MASK)
126
127#ifdef COM_MULTIPORT
128/* checks in flags for multiport and which is multiport "master chip"
129 * for a given card
130 */
131#define	COM_ISMULTIPORT(flags)	((flags) & 0x01)
132#define	COM_MPMASTER(flags)	(((flags) >> 8) & 0x0ff)
133#define	COM_NOTAST4(flags)	((flags) & 0x04)
134#endif /* COM_MULTIPORT */
135
136#define	COM_CONSOLE(flags)	((flags) & 0x10)
137#define	COM_FORCECONSOLE(flags)	((flags) & 0x20)
138#define	COM_LLCONSOLE(flags)	((flags) & 0x40)
139#define	COM_DEBUGGER(flags)	((flags) & 0x80)
140#define	COM_LOSESOUTINTS(flags)	((flags) & 0x08)
141#define	COM_NOFIFO(flags)		((flags) & 0x02)
142#define COM_ST16650A(flags)	((flags) & 0x20000)
143#define COM_C_NOPROBE		(0x40000)
144#define COM_NOPROBE(flags)	((flags) & COM_C_NOPROBE)
145#define COM_C_IIR_TXRDYBUG	(0x80000)
146#define COM_IIR_TXRDYBUG(flags)	((flags) & COM_C_IIR_TXRDYBUG)
147#define	COM_FIFOSIZE(flags)	(((flags) & 0xff000000) >> 24)
148
149#define	com_scr		7	/* scratch register for 16450-16550 (R/W) */
150
151/*
152 * com state bits.
153 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
154 * than the other bits so that they can be tested as a group without masking
155 * off the low bits.
156 *
157 * The following com and tty flags correspond closely:
158 *	CS_BUSY		= TS_BUSY (maintained by comstart(), siopoll() and
159 *				   siostop())
160 *	CS_TTGO		= ~TS_TTSTOP (maintained by comparam() and comstart())
161 *	CS_CTS_OFLOW	= CCTS_OFLOW (maintained by comparam())
162 *	CS_RTS_IFLOW	= CRTS_IFLOW (maintained by comparam())
163 * TS_FLUSH is not used.
164 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
165 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
166 */
167#define	CS_BUSY		0x80	/* output in progress */
168#define	CS_TTGO		0x40	/* output not stopped by XOFF */
169#define	CS_ODEVREADY	0x20	/* external device h/w ready (CTS) */
170#define	CS_CHECKMSR	1	/* check of MSR scheduled */
171#define	CS_CTS_OFLOW	2	/* use CTS output flow control */
172#define	CS_DTR_OFF	0x10	/* DTR held off */
173#define	CS_ODONE	4	/* output completed */
174#define	CS_RTS_IFLOW	8	/* use RTS input flow control */
175#define	CSE_BUSYCHECK	1	/* siobusycheck() scheduled */
176
177static	char const * const	error_desc[] = {
178#define	CE_OVERRUN			0
179	"silo overflow",
180#define	CE_INTERRUPT_BUF_OVERFLOW	1
181	"interrupt-level buffer overflow",
182#define	CE_TTY_BUF_OVERFLOW		2
183	"tty-level buffer overflow",
184};
185
186#define	CE_NTYPES			3
187#define	CE_RECORD(com, errnum)		(++(com)->delta_error_counts[errnum])
188
189/* types.  XXX - should be elsewhere */
190typedef u_int	Port_t;		/* hardware port */
191typedef u_char	bool_t;		/* boolean */
192
193/* queue of linear buffers */
194struct lbq {
195	u_char	*l_head;	/* next char to process */
196	u_char	*l_tail;	/* one past the last char to process */
197	struct lbq *l_next;	/* next in queue */
198	bool_t	l_queued;	/* nonzero if queued */
199};
200
201/* com device structure */
202struct com_s {
203	u_int	flags;		/* Copy isa device flags */
204	u_char	state;		/* miscellaneous flag bits */
205	bool_t  active_out;	/* nonzero if the callout device is open */
206	u_char	cfcr_image;	/* copy of value written to CFCR */
207#ifdef COM_ESP
208	bool_t	esp;		/* is this unit a hayes esp board? */
209#endif
210	u_char	extra_state;	/* more flag bits, separate for order trick */
211	u_char	fifo_image;	/* copy of value written to FIFO */
212	bool_t	hasfifo;	/* nonzero for 16550 UARTs */
213	bool_t	st16650a;	/* Is a Startech 16650A or RTS/CTS compat */
214	bool_t	loses_outints;	/* nonzero if device loses output interrupts */
215	u_char	mcr_image;	/* copy of value written to MCR */
216#ifdef COM_MULTIPORT
217	bool_t	multiport;	/* is this unit part of a multiport device? */
218#endif /* COM_MULTIPORT */
219	bool_t	no_irq;		/* nonzero if irq is not attached */
220	bool_t  gone;		/* hardware disappeared */
221	bool_t	poll;		/* nonzero if polling is required */
222	bool_t	poll_output;	/* nonzero if polling for output is required */
223	int	unit;		/* unit	number */
224	int	dtr_wait;	/* time to hold DTR down on close (* 1/hz) */
225	u_int	tx_fifo_size;
226	u_int	wopeners;	/* # processes waiting for DCD in open() */
227
228	/*
229	 * The high level of the driver never reads status registers directly
230	 * because there would be too many side effects to handle conveniently.
231	 * Instead, it reads copies of the registers stored here by the
232	 * interrupt handler.
233	 */
234	u_char	last_modem_status;	/* last MSR read by intr handler */
235	u_char	prev_modem_status;	/* last MSR handled by high level */
236
237	u_char	hotchar;	/* ldisc-specific char to be handled ASAP */
238	u_char	*ibuf;		/* start of input buffer */
239	u_char	*ibufend;	/* end of input buffer */
240	u_char	*ibufold;	/* old input buffer, to be freed */
241	u_char	*ihighwater;	/* threshold in input buffer */
242	u_char	*iptr;		/* next free spot in input buffer */
243	int	ibufsize;	/* size of ibuf (not include error bytes) */
244	int	ierroff;	/* offset of error bytes in ibuf */
245
246	struct lbq	obufq;	/* head of queue of output buffers */
247	struct lbq	obufs[2];	/* output buffers */
248
249	Port_t	data_port;	/* i/o ports */
250#ifdef COM_ESP
251	Port_t	esp_port;
252#endif
253	Port_t	int_id_port;
254	Port_t	iobase;
255	Port_t	modem_ctl_port;
256	Port_t	line_status_port;
257	Port_t	modem_status_port;
258	Port_t	intr_ctl_port;	/* Ports of IIR register */
259
260	struct tty	*tp;	/* cross reference */
261
262	/* Initial state. */
263	struct termios	it_in;	/* should be in struct tty */
264	struct termios	it_out;
265
266	/* Lock state. */
267	struct termios	lt_in;	/* should be in struct tty */
268	struct termios	lt_out;
269
270	bool_t	do_timestamp;
271	bool_t	do_dcd_timestamp;
272	struct timeval	timestamp;
273	struct timeval	dcd_timestamp;
274	struct	pps_state pps;
275
276	u_long	bytes_in;	/* statistics */
277	u_long	bytes_out;
278	u_int	delta_error_counts[CE_NTYPES];
279	u_long	error_counts[CE_NTYPES];
280
281	struct resource *irqres;
282	struct resource *ioportres;
283
284	/*
285	 * Data area for output buffers.  Someday we should build the output
286	 * buffer queue without copying data.
287	 */
288	u_char	obuf1[256];
289	u_char	obuf2[256];
290};
291
292#ifdef COM_ESP
293static	int	espattach	__P((struct com_s *com, Port_t esp_port));
294#endif
295static	int	sioattach	__P((device_t dev));
296
297static	timeout_t siobusycheck;
298static	timeout_t siodtrwakeup;
299static	void	comhardclose	__P((struct com_s *com));
300static	void	sioinput	__P((struct com_s *com));
301static	void	siointr1	__P((struct com_s *com));
302static	void	siointr		__P((void *arg));
303static	int	commctl		__P((struct com_s *com, int bits, int how));
304static	int	comparam	__P((struct tty *tp, struct termios *t));
305static	swihand_t siopoll;
306static	int	sioprobe	__P((device_t dev));
307static	void	siosettimeout	__P((void));
308static	int	siosetwater	__P((struct com_s *com, speed_t speed));
309static	void	comstart	__P((struct tty *tp));
310static	timeout_t comwakeup;
311static	void	disc_optim	__P((struct tty	*tp, struct termios *t,
312				     struct com_s *com));
313
314
315static char driver_name[] = "sio";
316
317/* table and macro for fast conversion from a unit number to its com struct */
318static	devclass_t	sio_devclass;
319#define	com_addr(unit)	((struct com_s *) \
320			 devclass_get_softc(sio_devclass, unit))
321
322static device_method_t sio_methods[] = {
323	/* Device interface */
324	DEVMETHOD(device_probe,		sioprobe),
325	DEVMETHOD(device_attach,	sioattach),
326
327	{ 0, 0 }
328};
329
330static driver_t sio_driver = {
331	driver_name,
332	sio_methods,
333	sizeof(struct com_s),
334};
335
336static	d_open_t	sioopen;
337static	d_close_t	sioclose;
338static	d_read_t	sioread;
339static	d_write_t	siowrite;
340static	d_ioctl_t	sioioctl;
341static	d_stop_t	siostop;
342static	d_devtotty_t	siodevtotty;
343
344#define	CDEV_MAJOR	28
345static struct cdevsw sio_cdevsw = {
346	/* open */	sioopen,
347	/* close */	sioclose,
348	/* read */	sioread,
349	/* write */	siowrite,
350	/* ioctl */	sioioctl,
351	/* stop */	siostop,
352	/* reset */	noreset,
353	/* devtotty */	siodevtotty,
354	/* poll */	ttpoll,
355	/* mmap */	nommap,
356	/* strategy */	nostrategy,
357	/* name */	driver_name,
358	/* parms */	noparms,
359	/* maj */	CDEV_MAJOR,
360	/* dump */	nodump,
361	/* psize */	nopsize,
362	/* flags */	D_TTY,
363	/* maxio */	0,
364	/* bmaj */	-1
365};
366
367int	comconsole = -1;
368static	volatile speed_t	comdefaultrate = CONSPEED;
369#ifdef __alpha__
370static	volatile speed_t	gdbdefaultrate = CONSPEED;
371#endif
372static	u_int	com_events;	/* input chars + weighted output completions */
373static	Port_t	siocniobase;
374static	int	siocnunit;
375static	Port_t	siogdbiobase;
376static	int	siogdbunit = -1;
377static	bool_t	sio_registered;
378static	int	sio_timeout;
379static	int	sio_timeouts_until_log;
380static	struct	callout_handle sio_timeout_handle
381    = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
382
383static	struct speedtab comspeedtab[] = {
384	{ 0,		0 },
385	{ 50,		COMBRD(50) },
386	{ 75,		COMBRD(75) },
387	{ 110,		COMBRD(110) },
388	{ 134,		COMBRD(134) },
389	{ 150,		COMBRD(150) },
390	{ 200,		COMBRD(200) },
391	{ 300,		COMBRD(300) },
392	{ 600,		COMBRD(600) },
393	{ 1200,		COMBRD(1200) },
394	{ 1800,		COMBRD(1800) },
395	{ 2400,		COMBRD(2400) },
396	{ 4800,		COMBRD(4800) },
397	{ 9600,		COMBRD(9600) },
398	{ 19200,	COMBRD(19200) },
399	{ 38400,	COMBRD(38400) },
400	{ 57600,	COMBRD(57600) },
401	{ 115200,	COMBRD(115200) },
402	{ -1,		-1 }
403};
404
405#ifdef COM_ESP
406/* XXX configure this properly. */
407static	Port_t	likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
408static	Port_t	likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
409#endif
410
411/*
412 * handle sysctl read/write requests for console speed
413 *
414 * In addition to setting comdefaultrate for I/O through /dev/console,
415 * also set the initial and lock values for the /dev/ttyXX device
416 * if there is one associated with the console.  Finally, if the /dev/tty
417 * device has already been open, change the speed on the open running port
418 * itself.
419 */
420
421static int
422sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
423{
424	int error, s;
425	speed_t newspeed;
426	struct com_s *com;
427	struct tty *tp;
428
429	newspeed = comdefaultrate;
430
431	error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
432	if (error || !req->newptr)
433		return (error);
434
435	comdefaultrate = newspeed;
436
437	if (comconsole < 0)		/* serial console not selected? */
438		return (0);
439
440	com = com_addr(comconsole);
441	if (!com)
442		return (ENXIO);
443
444	/*
445	 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
446	 * (note, the lock rates really are boolean -- if non-zero, disallow
447	 *  speed changes)
448	 */
449	com->it_in.c_ispeed  = com->it_in.c_ospeed =
450	com->lt_in.c_ispeed  = com->lt_in.c_ospeed =
451	com->it_out.c_ispeed = com->it_out.c_ospeed =
452	com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
453
454	/*
455	 * if we're open, change the running rate too
456	 */
457	tp = com->tp;
458	if (tp && (tp->t_state & TS_ISOPEN)) {
459		tp->t_termios.c_ispeed =
460		tp->t_termios.c_ospeed = comdefaultrate;
461		s = spltty();
462		error = comparam(tp, &tp->t_termios);
463		splx(s);
464	}
465	return error;
466}
467
468SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
469	    0, 0, sysctl_machdep_comdefaultrate, "I", "");
470
471#if NCARD > 0
472/*
473 *	PC-Card (PCMCIA) specific code.
474 */
475static int	sioinit		__P((struct pccard_devinfo *));
476static void	siounload	__P((struct pccard_devinfo *));
477static int	card_intr	__P((struct pccard_devinfo *));
478
479PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask);
480
481/*
482 *	Initialize the device - called from Slot manager.
483 */
484int
485sioinit(struct pccard_devinfo *devi)
486{
487
488	/* validate unit number. */
489	if (devi->isahd.id_unit >= (NSIOTOT))
490		return(ENODEV);
491	/* Make sure it isn't already probed. */
492	if (com_addr(devi->isahd.id_unit))
493		return(EBUSY);
494
495	/* It's already probed as serial by Upper */
496	devi->isahd.id_flags |= COM_C_NOPROBE;
497
498	/*
499	 * attach the device.
500	 */
501	if (sioattach(devi->isahd.id_device) == 0)
502		return(ENXIO);
503
504	return(0);
505}
506
507/*
508 *	siounload - unload the driver and clear the table.
509 *	XXX TODO:
510 *	This is usually called when the card is ejected, but
511 *	can be caused by a modunload of a controller driver.
512 *	The idea is to reset the driver's view of the device
513 *	and ensure that any driver entry points such as
514 *	read and write do not hang.
515 */
516static void
517siounload(struct pccard_devinfo *devi)
518{
519	struct com_s	*com;
520
521	if (!devi) {
522		printf("NULL devi in siounload\n");
523		return;
524	}
525	com = com_addr(devi->isahd.id_unit);
526	if (!com) {
527		printf("NULL com in siounload\n");
528		return;
529	}
530	if (!com->iobase) {
531		printf("sio%d already unloaded!\n",devi->isahd.id_unit);
532		return;
533	}
534	if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
535		com->gone = 1;
536		printf("sio%d: unload\n", devi->isahd.id_unit);
537		com->tp->t_gen++;
538		ttyclose(com->tp);
539		ttwakeup(com->tp);
540		ttwwakeup(com->tp);
541	} else {
542		if (com->ibuf != NULL)
543			free(com->ibuf, M_DEVBUF);
544		free(com, M_DEVBUF);
545		printf("sio%d: unload,gone\n", devi->isahd.id_unit);
546	}
547}
548
549/*
550 *	card_intr - Shared interrupt called from
551 *	front end of PC-Card handler.
552 */
553static int
554card_intr(struct pccard_devinfo *devi)
555{
556	struct com_s	*com;
557
558	COM_LOCK();
559	com = com_addr(devi->isahd.id_unit);
560	if (com && !com->gone)
561		siointr1(com_addr(devi->isahd.id_unit));
562	COM_UNLOCK();
563	return(1);
564}
565#endif /* NCARD > 0 */
566
567#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
568#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
569
570static struct isa_pnp_id sio_ids[] = {
571	{0x0005d041, "Standard PC COM port"},	/* PNP0500 */
572	{0x0105d041, "16550A-compatible COM port"},	/* PNP0501 */
573	{0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
574	{0x1005d041, "Generic IRDA-compatible device"},	/* PNP0510 */
575	{0x1105d041, "Generic IRDA-compatible device"},	/* PNP0511 */
576	{0x31307256, "USR3031"},	/* USR3031 */
577	{0}
578};
579
580static int
581sioprobe(dev)
582	device_t	dev;
583{
584	static bool_t	already_init;
585	bool_t		failures[10];
586	int		fn;
587	device_t	idev;
588	Port_t		iobase;
589	intrmask_t	irqmap[4];
590	intrmask_t	irqs;
591	u_char		mcr_image;
592	int		result;
593	device_t	xdev;
594	u_int		flags = device_get_flags(dev);
595	int		rid;
596	struct resource *port;
597
598	/* Check isapnp ids */
599	if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
600		return (ENXIO);
601
602	rid = 0;
603	port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
604				  0, ~0, IO_COMSIZE, RF_ACTIVE);
605	if (!port)
606		return ENXIO;
607
608	if (!already_init) {
609		/*
610		 * Turn off MCR_IENABLE for all likely serial ports.  An unused
611		 * port with its MCR_IENABLE gate open will inhibit interrupts
612		 * from any used port that shares the interrupt vector.
613		 * XXX the gate enable is elsewhere for some multiports.
614		 */
615		device_t *devs;
616		int count, i;
617
618		devclass_get_devices(sio_devclass, &devs, &count);
619		for (i = 0; i < count; i++) {
620			xdev = devs[i];
621			if (device_is_enabled(xdev))
622				outb(isa_get_port(xdev) + com_mcr, 0);
623		}
624		free(devs, M_TEMP);
625		already_init = TRUE;
626	}
627
628	if (COM_LLCONSOLE(flags)) {
629		printf("sio%d: reserved for low-level i/o\n",
630		       device_get_unit(dev));
631		return (ENXIO);
632	}
633
634	/*
635	 * If the device is on a multiport card and has an AST/4
636	 * compatible interrupt control register, initialize this
637	 * register and prepare to leave MCR_IENABLE clear in the mcr.
638	 * Otherwise, prepare to set MCR_IENABLE in the mcr.
639	 * Point idev to the device struct giving the correct id_irq.
640	 * This is the struct for the master device if there is one.
641	 */
642	idev = dev;
643	mcr_image = MCR_IENABLE;
644#ifdef COM_MULTIPORT
645	if (COM_ISMULTIPORT(flags)) {
646		idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
647		if (idev == NULL) {
648			printf("sio%d: master device %d not configured\n",
649			       device_get_unit(dev), COM_MPMASTER(flags));
650			idev = dev;
651		}
652		if (!COM_NOTAST4(flags)) {
653			outb(isa_get_port(idev) + com_scr,
654			     isa_get_irq(idev) >= 0 ? 0x80 : 0);
655			mcr_image = 0;
656		}
657	}
658#endif /* COM_MULTIPORT */
659	if (isa_get_irq(idev) < 0)
660		mcr_image = 0;
661
662	bzero(failures, sizeof failures);
663	iobase = rman_get_start(port);
664
665	/*
666	 * We don't want to get actual interrupts, just masked ones.
667	 * Interrupts from this line should already be masked in the ICU,
668	 * but mask them in the processor as well in case there are some
669	 * (misconfigured) shared interrupts.
670	 */
671	disable_intr();
672/* EXTRA DELAY? */
673
674	/*
675	 * Initialize the speed and the word size and wait long enough to
676	 * drain the maximum of 16 bytes of junk in device output queues.
677	 * The speed is undefined after a master reset and must be set
678	 * before relying on anything related to output.  There may be
679	 * junk after a (very fast) soft reboot and (apparently) after
680	 * master reset.
681	 * XXX what about the UART bug avoided by waiting in comparam()?
682	 * We don't want to to wait long enough to drain at 2 bps.
683	 */
684	if (iobase == siocniobase)
685		DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
686	else {
687		outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
688		outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
689		outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
690		outb(iobase + com_cfcr, CFCR_8BITS);
691		DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
692	}
693
694	/*
695	 * Enable the interrupt gate and disable device interupts.  This
696	 * should leave the device driving the interrupt line low and
697	 * guarantee an edge trigger if an interrupt can be generated.
698	 */
699/* EXTRA DELAY? */
700	outb(iobase + com_mcr, mcr_image);
701	outb(iobase + com_ier, 0);
702	DELAY(1000);		/* XXX */
703	irqmap[0] = isa_irq_pending();
704
705	/*
706	 * Attempt to set loopback mode so that we can send a null byte
707	 * without annoying any external device.
708	 */
709/* EXTRA DELAY? */
710	outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
711
712	/*
713	 * Attempt to generate an output interrupt.  On 8250's, setting
714	 * IER_ETXRDY generates an interrupt independent of the current
715	 * setting and independent of whether the THR is empty.  On 16450's,
716	 * setting IER_ETXRDY generates an interrupt independent of the
717	 * current setting.  On 16550A's, setting IER_ETXRDY only
718	 * generates an interrupt when IER_ETXRDY is not already set.
719	 */
720	outb(iobase + com_ier, IER_ETXRDY);
721
722	/*
723	 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
724	 * an interrupt.  They'd better generate one for actually doing
725	 * output.  Loopback may be broken on the same incompatibles but
726	 * it's unlikely to do more than allow the null byte out.
727	 */
728	outb(iobase + com_data, 0);
729	DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
730
731	/*
732	 * Turn off loopback mode so that the interrupt gate works again
733	 * (MCR_IENABLE was hidden).  This should leave the device driving
734	 * an interrupt line high.  It doesn't matter if the interrupt
735	 * line oscillates while we are not looking at it, since interrupts
736	 * are disabled.
737	 */
738/* EXTRA DELAY? */
739	outb(iobase + com_mcr, mcr_image);
740
741	/*
742	 * It's a definitly Serial PCMCIA(16550A), but still be required
743	 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
744	 */
745	if ( COM_NOPROBE(flags) ) {
746		/* Reading IIR register twice */
747		for ( fn = 0; fn < 2; fn ++ ) {
748			DELAY(10000);
749			failures[6] = inb(iobase + com_iir);
750		}
751		/* Check IIR_TXRDY clear ? */
752		result = 0;
753		if ( failures[6] & IIR_TXRDY ) {
754			/* Nop, Double check with clearing IER */
755			outb(iobase + com_ier, 0);
756			if ( inb(iobase + com_iir) & IIR_NOPEND ) {
757				/* Ok. we're familia this gang */
758				SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */
759			} else {
760				/* Unknown, Just omit this chip.. XXX */
761				result = ENXIO;
762			}
763		} else {
764			/* OK. this is well-known guys */
765			CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/
766		}
767		outb(iobase + com_cfcr, CFCR_8BITS);
768		enable_intr();
769		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
770		return (iobase == siocniobase ? 0 : result);
771	}
772
773	/*
774	 * Check that
775	 *	o the CFCR, IER and MCR in UART hold the values written to them
776	 *	  (the values happen to be all distinct - this is good for
777	 *	  avoiding false positive tests from bus echoes).
778	 *	o an output interrupt is generated and its vector is correct.
779	 *	o the interrupt goes away when the IIR in the UART is read.
780	 */
781/* EXTRA DELAY? */
782	failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
783	failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
784	failures[2] = inb(iobase + com_mcr) - mcr_image;
785	DELAY(10000);		/* Some internal modems need this time */
786	irqmap[1] = isa_irq_pending();
787	failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
788	DELAY(1000);		/* XXX */
789	irqmap[2] = isa_irq_pending();
790	failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
791
792	/*
793	 * Turn off all device interrupts and check that they go off properly.
794	 * Leave MCR_IENABLE alone.  For ports without a master port, it gates
795	 * the OUT2 output of the UART to
796	 * the ICU input.  Closing the gate would give a floating ICU input
797	 * (unless there is another device driving it) and spurious interrupts.
798	 * (On the system that this was first tested on, the input floats high
799	 * and gives a (masked) interrupt as soon as the gate is closed.)
800	 */
801	outb(iobase + com_ier, 0);
802	outb(iobase + com_cfcr, CFCR_8BITS);	/* dummy to avoid bus echo */
803	failures[7] = inb(iobase + com_ier);
804	DELAY(1000);		/* XXX */
805	irqmap[3] = isa_irq_pending();
806	failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
807
808	enable_intr();
809
810	irqs = irqmap[1] & ~irqmap[0];
811	if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0)
812		printf(
813		"sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
814		    device_get_unit(dev), isa_get_irq(idev), irqs);
815	if (bootverbose)
816		printf("sio%d: irq maps: %#x %#x %#x %#x\n",
817		    device_get_unit(dev),
818		    irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
819
820	result = 0;
821	for (fn = 0; fn < sizeof failures; ++fn)
822		if (failures[fn]) {
823			outb(iobase + com_mcr, 0);
824			result = ENXIO;
825			if (bootverbose) {
826				printf("sio%d: probe failed test(s):",
827				    device_get_unit(dev));
828				for (fn = 0; fn < sizeof failures; ++fn)
829					if (failures[fn])
830						printf(" %d", fn);
831				printf("\n");
832			}
833			break;
834		}
835	bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
836	return (iobase == siocniobase ? 0 : result);
837}
838
839#ifdef COM_ESP
840static int
841espattach(com, esp_port)
842	struct com_s		*com;
843	Port_t			esp_port;
844{
845	u_char	dips;
846	u_char	val;
847
848	/*
849	 * Check the ESP-specific I/O port to see if we're an ESP
850	 * card.  If not, return failure immediately.
851	 */
852	if ((inb(esp_port) & 0xf3) == 0) {
853		printf(" port 0x%x is not an ESP board?\n", esp_port);
854		return (0);
855	}
856
857	/*
858	 * We've got something that claims to be a Hayes ESP card.
859	 * Let's hope so.
860	 */
861
862	/* Get the dip-switch configuration */
863	outb(esp_port + ESP_CMD1, ESP_GETDIPS);
864	dips = inb(esp_port + ESP_STATUS1);
865
866	/*
867	 * Bits 0,1 of dips say which COM port we are.
868	 */
869	if (com->iobase == likely_com_ports[dips & 0x03])
870		printf(" : ESP");
871	else {
872		printf(" esp_port has com %d\n", dips & 0x03);
873		return (0);
874	}
875
876	/*
877	 * Check for ESP version 2.0 or later:  bits 4,5,6 = 010.
878	 */
879	outb(esp_port + ESP_CMD1, ESP_GETTEST);
880	val = inb(esp_port + ESP_STATUS1);	/* clear reg 1 */
881	val = inb(esp_port + ESP_STATUS2);
882	if ((val & 0x70) < 0x20) {
883		printf("-old (%o)", val & 0x70);
884		return (0);
885	}
886
887	/*
888	 * Check for ability to emulate 16550:  bit 7 == 1
889	 */
890	if ((dips & 0x80) == 0) {
891		printf(" slave");
892		return (0);
893	}
894
895	/*
896	 * Okay, we seem to be a Hayes ESP card.  Whee.
897	 */
898	com->esp = TRUE;
899	com->esp_port = esp_port;
900	return (1);
901}
902#endif /* COM_ESP */
903
904static int
905sioattach(dev)
906	device_t	dev;
907{
908	struct com_s	*com;
909#ifdef COM_ESP
910	Port_t		*espp;
911#endif
912	Port_t		iobase;
913	int		unit;
914	void		*ih;
915	u_int		flags = device_get_flags(dev);
916	int		rid;
917	struct resource *port;
918
919	rid = 0;
920	port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
921				  0, ~0, IO_COMSIZE, RF_ACTIVE);
922	if (!port)
923		return ENXIO;
924
925	iobase = rman_get_start(port);
926	unit = device_get_unit(dev);
927	com = device_get_softc(dev);
928
929	/*
930	 * sioprobe() has initialized the device registers as follows:
931	 *	o cfcr = CFCR_8BITS.
932	 *	  It is most important that CFCR_DLAB is off, so that the
933	 *	  data port is not hidden when we enable interrupts.
934	 *	o ier = 0.
935	 *	  Interrupts are only enabled when the line is open.
936	 *	o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
937	 *	  interrupt control register or the config specifies no irq.
938	 *	  Keeping MCR_DTR and MCR_RTS off might stop the external
939	 *	  device from sending before we are ready.
940	 */
941	bzero(com, sizeof *com);
942	com->unit = unit;
943	com->ioportres = port;
944	com->cfcr_image = CFCR_8BITS;
945	com->dtr_wait = 3 * hz;
946	com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
947	com->no_irq = isa_get_irq(dev) < 0;
948	com->tx_fifo_size = 1;
949	com->obufs[0].l_head = com->obuf1;
950	com->obufs[1].l_head = com->obuf2;
951
952	com->iobase = iobase;
953	com->data_port = iobase + com_data;
954	com->int_id_port = iobase + com_iir;
955	com->modem_ctl_port = iobase + com_mcr;
956	com->mcr_image = inb(com->modem_ctl_port);
957	com->line_status_port = iobase + com_lsr;
958	com->modem_status_port = iobase + com_msr;
959	com->intr_ctl_port = iobase + com_ier;
960
961	/*
962	 * We don't use all the flags from <sys/ttydefaults.h> since they
963	 * are only relevant for logins.  It's important to have echo off
964	 * initially so that the line doesn't start blathering before the
965	 * echo flag can be turned off.
966	 */
967	com->it_in.c_iflag = 0;
968	com->it_in.c_oflag = 0;
969	com->it_in.c_cflag = TTYDEF_CFLAG;
970	com->it_in.c_lflag = 0;
971	if (unit == comconsole) {
972		com->it_in.c_iflag = TTYDEF_IFLAG;
973		com->it_in.c_oflag = TTYDEF_OFLAG;
974		com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
975		com->it_in.c_lflag = TTYDEF_LFLAG;
976		com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
977		com->lt_out.c_ispeed = com->lt_out.c_ospeed =
978		com->lt_in.c_ispeed = com->lt_in.c_ospeed =
979		com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
980	} else
981		com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
982	if (siosetwater(com, com->it_in.c_ispeed) != 0) {
983		enable_intr();
984		free(com, M_DEVBUF);
985		return (0);
986	}
987	enable_intr();
988	termioschars(&com->it_in);
989	com->it_out = com->it_in;
990
991	/* attempt to determine UART type */
992	printf("sio%d: type", unit);
993
994
995#ifdef COM_MULTIPORT
996	if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
997#else
998	if (!COM_IIR_TXRDYBUG(flags))
999#endif
1000	{
1001		u_char	scr;
1002		u_char	scr1;
1003		u_char	scr2;
1004
1005		scr = inb(iobase + com_scr);
1006		outb(iobase + com_scr, 0xa5);
1007		scr1 = inb(iobase + com_scr);
1008		outb(iobase + com_scr, 0x5a);
1009		scr2 = inb(iobase + com_scr);
1010		outb(iobase + com_scr, scr);
1011		if (scr1 != 0xa5 || scr2 != 0x5a) {
1012			printf(" 8250");
1013			goto determined_type;
1014		}
1015	}
1016	outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1017	DELAY(100);
1018	com->st16650a = 0;
1019	switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1020	case FIFO_RX_LOW:
1021		printf(" 16450");
1022		break;
1023	case FIFO_RX_MEDL:
1024		printf(" 16450?");
1025		break;
1026	case FIFO_RX_MEDH:
1027		printf(" 16550?");
1028		break;
1029	case FIFO_RX_HIGH:
1030		if (COM_NOFIFO(flags)) {
1031			printf(" 16550A fifo disabled");
1032		} else {
1033			com->hasfifo = TRUE;
1034			if (COM_ST16650A(flags)) {
1035				com->st16650a = 1;
1036				com->tx_fifo_size = 32;
1037				printf(" ST16650A");
1038			} else {
1039				com->tx_fifo_size = COM_FIFOSIZE(flags);
1040				printf(" 16550A");
1041			}
1042		}
1043#ifdef COM_ESP
1044		for (espp = likely_esp_ports; *espp != 0; espp++)
1045			if (espattach(com, *espp)) {
1046				com->tx_fifo_size = 1024;
1047				break;
1048			}
1049#endif
1050		if (!com->st16650a) {
1051			if (!com->tx_fifo_size)
1052				com->tx_fifo_size = 16;
1053			else
1054				printf(" lookalike with %d bytes FIFO",
1055				    com->tx_fifo_size);
1056		}
1057
1058		break;
1059	}
1060
1061#ifdef COM_ESP
1062	if (com->esp) {
1063		/*
1064		 * Set 16550 compatibility mode.
1065		 * We don't use the ESP_MODE_SCALE bit to increase the
1066		 * fifo trigger levels because we can't handle large
1067		 * bursts of input.
1068		 * XXX flow control should be set in comparam(), not here.
1069		 */
1070		outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1071		outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1072
1073		/* Set RTS/CTS flow control. */
1074		outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1075		outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1076		outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1077
1078		/* Set flow-control levels. */
1079		outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1080		outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1081		outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1082		outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1083		outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1084	}
1085#endif /* COM_ESP */
1086	outb(iobase + com_fifo, 0);
1087determined_type: ;
1088
1089#ifdef COM_MULTIPORT
1090	if (COM_ISMULTIPORT(flags)) {
1091		com->multiport = TRUE;
1092		printf(" (multiport");
1093		if (unit == COM_MPMASTER(flags))
1094			printf(" master");
1095		printf(")");
1096		com->no_irq =
1097			isa_get_irq(devclass_get_device
1098				    (sio_devclass, COM_MPMASTER(flags))) < 0;
1099	 }
1100#endif /* COM_MULTIPORT */
1101	if (unit == comconsole)
1102		printf(", console");
1103	if ( COM_IIR_TXRDYBUG(flags) )
1104		printf(" with a bogus IIR_TXRDY register");
1105	printf("\n");
1106
1107	if (!sio_registered) {
1108		register_swi(SWI_TTY, siopoll);
1109		sio_registered = TRUE;
1110	}
1111	make_dev(&sio_cdevsw, unit,
1112	    UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1113	make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE,
1114	    UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1115	make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE,
1116	    UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1117	make_dev(&sio_cdevsw, unit | CALLOUT_MASK,
1118	    UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1119	make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE,
1120	    UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1121	make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE,
1122	    UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1123	com->flags = flags;
1124	com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1125	pps_init(&com->pps);
1126
1127	rid = 0;
1128	com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
1129	    RF_SHAREABLE | RF_ACTIVE);
1130	BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1131		       INTR_TYPE_TTY | INTR_TYPE_FAST,
1132		       siointr, com, &ih);
1133
1134	return (0);
1135}
1136
1137static int
1138sioopen(dev, flag, mode, p)
1139	dev_t		dev;
1140	int		flag;
1141	int		mode;
1142	struct proc	*p;
1143{
1144	struct com_s	*com;
1145	int		error;
1146	Port_t		iobase;
1147	int		mynor;
1148	int		s;
1149	struct tty	*tp;
1150	int		unit;
1151
1152	mynor = minor(dev);
1153	unit = MINOR_TO_UNIT(mynor);
1154	if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
1155		return (ENXIO);
1156	if (com->gone)
1157		return (ENXIO);
1158	if (mynor & CONTROL_MASK)
1159		return (0);
1160	tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1161	s = spltty();
1162	/*
1163	 * We jump to this label after all non-interrupted sleeps to pick
1164	 * up any changes of the device state.
1165	 */
1166open_top:
1167	while (com->state & CS_DTR_OFF) {
1168		error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1169		if (com_addr(unit) == NULL)
1170			return (ENXIO);
1171		if (error != 0 || com->gone)
1172			goto out;
1173	}
1174	if (tp->t_state & TS_ISOPEN) {
1175		/*
1176		 * The device is open, so everything has been initialized.
1177		 * Handle conflicts.
1178		 */
1179		if (mynor & CALLOUT_MASK) {
1180			if (!com->active_out) {
1181				error = EBUSY;
1182				goto out;
1183			}
1184		} else {
1185			if (com->active_out) {
1186				if (flag & O_NONBLOCK) {
1187					error = EBUSY;
1188					goto out;
1189				}
1190				error =	tsleep(&com->active_out,
1191					       TTIPRI | PCATCH, "siobi", 0);
1192				if (com_addr(unit) == NULL)
1193					return (ENXIO);
1194				if (error != 0 || com->gone)
1195					goto out;
1196				goto open_top;
1197			}
1198		}
1199		if (tp->t_state & TS_XCLUDE &&
1200		    suser(p)) {
1201			error = EBUSY;
1202			goto out;
1203		}
1204	} else {
1205		/*
1206		 * The device isn't open, so there are no conflicts.
1207		 * Initialize it.  Initialization is done twice in many
1208		 * cases: to preempt sleeping callin opens if we are
1209		 * callout, and to complete a callin open after DCD rises.
1210		 */
1211		tp->t_oproc = comstart;
1212		tp->t_param = comparam;
1213		tp->t_dev = dev;
1214		tp->t_termios = mynor & CALLOUT_MASK
1215				? com->it_out : com->it_in;
1216		(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1217		com->poll = com->no_irq;
1218		com->poll_output = com->loses_outints;
1219		++com->wopeners;
1220		error = comparam(tp, &tp->t_termios);
1221		--com->wopeners;
1222		if (error != 0)
1223			goto out;
1224		/*
1225		 * XXX we should goto open_top if comparam() slept.
1226		 */
1227		iobase = com->iobase;
1228		if (com->hasfifo) {
1229			/*
1230			 * (Re)enable and drain fifos.
1231			 *
1232			 * Certain SMC chips cause problems if the fifos
1233			 * are enabled while input is ready.  Turn off the
1234			 * fifo if necessary to clear the input.  We test
1235			 * the input ready bit after enabling the fifos
1236			 * since we've already enabled them in comparam()
1237			 * and to handle races between enabling and fresh
1238			 * input.
1239			 */
1240			while (TRUE) {
1241				outb(iobase + com_fifo,
1242				     FIFO_RCV_RST | FIFO_XMT_RST
1243				     | com->fifo_image);
1244				/*
1245				 * XXX the delays are for superstitious
1246				 * historical reasons.  It must be less than
1247				 * the character time at the maximum
1248				 * supported speed (87 usec at 115200 bps
1249				 * 8N1).  Otherwise we might loop endlessly
1250				 * if data is streaming in.  We used to use
1251				 * delays of 100.  That usually worked
1252				 * because DELAY(100) used to usually delay
1253				 * for about 85 usec instead of 100.
1254				 */
1255				DELAY(50);
1256				if (!(inb(com->line_status_port) & LSR_RXRDY))
1257					break;
1258				outb(iobase + com_fifo, 0);
1259				DELAY(50);
1260				(void) inb(com->data_port);
1261			}
1262		}
1263
1264		disable_intr();
1265		(void) inb(com->line_status_port);
1266		(void) inb(com->data_port);
1267		com->prev_modem_status = com->last_modem_status
1268		    = inb(com->modem_status_port);
1269		if (COM_IIR_TXRDYBUG(com->flags)) {
1270			outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
1271						| IER_EMSC);
1272		} else {
1273			outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
1274						| IER_ERLS | IER_EMSC);
1275		}
1276		enable_intr();
1277		/*
1278		 * Handle initial DCD.  Callout devices get a fake initial
1279		 * DCD (trapdoor DCD).  If we are callout, then any sleeping
1280		 * callin opens get woken up and resume sleeping on "siobi"
1281		 * instead of "siodcd".
1282		 */
1283		/*
1284		 * XXX `mynor & CALLOUT_MASK' should be
1285		 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
1286		 * TRAPDOOR_CARRIER is the default initial state for callout
1287		 * devices and SOFT_CARRIER is like CLOCAL except it hides
1288		 * the true carrier.
1289		 */
1290		if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
1291			(*linesw[tp->t_line].l_modem)(tp, 1);
1292	}
1293	/*
1294	 * Wait for DCD if necessary.
1295	 */
1296	if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
1297	    && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
1298		++com->wopeners;
1299		error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
1300		if (com_addr(unit) == NULL)
1301			return (ENXIO);
1302		--com->wopeners;
1303		if (error != 0 || com->gone)
1304			goto out;
1305		goto open_top;
1306	}
1307	error =	(*linesw[tp->t_line].l_open)(dev, tp);
1308	disc_optim(tp, &tp->t_termios, com);
1309	if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
1310		com->active_out = TRUE;
1311	siosettimeout();
1312out:
1313	splx(s);
1314	if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
1315		comhardclose(com);
1316	return (error);
1317}
1318
1319static int
1320sioclose(dev, flag, mode, p)
1321	dev_t		dev;
1322	int		flag;
1323	int		mode;
1324	struct proc	*p;
1325{
1326	struct com_s	*com;
1327	int		mynor;
1328	int		s;
1329	struct tty	*tp;
1330
1331	mynor = minor(dev);
1332	if (mynor & CONTROL_MASK)
1333		return (0);
1334	com = com_addr(MINOR_TO_UNIT(mynor));
1335	tp = com->tp;
1336	s = spltty();
1337	(*linesw[tp->t_line].l_close)(tp, flag);
1338	disc_optim(tp, &tp->t_termios, com);
1339	siostop(tp, FREAD | FWRITE);
1340	comhardclose(com);
1341	ttyclose(tp);
1342	siosettimeout();
1343	splx(s);
1344	if (com->gone) {
1345		printf("sio%d: gone\n", com->unit);
1346		s = spltty();
1347		if (com->ibuf != NULL)
1348			free(com->ibuf, M_DEVBUF);
1349		bzero(tp, sizeof *tp);
1350		free(com, M_DEVBUF);
1351		splx(s);
1352	}
1353	return (0);
1354}
1355
1356static void
1357comhardclose(com)
1358	struct com_s	*com;
1359{
1360	Port_t		iobase;
1361	int		s;
1362	struct tty	*tp;
1363	int		unit;
1364
1365	unit = com->unit;
1366	iobase = com->iobase;
1367	s = spltty();
1368	com->poll = FALSE;
1369	com->poll_output = FALSE;
1370	com->do_timestamp = FALSE;
1371	com->do_dcd_timestamp = FALSE;
1372	com->pps.ppsparam.mode = 0;
1373	outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1374	{
1375		outb(iobase + com_ier, 0);
1376		tp = com->tp;
1377		if (tp->t_cflag & HUPCL
1378		    /*
1379		     * XXX we will miss any carrier drop between here and the
1380		     * next open.  Perhaps we should watch DCD even when the
1381		     * port is closed; it is not sufficient to check it at
1382		     * the next open because it might go up and down while
1383		     * we're not watching.
1384		     */
1385		    || (!com->active_out
1386		        && !(com->prev_modem_status & MSR_DCD)
1387		        && !(com->it_in.c_cflag & CLOCAL))
1388		    || !(tp->t_state & TS_ISOPEN)) {
1389			(void)commctl(com, TIOCM_DTR, DMBIC);
1390			if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
1391				timeout(siodtrwakeup, com, com->dtr_wait);
1392				com->state |= CS_DTR_OFF;
1393			}
1394		}
1395	}
1396	if (com->hasfifo) {
1397		/*
1398		 * Disable fifos so that they are off after controlled
1399		 * reboots.  Some BIOSes fail to detect 16550s when the
1400		 * fifos are enabled.
1401		 */
1402		outb(iobase + com_fifo, 0);
1403	}
1404	com->active_out = FALSE;
1405	wakeup(&com->active_out);
1406	wakeup(TSA_CARR_ON(tp));	/* restart any wopeners */
1407	splx(s);
1408}
1409
1410static int
1411sioread(dev, uio, flag)
1412	dev_t		dev;
1413	struct uio	*uio;
1414	int		flag;
1415{
1416	int		mynor;
1417	struct com_s	*com;
1418
1419	mynor = minor(dev);
1420	if (mynor & CONTROL_MASK)
1421		return (ENODEV);
1422	com = com_addr(MINOR_TO_UNIT(mynor));
1423	if (com->gone)
1424		return (ENODEV);
1425	return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
1426}
1427
1428static int
1429siowrite(dev, uio, flag)
1430	dev_t		dev;
1431	struct uio	*uio;
1432	int		flag;
1433{
1434	int		mynor;
1435	struct com_s	*com;
1436	int		unit;
1437
1438	mynor = minor(dev);
1439	if (mynor & CONTROL_MASK)
1440		return (ENODEV);
1441
1442	unit = MINOR_TO_UNIT(mynor);
1443	com = com_addr(unit);
1444	if (com->gone)
1445		return (ENODEV);
1446	/*
1447	 * (XXX) We disallow virtual consoles if the physical console is
1448	 * a serial port.  This is in case there is a display attached that
1449	 * is not the console.  In that situation we don't need/want the X
1450	 * server taking over the console.
1451	 */
1452	if (constty != NULL && unit == comconsole)
1453		constty = NULL;
1454	return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
1455}
1456
1457static void
1458siobusycheck(chan)
1459	void	*chan;
1460{
1461	struct com_s	*com;
1462	int		s;
1463
1464	com = (struct com_s *)chan;
1465
1466	/*
1467	 * Clear TS_BUSY if low-level output is complete.
1468	 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1469	 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1470	 * called again.  Reading the line status port outside of siointr1()
1471	 * is safe because CS_BUSY is clear so there are no output interrupts
1472	 * to lose.
1473	 */
1474	s = spltty();
1475	if (com->state & CS_BUSY)
1476		com->extra_state &= ~CSE_BUSYCHECK;	/* False alarm. */
1477	else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1478	    == (LSR_TSRE | LSR_TXRDY)) {
1479		com->tp->t_state &= ~TS_BUSY;
1480		ttwwakeup(com->tp);
1481		com->extra_state &= ~CSE_BUSYCHECK;
1482	} else
1483		timeout(siobusycheck, com, hz / 100);
1484	splx(s);
1485}
1486
1487static void
1488siodtrwakeup(chan)
1489	void	*chan;
1490{
1491	struct com_s	*com;
1492
1493	com = (struct com_s *)chan;
1494	com->state &= ~CS_DTR_OFF;
1495	wakeup(&com->dtr_wait);
1496}
1497
1498static void
1499sioinput(com)
1500	struct com_s	*com;
1501{
1502	u_char		*buf;
1503	int		incc;
1504	u_char		line_status;
1505	int		recv_data;
1506	struct tty	*tp;
1507
1508	buf = com->ibuf;
1509	tp = com->tp;
1510	if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1511		com_events -= (com->iptr - com->ibuf);
1512		com->iptr = com->ibuf;
1513		return;
1514	}
1515	if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1516		/*
1517		 * Avoid the grotesquely inefficient lineswitch routine
1518		 * (ttyinput) in "raw" mode.  It usually takes about 450
1519		 * instructions (that's without canonical processing or echo!).
1520		 * slinput is reasonably fast (usually 40 instructions plus
1521		 * call overhead).
1522		 */
1523		do {
1524			enable_intr();
1525			incc = com->iptr - buf;
1526			if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1527			    && (com->state & CS_RTS_IFLOW
1528				|| tp->t_iflag & IXOFF)
1529			    && !(tp->t_state & TS_TBLOCK))
1530				ttyblock(tp);
1531			com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1532				+= b_to_q((char *)buf, incc, &tp->t_rawq);
1533			buf += incc;
1534			tk_nin += incc;
1535			tk_rawcc += incc;
1536			tp->t_rawcc += incc;
1537			ttwakeup(tp);
1538			if (tp->t_state & TS_TTSTOP
1539			    && (tp->t_iflag & IXANY
1540				|| tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1541				tp->t_state &= ~TS_TTSTOP;
1542				tp->t_lflag &= ~FLUSHO;
1543				comstart(tp);
1544			}
1545			disable_intr();
1546		} while (buf < com->iptr);
1547	} else {
1548		do {
1549			enable_intr();
1550			line_status = buf[com->ierroff];
1551			recv_data = *buf++;
1552			if (line_status
1553			    & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1554				if (line_status & LSR_BI)
1555					recv_data |= TTY_BI;
1556				if (line_status & LSR_FE)
1557					recv_data |= TTY_FE;
1558				if (line_status & LSR_OE)
1559					recv_data |= TTY_OE;
1560				if (line_status & LSR_PE)
1561					recv_data |= TTY_PE;
1562			}
1563			(*linesw[tp->t_line].l_rint)(recv_data, tp);
1564			disable_intr();
1565		} while (buf < com->iptr);
1566	}
1567	com_events -= (com->iptr - com->ibuf);
1568	com->iptr = com->ibuf;
1569
1570	/*
1571	 * There is now room for another low-level buffer full of input,
1572	 * so enable RTS if it is now disabled and there is room in the
1573	 * high-level buffer.
1574	 */
1575	if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1576	    !(tp->t_state & TS_TBLOCK))
1577		outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1578}
1579
1580void
1581siointr(arg)
1582	void		*arg;
1583{
1584#ifndef COM_MULTIPORT
1585	COM_LOCK();
1586	siointr1((struct com_s *) arg);
1587	COM_UNLOCK();
1588#else /* COM_MULTIPORT */
1589	bool_t		possibly_more_intrs;
1590	int		unit;
1591	struct com_s	*com;
1592
1593	/*
1594	 * Loop until there is no activity on any port.  This is necessary
1595	 * to get an interrupt edge more than to avoid another interrupt.
1596	 * If the IRQ signal is just an OR of the IRQ signals from several
1597	 * devices, then the edge from one may be lost because another is
1598	 * on.
1599	 */
1600	COM_LOCK();
1601	do {
1602		possibly_more_intrs = FALSE;
1603		for (unit = 0; unit < NSIOTOT; ++unit) {
1604			com = com_addr(unit);
1605			/*
1606			 * XXX COM_LOCK();
1607			 * would it work here, or be counter-productive?
1608			 */
1609			if (com != NULL
1610			    && !com->gone
1611			    && (inb(com->int_id_port) & IIR_IMASK)
1612			       != IIR_NOPEND) {
1613				siointr1(com);
1614				possibly_more_intrs = TRUE;
1615			}
1616			/* XXX COM_UNLOCK(); */
1617		}
1618	} while (possibly_more_intrs);
1619	COM_UNLOCK();
1620#endif /* COM_MULTIPORT */
1621}
1622
1623static void
1624siointr1(com)
1625	struct com_s	*com;
1626{
1627	u_char	line_status;
1628	u_char	modem_status;
1629	u_char	*ioptr;
1630	u_char	recv_data;
1631	u_char	int_ctl;
1632	u_char	int_ctl_new;
1633	struct	timecounter *tc;
1634	u_int	count;
1635
1636	int_ctl = inb(com->intr_ctl_port);
1637	int_ctl_new = int_ctl;
1638
1639	while (!com->gone) {
1640		if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
1641			modem_status = inb(com->modem_status_port);
1642		        if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
1643				tc = timecounter;
1644				count = tc->tc_get_timecount(tc);
1645				pps_event(&com->pps, tc, count,
1646				    (modem_status & MSR_DCD) ?
1647				    PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
1648			}
1649		}
1650		line_status = inb(com->line_status_port);
1651
1652		/* input event? (check first to help avoid overruns) */
1653		while (line_status & LSR_RCV_MASK) {
1654			/* break/unnattached error bits or real input? */
1655			if (!(line_status & LSR_RXRDY))
1656				recv_data = 0;
1657			else
1658				recv_data = inb(com->data_port);
1659			if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
1660				/*
1661				 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
1662				 * Otherwise, push the work to a higher level
1663				 * (to handle PARMRK) if we're bypassing.
1664				 * Otherwise, convert BI/FE and PE+INPCK to 0.
1665				 *
1666				 * This makes bypassing work right in the
1667				 * usual "raw" case (IGNBRK set, and IGNPAR
1668				 * and INPCK clear).
1669				 *
1670				 * Note: BI together with FE/PE means just BI.
1671				 */
1672				if (line_status & LSR_BI) {
1673#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
1674					if (com->unit == comconsole) {
1675						breakpoint();
1676						goto cont;
1677					}
1678#endif
1679					if (com->tp == NULL
1680					    || com->tp->t_iflag & IGNBRK)
1681						goto cont;
1682				} else {
1683					if (com->tp == NULL
1684					    || com->tp->t_iflag & IGNPAR)
1685						goto cont;
1686				}
1687				if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
1688				    && (line_status & (LSR_BI | LSR_FE)
1689					|| com->tp->t_iflag & INPCK))
1690					recv_data = 0;
1691			}
1692			++com->bytes_in;
1693			if (com->hotchar != 0 && recv_data == com->hotchar)
1694				setsofttty();
1695			ioptr = com->iptr;
1696			if (ioptr >= com->ibufend)
1697				CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
1698			else {
1699				if (com->do_timestamp)
1700					microtime(&com->timestamp);
1701				++com_events;
1702				schedsofttty();
1703#if 0 /* for testing input latency vs efficiency */
1704if (com->iptr - com->ibuf == 8)
1705	setsofttty();
1706#endif
1707				ioptr[0] = recv_data;
1708				ioptr[com->ierroff] = line_status;
1709				com->iptr = ++ioptr;
1710				if (ioptr == com->ihighwater
1711				    && com->state & CS_RTS_IFLOW)
1712					outb(com->modem_ctl_port,
1713					     com->mcr_image &= ~MCR_RTS);
1714				if (line_status & LSR_OE)
1715					CE_RECORD(com, CE_OVERRUN);
1716			}
1717cont:
1718			/*
1719			 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
1720			 * jump from the top of the loop to here
1721			 */
1722			line_status = inb(com->line_status_port) & 0x7F;
1723		}
1724
1725		/* modem status change? (always check before doing output) */
1726		modem_status = inb(com->modem_status_port);
1727		if (modem_status != com->last_modem_status) {
1728			if (com->do_dcd_timestamp
1729			    && !(com->last_modem_status & MSR_DCD)
1730			    && modem_status & MSR_DCD)
1731				microtime(&com->dcd_timestamp);
1732
1733			/*
1734			 * Schedule high level to handle DCD changes.  Note
1735			 * that we don't use the delta bits anywhere.  Some
1736			 * UARTs mess them up, and it's easy to remember the
1737			 * previous bits and calculate the delta.
1738			 */
1739			com->last_modem_status = modem_status;
1740			if (!(com->state & CS_CHECKMSR)) {
1741				com_events += LOTS_OF_EVENTS;
1742				com->state |= CS_CHECKMSR;
1743				setsofttty();
1744			}
1745
1746			/* handle CTS change immediately for crisp flow ctl */
1747			if (com->state & CS_CTS_OFLOW) {
1748				if (modem_status & MSR_CTS)
1749					com->state |= CS_ODEVREADY;
1750				else
1751					com->state &= ~CS_ODEVREADY;
1752			}
1753		}
1754
1755		/* output queued and everything ready? */
1756		if (line_status & LSR_TXRDY
1757		    && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
1758			ioptr = com->obufq.l_head;
1759			if (com->tx_fifo_size > 1) {
1760				u_int	ocount;
1761
1762				ocount = com->obufq.l_tail - ioptr;
1763				if (ocount > com->tx_fifo_size)
1764					ocount = com->tx_fifo_size;
1765				com->bytes_out += ocount;
1766				do
1767					outb(com->data_port, *ioptr++);
1768				while (--ocount != 0);
1769			} else {
1770				outb(com->data_port, *ioptr++);
1771				++com->bytes_out;
1772			}
1773			com->obufq.l_head = ioptr;
1774			if (COM_IIR_TXRDYBUG(com->flags)) {
1775				int_ctl_new = int_ctl | IER_ETXRDY;
1776			}
1777			if (ioptr >= com->obufq.l_tail) {
1778				struct lbq	*qp;
1779
1780				qp = com->obufq.l_next;
1781				qp->l_queued = FALSE;
1782				qp = qp->l_next;
1783				if (qp != NULL) {
1784					com->obufq.l_head = qp->l_head;
1785					com->obufq.l_tail = qp->l_tail;
1786					com->obufq.l_next = qp;
1787				} else {
1788					/* output just completed */
1789					if ( COM_IIR_TXRDYBUG(com->flags) ) {
1790						int_ctl_new = int_ctl & ~IER_ETXRDY;
1791					}
1792					com->state &= ~CS_BUSY;
1793				}
1794				if (!(com->state & CS_ODONE)) {
1795					com_events += LOTS_OF_EVENTS;
1796					com->state |= CS_ODONE;
1797					setsofttty();	/* handle at high level ASAP */
1798				}
1799			}
1800			if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
1801				outb(com->intr_ctl_port, int_ctl_new);
1802			}
1803		}
1804
1805		/* finished? */
1806#ifndef COM_MULTIPORT
1807		if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
1808#endif /* COM_MULTIPORT */
1809			return;
1810	}
1811}
1812
1813static int
1814sioioctl(dev, cmd, data, flag, p)
1815	dev_t		dev;
1816	u_long		cmd;
1817	caddr_t		data;
1818	int		flag;
1819	struct proc	*p;
1820{
1821	struct com_s	*com;
1822	int		error;
1823	Port_t		iobase;
1824	int		mynor;
1825	int		s;
1826	struct tty	*tp;
1827#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
1828	u_long		oldcmd;
1829	struct termios	term;
1830#endif
1831
1832	mynor = minor(dev);
1833	com = com_addr(MINOR_TO_UNIT(mynor));
1834	if (com->gone)
1835		return (ENODEV);
1836	iobase = com->iobase;
1837	if (mynor & CONTROL_MASK) {
1838		struct termios	*ct;
1839
1840		switch (mynor & CONTROL_MASK) {
1841		case CONTROL_INIT_STATE:
1842			ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
1843			break;
1844		case CONTROL_LOCK_STATE:
1845			ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
1846			break;
1847		default:
1848			return (ENODEV);	/* /dev/nodev */
1849		}
1850		switch (cmd) {
1851		case TIOCSETA:
1852			error = suser(p);
1853			if (error != 0)
1854				return (error);
1855			*ct = *(struct termios *)data;
1856			return (0);
1857		case TIOCGETA:
1858			*(struct termios *)data = *ct;
1859			return (0);
1860		case TIOCGETD:
1861			*(int *)data = TTYDISC;
1862			return (0);
1863		case TIOCGWINSZ:
1864			bzero(data, sizeof(struct winsize));
1865			return (0);
1866		default:
1867			return (ENOTTY);
1868		}
1869	}
1870	tp = com->tp;
1871#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
1872	term = tp->t_termios;
1873	oldcmd = cmd;
1874	error = ttsetcompat(tp, &cmd, data, &term);
1875	if (error != 0)
1876		return (error);
1877	if (cmd != oldcmd)
1878		data = (caddr_t)&term;
1879#endif
1880	if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
1881		int	cc;
1882		struct termios *dt = (struct termios *)data;
1883		struct termios *lt = mynor & CALLOUT_MASK
1884				     ? &com->lt_out : &com->lt_in;
1885
1886		dt->c_iflag = (tp->t_iflag & lt->c_iflag)
1887			      | (dt->c_iflag & ~lt->c_iflag);
1888		dt->c_oflag = (tp->t_oflag & lt->c_oflag)
1889			      | (dt->c_oflag & ~lt->c_oflag);
1890		dt->c_cflag = (tp->t_cflag & lt->c_cflag)
1891			      | (dt->c_cflag & ~lt->c_cflag);
1892		dt->c_lflag = (tp->t_lflag & lt->c_lflag)
1893			      | (dt->c_lflag & ~lt->c_lflag);
1894		for (cc = 0; cc < NCCS; ++cc)
1895			if (lt->c_cc[cc] != 0)
1896				dt->c_cc[cc] = tp->t_cc[cc];
1897		if (lt->c_ispeed != 0)
1898			dt->c_ispeed = tp->t_ispeed;
1899		if (lt->c_ospeed != 0)
1900			dt->c_ospeed = tp->t_ospeed;
1901	}
1902	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1903	if (error != ENOIOCTL)
1904		return (error);
1905	s = spltty();
1906	error = ttioctl(tp, cmd, data, flag);
1907	disc_optim(tp, &tp->t_termios, com);
1908	if (error != ENOIOCTL) {
1909		splx(s);
1910		return (error);
1911	}
1912	switch (cmd) {
1913	case TIOCSBRK:
1914		outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
1915		break;
1916	case TIOCCBRK:
1917		outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1918		break;
1919	case TIOCSDTR:
1920		(void)commctl(com, TIOCM_DTR, DMBIS);
1921		break;
1922	case TIOCCDTR:
1923		(void)commctl(com, TIOCM_DTR, DMBIC);
1924		break;
1925	/*
1926	 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set.  The
1927	 * changes get undone on the next call to comparam().
1928	 */
1929	case TIOCMSET:
1930		(void)commctl(com, *(int *)data, DMSET);
1931		break;
1932	case TIOCMBIS:
1933		(void)commctl(com, *(int *)data, DMBIS);
1934		break;
1935	case TIOCMBIC:
1936		(void)commctl(com, *(int *)data, DMBIC);
1937		break;
1938	case TIOCMGET:
1939		*(int *)data = commctl(com, 0, DMGET);
1940		break;
1941	case TIOCMSDTRWAIT:
1942		/* must be root since the wait applies to following logins */
1943		error = suser(p);
1944		if (error != 0) {
1945			splx(s);
1946			return (error);
1947		}
1948		com->dtr_wait = *(int *)data * hz / 100;
1949		break;
1950	case TIOCMGDTRWAIT:
1951		*(int *)data = com->dtr_wait * 100 / hz;
1952		break;
1953	case TIOCTIMESTAMP:
1954		com->do_timestamp = TRUE;
1955		*(struct timeval *)data = com->timestamp;
1956		break;
1957	case TIOCDCDTIMESTAMP:
1958		com->do_dcd_timestamp = TRUE;
1959		*(struct timeval *)data = com->dcd_timestamp;
1960		break;
1961	default:
1962		splx(s);
1963		error = pps_ioctl(cmd, data, &com->pps);
1964		if (error == ENODEV)
1965			error = ENOTTY;
1966		return (error);
1967	}
1968	splx(s);
1969	return (0);
1970}
1971
1972static void
1973siopoll()
1974{
1975	int		unit;
1976
1977	if (com_events == 0)
1978		return;
1979repeat:
1980	for (unit = 0; unit < NSIOTOT; ++unit) {
1981		struct com_s	*com;
1982		int		incc;
1983		struct tty	*tp;
1984
1985		com = com_addr(unit);
1986		if (com == NULL)
1987			continue;
1988		tp = com->tp;
1989		if (tp == NULL || com->gone) {
1990			/*
1991			 * Discard any events related to never-opened or
1992			 * going-away devices.
1993			 */
1994			disable_intr();
1995			incc = com->iptr - com->ibuf;
1996			com->iptr = com->ibuf;
1997			if (com->state & CS_CHECKMSR) {
1998				incc += LOTS_OF_EVENTS;
1999				com->state &= ~CS_CHECKMSR;
2000			}
2001			com_events -= incc;
2002			enable_intr();
2003			continue;
2004		}
2005		if (com->iptr != com->ibuf) {
2006			disable_intr();
2007			sioinput(com);
2008			enable_intr();
2009		}
2010		if (com->state & CS_CHECKMSR) {
2011			u_char	delta_modem_status;
2012
2013			disable_intr();
2014			delta_modem_status = com->last_modem_status
2015					     ^ com->prev_modem_status;
2016			com->prev_modem_status = com->last_modem_status;
2017			com_events -= LOTS_OF_EVENTS;
2018			com->state &= ~CS_CHECKMSR;
2019			enable_intr();
2020			if (delta_modem_status & MSR_DCD)
2021				(*linesw[tp->t_line].l_modem)
2022					(tp, com->prev_modem_status & MSR_DCD);
2023		}
2024		if (com->state & CS_ODONE) {
2025			disable_intr();
2026			com_events -= LOTS_OF_EVENTS;
2027			com->state &= ~CS_ODONE;
2028			enable_intr();
2029			if (!(com->state & CS_BUSY)
2030			    && !(com->extra_state & CSE_BUSYCHECK)) {
2031				timeout(siobusycheck, com, hz / 100);
2032				com->extra_state |= CSE_BUSYCHECK;
2033			}
2034			(*linesw[tp->t_line].l_start)(tp);
2035		}
2036		if (com_events == 0)
2037			break;
2038	}
2039	if (com_events >= LOTS_OF_EVENTS)
2040		goto repeat;
2041}
2042
2043static int
2044comparam(tp, t)
2045	struct tty	*tp;
2046	struct termios	*t;
2047{
2048	u_int		cfcr;
2049	int		cflag;
2050	struct com_s	*com;
2051	int		divisor;
2052	u_char		dlbh;
2053	u_char		dlbl;
2054	Port_t		iobase;
2055	int		s;
2056	int		unit;
2057
2058	/* do historical conversions */
2059	if (t->c_ispeed == 0)
2060		t->c_ispeed = t->c_ospeed;
2061
2062	/* check requested parameters */
2063	divisor = ttspeedtab(t->c_ospeed, comspeedtab);
2064	if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed))
2065		return (EINVAL);
2066
2067	/* parameters are OK, convert them to the com struct and the device */
2068	unit = DEV_TO_UNIT(tp->t_dev);
2069	com = com_addr(unit);
2070	iobase = com->iobase;
2071	s = spltty();
2072	if (divisor == 0)
2073		(void)commctl(com, TIOCM_DTR, DMBIC);	/* hang up line */
2074	else
2075		(void)commctl(com, TIOCM_DTR, DMBIS);
2076	cflag = t->c_cflag;
2077	switch (cflag & CSIZE) {
2078	case CS5:
2079		cfcr = CFCR_5BITS;
2080		break;
2081	case CS6:
2082		cfcr = CFCR_6BITS;
2083		break;
2084	case CS7:
2085		cfcr = CFCR_7BITS;
2086		break;
2087	default:
2088		cfcr = CFCR_8BITS;
2089		break;
2090	}
2091	if (cflag & PARENB) {
2092		cfcr |= CFCR_PENAB;
2093		if (!(cflag & PARODD))
2094			cfcr |= CFCR_PEVEN;
2095	}
2096	if (cflag & CSTOPB)
2097		cfcr |= CFCR_STOPB;
2098
2099	if (com->hasfifo && divisor != 0) {
2100		/*
2101		 * Use a fifo trigger level low enough so that the input
2102		 * latency from the fifo is less than about 16 msec and
2103		 * the total latency is less than about 30 msec.  These
2104		 * latencies are reasonable for humans.  Serial comms
2105		 * protocols shouldn't expect anything better since modem
2106		 * latencies are larger.
2107		 */
2108		com->fifo_image = t->c_ospeed <= 4800
2109				  ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
2110#ifdef COM_ESP
2111		/*
2112		 * The Hayes ESP card needs the fifo DMA mode bit set
2113		 * in compatibility mode.  If not, it will interrupt
2114		 * for each character received.
2115		 */
2116		if (com->esp)
2117			com->fifo_image |= FIFO_DMA_MODE;
2118#endif
2119		outb(iobase + com_fifo, com->fifo_image);
2120	}
2121
2122	/*
2123	 * This returns with interrupts disabled so that we can complete
2124	 * the speed change atomically.  Keeping interrupts disabled is
2125	 * especially important while com_data is hidden.
2126	 */
2127	(void) siosetwater(com, t->c_ispeed);
2128
2129	if (divisor != 0) {
2130		outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
2131		/*
2132		 * Only set the divisor registers if they would change,
2133		 * since on some 16550 incompatibles (UMC8669F), setting
2134		 * them while input is arriving them loses sync until
2135		 * data stops arriving.
2136		 */
2137		dlbl = divisor & 0xFF;
2138		if (inb(iobase + com_dlbl) != dlbl)
2139			outb(iobase + com_dlbl, dlbl);
2140		dlbh = (u_int) divisor >> 8;
2141		if (inb(iobase + com_dlbh) != dlbh)
2142			outb(iobase + com_dlbh, dlbh);
2143	}
2144
2145
2146	outb(iobase + com_cfcr, com->cfcr_image = cfcr);
2147
2148	if (!(tp->t_state & TS_TTSTOP))
2149		com->state |= CS_TTGO;
2150
2151	if (cflag & CRTS_IFLOW) {
2152		if (com->st16650a) {
2153			outb(iobase + com_cfcr, 0xbf);
2154			outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
2155		}
2156		com->state |= CS_RTS_IFLOW;
2157		/*
2158		 * If CS_RTS_IFLOW just changed from off to on, the change
2159		 * needs to be propagated to MCR_RTS.  This isn't urgent,
2160		 * so do it later by calling comstart() instead of repeating
2161		 * a lot of code from comstart() here.
2162		 */
2163	} else if (com->state & CS_RTS_IFLOW) {
2164		com->state &= ~CS_RTS_IFLOW;
2165		/*
2166		 * CS_RTS_IFLOW just changed from on to off.  Force MCR_RTS
2167		 * on here, since comstart() won't do it later.
2168		 */
2169		outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2170		if (com->st16650a) {
2171			outb(iobase + com_cfcr, 0xbf);
2172			outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
2173		}
2174	}
2175
2176
2177	/*
2178	 * Set up state to handle output flow control.
2179	 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2180	 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2181	 */
2182	com->state |= CS_ODEVREADY;
2183	com->state &= ~CS_CTS_OFLOW;
2184	if (cflag & CCTS_OFLOW) {
2185		com->state |= CS_CTS_OFLOW;
2186		if (!(com->last_modem_status & MSR_CTS))
2187			com->state &= ~CS_ODEVREADY;
2188		if (com->st16650a) {
2189			outb(iobase + com_cfcr, 0xbf);
2190			outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
2191		}
2192	} else {
2193		if (com->st16650a) {
2194			outb(iobase + com_cfcr, 0xbf);
2195			outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
2196		}
2197	}
2198
2199
2200	outb(iobase + com_cfcr, com->cfcr_image);
2201
2202
2203	/* XXX shouldn't call functions while intrs are disabled. */
2204	disc_optim(tp, t, com);
2205	/*
2206	 * Recover from fiddling with CS_TTGO.  We used to call siointr1()
2207	 * unconditionally, but that defeated the careful discarding of
2208	 * stale input in sioopen().
2209	 */
2210	if (com->state >= (CS_BUSY | CS_TTGO))
2211		siointr1(com);
2212
2213	enable_intr();
2214	splx(s);
2215	comstart(tp);
2216	if (com->ibufold != NULL) {
2217		free(com->ibufold, M_DEVBUF);
2218		com->ibufold = NULL;
2219	}
2220	return (0);
2221}
2222
2223static int
2224siosetwater(com, speed)
2225	struct com_s	*com;
2226	speed_t		speed;
2227{
2228	int		cp4ticks;
2229	u_char		*ibuf;
2230	int		ibufsize;
2231	struct tty	*tp;
2232
2233	/*
2234	 * Make the buffer size large enough to handle a softtty interrupt
2235	 * latency of about 2 ticks without loss of throughput or data
2236	 * (about 3 ticks if input flow control is not used or not honoured,
2237	 * but a bit less for CS5-CS7 modes).
2238	 */
2239	cp4ticks = speed / 10 / hz * 4;
2240	for (ibufsize = 128; ibufsize < cp4ticks;)
2241		ibufsize <<= 1;
2242	if (ibufsize == com->ibufsize) {
2243		disable_intr();
2244		return (0);
2245	}
2246
2247	/*
2248	 * Allocate input buffer.  The extra factor of 2 in the size is
2249	 * to allow for an error byte for each input byte.
2250	 */
2251	ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
2252	if (ibuf == NULL) {
2253		disable_intr();
2254		return (ENOMEM);
2255	}
2256
2257	/* Initialize non-critical variables. */
2258	com->ibufold = com->ibuf;
2259	com->ibufsize = ibufsize;
2260	tp = com->tp;
2261	if (tp != NULL) {
2262		tp->t_ififosize = 2 * ibufsize;
2263		tp->t_ispeedwat = (speed_t)-1;
2264		tp->t_ospeedwat = (speed_t)-1;
2265	}
2266
2267	/*
2268	 * Read current input buffer, if any.  Continue with interrupts
2269	 * disabled.
2270	 */
2271	disable_intr();
2272	if (com->iptr != com->ibuf)
2273		sioinput(com);
2274
2275	/*-
2276	 * Initialize critical variables, including input buffer watermarks.
2277	 * The external device is asked to stop sending when the buffer
2278	 * exactly reaches high water, or when the high level requests it.
2279	 * The high level is notified immediately (rather than at a later
2280	 * clock tick) when this watermark is reached.
2281	 * The buffer size is chosen so the watermark should almost never
2282	 * be reached.
2283	 * The low watermark is invisibly 0 since the buffer is always
2284	 * emptied all at once.
2285	 */
2286	com->iptr = com->ibuf = ibuf;
2287	com->ibufend = ibuf + ibufsize;
2288	com->ierroff = ibufsize;
2289	com->ihighwater = ibuf + 3 * ibufsize / 4;
2290	return (0);
2291}
2292
2293static void
2294comstart(tp)
2295	struct tty	*tp;
2296{
2297	struct com_s	*com;
2298	int		s;
2299	int		unit;
2300
2301	unit = DEV_TO_UNIT(tp->t_dev);
2302	com = com_addr(unit);
2303	s = spltty();
2304	disable_intr();
2305	if (tp->t_state & TS_TTSTOP)
2306		com->state &= ~CS_TTGO;
2307	else
2308		com->state |= CS_TTGO;
2309	if (tp->t_state & TS_TBLOCK) {
2310		if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2311			outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2312	} else {
2313		if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2314		    && com->state & CS_RTS_IFLOW)
2315			outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2316	}
2317	enable_intr();
2318	if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2319		ttwwakeup(tp);
2320		splx(s);
2321		return;
2322	}
2323	if (tp->t_outq.c_cc != 0) {
2324		struct lbq	*qp;
2325		struct lbq	*next;
2326
2327		if (!com->obufs[0].l_queued) {
2328			com->obufs[0].l_tail
2329			    = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2330						  sizeof com->obuf1);
2331			com->obufs[0].l_next = NULL;
2332			com->obufs[0].l_queued = TRUE;
2333			disable_intr();
2334			if (com->state & CS_BUSY) {
2335				qp = com->obufq.l_next;
2336				while ((next = qp->l_next) != NULL)
2337					qp = next;
2338				qp->l_next = &com->obufs[0];
2339			} else {
2340				com->obufq.l_head = com->obufs[0].l_head;
2341				com->obufq.l_tail = com->obufs[0].l_tail;
2342				com->obufq.l_next = &com->obufs[0];
2343				com->state |= CS_BUSY;
2344			}
2345			enable_intr();
2346		}
2347		if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2348			com->obufs[1].l_tail
2349			    = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2350						  sizeof com->obuf2);
2351			com->obufs[1].l_next = NULL;
2352			com->obufs[1].l_queued = TRUE;
2353			disable_intr();
2354			if (com->state & CS_BUSY) {
2355				qp = com->obufq.l_next;
2356				while ((next = qp->l_next) != NULL)
2357					qp = next;
2358				qp->l_next = &com->obufs[1];
2359			} else {
2360				com->obufq.l_head = com->obufs[1].l_head;
2361				com->obufq.l_tail = com->obufs[1].l_tail;
2362				com->obufq.l_next = &com->obufs[1];
2363				com->state |= CS_BUSY;
2364			}
2365			enable_intr();
2366		}
2367		tp->t_state |= TS_BUSY;
2368	}
2369	disable_intr();
2370	if (com->state >= (CS_BUSY | CS_TTGO))
2371		siointr1(com);	/* fake interrupt to start output */
2372	enable_intr();
2373	ttwwakeup(tp);
2374	splx(s);
2375}
2376
2377static void
2378siostop(tp, rw)
2379	struct tty	*tp;
2380	int		rw;
2381{
2382	struct com_s	*com;
2383
2384	com = com_addr(DEV_TO_UNIT(tp->t_dev));
2385	if (com->gone)
2386		return;
2387	disable_intr();
2388	if (rw & FWRITE) {
2389		if (com->hasfifo)
2390#ifdef COM_ESP
2391		    /* XXX avoid h/w bug. */
2392		    if (!com->esp)
2393#endif
2394			outb(com->iobase + com_fifo,
2395			     FIFO_XMT_RST | com->fifo_image);
2396		com->obufs[0].l_queued = FALSE;
2397		com->obufs[1].l_queued = FALSE;
2398		if (com->state & CS_ODONE)
2399			com_events -= LOTS_OF_EVENTS;
2400		com->state &= ~(CS_ODONE | CS_BUSY);
2401		com->tp->t_state &= ~TS_BUSY;
2402	}
2403	if (rw & FREAD) {
2404		if (com->hasfifo)
2405#ifdef COM_ESP
2406		    /* XXX avoid h/w bug. */
2407		    if (!com->esp)
2408#endif
2409			outb(com->iobase + com_fifo,
2410			     FIFO_RCV_RST | com->fifo_image);
2411		com_events -= (com->iptr - com->ibuf);
2412		com->iptr = com->ibuf;
2413	}
2414	enable_intr();
2415	comstart(tp);
2416}
2417
2418static struct tty *
2419siodevtotty(dev)
2420	dev_t	dev;
2421{
2422	int	mynor;
2423	int	unit;
2424
2425	mynor = minor(dev);
2426	if (mynor & CONTROL_MASK)
2427		return (NULL);
2428	unit = MINOR_TO_UNIT(mynor);
2429	if ((u_int) unit >= NSIOTOT)
2430		return (NULL);
2431	return (dev->si_tty);
2432}
2433
2434static int
2435commctl(com, bits, how)
2436	struct com_s	*com;
2437	int		bits;
2438	int		how;
2439{
2440	int	mcr;
2441	int	msr;
2442
2443	if (how == DMGET) {
2444		bits = TIOCM_LE;	/* XXX - always enabled while open */
2445		mcr = com->mcr_image;
2446		if (mcr & MCR_DTR)
2447			bits |= TIOCM_DTR;
2448		if (mcr & MCR_RTS)
2449			bits |= TIOCM_RTS;
2450		msr = com->prev_modem_status;
2451		if (msr & MSR_CTS)
2452			bits |= TIOCM_CTS;
2453		if (msr & MSR_DCD)
2454			bits |= TIOCM_CD;
2455		if (msr & MSR_DSR)
2456			bits |= TIOCM_DSR;
2457		/*
2458		 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
2459		 * more volatile by reading the modem status a lot.  Perhaps
2460		 * we should latch both bits until the status is read here.
2461		 */
2462		if (msr & (MSR_RI | MSR_TERI))
2463			bits |= TIOCM_RI;
2464		return (bits);
2465	}
2466	mcr = 0;
2467	if (bits & TIOCM_DTR)
2468		mcr |= MCR_DTR;
2469	if (bits & TIOCM_RTS)
2470		mcr |= MCR_RTS;
2471	if (com->gone)
2472		return(0);
2473	disable_intr();
2474	switch (how) {
2475	case DMSET:
2476		outb(com->modem_ctl_port,
2477		     com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
2478		break;
2479	case DMBIS:
2480		outb(com->modem_ctl_port, com->mcr_image |= mcr);
2481		break;
2482	case DMBIC:
2483		outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
2484		break;
2485	}
2486	enable_intr();
2487	return (0);
2488}
2489
2490static void
2491siosettimeout()
2492{
2493	struct com_s	*com;
2494	bool_t		someopen;
2495	int		unit;
2496
2497	/*
2498	 * Set our timeout period to 1 second if no polled devices are open.
2499	 * Otherwise set it to max(1/200, 1/hz).
2500	 * Enable timeouts iff some device is open.
2501	 */
2502	untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2503	sio_timeout = hz;
2504	someopen = FALSE;
2505	for (unit = 0; unit < NSIOTOT; ++unit) {
2506		com = com_addr(unit);
2507		if (com != NULL && com->tp != NULL
2508		    && com->tp->t_state & TS_ISOPEN && !com->gone) {
2509			someopen = TRUE;
2510			if (com->poll || com->poll_output) {
2511				sio_timeout = hz > 200 ? hz / 200 : 1;
2512				break;
2513			}
2514		}
2515	}
2516	if (someopen) {
2517		sio_timeouts_until_log = hz / sio_timeout;
2518		sio_timeout_handle = timeout(comwakeup, (void *)NULL,
2519					     sio_timeout);
2520	} else {
2521		/* Flush error messages, if any. */
2522		sio_timeouts_until_log = 1;
2523		comwakeup((void *)NULL);
2524		untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2525	}
2526}
2527
2528static void
2529comwakeup(chan)
2530	void	*chan;
2531{
2532	struct com_s	*com;
2533	int		unit;
2534
2535	sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
2536
2537	/*
2538	 * Recover from lost output interrupts.
2539	 * Poll any lines that don't use interrupts.
2540	 */
2541	for (unit = 0; unit < NSIOTOT; ++unit) {
2542		com = com_addr(unit);
2543		if (com != NULL && !com->gone
2544		    && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
2545			disable_intr();
2546			siointr1(com);
2547			enable_intr();
2548		}
2549	}
2550
2551	/*
2552	 * Check for and log errors, but not too often.
2553	 */
2554	if (--sio_timeouts_until_log > 0)
2555		return;
2556	sio_timeouts_until_log = hz / sio_timeout;
2557	for (unit = 0; unit < NSIOTOT; ++unit) {
2558		int	errnum;
2559
2560		com = com_addr(unit);
2561		if (com == NULL)
2562			continue;
2563		if (com->gone)
2564			continue;
2565		for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2566			u_int	delta;
2567			u_long	total;
2568
2569			disable_intr();
2570			delta = com->delta_error_counts[errnum];
2571			com->delta_error_counts[errnum] = 0;
2572			enable_intr();
2573			if (delta == 0)
2574				continue;
2575			total = com->error_counts[errnum] += delta;
2576			log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2577			    unit, delta, error_desc[errnum],
2578			    delta == 1 ? "" : "s", total);
2579		}
2580	}
2581}
2582
2583static void
2584disc_optim(tp, t, com)
2585	struct tty	*tp;
2586	struct termios	*t;
2587	struct com_s	*com;
2588{
2589	if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
2590	    && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
2591	    && (!(t->c_iflag & PARMRK)
2592		|| (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
2593	    && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
2594	    && linesw[tp->t_line].l_rint == ttyinput)
2595		tp->t_state |= TS_CAN_BYPASS_L_RINT;
2596	else
2597		tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
2598	com->hotchar = linesw[tp->t_line].l_hotchar;
2599}
2600
2601/*
2602 * Following are all routines needed for SIO to act as console
2603 */
2604#include <sys/cons.h>
2605
2606struct siocnstate {
2607	u_char	dlbl;
2608	u_char	dlbh;
2609	u_char	ier;
2610	u_char	cfcr;
2611	u_char	mcr;
2612};
2613
2614static speed_t siocngetspeed __P((Port_t, struct speedtab *));
2615static void siocnclose	__P((struct siocnstate *sp, Port_t iobase));
2616static void siocnopen	__P((struct siocnstate *sp, Port_t iobase, int speed));
2617static void siocntxwait	__P((Port_t iobase));
2618
2619static cn_probe_t siocnprobe;
2620static cn_init_t siocninit;
2621static cn_checkc_t siocncheckc;
2622static cn_getc_t siocngetc;
2623static cn_putc_t siocnputc;
2624
2625#ifdef __i386__
2626CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, siocnputc);
2627
2628#endif
2629
2630/* To get the GDB related variables */
2631#if DDB > 0
2632#include <ddb/ddb.h>
2633#endif
2634
2635static void
2636siocntxwait(iobase)
2637	Port_t	iobase;
2638{
2639	int	timo;
2640
2641	/*
2642	 * Wait for any pending transmission to finish.  Required to avoid
2643	 * the UART lockup bug when the speed is changed, and for normal
2644	 * transmits.
2645	 */
2646	timo = 100000;
2647	while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
2648	       != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
2649		;
2650}
2651
2652/*
2653 * Read the serial port specified and try to figure out what speed
2654 * it's currently running at.  We're assuming the serial port has
2655 * been initialized and is basicly idle.  This routine is only intended
2656 * to be run at system startup.
2657 *
2658 * If the value read from the serial port doesn't make sense, return 0.
2659 */
2660
2661static speed_t
2662siocngetspeed(iobase, table)
2663	Port_t iobase;
2664	struct speedtab *table;
2665{
2666	int	code;
2667	u_char	dlbh;
2668	u_char	dlbl;
2669	u_char  cfcr;
2670
2671	cfcr = inb(iobase + com_cfcr);
2672	outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2673
2674	dlbl = inb(iobase + com_dlbl);
2675	dlbh = inb(iobase + com_dlbh);
2676
2677	outb(iobase + com_cfcr, cfcr);
2678
2679	code = dlbh << 8 | dlbl;
2680
2681	for ( ; table->sp_speed != -1; table++)
2682		if (table->sp_code == code)
2683			return (table->sp_speed);
2684
2685	return 0;	/* didn't match anything sane */
2686}
2687
2688static void
2689siocnopen(sp, iobase, speed)
2690	struct siocnstate	*sp;
2691	Port_t			iobase;
2692	int			speed;
2693{
2694	int	divisor;
2695	u_char	dlbh;
2696	u_char	dlbl;
2697
2698	/*
2699	 * Save all the device control registers except the fifo register
2700	 * and set our default ones (cs8 -parenb speed=comdefaultrate).
2701	 * We can't save the fifo register since it is read-only.
2702	 */
2703	sp->ier = inb(iobase + com_ier);
2704	outb(iobase + com_ier, 0);	/* spltty() doesn't stop siointr() */
2705	siocntxwait(iobase);
2706	sp->cfcr = inb(iobase + com_cfcr);
2707	outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2708	sp->dlbl = inb(iobase + com_dlbl);
2709	sp->dlbh = inb(iobase + com_dlbh);
2710	/*
2711	 * Only set the divisor registers if they would change, since on
2712	 * some 16550 incompatibles (Startech), setting them clears the
2713	 * data input register.  This also reduces the effects of the
2714	 * UMC8669F bug.
2715	 */
2716	divisor = ttspeedtab(speed, comspeedtab);
2717	dlbl = divisor & 0xFF;
2718	if (sp->dlbl != dlbl)
2719		outb(iobase + com_dlbl, dlbl);
2720	dlbh = (u_int) divisor >> 8;
2721	if (sp->dlbh != dlbh)
2722		outb(iobase + com_dlbh, dlbh);
2723	outb(iobase + com_cfcr, CFCR_8BITS);
2724	sp->mcr = inb(iobase + com_mcr);
2725	/*
2726	 * We don't want interrupts, but must be careful not to "disable"
2727	 * them by clearing the MCR_IENABLE bit, since that might cause
2728	 * an interrupt by floating the IRQ line.
2729	 */
2730	outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
2731}
2732
2733static void
2734siocnclose(sp, iobase)
2735	struct siocnstate	*sp;
2736	Port_t			iobase;
2737{
2738	/*
2739	 * Restore the device control registers.
2740	 */
2741	siocntxwait(iobase);
2742	outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2743	if (sp->dlbl != inb(iobase + com_dlbl))
2744		outb(iobase + com_dlbl, sp->dlbl);
2745	if (sp->dlbh != inb(iobase + com_dlbh))
2746		outb(iobase + com_dlbh, sp->dlbh);
2747	outb(iobase + com_cfcr, sp->cfcr);
2748	/*
2749	 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
2750	 */
2751	outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
2752	outb(iobase + com_ier, sp->ier);
2753}
2754
2755static void
2756siocnprobe(cp)
2757	struct consdev	*cp;
2758{
2759	speed_t			boot_speed;
2760	u_char			cfcr;
2761	int			s, unit;
2762	struct siocnstate	sp;
2763
2764	/*
2765	 * Find our first enabled console, if any.  If it is a high-level
2766	 * console device, then initialize it and return successfully.
2767	 * If it is a low-level console device, then initialize it and
2768	 * return unsuccessfully.  It must be initialized in both cases
2769	 * for early use by console drivers and debuggers.  Initializing
2770	 * the hardware is not necessary in all cases, since the i/o
2771	 * routines initialize it on the fly, but it is necessary if
2772	 * input might arrive while the hardware is switched back to an
2773	 * uninitialized state.  We can't handle multiple console devices
2774	 * yet because our low-level routines don't take a device arg.
2775	 * We trust the user to set the console flags properly so that we
2776	 * don't need to probe.
2777	 */
2778	cp->cn_pri = CN_DEAD;
2779
2780	for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
2781		int flags;
2782		int disabled;
2783		if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
2784			if (disabled)
2785				continue;
2786		}
2787		if (resource_int_value("sio", unit, "flags", &flags))
2788			continue;
2789		if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
2790			int port;
2791			Port_t iobase;
2792
2793			if (resource_int_value("sio", unit, "port", &port))
2794				continue;
2795			iobase = port;
2796			s = spltty();
2797			if (boothowto & RB_SERIAL) {
2798				boot_speed = siocngetspeed(iobase, comspeedtab);
2799				if (boot_speed)
2800					comdefaultrate = boot_speed;
2801			}
2802
2803			/*
2804			 * Initialize the divisor latch.  We can't rely on
2805			 * siocnopen() to do this the first time, since it
2806			 * avoids writing to the latch if the latch appears
2807			 * to have the correct value.  Also, if we didn't
2808			 * just read the speed from the hardware, then we
2809			 * need to set the speed in hardware so that
2810			 * switching it later is null.
2811			 */
2812			cfcr = inb(iobase + com_cfcr);
2813			outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2814			outb(iobase + com_dlbl,
2815			     COMBRD(comdefaultrate) & 0xff);
2816			outb(iobase + com_dlbh,
2817			     (u_int) COMBRD(comdefaultrate) >> 8);
2818			outb(iobase + com_cfcr, cfcr);
2819
2820			siocnopen(&sp, iobase, comdefaultrate);
2821
2822			splx(s);
2823			if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
2824				cp->cn_dev = makedev(CDEV_MAJOR, unit);
2825				cp->cn_pri = COM_FORCECONSOLE(flags)
2826					     || boothowto & RB_SERIAL
2827					     ? CN_REMOTE : CN_NORMAL;
2828				siocniobase = iobase;
2829				siocnunit = unit;
2830			}
2831			if (COM_DEBUGGER(flags)) {
2832				printf("sio%d: gdb debugging port\n", unit);
2833				siogdbiobase = iobase;
2834				siogdbunit = unit;
2835#if DDB > 0
2836				gdbdev = makedev(CDEV_MAJOR, unit);
2837				gdb_getc = siocngetc;
2838				gdb_putc = siocnputc;
2839#endif
2840			}
2841		}
2842	}
2843#ifdef	__i386__
2844#if DDB > 0
2845	/*
2846	 * XXX Ugly Compatability.
2847	 * If no gdb port has been specified, set it to be the console
2848	 * as some configuration files don't specify the gdb port.
2849	 */
2850	if (gdbdev == NODEV && (boothowto & RB_GDB)) {
2851		printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
2852			siocnunit);
2853		printf("Set flag 0x80 on desired GDB port in your\n");
2854		printf("configuration file (currently sio only).\n");
2855		siogdbiobase = siocniobase;
2856		siogdbunit = siocnunit;
2857		gdbdev = makedev(CDEV_MAJOR, siocnunit);
2858		gdb_getc = siocngetc;
2859		gdb_putc = siocnputc;
2860	}
2861#endif
2862#endif
2863}
2864
2865#ifdef __alpha__
2866
2867CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc);
2868
2869int
2870siocnattach(port, speed)
2871	int port;
2872	int speed;
2873{
2874	int			s;
2875	u_char			cfcr;
2876	struct siocnstate	sp;
2877
2878	siocniobase = port;
2879	comdefaultrate = speed;
2880	sio_consdev.cn_pri = CN_NORMAL;
2881	sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
2882
2883	s = spltty();
2884
2885	/*
2886	 * Initialize the divisor latch.  We can't rely on
2887	 * siocnopen() to do this the first time, since it
2888	 * avoids writing to the latch if the latch appears
2889	 * to have the correct value.  Also, if we didn't
2890	 * just read the speed from the hardware, then we
2891	 * need to set the speed in hardware so that
2892	 * switching it later is null.
2893	 */
2894	cfcr = inb(siocniobase + com_cfcr);
2895	outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
2896	outb(siocniobase + com_dlbl,
2897	     COMBRD(comdefaultrate) & 0xff);
2898	outb(siocniobase + com_dlbh,
2899	     (u_int) COMBRD(comdefaultrate) >> 8);
2900	outb(siocniobase + com_cfcr, cfcr);
2901
2902	siocnopen(&sp, siocniobase, comdefaultrate);
2903	splx(s);
2904
2905	cn_tab = &sio_consdev;
2906	return 0;
2907}
2908
2909int
2910siogdbattach(port, speed)
2911	int port;
2912	int speed;
2913{
2914	int			s;
2915	u_char			cfcr;
2916	struct siocnstate	sp;
2917
2918	siogdbiobase = port;
2919	gdbdefaultrate = speed;
2920
2921	s = spltty();
2922
2923	/*
2924	 * Initialize the divisor latch.  We can't rely on
2925	 * siocnopen() to do this the first time, since it
2926	 * avoids writing to the latch if the latch appears
2927	 * to have the correct value.  Also, if we didn't
2928	 * just read the speed from the hardware, then we
2929	 * need to set the speed in hardware so that
2930	 * switching it later is null.
2931	 */
2932	cfcr = inb(siogdbiobase + com_cfcr);
2933	outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
2934	outb(siogdbiobase + com_dlbl,
2935	     COMBRD(gdbdefaultrate) & 0xff);
2936	outb(siogdbiobase + com_dlbh,
2937	     (u_int) COMBRD(gdbdefaultrate) >> 8);
2938	outb(siogdbiobase + com_cfcr, cfcr);
2939
2940	siocnopen(&sp, siogdbiobase, gdbdefaultrate);
2941	splx(s);
2942
2943	return 0;
2944}
2945
2946#endif
2947
2948static void
2949siocninit(cp)
2950	struct consdev	*cp;
2951{
2952	comconsole = DEV_TO_UNIT(cp->cn_dev);
2953}
2954
2955static int
2956siocncheckc(dev)
2957	dev_t	dev;
2958{
2959	int	c;
2960	Port_t	iobase;
2961	int	s;
2962	struct siocnstate	sp;
2963
2964	if (minor(dev) == siogdbunit)
2965		iobase = siogdbiobase;
2966	else
2967		iobase = siocniobase;
2968	s = spltty();
2969	siocnopen(&sp, iobase, comdefaultrate);
2970	if (inb(iobase + com_lsr) & LSR_RXRDY)
2971		c = inb(iobase + com_data);
2972	else
2973		c = -1;
2974	siocnclose(&sp, iobase);
2975	splx(s);
2976	return (c);
2977}
2978
2979
2980int
2981siocngetc(dev)
2982	dev_t	dev;
2983{
2984	int	c;
2985	Port_t	iobase;
2986	int	s;
2987	struct siocnstate	sp;
2988
2989	if (minor(dev) == siogdbunit)
2990		iobase = siogdbiobase;
2991	else
2992		iobase = siocniobase;
2993	s = spltty();
2994	siocnopen(&sp, iobase, comdefaultrate);
2995	while (!(inb(iobase + com_lsr) & LSR_RXRDY))
2996		;
2997	c = inb(iobase + com_data);
2998	siocnclose(&sp, iobase);
2999	splx(s);
3000	return (c);
3001}
3002
3003void
3004siocnputc(dev, c)
3005	dev_t	dev;
3006	int	c;
3007{
3008	int	s;
3009	struct siocnstate	sp;
3010	Port_t	iobase;
3011
3012	if (minor(dev) == siogdbunit)
3013		iobase = siogdbiobase;
3014	else
3015		iobase = siocniobase;
3016	s = spltty();
3017	siocnopen(&sp, iobase, comdefaultrate);
3018	siocntxwait(iobase);
3019	outb(iobase + com_data, c);
3020	siocnclose(&sp, iobase);
3021	splx(s);
3022}
3023
3024#ifdef __alpha__
3025int
3026siogdbgetc()
3027{
3028	int	c;
3029	Port_t	iobase;
3030	int	s;
3031	struct siocnstate	sp;
3032
3033	iobase = siogdbiobase;
3034	s = spltty();
3035	siocnopen(&sp, iobase, gdbdefaultrate);
3036	while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3037		;
3038	c = inb(iobase + com_data);
3039	siocnclose(&sp, iobase);
3040	splx(s);
3041	return (c);
3042}
3043
3044void
3045siogdbputc(c)
3046	int	c;
3047{
3048	int	s;
3049	struct siocnstate	sp;
3050
3051	s = spltty();
3052	siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3053	siocntxwait(siogdbiobase);
3054	outb(siogdbiobase + com_data, c);
3055	siocnclose(&sp, siogdbiobase);
3056	splx(s);
3057}
3058#endif
3059
3060DEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass, sio_cdevsw, 0, 0);
3061