if_sfreg.h revision 162317
1139825Simp/*- 249076Swpaul * Copyright (c) 1997, 1998, 1999 349076Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 449076Swpaul * 549076Swpaul * Redistribution and use in source and binary forms, with or without 649076Swpaul * modification, are permitted provided that the following conditions 749076Swpaul * are met: 849076Swpaul * 1. Redistributions of source code must retain the above copyright 949076Swpaul * notice, this list of conditions and the following disclaimer. 1049076Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1149076Swpaul * notice, this list of conditions and the following disclaimer in the 1249076Swpaul * documentation and/or other materials provided with the distribution. 1349076Swpaul * 3. All advertising materials mentioning features or use of this software 1449076Swpaul * must display the following acknowledgement: 1549076Swpaul * This product includes software developed by Bill Paul. 1649076Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1749076Swpaul * may be used to endorse or promote products derived from this software 1849076Swpaul * without specific prior written permission. 1949076Swpaul * 2049076Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2149076Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2249076Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2349076Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2449076Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2549076Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2649076Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2749076Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2849076Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2949076Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3049076Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3149076Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/sf/if_sfreg.h 162317 2006-09-15 11:01:23Z ru $ 3349076Swpaul */ 3449076Swpaul 3549076Swpaul/* 3649076Swpaul * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 3749076Swpaul * register space. These registers can be accessed in the following way: 3849076Swpaul * - PCI config registers are always accessible through PCI config space 3949076Swpaul * - Full 512K space mapped into memory using PCI memory mapped access 4049076Swpaul * - 256-byte I/O space mapped through PCI I/O access 4149076Swpaul * - Full 512K space mapped through indirect I/O using PCI I/O access 4249076Swpaul * It's possible to use either memory mapped mode or I/O mode to access 4349076Swpaul * the registers, but memory mapped is usually the easiest. All registers 4449076Swpaul * are 32 bits wide and must be accessed using 32-bit operations. 4549076Swpaul */ 4649076Swpaul 4749076Swpaul/* 4849076Swpaul * Adaptec PCI vendor ID. 4949076Swpaul */ 5049076Swpaul#define AD_VENDORID 0x9004 5149076Swpaul 5249076Swpaul/* 5349076Swpaul * AIC-6915 PCI device ID. 5449076Swpaul */ 5549076Swpaul#define AD_DEVICEID_STARFIRE 0x6915 5649076Swpaul 5749076Swpaul/* 5849076Swpaul * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 5949076Swpaul * the exact kind of NIC on which the ASIC is mounted. Currently there 6049076Swpaul * are six different variations. Note: the Adaptec manual lists code 0x28 6149076Swpaul * for two different NICs: the 62044 and the 69011/TX. This is a typo: 6249076Swpaul * the code for the 62044 is really 0x18. 6353468Swpaul * 6453468Swpaul * Note that there also appears to be an 0x19 code for a newer rev 6553468Swpaul * 62044 card. 6649076Swpaul */ 6749076Swpaul#define AD_SUBSYSID_62011_REV0 0x0008 /* single port 10/100baseTX 64-bit */ 6849076Swpaul#define AD_SUBSYSID_62011_REV1 0x0009 /* single port 10/100baseTX 64-bit */ 6949076Swpaul#define AD_SUBSYSID_62022 0x0010 /* dual port 10/100baseTX 64-bit */ 7053468Swpaul#define AD_SUBSYSID_62044_REV0 0x0018 /* quad port 10/100baseTX 64-bit */ 7153468Swpaul#define AD_SUBSYSID_62044_REV1 0x0019 /* quad port 10/100baseTX 64-bit */ 7249076Swpaul#define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit */ 7349076Swpaul#define AD_SUBSYSID_69011 0x0028 /* single port 10/100baseTX 32-bit */ 7449076Swpaul 7549076Swpaul/* 7649076Swpaul * Starfire internal register space map. The entire register space 7749076Swpaul * is available using PCI memory mapped mode. The SF_RMAP_INTREG 7849076Swpaul * space is available using PCI I/O mode. The entire space can be 7949076Swpaul * accessed using indirect I/O using the indirect I/O addr and 8049076Swpaul * indirect I/O data registers located within the SF_RMAP_INTREG space. 8149076Swpaul */ 8249076Swpaul#define SF_RMAP_ROMADDR_BASE 0x00000 /* Expansion ROM space */ 8349076Swpaul#define SF_RMAP_ROMADDR_MAX 0x3FFFF 8449076Swpaul 8549076Swpaul#define SF_RMAP_EXGPIO_BASE 0x40000 /* External general purpose regs */ 8649076Swpaul#define SF_RMAP_EXGPIO_MAX 0x3FFFF 8749076Swpaul 8849076Swpaul#define SF_RMAP_INTREG_BASE 0x50000 /* Internal functional registers */ 8949076Swpaul#define SF_RMAP_INTREG_MAX 0x500FF 9049076Swpaul#define SF_RMAP_GENREG_BASE 0x50100 /* General purpose registers */ 9149076Swpaul#define SF_RMAP_GENREG_MAX 0x5FFFF 9249076Swpaul 9349076Swpaul#define SF_RMAP_FIFO_BASE 0x60000 9449076Swpaul#define SF_RMAP_FIFO_MAX 0x6FFFF 9549076Swpaul 9649076Swpaul#define SF_RMAP_STS_BASE 0x70000 9749076Swpaul#define SF_RMAP_STS_MAX 0x70083 9849076Swpaul 9949076Swpaul#define SF_RMAP_RSVD_BASE 0x70084 10049076Swpaul#define SF_RMAP_RSVD_MAX 0x7FFFF 10149076Swpaul 10249076Swpaul/* 10349076Swpaul * PCI config header registers, 0x0000 to 0x003F 10449076Swpaul */ 10549076Swpaul#define SF_PCI_VENDOR_ID 0x0000 10649076Swpaul#define SF_PCI_DEVICE_ID 0x0002 10749076Swpaul#define SF_PCI_COMMAND 0x0004 10849076Swpaul#define SF_PCI_STATUS 0x0006 10949076Swpaul#define SF_PCI_REVID 0x0008 11049076Swpaul#define SF_PCI_CLASSCODE 0x0009 11149076Swpaul#define SF_PCI_CACHELEN 0x000C 11249076Swpaul#define SF_PCI_LATENCY_TIMER 0x000D 11349076Swpaul#define SF_PCI_HEADER_TYPE 0x000E 11449076Swpaul#define SF_PCI_LOMEM 0x0010 11549076Swpaul#define SF_PCI_LOIO 0x0014 11649076Swpaul#define SF_PCI_SUBVEN_ID 0x002C 11749076Swpaul#define SF_PCI_SYBSYS_ID 0x002E 11849076Swpaul#define SF_PCI_BIOSROM 0x0030 11949076Swpaul#define SF_PCI_INTLINE 0x003C 12049076Swpaul#define SF_PCI_INTPIN 0x003D 12149076Swpaul#define SF_PCI_MINGNT 0x003E 12249076Swpaul#define SF_PCI_MINLAT 0x003F 12349076Swpaul 12449076Swpaul/* 12549076Swpaul * PCI registers, 0x0040 to 0x006F 12649076Swpaul */ 12749076Swpaul#define SF_PCI_DEVCFG 0x0040 12849076Swpaul#define SF_BACCTL 0x0044 12949076Swpaul#define SF_PCI_MON1 0x0048 13049076Swpaul#define SF_PCI_MON2 0x004C 13149076Swpaul#define SF_PCI_CAPID 0x0050 /* 8 bits */ 13249076Swpaul#define SF_PCI_NEXTPTR 0x0051 /* 8 bits */ 13349076Swpaul#define SF_PCI_PWRMGMTCAP 0x0052 /* 16 bits */ 13449076Swpaul#define SF_PCI_PWRMGMTCTRL 0x0054 /* 16 bits */ 13549076Swpaul#define SF_PCI_PME_EVENT 0x0058 13649076Swpaul#define SF_PCI_EECTL 0x0060 13749076Swpaul#define SF_PCI_COMPLIANCE 0x0064 13849076Swpaul#define SF_INDIRECTIO_ADDR 0x0068 13949076Swpaul#define SF_INDIRECTIO_DATA 0x006C 14049076Swpaul 14149076Swpaul#define SF_PCIDEVCFG_RESET 0x00000001 14249076Swpaul#define SF_PCIDEVCFG_FORCE64 0x00000002 14349076Swpaul#define SF_PCIDEVCFG_SYSTEM64 0x00000004 14449076Swpaul#define SF_PCIDEVCFG_RSVD0 0x00000008 14549076Swpaul#define SF_PCIDEVCFG_INCR_INB 0x00000010 14649076Swpaul#define SF_PCIDEVCFG_ABTONPERR 0x00000020 14749076Swpaul#define SF_PCIDEVCFG_STPONPERR 0x00000040 14849076Swpaul#define SF_PCIDEVCFG_MR_ENB 0x00000080 14949076Swpaul#define SF_PCIDEVCFG_FIFOTHR 0x00000F00 15049076Swpaul#define SF_PCIDEVCFG_STPONCA 0x00001000 15149076Swpaul#define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master */ 15249076Swpaul#define SF_PCIDEVCFG_LATSTP 0x00004000 15349076Swpaul#define SF_PCIDEVCFG_BYTE_ENB 0x00008000 15449076Swpaul#define SF_PCIDEVCFG_EECSWIDTH 0x00070000 15549076Swpaul#define SF_PCIDEVCFG_STPMWCA 0x00080000 15649076Swpaul#define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 15749076Swpaul#define SF_PCIDEVCFG_INTR_ENB 0x00800000 15849076Swpaul#define SF_PCIDEVCFG_DPR_ENB 0x01000000 15949076Swpaul#define SF_PCIDEVCFG_RSVD1 0x02000000 16049076Swpaul#define SF_PCIDEVCFG_RSVD2 0x04000000 16149076Swpaul#define SF_PCIDEVCFG_STA_ENB 0x08000000 16249076Swpaul#define SF_PCIDEVCFG_RTA_ENB 0x10000000 16349076Swpaul#define SF_PCIDEVCFG_RMA_ENB 0x20000000 16449076Swpaul#define SF_PCIDEVCFG_SSE_ENB 0x40000000 16549076Swpaul#define SF_PCIDEVCFG_DPE_ENB 0x80000000 16649076Swpaul 16749076Swpaul#define SF_BACCTL_BACDMA_ENB 0x00000001 16849076Swpaul#define SF_BACCTL_PREFER_RXDMA 0x00000002 16949076Swpaul#define SF_BACCTL_PREFER_TXDMA 0x00000004 17049076Swpaul#define SF_BACCTL_SINGLE_DMA 0x00000008 17149076Swpaul#define SF_BACCTL_SWAPMODE_DATA 0x00000030 17249076Swpaul#define SF_BACCTL_SWAPMODE_DESC 0x000000C0 17349076Swpaul 17449076Swpaul#define SF_SWAPMODE_LE 0x00000000 17549076Swpaul#define SF_SWAPMODE_BE 0x00000010 17649076Swpaul 17749076Swpaul#define SF_PSTATE_MASK 0x0003 17849076Swpaul#define SF_PSTATE_D0 0x0000 17949076Swpaul#define SF_PSTATE_D1 0x0001 18049076Swpaul#define SF_PSTATE_D2 0x0002 18149076Swpaul#define SF_PSTATE_D3 0x0003 18249076Swpaul#define SF_PME_EN 0x0010 18349076Swpaul#define SF_PME_STATUS 0x8000 18449076Swpaul 18549076Swpaul 18649076Swpaul/* 18749076Swpaul * Ethernet registers 0x0070 to 0x00FF 18849076Swpaul */ 18949076Swpaul#define SF_GEN_ETH_CTL 0x0070 19049076Swpaul#define SF_TIMER_CTL 0x0074 19149076Swpaul#define SF_CURTIME 0x0078 19249076Swpaul#define SF_ISR 0x0080 19349076Swpaul#define SF_ISR_SHADOW 0x0084 19449076Swpaul#define SF_IMR 0x0088 19549076Swpaul#define SF_GPIO 0x008C 19649076Swpaul#define SF_TXDQ_CTL 0x0090 19749076Swpaul#define SF_TXDQ_ADDR_HIPRIO 0x0094 19849076Swpaul#define SF_TXDQ_ADDR_LOPRIO 0x0098 19949076Swpaul#define SF_TXDQ_ADDR_HIADDR 0x009C 20049076Swpaul#define SF_TXDQ_PRODIDX 0x00A0 20149076Swpaul#define SF_TXDQ_CONSIDX 0x00A4 20249076Swpaul#define SF_TXDMA_STS1 0x00A8 20349076Swpaul#define SF_TXDMA_STS2 0x00AC 20449076Swpaul#define SF_TX_FRAMCTL 0x00B0 20549076Swpaul#define SF_TXCQ_ADDR_HI 0x00B4 20649076Swpaul#define SF_TXCQ_CTL 0x00B8 20749076Swpaul#define SF_RXCQ_CTL_1 0x00BC 20849076Swpaul#define SF_RXCQ_CTL_2 0x00C0 20949076Swpaul#define SF_CQ_CONSIDX 0x00C4 21049076Swpaul#define SF_CQ_PRODIDX 0x00C8 21149076Swpaul#define SF_CQ_RXQ2 0x00CC 21249076Swpaul#define SF_RXDMA_CTL 0x00D0 21349076Swpaul#define SF_RXDQ_CTL_1 0x00D4 21449076Swpaul#define SF_RXDQ_CTL_2 0x00D8 21549076Swpaul#define SF_RXDQ_ADDR_HIADDR 0x00DC 21649076Swpaul#define SF_RXDQ_ADDR_Q1 0x00E0 21749076Swpaul#define SF_RXDQ_ADDR_Q2 0x00E4 21849076Swpaul#define SF_RXDQ_PTR_Q1 0x00E8 21949076Swpaul#define SF_RXDQ_PTR_Q2 0x00EC 22049076Swpaul#define SF_RXDMA_STS 0x00F0 22149076Swpaul#define SF_RXFILT 0x00F4 22249076Swpaul#define SF_RX_FRAMETEST_OUT 0x00F8 22349076Swpaul 22449076Swpaul/* Ethernet control register */ 22549076Swpaul#define SF_ETHCTL_RX_ENB 0x00000001 22649076Swpaul#define SF_ETHCTL_TX_ENB 0x00000002 22749076Swpaul#define SF_ETHCTL_RXDMA_ENB 0x00000004 22849076Swpaul#define SF_ETHCTL_TXDMA_ENB 0x00000008 22949076Swpaul#define SF_ETHCTL_RXGFP_ENB 0x00000010 23049076Swpaul#define SF_ETHCTL_TXGFP_ENB 0x00000020 23149076Swpaul#define SF_ETHCTL_SOFTINTR 0x00000800 23249076Swpaul 23349076Swpaul/* Timer control register */ 23449076Swpaul#define SF_TIMER_IMASK_INTERVAL 0x0000001F 23549076Swpaul#define SF_TIMER_IMASK_MODE 0x00000060 23649076Swpaul#define SF_TIMER_SMALLFRAME_BYP 0x00000100 23749076Swpaul#define SF_TIMER_SMALLRX_FRAME 0x00000600 23849076Swpaul#define SF_TIMER_TIMES_TEN 0x00000800 23949076Swpaul#define SF_TIMER_RXHIPRIO_BYP 0x00001000 24049076Swpaul#define SF_TIMER_TX_DMADONE_DLY 0x00002000 24149076Swpaul#define SF_TIMER_TX_QDONE_DLY 0x00004000 24249076Swpaul#define SF_TIMER_TX_FRDONE_DLY 0x00008000 24349076Swpaul#define SF_TIMER_GENTIMER 0x00FF0000 24449076Swpaul#define SF_TIMER_ONESHOT 0x01000000 24549076Swpaul#define SF_TIMER_GENTIMER_RES 0x02000000 24649076Swpaul#define SF_TIMER_TIMEST_RES 0x04000000 24749076Swpaul#define SF_TIMER_RXQ2DONE_DLY 0x10000000 24849076Swpaul#define SF_TIMER_EARLYRX2_DLY 0x20000000 24949076Swpaul#define SF_TIMER_RXQ1DONE_DLY 0x40000000 25049076Swpaul#define SF_TIMER_EARLYRX1_DLY 0x80000000 25149076Swpaul 25249076Swpaul/* Interrupt status register */ 25349076Swpaul#define SF_ISR_PCIINT_ASSERTED 0x00000001 25449076Swpaul#define SF_ISR_GFP_TX 0x00000002 25549076Swpaul#define SF_ISR_GFP_RX 0x00000004 25649076Swpaul#define SF_ISR_TX_BADID_HIPRIO 0x00000008 25749076Swpaul#define SF_ISR_TX_BADID_LOPRIO 0x00000010 25849076Swpaul#define SF_ISR_NO_TX_CSUM 0x00000020 25949076Swpaul#define SF_ISR_RXDQ2_NOBUFS 0x00000040 26049076Swpaul#define SF_ISR_RXGFP_NORESP 0x00000080 26149076Swpaul#define SF_ISR_RXDQ1_DMADONE 0x00000100 26249076Swpaul#define SF_ISR_RXDQ2_DMADONE 0x00000200 26349076Swpaul#define SF_ISR_RXDQ1_EARLY 0x00000400 26449076Swpaul#define SF_ISR_RXDQ2_EARLY 0x00000800 26549076Swpaul#define SF_ISR_TX_QUEUEDONE 0x00001000 26649076Swpaul#define SF_ISR_TX_DMADONE 0x00002000 26749076Swpaul#define SF_ISR_TX_TXDONE 0x00004000 26849076Swpaul#define SF_ISR_NORMALINTR 0x00008000 26949076Swpaul#define SF_ISR_RXDQ1_NOBUFS 0x00010000 27049076Swpaul#define SF_ISR_RXCQ2_NOBUFS 0x00020000 27149076Swpaul#define SF_ISR_TX_LOFIFO 0x00040000 27249076Swpaul#define SF_ISR_DMAERR 0x00080000 27349076Swpaul#define SF_ISR_PCIINT 0x00100000 27449076Swpaul#define SF_ISR_TXCQ_NOBUFS 0x00200000 27549076Swpaul#define SF_ISR_RXCQ1_NOBUFS 0x00400000 27649076Swpaul#define SF_ISR_SOFTINTR 0x00800000 27749076Swpaul#define SF_ISR_GENTIMER 0x01000000 27849076Swpaul#define SF_ISR_ABNORMALINTR 0x02000000 27949076Swpaul#define SF_ISR_RSVD0 0x04000000 28049076Swpaul#define SF_ISR_STATSOFLOW 0x08000000 28149076Swpaul#define SF_ISR_GPIO 0xF0000000 28249076Swpaul 28349076Swpaul/* 28449076Swpaul * Shadow interrupt status register. Unlike the normal IRQ register, 28549076Swpaul * reading bits here does not automatically cause them to reset. 28649076Swpaul */ 28749076Swpaul#define SF_SISR_PCIINT_ASSERTED 0x00000001 28849076Swpaul#define SF_SISR_GFP_TX 0x00000002 28949076Swpaul#define SF_SISR_GFP_RX 0x00000004 29049076Swpaul#define SF_SISR_TX_BADID_HIPRIO 0x00000008 29149076Swpaul#define SF_SISR_TX_BADID_LOPRIO 0x00000010 29249076Swpaul#define SF_SISR_NO_TX_CSUM 0x00000020 29349076Swpaul#define SF_SISR_RXDQ2_NOBUFS 0x00000040 29449076Swpaul#define SF_SISR_RXGFP_NORESP 0x00000080 29549076Swpaul#define SF_SISR_RXDQ1_DMADONE 0x00000100 29649076Swpaul#define SF_SISR_RXDQ2_DMADONE 0x00000200 29749076Swpaul#define SF_SISR_RXDQ1_EARLY 0x00000400 29849076Swpaul#define SF_SISR_RXDQ2_EARLY 0x00000800 29949076Swpaul#define SF_SISR_TX_QUEUEDONE 0x00001000 30049076Swpaul#define SF_SISR_TX_DMADONE 0x00002000 30149076Swpaul#define SF_SISR_TX_TXDONE 0x00004000 30249076Swpaul#define SF_SISR_NORMALINTR 0x00008000 30349076Swpaul#define SF_SISR_RXDQ1_NOBUFS 0x00010000 30449076Swpaul#define SF_SISR_RXCQ2_NOBUFS 0x00020000 30549076Swpaul#define SF_SISR_TX_LOFIFO 0x00040000 30649076Swpaul#define SF_SISR_DMAERR 0x00080000 30749076Swpaul#define SF_SISR_PCIINT 0x00100000 30849076Swpaul#define SF_SISR_TXCQ_NOBUFS 0x00200000 30949076Swpaul#define SF_SISR_RXCQ1_NOBUFS 0x00400000 31049076Swpaul#define SF_SISR_SOFTINTR 0x00800000 31149076Swpaul#define SF_SISR_GENTIMER 0x01000000 31249076Swpaul#define SF_SISR_ABNORMALINTR 0x02000000 31349076Swpaul#define SF_SISR_RSVD0 0x04000000 31449076Swpaul#define SF_SISR_STATSOFLOW 0x08000000 31549076Swpaul#define SF_SISR_GPIO 0xF0000000 31649076Swpaul 31749076Swpaul/* Interrupt mask register */ 31849076Swpaul#define SF_IMR_PCIINT_ASSERTED 0x00000001 31949076Swpaul#define SF_IMR_GFP_TX 0x00000002 32049076Swpaul#define SF_IMR_GFP_RX 0x00000004 32149076Swpaul#define SF_IMR_TX_BADID_HIPRIO 0x00000008 32249076Swpaul#define SF_IMR_TX_BADID_LOPRIO 0x00000010 32349076Swpaul#define SF_IMR_NO_TX_CSUM 0x00000020 32449076Swpaul#define SF_IMR_RXDQ2_NOBUFS 0x00000040 32549076Swpaul#define SF_IMR_RXGFP_NORESP 0x00000080 32649076Swpaul#define SF_IMR_RXDQ1_DMADONE 0x00000100 32749076Swpaul#define SF_IMR_RXDQ2_DMADONE 0x00000200 32849076Swpaul#define SF_IMR_RXDQ1_EARLY 0x00000400 32949076Swpaul#define SF_IMR_RXDQ2_EARLY 0x00000800 33049076Swpaul#define SF_IMR_TX_QUEUEDONE 0x00001000 33149076Swpaul#define SF_IMR_TX_DMADONE 0x00002000 33249076Swpaul#define SF_IMR_TX_TXDONE 0x00004000 33349076Swpaul#define SF_IMR_NORMALINTR 0x00008000 33449076Swpaul#define SF_IMR_RXDQ1_NOBUFS 0x00010000 33549076Swpaul#define SF_IMR_RXCQ2_NOBUFS 0x00020000 33649076Swpaul#define SF_IMR_TX_LOFIFO 0x00040000 33749076Swpaul#define SF_IMR_DMAERR 0x00080000 33849076Swpaul#define SF_IMR_PCIINT 0x00100000 33949076Swpaul#define SF_IMR_TXCQ_NOBUFS 0x00200000 34049076Swpaul#define SF_IMR_RXCQ1_NOBUFS 0x00400000 34149076Swpaul#define SF_IMR_SOFTINTR 0x00800000 34249076Swpaul#define SF_IMR_GENTIMER 0x01000000 34349076Swpaul#define SF_IMR_ABNORMALINTR 0x02000000 34449076Swpaul#define SF_IMR_RSVD0 0x04000000 34549076Swpaul#define SF_IMR_STATSOFLOW 0x08000000 34649076Swpaul#define SF_IMR_GPIO 0xF0000000 34749076Swpaul 34849076Swpaul#define SF_INTRS \ 34949076Swpaul (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \ 35049076Swpaul SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \ 35149076Swpaul SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \ 35281737Swpaul SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \ 35381737Swpaul SF_IMR_TX_LOFIFO) 35449076Swpaul 35549076Swpaul/* TX descriptor queue control registers */ 35649076Swpaul#define SF_TXDQCTL_DESCTYPE 0x00000007 35749076Swpaul#define SF_TXDQCTL_NODMACMP 0x00000008 35849076Swpaul#define SF_TXDQCTL_MINSPACE 0x00000070 35949076Swpaul#define SF_TXDQCTL_64BITADDR 0x00000080 36049076Swpaul#define SF_TXDQCTL_BURSTLEN 0x00003F00 36149076Swpaul#define SF_TXDQCTL_SKIPLEN 0x001F0000 36249076Swpaul#define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 36349076Swpaul 36449076Swpaul#define SF_TXBUFDESC_TYPE0 0x00000000 36549076Swpaul#define SF_TXBUFDESC_TYPE1 0x00000001 36649076Swpaul#define SF_TXBUFDESC_TYPE2 0x00000002 36749076Swpaul#define SF_TXBUFDESC_TYPE3 0x00000003 36849076Swpaul#define SF_TXBUFDESC_TYPE4 0x00000004 36949076Swpaul 37049076Swpaul#define SF_TXMINSPACE_UNLIMIT 0x00000000 37149076Swpaul#define SF_TXMINSPACE_32BYTES 0x00000010 37249076Swpaul#define SF_TXMINSPACE_64BYTES 0x00000020 37349076Swpaul#define SF_TXMINSPACE_128BYTES 0x00000030 37449076Swpaul#define SF_TXMINSPACE_256BYTES 0x00000040 37549076Swpaul 37649076Swpaul#define SF_TXSKIPLEN_0BYTES 0x00000000 37749076Swpaul#define SF_TXSKIPLEN_8BYTES 0x00010000 37849076Swpaul#define SF_TXSKIPLEN_16BYTES 0x00020000 37949076Swpaul#define SF_TXSKIPLEN_24BYTES 0x00030000 38049076Swpaul#define SF_TXSKIPLEN_32BYTES 0x00040000 38149076Swpaul 38249076Swpaul/* TX frame control register */ 38349076Swpaul#define SF_TXFRMCTL_TXTHRESH 0x000000FF 38449076Swpaul#define SF_TXFRMCTL_CPLAFTERTX 0x00000100 38549076Swpaul#define SF_TXFRMCRL_DEBUG 0x0000FE00 38649076Swpaul#define SF_TXFRMCTL_STATUS 0x01FF0000 38749076Swpaul#define SF_TXFRMCTL_MAC_TXIF 0xFE000000 38849076Swpaul 38949076Swpaul/* TX completion queue control register */ 39049076Swpaul#define SF_TXCQ_THRESH 0x0000000F 39149076Swpaul#define SF_TXCQ_COMMON 0x00000010 39249076Swpaul#define SF_TXCQ_SIZE 0x00000020 39349076Swpaul#define SF_TXCQ_WRITEENB 0x00000040 39449076Swpaul#define SF_TXCQ_USE_64BIT 0x00000080 39549076Swpaul#define SF_TXCQ_ADDR 0xFFFFFF00 39649076Swpaul 39749076Swpaul/* RX completion queue control register */ 39849076Swpaul#define SF_RXCQ_THRESH 0x0000000F 39949076Swpaul#define SF_RXCQ_TYPE 0x00000030 40049076Swpaul#define SF_RXCQ_WRITEENB 0x00000040 40149076Swpaul#define SF_RXCQ_USE_64BIT 0x00000080 40249076Swpaul#define SF_RXCQ_ADDR 0xFFFFFF00 40349076Swpaul 40449076Swpaul#define SF_RXCQTYPE_0 0x00000000 40549076Swpaul#define SF_RXCQTYPE_1 0x00000010 40649076Swpaul#define SF_RXCQTYPE_2 0x00000020 40749076Swpaul#define SF_RXCQTYPE_3 0x00000030 40849076Swpaul 40949076Swpaul/* TX descriptor queue producer index register */ 41049076Swpaul#define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 41149076Swpaul#define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 41249076Swpaul 41349076Swpaul/* TX descriptor queue consumer index register */ 41449076Swpaul#define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 41549076Swpaul#define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 41649076Swpaul 41749076Swpaul/* Completion queue consumer index register */ 41849076Swpaul#define SF_CQ_CONSIDX_RXQ1 0x000003FF 41949076Swpaul#define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 42049076Swpaul#define SF_CQ_CONSIDX_TXQ 0x03FF0000 42149076Swpaul#define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 42249076Swpaul 42349076Swpaul/* Completion queue producer index register */ 42449076Swpaul#define SF_CQ_PRODIDX_RXQ1 0x000003FF 42549076Swpaul#define SF_CQ_PRODIDX_TXQ 0x03FF0000 42649076Swpaul 42749076Swpaul/* RX completion queue 2 consumer/producer index register */ 42849076Swpaul#define SF_CQ_RXQ2_CONSIDX 0x000003FF 42949076Swpaul#define SF_CQ_RXQ2_RXTHRMODE 0x00008000 43049076Swpaul#define SF_CQ_RXQ2_PRODIDX 0x03FF0000 43149076Swpaul 43249076Swpaul#define SF_CQ_RXTHRMODE_INT_ON 0x00008000 43349076Swpaul#define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 43449076Swpaul#define SF_CQ_TXTHRMODE_INT_ON 0x80000000 43549076Swpaul#define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 43649076Swpaul 43749076Swpaul#define SF_IDX_LO(x) ((x) & 0x000007FF) 43849076Swpaul#define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF) 43949076Swpaul 44049076Swpaul/* RX DMA control register */ 44149076Swpaul#define SF_RXDMA_BURSTSIZE 0x0000007F 44249076Swpaul#define SF_RXDMA_FPTESTMODE 0x00000080 44349076Swpaul#define SF_RXDMA_HIPRIOTHRESH 0x00000F00 44449076Swpaul#define SF_RXDMA_RXEARLYTHRESH 0x0001F000 44549076Swpaul#define SF_RXDMA_DMACRC 0x00040000 44649076Swpaul#define SF_RXDMA_USEBKUPQUEUE 0x00080000 44749076Swpaul#define SF_RXDMA_QUEUEMODE 0x00700000 44849076Swpaul#define SF_RXDMA_RXCQ2_ON 0x00800000 44949076Swpaul#define SF_RXDMA_CSUMMODE 0x03000000 45049076Swpaul#define SF_RXDMA_DMAPAUSEPKTS 0x04000000 45149076Swpaul#define SF_RXDMA_DMACTLPKTS 0x08000000 45249076Swpaul#define SF_RXDMA_DMACRXERRPKTS 0x10000000 45349076Swpaul#define SF_RXDMA_DMABADPKTS 0x20000000 45449076Swpaul#define SF_RXDMA_DMARUNTS 0x40000000 45549076Swpaul#define SF_RXDMA_REPORTBADPKTS 0x80000000 45649076Swpaul 45749076Swpaul#define SF_RXDQMODE_Q1ONLY 0x00100000 45849076Swpaul#define SF_RXDQMODE_Q2_ON_FP 0x00200000 45949076Swpaul#define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 46049076Swpaul#define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 46149076Swpaul#define SF_RXDQMODE_SPLITHDR 0x00500000 46249076Swpaul 46349076Swpaul#define SF_RXCSUMMODE_IGNORE 0x00000000 46449076Swpaul#define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 46549076Swpaul#define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 46649076Swpaul#define SF_RXCSUMMODE_RSVD 0x03000000 46749076Swpaul 46849076Swpaul/* RX descriptor queue control registers */ 46949076Swpaul#define SF_RXDQCTL_MINDESCTHR 0x0000007F 47049076Swpaul#define SF_RXDQCTL_Q1_WE 0x00000080 47149076Swpaul#define SF_RXDQCTL_DESCSPACE 0x00000700 47249076Swpaul#define SF_RXDQCTL_64BITDADDR 0x00000800 47349076Swpaul#define SF_RXDQCTL_64BITBADDR 0x00001000 47449076Swpaul#define SF_RXDQCTL_VARIABLE 0x00002000 47549076Swpaul#define SF_RXDQCTL_ENTRIES 0x00004000 47649076Swpaul#define SF_RXDQCTL_PREFETCH 0x00008000 47749076Swpaul#define SF_RXDQCTL_BUFLEN 0xFFFF0000 47849076Swpaul 47949076Swpaul#define SF_DESCSPACE_4BYTES 0x00000000 48049076Swpaul#define SF_DESCSPACE_8BYTES 0x00000100 48149076Swpaul#define SF_DESCSPACE_16BYTES 0x00000200 48249076Swpaul#define SF_DESCSPACE_32BYTES 0x00000300 48349076Swpaul#define SF_DESCSPACE_64BYTES 0x00000400 48449076Swpaul#define SF_DESCSPACE_128_BYTES 0x00000500 48549076Swpaul 48649076Swpaul/* RX buffer consumer/producer index registers */ 48749076Swpaul#define SF_RXDQ_PRODIDX 0x000007FF 48849076Swpaul#define SF_RXDQ_CONSIDX 0x07FF0000 48949076Swpaul 49049076Swpaul/* RX filter control register */ 49149076Swpaul#define SF_RXFILT_PROMISC 0x00000001 49249076Swpaul#define SF_RXFILT_ALLMULTI 0x00000002 49349076Swpaul#define SF_RXFILT_BROAD 0x00000004 49449076Swpaul#define SF_RXFILT_HASHPRIO 0x00000008 49549076Swpaul#define SF_RXFILT_HASHMODE 0x00000030 49649076Swpaul#define SF_RXFILT_PERFMODE 0x000000C0 49749076Swpaul#define SF_RXFILT_VLANMODE 0x00000300 49849076Swpaul#define SF_RXFILT_WAKEMODE 0x00000C00 49949076Swpaul#define SF_RXFILT_MULTI_NOBROAD 0x00001000 50049076Swpaul#define SF_RXFILT_MIN_VLANPRIO 0x0000E000 50149076Swpaul#define SF_RXFILT_PEFECTPRIO 0xFFFF0000 50249076Swpaul 50349076Swpaul/* Hash filtering mode */ 50449076Swpaul#define SF_HASHMODE_OFF 0x00000000 50549076Swpaul#define SF_HASHMODE_WITHVLAN 0x00000010 50649076Swpaul#define SF_HASHMODE_ANYVLAN 0x00000020 50749076Swpaul#define SF_HASHMODE_ANY 0x00000030 50849076Swpaul 50949076Swpaul/* Perfect filtering mode */ 51049076Swpaul#define SF_PERFMODE_OFF 0x00000000 51149076Swpaul#define SF_PERFMODE_NORMAL 0x00000040 51249076Swpaul#define SF_PERFMODE_INVERSE 0x00000080 51349076Swpaul#define SF_PERFMODE_VLAN 0x000000C0 51449076Swpaul 51549076Swpaul/* VLAN mode */ 51649076Swpaul#define SF_VLANMODE_OFF 0x00000000 51749076Swpaul#define SF_VLANMODE_NOSTRIP 0x00000100 51849076Swpaul#define SF_VLANMODE_STRIP 0x00000200 51949076Swpaul#define SF_VLANMODE_RSVD 0x00000300 52049076Swpaul 52149076Swpaul/* Wakeup mode */ 52249076Swpaul#define SF_WAKEMODE_OFF 0x00000000 52349076Swpaul#define SF_WAKEMODE_FILTER 0x00000400 52449076Swpaul#define SF_WAKEMODE_FP 0x00000800 52549076Swpaul#define SF_WAKEMODE_HIPRIO 0x00000C00 52649076Swpaul 52749076Swpaul/* 52849076Swpaul * Extra PCI registers 0x0100 to 0x0FFF 52949076Swpaul */ 53049076Swpaul#define SF_PCI_TARGSTAT 0x0100 53149076Swpaul#define SF_PCI_MASTSTAT1 0x0104 53249076Swpaul#define SF_PCI_MASTSTAT2 0x0108 53349076Swpaul#define SF_PCI_DMAHOSTADDR_LO 0x010C 53449076Swpaul#define SF_BAC_DMADIAG0 0x0110 53549076Swpaul#define SF_BAC_DMADIAG1 0x0114 53649076Swpaul#define SF_BAC_DMADIAG2 0x0118 53749076Swpaul#define SF_BAC_DMADIAG3 0x011C 53849076Swpaul#define SF_PAR0 0x0120 53949076Swpaul#define SF_PAR1 0x0124 54049076Swpaul#define SF_PCICB_FUNCEVENT 0x0130 54149076Swpaul#define SF_PCICB_FUNCEVENT_MASK 0x0134 54249076Swpaul#define SF_PCICB_FUNCSTATE 0x0138 54349076Swpaul#define SF_PCICB_FUNCFORCE 0x013C 54449076Swpaul 54549076Swpaul/* 54649076Swpaul * Serial EEPROM registers 0x1000 to 0x1FFF 54749076Swpaul * Presumeably the EEPROM is mapped into this 8K window. 54849076Swpaul */ 54949076Swpaul#define SF_EEADDR_BASE 0x1000 55049076Swpaul#define SF_EEADDR_MAX 0x1FFF 55149076Swpaul 55249076Swpaul#define SF_EE_NODEADDR 14 55349076Swpaul 55449076Swpaul/* 55549076Swpaul * MII registers registers 0x2000 to 0x3FFF 55649076Swpaul * There are 32 sets of 32 registers, one set for each possible 55749076Swpaul * PHY address. Each 32 bit register is split into a 16-bit data 55849076Swpaul * port and a couple of status bits. 55949076Swpaul */ 56049076Swpaul 56149076Swpaul#define SF_MIIADDR_BASE 0x2000 56249076Swpaul#define SF_MIIADDR_MAX 0x3FFF 56349076Swpaul#define SF_MII_BLOCKS 32 56449076Swpaul 56549076Swpaul#define SF_MII_DATAVALID 0x80000000 56649076Swpaul#define SF_MII_BUSY 0x40000000 56749076Swpaul#define SF_MII_DATAPORT 0x0000FFFF 56849076Swpaul 56949076Swpaul#define SF_PHY_REG(phy, reg) \ 57049076Swpaul (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \ 57149076Swpaul (reg * sizeof(u_int32_t))) 57249076Swpaul 57349076Swpaul/* 57449076Swpaul * Ethernet extra registers 0x4000 to 0x4FFF 57549076Swpaul */ 57649076Swpaul#define SF_TESTMODE 0x4000 57749076Swpaul#define SF_RX_FRAMEPROC_CTL 0x4004 57849076Swpaul#define SF_TX_FRAMEPROC_CTL 0x4008 57949076Swpaul 58049076Swpaul/* 58149076Swpaul * MAC registers 0x5000 to 0x5FFF 58249076Swpaul */ 58349076Swpaul#define SF_MACCFG_1 0x5000 58449076Swpaul#define SF_MACCFG_2 0x5004 58549076Swpaul#define SF_BKTOBKIPG 0x5008 58649076Swpaul#define SF_NONBKTOBKIPG 0x500C 58749076Swpaul#define SF_COLRETRY 0x5010 58849076Swpaul#define SF_MAXLEN 0x5014 58949076Swpaul#define SF_TXNIBBLECNT 0x5018 59049076Swpaul#define SF_TXBYTECNT 0x501C 59149076Swpaul#define SF_RETXCNT 0x5020 59249076Swpaul#define SF_RANDNUM 0x5024 59349076Swpaul#define SF_RANDNUM_MASK 0x5028 59449076Swpaul#define SF_TOTALTXCNT 0x5034 59549076Swpaul#define SF_RXBYTECNT 0x5040 59649076Swpaul#define SF_TXPAUSETIMER 0x5060 59749076Swpaul#define SF_VLANTYPE 0x5064 59849076Swpaul#define SF_MIISTATUS 0x5070 59949076Swpaul 60049076Swpaul#define SF_MACCFG1_HUGEFRAMES 0x00000001 60149076Swpaul#define SF_MACCFG1_FULLDUPLEX 0x00000002 60249076Swpaul#define SF_MACCFG1_AUTOPAD 0x00000004 60349076Swpaul#define SF_MACCFG1_HDJAM 0x00000008 60449076Swpaul#define SF_MACCFG1_DELAYCRC 0x00000010 60549076Swpaul#define SF_MACCFG1_NOBACKOFF 0x00000020 60649076Swpaul#define SF_MACCFG1_LENGTHCHECK 0x00000040 60749076Swpaul#define SF_MACCFG1_PUREPREAMBLE 0x00000080 60849076Swpaul#define SF_MACCFG1_PASSALLRX 0x00000100 60949076Swpaul#define SF_MACCFG1_PREAM_DETCNT 0x00000200 61049076Swpaul#define SF_MACCFG1_RX_FLOWENB 0x00000400 61149076Swpaul#define SF_MACCFG1_TX_FLOWENB 0x00000800 61249076Swpaul#define SF_MACCFG1_TESTMODE 0x00003000 61349076Swpaul#define SF_MACCFG1_MIILOOPBK 0x00004000 61449076Swpaul#define SF_MACCFG1_SOFTRESET 0x00008000 61549076Swpaul 61649076Swpaul/* 61754161Swpaul * There are the recommended IPG nibble counter settings 61854161Swpaul * specified in the Adaptec manual for full duplex and 61954161Swpaul * half duplex operation. 62054161Swpaul */ 62154161Swpaul#define SF_IPGT_FDX 0x15 62254161Swpaul#define SF_IPGT_HDX 0x11 62354161Swpaul 62454161Swpaul/* 62549076Swpaul * RX filter registers 0x6000 to 0x6FFF 62649076Swpaul */ 62749076Swpaul#define SF_RXFILT_PERFECT_BASE 0x6000 62849076Swpaul#define SF_RXFILT_PERFECT_MAX 0x60FF 62949076Swpaul#define SF_RXFILT_PERFECT_SKIP 0x0010 63049076Swpaul#define SF_RXFILT_PERFECT_CNT 0x0010 63149076Swpaul 63249076Swpaul#define SF_RXFILT_HASH_BASE 0x6100 63349076Swpaul#define SF_RXFILT_HASH_MAX 0x62FF 63449076Swpaul#define SF_RXFILT_HASH_SKIP 0x0010 63549076Swpaul#define SF_RXFILT_HASH_CNT 0x001F 63649076Swpaul#define SF_RXFILT_HASH_ADDROFF 0x0000 63749076Swpaul#define SF_RXFILT_HASH_PRIOOFF 0x0004 63849076Swpaul#define SF_RXFILT_HASH_VLANOFF 0x0008 63949076Swpaul 64049076Swpaul/* 64149076Swpaul * Statistics registers 0x7000 to 0x7FFF 64249076Swpaul */ 64349076Swpaul#define SF_STATS_BASE 0x7000 64449076Swpaul#define SF_STATS_END 0x7FFF 64549076Swpaul 64649076Swpaul/* 64749076Swpaul * TX frame processor instruction space 0x8000 to 0x9FFF 64849076Swpaul */ 64949076Swpaul 65049076Swpaul/* 65149076Swpaul * RX frame processor instruction space 0xA000 to 0xBFFF 65249076Swpaul */ 65349076Swpaul 65449076Swpaul/* 65549076Swpaul * Ethernet FIFO access space 0xC000 to 0xDFFF 65649076Swpaul */ 65749076Swpaul 65849076Swpaul/* 65949076Swpaul * Reserved 0xE000 to 0xFFFF 66049076Swpaul */ 66149076Swpaul 66249076Swpaul/* 66349076Swpaul * Descriptor data structures. 66449076Swpaul */ 66549076Swpaul 66649076Swpaul 66749076Swpaul/* Receive descriptor formats. */ 66849076Swpaul#define SF_RX_MINSPACING 8 66949076Swpaul#define SF_RX_DLIST_CNT 256 67049076Swpaul#define SF_RX_CLIST_CNT 1024 67149076Swpaul#define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF) 67249076Swpaul 67349076Swpaul/* 67449076Swpaul * RX buffer descriptor type 0, 32-bit addressing. Note that we 67549076Swpaul * program the RX buffer queue control register(s) to allow a 67649076Swpaul * descriptor spacing of 16 bytes, which leaves room after each 67749076Swpaul * descriptor to store a pointer to the mbuf for each buffer. 67849076Swpaul */ 67949076Swpaulstruct sf_rx_bufdesc_type0 { 68049076Swpaul u_int32_t sf_valid:1, 68149076Swpaul sf_end:1, 68249076Swpaul sf_addrlo:30; 68349076Swpaul u_int32_t sf_pad0; 68449076Swpaul#ifdef __i386__ 68549076Swpaul u_int32_t sf_pad1; 68649076Swpaul#endif 68749076Swpaul struct mbuf *sf_mbuf; 68849076Swpaul}; 68949076Swpaul 69049076Swpaul/* 69149076Swpaul * RX buffer descriptor type 0, 64-bit addressing. 69249076Swpaul */ 69349076Swpaulstruct sf_rx_bufdesc_type1 { 69449076Swpaul u_int32_t sf_valid:1, 69549076Swpaul sf_end:1, 69649076Swpaul sf_addrlo:30; 69749076Swpaul u_int32_t sf_addrhi; 69849076Swpaul#ifdef __i386__ 69949076Swpaul u_int32_t sf_pad; 70049076Swpaul#endif 70149076Swpaul struct mbuf *sf_mbuf; 70249076Swpaul}; 70349076Swpaul 70449076Swpaul/* 70549076Swpaul * RX completion descriptor, type 0 (short). 70649076Swpaul */ 70749076Swpaulstruct sf_rx_cmpdesc_type0 { 70849076Swpaul u_int32_t sf_len:16, 70949076Swpaul sf_endidx:11, 71049076Swpaul sf_status1:3, 71149076Swpaul sf_id:2; 71249076Swpaul}; 71349076Swpaul 71449076Swpaul/* 71549076Swpaul * RX completion descriptor, type 1 (basic). Includes vlan ID 71649076Swpaul * if this is a vlan-addressed packet, plus extended status. 71749076Swpaul */ 71849076Swpaulstruct sf_rx_cmpdesc_type1 { 71949076Swpaul u_int32_t sf_len:16, 72049076Swpaul sf_endidx:11, 72149076Swpaul sf_status1:3, 72249076Swpaul sf_id:2; 72349076Swpaul u_int16_t sf_status2; 72449076Swpaul u_int16_t sf_vlanid; 72549076Swpaul}; 72649076Swpaul 72749076Swpaul/* 72849076Swpaul * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 72949076Swpaul * checksum instead of vlan tag, plus extended status. 73049076Swpaul */ 73149076Swpaulstruct sf_rx_cmpdesc_type2 { 73249076Swpaul u_int32_t sf_len:16, 73349076Swpaul sf_endidx:11, 73449076Swpaul sf_status1:3, 73549076Swpaul sf_id:2; 73649076Swpaul u_int16_t sf_status2; 73749076Swpaul u_int16_t sf_cksum; 73849076Swpaul}; 73949076Swpaul 74049076Swpaul/* 74149076Swpaul * RX completion descriptor type 3 (full). Includes timestamp, partial 74249076Swpaul * TCP/IP checksum, vlan tag plus priority, two extended status fields. 74349076Swpaul */ 74449076Swpaulstruct sf_rx_cmpdesc_type3 { 74549076Swpaul u_int32_t sf_len:16, 74649076Swpaul sf_endidx:11, 74749076Swpaul sf_status1:3, 74849076Swpaul sf_id:2; 74949076Swpaul u_int32_t sf_startidx:10, 75049076Swpaul sf_status3:6, 75149076Swpaul sf_status2:16; 75249076Swpaul u_int16_t sf_cksum; 75349076Swpaul u_int16_t sf_vlanid_prio; 75449076Swpaul u_int32_t sf_timestamp; 75549076Swpaul}; 75649076Swpaul 75749076Swpaul#define SF_RXSTAT1_QUEUE 0x1 75849076Swpaul#define SF_RXSTAT1_FIFOFULL 0x2 75949076Swpaul#define SF_RXSTAT1_OK 0x4 76049076Swpaul 76149076Swpaul /* 0=unknown,5=unsupported */ 76249076Swpaul#define SF_RXSTAT2_FRAMETYPE 0x0007 /* 1=IPv4,2=IPv2,3=IPX,4=ICMP */ 76349076Swpaul#define SF_RXSTAT2_UDP 0x0008 76449076Swpaul#define SF_RXSTAT2_TCP 0x0010 76549076Swpaul#define SF_RXSTAT2_FRAG 0x0020 76649076Swpaul#define SF_RXSTAT2_PCSUM_OK 0x0040 /* partial checksum ok */ 76749076Swpaul#define SF_RXSTAT2_CSUM_BAD 0x0080 /* TCP/IP checksum bad */ 76849076Swpaul#define SF_RXSTAT2_CSUM_OK 0x0100 /* TCP/IP checksum ok */ 76949076Swpaul#define SF_RXSTAT2_VLAN 0x0200 77049076Swpaul#define SF_RXSTAT2_BADRXCODE 0x0400 77149076Swpaul#define SF_RXSTAT2_DRIBBLE 0x0800 77249076Swpaul#define SF_RXSTAT2_ISL_CRCERR 0x1000 77349076Swpaul#define SF_RXSTAT2_CRCERR 0x2000 77449076Swpaul#define SF_RXSTAT2_HASH 0x4000 77549076Swpaul#define SF_RXSTAT2_PERFECT 0x8000 77649076Swpaul 77749076Swpaul#define SF_RXSTAT3_TRAILER 0x01 77849076Swpaul#define SF_RXSTAT3_HEADER 0x02 77949076Swpaul#define SF_RXSTAT3_CONTROL 0x04 78049076Swpaul#define SF_RXSTAT3_PAUSE 0x08 78149076Swpaul#define SF_RXSTAT3_ISL 0x10 78249076Swpaul 78349076Swpaul/* 78449076Swpaul * Transmit descriptor formats. 78549076Swpaul * Each transmit descriptor type allows for a skip field at the 78649076Swpaul * start of each structure. The size of the skip field can vary, 78749076Swpaul * however we always set it for 8 bytes, which is enough to hold 78849076Swpaul * a pointer (32 bits on x86, 64-bits on alpha) that we can use 78949076Swpaul * to hold the address of the head of the mbuf chain for the 79049076Swpaul * frame or fragment associated with the descriptor. This saves 79149076Swpaul * us from having to create a separate pointer array to hold 79249076Swpaul * the mbuf addresses. 79349076Swpaul */ 79449076Swpaul#define SF_TX_BUFDESC_ID 0xB 79549076Swpaul#define SF_MAXFRAGS 14 79649076Swpaul#define SF_TX_MINSPACING 128 79749076Swpaul#define SF_TX_DLIST_CNT 128 79849076Swpaul#define SF_TX_DLIST_SIZE 16384 79949076Swpaul#define SF_TX_SKIPLEN 1 80049076Swpaul#define SF_TX_CLIST_CNT 1024 80149076Swpaul 80249076Swpaulstruct sf_frag { 80349076Swpaul u_int32_t sf_addr; 80449076Swpaul u_int16_t sf_fraglen; 80549076Swpaul u_int16_t sf_pktlen; 80649076Swpaul}; 80749076Swpaul 80849076Swpaulstruct sf_frag_msdos { 80949076Swpaul u_int16_t sf_pktlen; 81049076Swpaul u_int16_t sf_fraglen; 81149076Swpaul u_int32_t sf_addr; 81249076Swpaul}; 81349076Swpaul 81449076Swpaul/* 81549076Swpaul * TX frame descriptor type 0, 32-bit addressing. One descriptor can 81649076Swpaul * be used to map multiple packet fragments. We use this format since 81749076Swpaul * BSD networking fragments packet data across mbuf chains. Note that 81849076Swpaul * the number of fragments can be variable depending on how the descriptor 81949076Swpaul * spacing is specified in the TX descriptor queue control register. 82049076Swpaul * We always use a spacing of 128 bytes, and a skipfield length of 8 82149076Swpaul * bytes: this means 16 bytes for the descriptor, including the skipfield, 82249076Swpaul * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 82349076Swpaul * which allows for 14 fragments per descriptor. The total size of the 82449076Swpaul * transmit buffer queue is limited to 16384 bytes, so with a spacing of 82549076Swpaul * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 82649076Swpaul */ 82749076Swpaulstruct sf_tx_bufdesc_type0 { 82849076Swpaul#ifdef __i386__ 82949076Swpaul u_int32_t sf_pad; 83049076Swpaul#endif 83149076Swpaul struct mbuf *sf_mbuf; 83249076Swpaul u_int32_t sf_rsvd0:24, 83349076Swpaul sf_crcen:1, 83449076Swpaul sf_caltcp:1, 83549076Swpaul sf_end:1, 83649076Swpaul sf_intr:1, 83749076Swpaul sf_id:4; 83849076Swpaul u_int8_t sf_fragcnt; 83949076Swpaul u_int8_t sf_rsvd2; 84049076Swpaul u_int16_t sf_rsvd1; 84149076Swpaul struct sf_frag sf_frags[14]; 84249076Swpaul}; 84349076Swpaul 84449076Swpaul/* 84549076Swpaul * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 84649076Swpaul * maps a single fragment. 84749076Swpaul */ 84849076Swpaulstruct sf_tx_bufdesc_type1 { 84949076Swpaul#ifdef __i386__ 85049076Swpaul u_int32_t sf_pad; 85149076Swpaul#endif 85249076Swpaul struct mbuf *sf_mbuf; 85349076Swpaul u_int32_t sf_fraglen:16, 85449076Swpaul sf_fragcnt:8, 85549076Swpaul sf_crcen:1, 85649076Swpaul sf_caltcp:1, 85749076Swpaul sf_end:1, 85849076Swpaul sf_intr:1, 85949076Swpaul sf_id:4; 86049076Swpaul u_int32_t sf_addr; 86149076Swpaul}; 86249076Swpaul 86349076Swpaul/* 86449076Swpaul * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 86549076Swpaul * maps a single fragment. 86649076Swpaul */ 86749076Swpaulstruct sf_tx_bufdesc_type2 { 86849076Swpaul#ifdef __i386__ 86949076Swpaul u_int32_t sf_pad; 87049076Swpaul#endif 87149076Swpaul struct mbuf *sf_mbuf; 87249076Swpaul u_int32_t sf_fraglen:16, 87349076Swpaul sf_fragcnt:8, 87449076Swpaul sf_crcen:1, 87549076Swpaul sf_caltcp:1, 87649076Swpaul sf_end:1, 87749076Swpaul sf_intr:1, 87849076Swpaul sf_id:4; 87949076Swpaul u_int32_t sf_addrlo; 88049076Swpaul u_int32_t sf_addrhi; 88149076Swpaul}; 88249076Swpaul 88349076Swpaul/* TX buffer descriptor type 3 is not defined. */ 88449076Swpaul 88549076Swpaul/* 88649076Swpaul * TX frame descriptor type 4, 32-bit addressing. This is a special 88749076Swpaul * case of the type 0 descriptor, identical except that the fragment 88849076Swpaul * address and length fields are ordered differently. This is done 88949076Swpaul * to optimize copies in MS-DOS and OS/2 drivers. 89049076Swpaul */ 89149076Swpaulstruct sf_tx_bufdesc_type4 { 89249076Swpaul#ifdef __i386__ 89349076Swpaul u_int32_t sf_pad; 89449076Swpaul#endif 89549076Swpaul struct mbuf *sf_mbuf; 89649076Swpaul u_int32_t sf_rsvd0:24, 89749076Swpaul sf_crcen:1, 89849076Swpaul sf_caltcp:1, 89949076Swpaul sf_end:1, 90049076Swpaul sf_intr:1, 90149076Swpaul sf_id:4; 90249076Swpaul u_int8_t sf_fragcnt; 90349076Swpaul u_int8_t sf_rsvd2; 90449076Swpaul u_int16_t sf_rsvd1; 90549076Swpaul struct sf_frag_msdos sf_frags[14]; 90649076Swpaul}; 90749076Swpaul 90849076Swpaul/* 90949076Swpaul * Transmit completion queue descriptor formats. 91049076Swpaul */ 91149076Swpaul 91249076Swpaul/* 91349076Swpaul * Transmit DMA completion descriptor, type 0. 91449076Swpaul */ 91549076Swpaul#define SF_TXCMPTYPE_DMA 0x4 91649076Swpaulstruct sf_tx_cmpdesc_type0 { 91749076Swpaul u_int32_t sf_index:15, 91849076Swpaul sf_priority:1, 91949076Swpaul sf_timestamp:13, 92049076Swpaul sf_type:3; 92149076Swpaul}; 92249076Swpaul 92349076Swpaul/* 92449076Swpaul * Transmit completion descriptor, type 1. 92549076Swpaul */ 92649076Swpaul#define SF_TXCMPTYPE_TX 0x5 92749076Swpaulstruct sf_tx_cmpdesc_type1 { 92849076Swpaul u_int32_t sf_index:15, 92949076Swpaul sf_priority:1, 93049076Swpaul sf_txstat:13, 93149076Swpaul sf_type:3; 93249076Swpaul}; 93349076Swpaul 93449076Swpaul#define SF_TXSTAT_CRCERR 0x0001 93549076Swpaul#define SF_TXSTAT_LENCHECKERR 0x0002 93649076Swpaul#define SF_TXSTAT_LENRANGEERR 0x0004 93749076Swpaul#define SF_TXSTAT_TX_OK 0x0008 93849076Swpaul#define SF_TXSTAT_TX_DEFERED 0x0010 93949076Swpaul#define SF_TXSTAT_EXCESS_DEFER 0x0020 94049076Swpaul#define SF_TXSTAT_EXCESS_COLL 0x0040 94149076Swpaul#define SF_TXSTAT_LATE_COLL 0x0080 94249076Swpaul#define SF_TXSTAT_TOOBIG 0x0100 94349076Swpaul#define SF_TXSTAT_TX_UNDERRUN 0x0200 94449076Swpaul#define SF_TXSTAT_CTLFRAME_OK 0x0400 94549076Swpaul#define SF_TXSTAT_PAUSEFRAME_OK 0x0800 94649076Swpaul#define SF_TXSTAT_PAUSED 0x1000 94749076Swpaul 94849076Swpaul/* Statistics counters. */ 94949076Swpaulstruct sf_stats { 95049076Swpaul u_int32_t sf_tx_frames; 95149076Swpaul u_int32_t sf_tx_single_colls; 95249076Swpaul u_int32_t sf_tx_multi_colls; 95349076Swpaul u_int32_t sf_tx_crcerrs; 95449076Swpaul u_int32_t sf_tx_bytes; 95549076Swpaul u_int32_t sf_tx_defered; 95649076Swpaul u_int32_t sf_tx_late_colls; 95749076Swpaul u_int32_t sf_tx_pause_frames; 95849076Swpaul u_int32_t sf_tx_control_frames; 95949076Swpaul u_int32_t sf_tx_excess_colls; 96049076Swpaul u_int32_t sf_tx_excess_defer; 96149076Swpaul u_int32_t sf_tx_mcast_frames; 96249076Swpaul u_int32_t sf_tx_bcast_frames; 96349076Swpaul u_int32_t sf_tx_frames_lost; 96449076Swpaul u_int32_t sf_rx_rx_frames; 96549076Swpaul u_int32_t sf_rx_crcerrs; 96649076Swpaul u_int32_t sf_rx_alignerrs; 96749076Swpaul u_int32_t sf_rx_bytes; 96849076Swpaul u_int32_t sf_rx_control_frames; 96949076Swpaul u_int32_t sf_rx_unsup_control_frames; 97049076Swpaul u_int32_t sf_rx_giants; 97149076Swpaul u_int32_t sf_rx_runts; 97249076Swpaul u_int32_t sf_rx_jabbererrs; 97349076Swpaul u_int32_t sf_rx_pkts_64; 97449076Swpaul u_int32_t sf_rx_pkts_65_127; 97549076Swpaul u_int32_t sf_rx_pkts_128_255; 97649076Swpaul u_int32_t sf_rx_pkts_256_511; 97749076Swpaul u_int32_t sf_rx_pkts_512_1023; 97849076Swpaul u_int32_t sf_rx_pkts_1024_1518; 97949076Swpaul u_int32_t sf_rx_frames_lost; 98049076Swpaul u_int16_t sf_tx_underruns; 98149076Swpaul u_int16_t sf_pad; 98249076Swpaul}; 98349076Swpaul 98449076Swpaul/* 98549076Swpaul * register space access macros 98649076Swpaul */ 98749076Swpaul#define CSR_WRITE_4(sc, reg, val) \ 98849076Swpaul bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val) 98949076Swpaul 99049076Swpaul#define CSR_READ_4(sc, reg) \ 99149076Swpaul bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg) 99249076Swpaul 99349076Swpaul#define CSR_READ_1(sc, reg) \ 99449076Swpaul bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg) 99549076Swpaul 99649076Swpaul 99749076Swpaulstruct sf_type { 99849076Swpaul u_int16_t sf_vid; 99949076Swpaul u_int16_t sf_did; 100049076Swpaul char *sf_name; 100149076Swpaul}; 100249076Swpaul 100349076Swpaul#define SF_INC(x, y) (x) = (x + 1) % y 100449076Swpaul 100549076Swpaul#define ETHER_ALIGN 2 100649076Swpaul 100749076Swpaul/* 100849076Swpaul * Note: alignment is important here: each list must be aligned to 100949076Swpaul * a 256-byte boundary. It turns out that each ring is some multiple 101049076Swpaul * of 4K in length, so we can stack them all on top of each other 101149076Swpaul * and just worry about aligning the whole mess. There's one transmit 101249076Swpaul * buffer ring and two receive buffer rings: one RX ring is for small 101349076Swpaul * packets and the other is for large packets. Each buffer ring also 101449076Swpaul * has a companion completion queue. 101549076Swpaul */ 101649076Swpaulstruct sf_list_data { 101749076Swpaul struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT]; 101849076Swpaul struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 101949076Swpaul struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 102050863Swpaul#ifdef notdef 102150863Swpaul /* 102250863Swpaul * Unfortunately, because the Starfire doesn't allow arbitrary 102350863Swpaul * byte alignment, we have to copy packets in the RX handler in 102450863Swpaul * order to align the payload correctly. This means that we 102550863Swpaul * don't gain anything by having separate large and small descriptor 102650863Swpaul * lists, so for now we don't bother with the small one. 102750863Swpaul */ 102849076Swpaul struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 102950863Swpaul#endif 103049076Swpaul struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 103149076Swpaul}; 103249076Swpaul 103349076Swpaulstruct sf_softc { 1034147256Sbrooks struct ifnet *sf_ifp; /* interface info */ 1035162317Sru device_t sf_dev; /* device info */ 103649076Swpaul bus_space_handle_t sf_bhandle; /* bus space handle */ 103749076Swpaul bus_space_tag_t sf_btag; /* bus space tag */ 103849076Swpaul void *sf_intrhand; /* interrupt handler cookie */ 103949076Swpaul struct resource *sf_irq; /* irq resource descriptor */ 104049076Swpaul struct resource *sf_res; /* mem/ioport resource */ 104149076Swpaul struct sf_type *sf_info; /* Starfire adapter info */ 104250675Swpaul device_t sf_miibus; 104349076Swpaul struct sf_list_data *sf_ldata; 104449076Swpaul int sf_tx_cnt; 104554161Swpaul u_int8_t sf_link; 104654161Swpaul int sf_if_flags; 1047149240Sjhb struct callout sf_stat_callout; 104867087Swpaul struct mtx sf_mtx; 1049137557Sbrueffer#ifdef DEVICE_POLLING 1050137557Sbrueffer int rxcycles; 1051137834Sbrueffer#endif /* DEVICE_POLLING */ 105249076Swpaul}; 105349076Swpaul 105467087Swpaul 105572200Sbmilekic#define SF_LOCK(_sc) mtx_lock(&(_sc)->sf_mtx) 105672200Sbmilekic#define SF_UNLOCK(_sc) mtx_unlock(&(_sc)->sf_mtx) 1057122689Ssam#define SF_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sf_mtx, MA_OWNED) 105867087Swpaul 105949076Swpaul#define SF_TIMEOUT 1000 1060