if_pcn.c revision 213893
1/*- 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/pcn/if_pcn.c 213893 2010-10-15 14:52:11Z marius $"); 36 37/* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available 39 * from http://www.amd.com. 40 * 41 * The AMD PCnet/PCI controllers are more advanced and functional 42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 43 * backwards compatibility with the LANCE and thus can be made 44 * to work with older LANCE drivers. This is in fact how the 45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 46 * is that the PCnet/PCI devices offer several performance enhancements 47 * which can't be exploited in LANCE compatibility mode. Chief among 48 * these enhancements is the ability to perform PCI DMA operations 49 * using 32-bit addressing (which eliminates the need for ISA 50 * bounce-buffering), and special receive buffer alignment (which 51 * allows the receive handler to pass packets to the upper protocol 52 * layers without copying on both the x86 and alpha platforms). 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/module.h> 62#include <sys/socket.h> 63 64#include <net/if.h> 65#include <net/if_arp.h> 66#include <net/ethernet.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69#include <net/if_types.h> 70 71#include <net/bpf.h> 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <dev/pci/pcireg.h> 84#include <dev/pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <dev/pcn/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "device miibus" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static const struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static const struct pcn_chipid { 107 u_int32_t id; 108 const char *name; 109} pcn_chipid[] = { 110 { Am79C971, "Am79C971" }, 111 { Am79C972, "Am79C972" }, 112 { Am79C973, "Am79C973" }, 113 { Am79C978, "Am79C978" }, 114 { Am79C975, "Am79C975" }, 115 { Am79C976, "Am79C976" }, 116 { 0, NULL }, 117}; 118 119static const char *pcn_chipid_name(u_int32_t); 120static u_int32_t pcn_chip_id(device_t); 121static const struct pcn_type *pcn_match(u_int16_t, u_int16_t); 122 123static u_int32_t pcn_csr_read(struct pcn_softc *, int); 124static u_int16_t pcn_csr_read16(struct pcn_softc *, int); 125static u_int16_t pcn_bcr_read16(struct pcn_softc *, int); 126static void pcn_csr_write(struct pcn_softc *, int, int); 127static u_int32_t pcn_bcr_read(struct pcn_softc *, int); 128static void pcn_bcr_write(struct pcn_softc *, int, int); 129 130static int pcn_probe(device_t); 131static int pcn_attach(device_t); 132static int pcn_detach(device_t); 133 134static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *); 135static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *); 136static void pcn_rxeof(struct pcn_softc *); 137static void pcn_txeof(struct pcn_softc *); 138static void pcn_intr(void *); 139static void pcn_tick(void *); 140static void pcn_start(struct ifnet *); 141static void pcn_start_locked(struct ifnet *); 142static int pcn_ioctl(struct ifnet *, u_long, caddr_t); 143static void pcn_init(void *); 144static void pcn_init_locked(struct pcn_softc *); 145static void pcn_stop(struct pcn_softc *); 146static void pcn_watchdog(struct pcn_softc *); 147static int pcn_shutdown(device_t); 148static int pcn_ifmedia_upd(struct ifnet *); 149static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *); 150 151static int pcn_miibus_readreg(device_t, int, int); 152static int pcn_miibus_writereg(device_t, int, int, int); 153static void pcn_miibus_statchg(device_t); 154 155static void pcn_setfilt(struct ifnet *); 156static void pcn_setmulti(struct pcn_softc *); 157static void pcn_reset(struct pcn_softc *); 158static int pcn_list_rx_init(struct pcn_softc *); 159static int pcn_list_tx_init(struct pcn_softc *); 160 161#ifdef PCN_USEIOSPACE 162#define PCN_RES SYS_RES_IOPORT 163#define PCN_RID PCN_PCI_LOIO 164#else 165#define PCN_RES SYS_RES_MEMORY 166#define PCN_RID PCN_PCI_LOMEM 167#endif 168 169static device_method_t pcn_methods[] = { 170 /* Device interface */ 171 DEVMETHOD(device_probe, pcn_probe), 172 DEVMETHOD(device_attach, pcn_attach), 173 DEVMETHOD(device_detach, pcn_detach), 174 DEVMETHOD(device_shutdown, pcn_shutdown), 175 176 /* bus interface */ 177 DEVMETHOD(bus_print_child, bus_generic_print_child), 178 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 179 180 /* MII interface */ 181 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 182 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 183 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 184 185 { 0, 0 } 186}; 187 188static driver_t pcn_driver = { 189 "pcn", 190 pcn_methods, 191 sizeof(struct pcn_softc) 192}; 193 194static devclass_t pcn_devclass; 195 196DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 197DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 198 199#define PCN_CSR_SETBIT(sc, reg, x) \ 200 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 201 202#define PCN_CSR_CLRBIT(sc, reg, x) \ 203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 204 205#define PCN_BCR_SETBIT(sc, reg, x) \ 206 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 207 208#define PCN_BCR_CLRBIT(sc, reg, x) \ 209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 210 211static u_int32_t 212pcn_csr_read(sc, reg) 213 struct pcn_softc *sc; 214 int reg; 215{ 216 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 217 return(CSR_READ_4(sc, PCN_IO32_RDP)); 218} 219 220static u_int16_t 221pcn_csr_read16(sc, reg) 222 struct pcn_softc *sc; 223 int reg; 224{ 225 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 226 return(CSR_READ_2(sc, PCN_IO16_RDP)); 227} 228 229static void 230pcn_csr_write(sc, reg, val) 231 struct pcn_softc *sc; 232 int reg; 233 int val; 234{ 235 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 236 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 237 return; 238} 239 240static u_int32_t 241pcn_bcr_read(sc, reg) 242 struct pcn_softc *sc; 243 int reg; 244{ 245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 246 return(CSR_READ_4(sc, PCN_IO32_BDP)); 247} 248 249static u_int16_t 250pcn_bcr_read16(sc, reg) 251 struct pcn_softc *sc; 252 int reg; 253{ 254 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 255 return(CSR_READ_2(sc, PCN_IO16_BDP)); 256} 257 258static void 259pcn_bcr_write(sc, reg, val) 260 struct pcn_softc *sc; 261 int reg; 262 int val; 263{ 264 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 265 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 266 return; 267} 268 269static int 270pcn_miibus_readreg(dev, phy, reg) 271 device_t dev; 272 int phy, reg; 273{ 274 struct pcn_softc *sc; 275 int val; 276 277 sc = device_get_softc(dev); 278 279 /* 280 * At least Am79C971 with DP83840A wedge when isolating the 281 * external PHY so we can't allow multiple external PHYs. 282 * There are cards that use Am79C971 with both the internal 283 * and an external PHY though. 284 * For internal PHYs it doesn't really matter whether we can 285 * isolate the remaining internal and the external ones in 286 * the PHY drivers as the internal PHYs have to be enabled 287 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc. 288 * With Am79C97{3,5,8} we don't support switching beetween 289 * the internal and external PHYs, yet, so we can't allow 290 * multiple PHYs with these either. 291 * Am79C97{2,6} actually only support external PHYs (not 292 * connectable internal ones respond at the usual addresses, 293 * which don't hurt if we let them show up on the bus) and 294 * isolating them works. 295 */ 296 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) || 297 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 || 298 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr != -1 && 299 phy != sc->pcn_extphyaddr) 300 return(0); 301 302 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 303 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 304 if (val == 0xFFFF) 305 return(0); 306 307 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) || 308 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 || 309 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr == -1) 310 sc->pcn_extphyaddr = phy; 311 312 return(val); 313} 314 315static int 316pcn_miibus_writereg(dev, phy, reg, data) 317 device_t dev; 318 int phy, reg, data; 319{ 320 struct pcn_softc *sc; 321 322 sc = device_get_softc(dev); 323 324 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 325 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 326 327 return(0); 328} 329 330static void 331pcn_miibus_statchg(dev) 332 device_t dev; 333{ 334 struct pcn_softc *sc; 335 struct mii_data *mii; 336 337 sc = device_get_softc(dev); 338 mii = device_get_softc(sc->pcn_miibus); 339 340 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 341 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 342 } else { 343 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 344 } 345 346 return; 347} 348 349static void 350pcn_setmulti(sc) 351 struct pcn_softc *sc; 352{ 353 struct ifnet *ifp; 354 struct ifmultiaddr *ifma; 355 u_int32_t h, i; 356 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 357 358 ifp = sc->pcn_ifp; 359 360 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 361 362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 363 for (i = 0; i < 4; i++) 364 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 365 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 366 return; 367 } 368 369 /* first, zot all the existing hash bits */ 370 for (i = 0; i < 4; i++) 371 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 372 373 /* now program new ones */ 374 if_maddr_rlock(ifp); 375 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 376 if (ifma->ifma_addr->sa_family != AF_LINK) 377 continue; 378 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 379 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 380 hashes[h >> 4] |= 1 << (h & 0xF); 381 } 382 if_maddr_runlock(ifp); 383 384 for (i = 0; i < 4; i++) 385 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 386 387 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 388 389 return; 390} 391 392static void 393pcn_reset(sc) 394 struct pcn_softc *sc; 395{ 396 /* 397 * Issue a reset by reading from the RESET register. 398 * Note that we don't know if the chip is operating in 399 * 16-bit or 32-bit mode at this point, so we attempt 400 * to reset the chip both ways. If one fails, the other 401 * will succeed. 402 */ 403 CSR_READ_2(sc, PCN_IO16_RESET); 404 CSR_READ_4(sc, PCN_IO32_RESET); 405 406 /* Wait a little while for the chip to get its brains in order. */ 407 DELAY(1000); 408 409 /* Select 32-bit (DWIO) mode */ 410 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 411 412 /* Select software style 3. */ 413 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 414 415 return; 416} 417 418static const char * 419pcn_chipid_name(u_int32_t id) 420{ 421 const struct pcn_chipid *p; 422 423 p = pcn_chipid; 424 while (p->name) { 425 if (id == p->id) 426 return (p->name); 427 p++; 428 } 429 return ("Unknown"); 430} 431 432static u_int32_t 433pcn_chip_id(device_t dev) 434{ 435 struct pcn_softc *sc; 436 u_int32_t chip_id; 437 438 sc = device_get_softc(dev); 439 /* 440 * Note: we can *NOT* put the chip into 441 * 32-bit mode yet. The le(4) driver will only 442 * work in 16-bit mode, and once the chip 443 * goes into 32-bit mode, the only way to 444 * get it out again is with a hardware reset. 445 * So if pcn_probe() is called before the 446 * le(4) driver's probe routine, the chip will 447 * be locked into 32-bit operation and the 448 * le(4) driver will be unable to attach to it. 449 * Note II: if the chip happens to already 450 * be in 32-bit mode, we still need to check 451 * the chip ID, but first we have to detect 452 * 32-bit mode using only 16-bit operations. 453 * The safest way to do this is to read the 454 * PCI subsystem ID from BCR23/24 and compare 455 * that with the value read from PCI config 456 * space. 457 */ 458 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 459 chip_id <<= 16; 460 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 461 /* 462 * Note III: the test for 0x10001000 is a hack to 463 * pacify VMware, who's pseudo-PCnet interface is 464 * broken. Reading the subsystem register from PCI 465 * config space yields 0x00000000 while reading the 466 * same value from I/O space yields 0x10001000. It's 467 * not supposed to be that way. 468 */ 469 if (chip_id == pci_read_config(dev, 470 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 471 /* We're in 16-bit mode. */ 472 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 473 chip_id <<= 16; 474 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 475 } else { 476 /* We're in 32-bit mode. */ 477 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 478 chip_id <<= 16; 479 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 480 } 481 482 return (chip_id); 483} 484 485static const struct pcn_type * 486pcn_match(u_int16_t vid, u_int16_t did) 487{ 488 const struct pcn_type *t; 489 490 t = pcn_devs; 491 while (t->pcn_name != NULL) { 492 if ((vid == t->pcn_vid) && (did == t->pcn_did)) 493 return (t); 494 t++; 495 } 496 return (NULL); 497} 498 499/* 500 * Probe for an AMD chip. Check the PCI vendor and device 501 * IDs against our list and return a device name if we find a match. 502 */ 503static int 504pcn_probe(dev) 505 device_t dev; 506{ 507 const struct pcn_type *t; 508 struct pcn_softc *sc; 509 int rid; 510 u_int32_t chip_id; 511 512 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev)); 513 if (t == NULL) 514 return (ENXIO); 515 sc = device_get_softc(dev); 516 517 /* 518 * Temporarily map the I/O space so we can read the chip ID register. 519 */ 520 rid = PCN_RID; 521 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 522 if (sc->pcn_res == NULL) { 523 device_printf(dev, "couldn't map ports/memory\n"); 524 return(ENXIO); 525 } 526 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 527 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 528 529 chip_id = pcn_chip_id(dev); 530 531 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 532 533 switch((chip_id >> 12) & PART_MASK) { 534 case Am79C971: 535 case Am79C972: 536 case Am79C973: 537 case Am79C975: 538 case Am79C976: 539 case Am79C978: 540 break; 541 default: 542 return(ENXIO); 543 } 544 device_set_desc(dev, t->pcn_name); 545 return(BUS_PROBE_DEFAULT); 546} 547 548/* 549 * Attach the interface. Allocate softc structures, do ifmedia 550 * setup and ethernet/BPF attach. 551 */ 552static int 553pcn_attach(dev) 554 device_t dev; 555{ 556 u_int32_t eaddr[2]; 557 struct pcn_softc *sc; 558 struct mii_data *mii; 559 struct mii_softc *miisc; 560 struct ifnet *ifp; 561 int error = 0, rid; 562 563 sc = device_get_softc(dev); 564 565 /* Initialize our mutex. */ 566 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 567 MTX_DEF); 568 /* 569 * Map control/status registers. 570 */ 571 pci_enable_busmaster(dev); 572 573 /* Retrieve the chip ID */ 574 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK; 575 device_printf(dev, "Chip ID %04x (%s)\n", 576 sc->pcn_type, pcn_chipid_name(sc->pcn_type)); 577 578 rid = PCN_RID; 579 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 580 581 if (sc->pcn_res == NULL) { 582 device_printf(dev, "couldn't map ports/memory\n"); 583 error = ENXIO; 584 goto fail; 585 } 586 587 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 588 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 589 590 /* Allocate interrupt */ 591 rid = 0; 592 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 593 RF_SHAREABLE | RF_ACTIVE); 594 595 if (sc->pcn_irq == NULL) { 596 device_printf(dev, "couldn't map interrupt\n"); 597 error = ENXIO; 598 goto fail; 599 } 600 601 /* Reset the adapter. */ 602 pcn_reset(sc); 603 604 /* 605 * Get station address from the EEPROM. 606 */ 607 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 608 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 609 610 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0); 611 612 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 613 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 614 615 if (sc->pcn_ldata == NULL) { 616 device_printf(dev, "no memory for list buffers!\n"); 617 error = ENXIO; 618 goto fail; 619 } 620 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 621 622 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER); 623 if (ifp == NULL) { 624 device_printf(dev, "can not if_alloc()\n"); 625 error = ENOSPC; 626 goto fail; 627 } 628 ifp->if_softc = sc; 629 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 631 ifp->if_ioctl = pcn_ioctl; 632 ifp->if_start = pcn_start; 633 ifp->if_init = pcn_init; 634 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 635 636 /* 637 * Do MII setup. Note that loopback support isn't implemented. 638 * See the comment in pcn_miibus_readreg() for why we can't 639 * universally pass MIIF_NOISOLATE here. 640 */ 641 sc->pcn_extphyaddr = -1; 642 error = mii_attach(dev, &sc->pcn_miibus, ifp, pcn_ifmedia_upd, 643 pcn_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 644 MIIF_NOLOOP); 645 if (error != 0) { 646 device_printf(dev, "attaching PHYs failed\n"); 647 goto fail; 648 } 649 /* 650 * Record the media instances of internal PHYs, which map the 651 * built-in interfaces to the MII, so we can set the active 652 * PHY/port based on the currently selected media. 653 */ 654 sc->pcn_inst_10bt = -1; 655 mii = device_get_softc(sc->pcn_miibus); 656 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 657 switch (miisc->mii_phy) { 658 case PCN_PHYAD_10BT: 659 sc->pcn_inst_10bt = miisc->mii_inst; 660 break; 661 /* 662 * XXX deal with the Am79C97{3,5} internal 100baseT 663 * and the Am79C978 internal HomePNA PHYs. 664 */ 665 } 666 } 667 668 /* 669 * Call MI attach routine. 670 */ 671 ether_ifattach(ifp, (u_int8_t *) eaddr); 672 673 /* Hook interrupt last to avoid having to lock softc */ 674 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE, 675 NULL, pcn_intr, sc, &sc->pcn_intrhand); 676 677 if (error) { 678 device_printf(dev, "couldn't set up irq\n"); 679 ether_ifdetach(ifp); 680 goto fail; 681 } 682 683fail: 684 if (error) 685 pcn_detach(dev); 686 687 return(error); 688} 689 690/* 691 * Shutdown hardware and free up resources. This can be called any 692 * time after the mutex has been initialized. It is called in both 693 * the error case in attach and the normal detach case so it needs 694 * to be careful about only freeing resources that have actually been 695 * allocated. 696 */ 697static int 698pcn_detach(dev) 699 device_t dev; 700{ 701 struct pcn_softc *sc; 702 struct ifnet *ifp; 703 704 sc = device_get_softc(dev); 705 ifp = sc->pcn_ifp; 706 707 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 708 709 /* These should only be active if attach succeeded */ 710 if (device_is_attached(dev)) { 711 PCN_LOCK(sc); 712 pcn_reset(sc); 713 pcn_stop(sc); 714 PCN_UNLOCK(sc); 715 callout_drain(&sc->pcn_stat_callout); 716 ether_ifdetach(ifp); 717 } 718 if (sc->pcn_miibus) 719 device_delete_child(dev, sc->pcn_miibus); 720 bus_generic_detach(dev); 721 722 if (sc->pcn_intrhand) 723 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 724 if (sc->pcn_irq) 725 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 726 if (sc->pcn_res) 727 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 728 729 if (ifp) 730 if_free(ifp); 731 732 if (sc->pcn_ldata) { 733 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 734 M_DEVBUF); 735 } 736 737 mtx_destroy(&sc->pcn_mtx); 738 739 return(0); 740} 741 742/* 743 * Initialize the transmit descriptors. 744 */ 745static int 746pcn_list_tx_init(sc) 747 struct pcn_softc *sc; 748{ 749 struct pcn_list_data *ld; 750 struct pcn_ring_data *cd; 751 int i; 752 753 cd = &sc->pcn_cdata; 754 ld = sc->pcn_ldata; 755 756 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 757 cd->pcn_tx_chain[i] = NULL; 758 ld->pcn_tx_list[i].pcn_tbaddr = 0; 759 ld->pcn_tx_list[i].pcn_txctl = 0; 760 ld->pcn_tx_list[i].pcn_txstat = 0; 761 } 762 763 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 764 765 return(0); 766} 767 768 769/* 770 * Initialize the RX descriptors and allocate mbufs for them. 771 */ 772static int 773pcn_list_rx_init(sc) 774 struct pcn_softc *sc; 775{ 776 struct pcn_ring_data *cd; 777 int i; 778 779 cd = &sc->pcn_cdata; 780 781 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 782 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 783 return(ENOBUFS); 784 } 785 786 cd->pcn_rx_prod = 0; 787 788 return(0); 789} 790 791/* 792 * Initialize an RX descriptor and attach an MBUF cluster. 793 */ 794static int 795pcn_newbuf(sc, idx, m) 796 struct pcn_softc *sc; 797 int idx; 798 struct mbuf *m; 799{ 800 struct mbuf *m_new = NULL; 801 struct pcn_rx_desc *c; 802 803 c = &sc->pcn_ldata->pcn_rx_list[idx]; 804 805 if (m == NULL) { 806 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 807 if (m_new == NULL) 808 return(ENOBUFS); 809 810 MCLGET(m_new, M_DONTWAIT); 811 if (!(m_new->m_flags & M_EXT)) { 812 m_freem(m_new); 813 return(ENOBUFS); 814 } 815 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 816 } else { 817 m_new = m; 818 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 819 m_new->m_data = m_new->m_ext.ext_buf; 820 } 821 822 m_adj(m_new, ETHER_ALIGN); 823 824 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 825 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 826 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 827 c->pcn_bufsz |= PCN_RXLEN_MBO; 828 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 829 830 return(0); 831} 832 833/* 834 * A frame has been uploaded: pass the resulting mbuf chain up to 835 * the higher level protocols. 836 */ 837static void 838pcn_rxeof(sc) 839 struct pcn_softc *sc; 840{ 841 struct mbuf *m; 842 struct ifnet *ifp; 843 struct pcn_rx_desc *cur_rx; 844 int i; 845 846 PCN_LOCK_ASSERT(sc); 847 848 ifp = sc->pcn_ifp; 849 i = sc->pcn_cdata.pcn_rx_prod; 850 851 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 852 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 853 m = sc->pcn_cdata.pcn_rx_chain[i]; 854 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 855 856 /* 857 * If an error occurs, update stats, clear the 858 * status word and leave the mbuf cluster in place: 859 * it should simply get re-used next time this descriptor 860 * comes up in the ring. 861 */ 862 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 863 ifp->if_ierrors++; 864 pcn_newbuf(sc, i, m); 865 PCN_INC(i, PCN_RX_LIST_CNT); 866 continue; 867 } 868 869 if (pcn_newbuf(sc, i, NULL)) { 870 /* Ran out of mbufs; recycle this one. */ 871 pcn_newbuf(sc, i, m); 872 ifp->if_ierrors++; 873 PCN_INC(i, PCN_RX_LIST_CNT); 874 continue; 875 } 876 877 PCN_INC(i, PCN_RX_LIST_CNT); 878 879 /* No errors; receive the packet. */ 880 ifp->if_ipackets++; 881 m->m_len = m->m_pkthdr.len = 882 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 883 m->m_pkthdr.rcvif = ifp; 884 885 PCN_UNLOCK(sc); 886 (*ifp->if_input)(ifp, m); 887 PCN_LOCK(sc); 888 } 889 890 sc->pcn_cdata.pcn_rx_prod = i; 891 892 return; 893} 894 895/* 896 * A frame was downloaded to the chip. It's safe for us to clean up 897 * the list buffers. 898 */ 899 900static void 901pcn_txeof(sc) 902 struct pcn_softc *sc; 903{ 904 struct pcn_tx_desc *cur_tx = NULL; 905 struct ifnet *ifp; 906 u_int32_t idx; 907 908 ifp = sc->pcn_ifp; 909 910 /* 911 * Go through our tx list and free mbufs for those 912 * frames that have been transmitted. 913 */ 914 idx = sc->pcn_cdata.pcn_tx_cons; 915 while (idx != sc->pcn_cdata.pcn_tx_prod) { 916 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 917 918 if (!PCN_OWN_TXDESC(cur_tx)) 919 break; 920 921 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 922 sc->pcn_cdata.pcn_tx_cnt--; 923 PCN_INC(idx, PCN_TX_LIST_CNT); 924 continue; 925 } 926 927 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 928 ifp->if_oerrors++; 929 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 930 ifp->if_collisions++; 931 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 932 ifp->if_collisions++; 933 } 934 935 ifp->if_collisions += 936 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 937 938 ifp->if_opackets++; 939 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 940 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 941 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 942 } 943 944 sc->pcn_cdata.pcn_tx_cnt--; 945 PCN_INC(idx, PCN_TX_LIST_CNT); 946 } 947 948 if (idx != sc->pcn_cdata.pcn_tx_cons) { 949 /* Some buffers have been freed. */ 950 sc->pcn_cdata.pcn_tx_cons = idx; 951 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 952 } 953 sc->pcn_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 954 955 return; 956} 957 958static void 959pcn_tick(xsc) 960 void *xsc; 961{ 962 struct pcn_softc *sc; 963 struct mii_data *mii; 964 struct ifnet *ifp; 965 966 sc = xsc; 967 ifp = sc->pcn_ifp; 968 PCN_LOCK_ASSERT(sc); 969 970 mii = device_get_softc(sc->pcn_miibus); 971 mii_tick(mii); 972 973 /* link just died */ 974 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 975 sc->pcn_link = 0; 976 977 /* link just came up, restart */ 978 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 979 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 980 sc->pcn_link++; 981 if (ifp->if_snd.ifq_head != NULL) 982 pcn_start_locked(ifp); 983 } 984 985 if (sc->pcn_timer > 0 && --sc->pcn_timer == 0) 986 pcn_watchdog(sc); 987 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc); 988 989 return; 990} 991 992static void 993pcn_intr(arg) 994 void *arg; 995{ 996 struct pcn_softc *sc; 997 struct ifnet *ifp; 998 u_int32_t status; 999 1000 sc = arg; 1001 ifp = sc->pcn_ifp; 1002 1003 PCN_LOCK(sc); 1004 1005 /* Suppress unwanted interrupts */ 1006 if (!(ifp->if_flags & IFF_UP)) { 1007 pcn_stop(sc); 1008 PCN_UNLOCK(sc); 1009 return; 1010 } 1011 1012 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 1013 1014 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 1015 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 1016 1017 if (status & PCN_CSR_RINT) 1018 pcn_rxeof(sc); 1019 1020 if (status & PCN_CSR_TINT) 1021 pcn_txeof(sc); 1022 1023 if (status & PCN_CSR_ERR) { 1024 pcn_init_locked(sc); 1025 break; 1026 } 1027 } 1028 1029 if (ifp->if_snd.ifq_head != NULL) 1030 pcn_start_locked(ifp); 1031 1032 PCN_UNLOCK(sc); 1033 return; 1034} 1035 1036/* 1037 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1038 * pointers to the fragment pointers. 1039 */ 1040static int 1041pcn_encap(sc, m_head, txidx) 1042 struct pcn_softc *sc; 1043 struct mbuf *m_head; 1044 u_int32_t *txidx; 1045{ 1046 struct pcn_tx_desc *f = NULL; 1047 struct mbuf *m; 1048 int frag, cur, cnt = 0; 1049 1050 /* 1051 * Start packing the mbufs in this chain into 1052 * the fragment pointers. Stop when we run out 1053 * of fragments or hit the end of the mbuf chain. 1054 */ 1055 m = m_head; 1056 cur = frag = *txidx; 1057 1058 for (m = m_head; m != NULL; m = m->m_next) { 1059 if (m->m_len == 0) 1060 continue; 1061 1062 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1063 return(ENOBUFS); 1064 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1065 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1066 f->pcn_txctl |= PCN_TXCTL_MBO; 1067 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1068 if (cnt == 0) 1069 f->pcn_txctl |= PCN_TXCTL_STP; 1070 else 1071 f->pcn_txctl |= PCN_TXCTL_OWN; 1072 cur = frag; 1073 PCN_INC(frag, PCN_TX_LIST_CNT); 1074 cnt++; 1075 } 1076 1077 if (m != NULL) 1078 return(ENOBUFS); 1079 1080 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1081 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1082 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1083 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1084 sc->pcn_cdata.pcn_tx_cnt += cnt; 1085 *txidx = frag; 1086 1087 return(0); 1088} 1089 1090/* 1091 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1092 * to the mbuf data regions directly in the transmit lists. We also save a 1093 * copy of the pointers since the transmit list fragment pointers are 1094 * physical addresses. 1095 */ 1096static void 1097pcn_start(ifp) 1098 struct ifnet *ifp; 1099{ 1100 struct pcn_softc *sc; 1101 1102 sc = ifp->if_softc; 1103 PCN_LOCK(sc); 1104 pcn_start_locked(ifp); 1105 PCN_UNLOCK(sc); 1106} 1107 1108static void 1109pcn_start_locked(ifp) 1110 struct ifnet *ifp; 1111{ 1112 struct pcn_softc *sc; 1113 struct mbuf *m_head = NULL; 1114 u_int32_t idx; 1115 1116 sc = ifp->if_softc; 1117 1118 PCN_LOCK_ASSERT(sc); 1119 1120 if (!sc->pcn_link) 1121 return; 1122 1123 idx = sc->pcn_cdata.pcn_tx_prod; 1124 1125 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1126 return; 1127 1128 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1129 IF_DEQUEUE(&ifp->if_snd, m_head); 1130 if (m_head == NULL) 1131 break; 1132 1133 if (pcn_encap(sc, m_head, &idx)) { 1134 IF_PREPEND(&ifp->if_snd, m_head); 1135 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1136 break; 1137 } 1138 1139 /* 1140 * If there's a BPF listener, bounce a copy of this frame 1141 * to him. 1142 */ 1143 BPF_MTAP(ifp, m_head); 1144 1145 } 1146 1147 /* Transmit */ 1148 sc->pcn_cdata.pcn_tx_prod = idx; 1149 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1150 1151 /* 1152 * Set a timeout in case the chip goes out to lunch. 1153 */ 1154 sc->pcn_timer = 5; 1155 1156 return; 1157} 1158 1159static void 1160pcn_setfilt(ifp) 1161 struct ifnet *ifp; 1162{ 1163 struct pcn_softc *sc; 1164 1165 sc = ifp->if_softc; 1166 1167 /* If we want promiscuous mode, set the allframes bit. */ 1168 if (ifp->if_flags & IFF_PROMISC) { 1169 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1170 } else { 1171 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1172 } 1173 1174 /* Set the capture broadcast bit to capture broadcast frames. */ 1175 if (ifp->if_flags & IFF_BROADCAST) { 1176 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1177 } else { 1178 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1179 } 1180 1181 return; 1182} 1183 1184static void 1185pcn_init(xsc) 1186 void *xsc; 1187{ 1188 struct pcn_softc *sc = xsc; 1189 1190 PCN_LOCK(sc); 1191 pcn_init_locked(sc); 1192 PCN_UNLOCK(sc); 1193} 1194 1195static void 1196pcn_init_locked(sc) 1197 struct pcn_softc *sc; 1198{ 1199 struct ifnet *ifp = sc->pcn_ifp; 1200 struct mii_data *mii = NULL; 1201 struct ifmedia_entry *ife; 1202 1203 PCN_LOCK_ASSERT(sc); 1204 1205 /* 1206 * Cancel pending I/O and free all RX/TX buffers. 1207 */ 1208 pcn_stop(sc); 1209 pcn_reset(sc); 1210 1211 mii = device_get_softc(sc->pcn_miibus); 1212 ife = mii->mii_media.ifm_cur; 1213 1214 /* Set MAC address */ 1215 pcn_csr_write(sc, PCN_CSR_PAR0, 1216 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]); 1217 pcn_csr_write(sc, PCN_CSR_PAR1, 1218 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]); 1219 pcn_csr_write(sc, PCN_CSR_PAR2, 1220 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]); 1221 1222 /* Init circular RX list. */ 1223 if (pcn_list_rx_init(sc) == ENOBUFS) { 1224 if_printf(ifp, "initialization failed: no " 1225 "memory for rx buffers\n"); 1226 pcn_stop(sc); 1227 return; 1228 } 1229 1230 /* 1231 * Init tx descriptors. 1232 */ 1233 pcn_list_tx_init(sc); 1234 1235 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */ 1236 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL); 1237 1238 /* 1239 * Set up the port based on the currently selected media. 1240 * For Am79C978 we've to unconditionally set PCN_PORT_MII and 1241 * set the PHY in PCN_BCR_PHYSEL instead. 1242 */ 1243 if (sc->pcn_type != Am79C978 && 1244 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt) 1245 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET); 1246 else 1247 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1248 1249 /* Set up RX filter. */ 1250 pcn_setfilt(ifp); 1251 1252 /* 1253 * Load the multicast filter. 1254 */ 1255 pcn_setmulti(sc); 1256 1257 /* 1258 * Load the addresses of the RX and TX lists. 1259 */ 1260 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1261 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1262 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1263 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1264 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1265 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1266 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1267 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1268 1269 /* Set the RX and TX ring sizes. */ 1270 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1271 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1272 1273 /* We're not using the initialization block. */ 1274 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1275 1276 /* Enable fast suspend mode. */ 1277 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1278 1279 /* 1280 * Enable burst read and write. Also set the no underflow 1281 * bit. This will avoid transmit underruns in certain 1282 * conditions while still providing decent performance. 1283 */ 1284 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1285 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1286 1287 /* Enable graceful recovery from underflow. */ 1288 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1289 1290 /* Enable auto-padding of short TX frames. */ 1291 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1292 1293 /* Disable MII autoneg (we handle this ourselves). */ 1294 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1295 1296 if (sc->pcn_type == Am79C978) 1297 /* XXX support other PHYs? */ 1298 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1299 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1300 1301 /* Enable interrupts and start the controller running. */ 1302 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1303 1304 mii_mediachg(mii); 1305 1306 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1307 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1308 1309 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc); 1310 1311 return; 1312} 1313 1314/* 1315 * Set media options. 1316 */ 1317static int 1318pcn_ifmedia_upd(ifp) 1319 struct ifnet *ifp; 1320{ 1321 struct pcn_softc *sc; 1322 1323 sc = ifp->if_softc; 1324 1325 PCN_LOCK(sc); 1326 1327 /* 1328 * At least Am79C971 with DP83840A can wedge when switching 1329 * from the internal 10baseT PHY to the external PHY without 1330 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE 1331 * the PCnet chip has to be powered down or stopped anyway 1332 * and although documented otherwise it doesn't take effect 1333 * until the next initialization. 1334 */ 1335 sc->pcn_link = 0; 1336 pcn_stop(sc); 1337 pcn_reset(sc); 1338 pcn_init_locked(sc); 1339 if (ifp->if_snd.ifq_head != NULL) 1340 pcn_start_locked(ifp); 1341 1342 PCN_UNLOCK(sc); 1343 1344 return(0); 1345} 1346 1347/* 1348 * Report current media status. 1349 */ 1350static void 1351pcn_ifmedia_sts(ifp, ifmr) 1352 struct ifnet *ifp; 1353 struct ifmediareq *ifmr; 1354{ 1355 struct pcn_softc *sc; 1356 struct mii_data *mii; 1357 1358 sc = ifp->if_softc; 1359 1360 mii = device_get_softc(sc->pcn_miibus); 1361 PCN_LOCK(sc); 1362 mii_pollstat(mii); 1363 ifmr->ifm_active = mii->mii_media_active; 1364 ifmr->ifm_status = mii->mii_media_status; 1365 PCN_UNLOCK(sc); 1366 1367 return; 1368} 1369 1370static int 1371pcn_ioctl(ifp, command, data) 1372 struct ifnet *ifp; 1373 u_long command; 1374 caddr_t data; 1375{ 1376 struct pcn_softc *sc = ifp->if_softc; 1377 struct ifreq *ifr = (struct ifreq *) data; 1378 struct mii_data *mii = NULL; 1379 int error = 0; 1380 1381 switch(command) { 1382 case SIOCSIFFLAGS: 1383 PCN_LOCK(sc); 1384 if (ifp->if_flags & IFF_UP) { 1385 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1386 ifp->if_flags & IFF_PROMISC && 1387 !(sc->pcn_if_flags & IFF_PROMISC)) { 1388 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1389 PCN_EXTCTL1_SPND); 1390 pcn_setfilt(ifp); 1391 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1392 PCN_EXTCTL1_SPND); 1393 pcn_csr_write(sc, PCN_CSR_CSR, 1394 PCN_CSR_INTEN|PCN_CSR_START); 1395 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1396 !(ifp->if_flags & IFF_PROMISC) && 1397 sc->pcn_if_flags & IFF_PROMISC) { 1398 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1399 PCN_EXTCTL1_SPND); 1400 pcn_setfilt(ifp); 1401 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1402 PCN_EXTCTL1_SPND); 1403 pcn_csr_write(sc, PCN_CSR_CSR, 1404 PCN_CSR_INTEN|PCN_CSR_START); 1405 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1406 pcn_init_locked(sc); 1407 } else { 1408 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1409 pcn_stop(sc); 1410 } 1411 sc->pcn_if_flags = ifp->if_flags; 1412 PCN_UNLOCK(sc); 1413 error = 0; 1414 break; 1415 case SIOCADDMULTI: 1416 case SIOCDELMULTI: 1417 PCN_LOCK(sc); 1418 pcn_setmulti(sc); 1419 PCN_UNLOCK(sc); 1420 error = 0; 1421 break; 1422 case SIOCGIFMEDIA: 1423 case SIOCSIFMEDIA: 1424 mii = device_get_softc(sc->pcn_miibus); 1425 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1426 break; 1427 default: 1428 error = ether_ioctl(ifp, command, data); 1429 break; 1430 } 1431 1432 return(error); 1433} 1434 1435static void 1436pcn_watchdog(struct pcn_softc *sc) 1437{ 1438 struct ifnet *ifp; 1439 1440 PCN_LOCK_ASSERT(sc); 1441 ifp = sc->pcn_ifp; 1442 1443 ifp->if_oerrors++; 1444 if_printf(ifp, "watchdog timeout\n"); 1445 1446 pcn_stop(sc); 1447 pcn_reset(sc); 1448 pcn_init_locked(sc); 1449 1450 if (ifp->if_snd.ifq_head != NULL) 1451 pcn_start_locked(ifp); 1452} 1453 1454/* 1455 * Stop the adapter and free any mbufs allocated to the 1456 * RX and TX lists. 1457 */ 1458static void 1459pcn_stop(struct pcn_softc *sc) 1460{ 1461 register int i; 1462 struct ifnet *ifp; 1463 1464 PCN_LOCK_ASSERT(sc); 1465 ifp = sc->pcn_ifp; 1466 sc->pcn_timer = 0; 1467 1468 callout_stop(&sc->pcn_stat_callout); 1469 1470 /* Turn off interrupts */ 1471 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1472 /* Stop adapter */ 1473 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1474 sc->pcn_link = 0; 1475 1476 /* 1477 * Free data in the RX lists. 1478 */ 1479 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1480 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1481 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1482 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1483 } 1484 } 1485 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1486 sizeof(sc->pcn_ldata->pcn_rx_list)); 1487 1488 /* 1489 * Free the TX list buffers. 1490 */ 1491 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1492 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1493 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1494 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1495 } 1496 } 1497 1498 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1499 sizeof(sc->pcn_ldata->pcn_tx_list)); 1500 1501 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1502 1503 return; 1504} 1505 1506/* 1507 * Stop all chip I/O so that the kernel's probe routines don't 1508 * get confused by errant DMAs when rebooting. 1509 */ 1510static int 1511pcn_shutdown(device_t dev) 1512{ 1513 struct pcn_softc *sc; 1514 1515 sc = device_get_softc(dev); 1516 1517 PCN_LOCK(sc); 1518 pcn_reset(sc); 1519 pcn_stop(sc); 1520 PCN_UNLOCK(sc); 1521 1522 return 0; 1523} 1524