186557Stmm/*- 286557Stmm * Copyright (c) 1999 The NetBSD Foundation, Inc. 386557Stmm * All rights reserved. 486557Stmm * 586557Stmm * This code is derived from software contributed to The NetBSD Foundation 686557Stmm * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 786557Stmm * NASA Ames Research Center. 886557Stmm * 986557Stmm * Redistribution and use in source and binary forms, with or without 1086557Stmm * modification, are permitted provided that the following conditions 1186557Stmm * are met: 1286557Stmm * 1. Redistributions of source code must retain the above copyright 1386557Stmm * notice, this list of conditions and the following disclaimer. 1486557Stmm * 2. Redistributions in binary form must reproduce the above copyright 1586557Stmm * notice, this list of conditions and the following disclaimer in the 1686557Stmm * documentation and/or other materials provided with the distribution. 1786557Stmm * 1886557Stmm * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 1986557Stmm * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2086557Stmm * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2186557Stmm * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2286557Stmm * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2386557Stmm * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2486557Stmm * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2586557Stmm * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2686557Stmm * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2786557Stmm * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2886557Stmm * POSSIBILITY OF SUCH DAMAGE. 2986557Stmm * 30141752Smarius * from: NetBSD: ofw_pci.h,v 1.5 2003/10/22 09:04:39 mjl Exp 3186557Stmm * 3286557Stmm * $FreeBSD: releng/10.2/sys/dev/ofw/ofw_pci.h 204520 2010-03-01 16:52:11Z joel $ 3386557Stmm */ 3486557Stmm 3586557Stmm#ifndef _DEV_OFW_OFW_PCI_H_ 3686557Stmm#define _DEV_OFW_OFW_PCI_H_ 3786557Stmm 3886557Stmm/* 3986557Stmm * PCI Bus Binding to: 4086557Stmm * 4186557Stmm * IEEE Std 1275-1994 4286557Stmm * Standard for Boot (Initialization Configuration) Firmware 4386557Stmm * 4486557Stmm * Revision 2.1 4586557Stmm */ 4686557Stmm 4786557Stmm/* 4886557Stmm * Section 2.2.1. Physical Address Formats 4986557Stmm * 5086557Stmm * A PCI physical address is represented by 3 address cells: 5186557Stmm * 5286557Stmm * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr 5386557Stmm * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 5486557Stmm * phys.lo cell: llllllll llllllll llllllll llllllll 5586557Stmm * 5686557Stmm * n nonrelocatable 57141752Smarius * p prefetchable 5886557Stmm * t aliased below 1MB (memory) or 64k (i/o) 5986557Stmm * ss space code 6086557Stmm * b bus number 6186557Stmm * d device number 6286557Stmm * f function number 6386557Stmm * r register number 6486557Stmm * h high 32-bits of PCI address 6586557Stmm * l low 32-bits of PCI address 6686557Stmm */ 6786557Stmm 6886557Stmm#define OFW_PCI_PHYS_HI_NONRELOCATABLE 0x80000000 6986557Stmm#define OFW_PCI_PHYS_HI_PREFETCHABLE 0x40000000 7086557Stmm#define OFW_PCI_PHYS_HI_ALIASED 0x20000000 7186557Stmm#define OFW_PCI_PHYS_HI_SPACEMASK 0x03000000 7286557Stmm#define OFW_PCI_PHYS_HI_BUSMASK 0x00ff0000 7386557Stmm#define OFW_PCI_PHYS_HI_BUSSHIFT 16 7486557Stmm#define OFW_PCI_PHYS_HI_DEVICEMASK 0x0000f800 7586557Stmm#define OFW_PCI_PHYS_HI_DEVICESHIFT 11 7686557Stmm#define OFW_PCI_PHYS_HI_FUNCTIONMASK 0x00000700 7786557Stmm#define OFW_PCI_PHYS_HI_FUNCTIONSHIFT 8 7886557Stmm#define OFW_PCI_PHYS_HI_REGISTERMASK 0x000000ff 7986557Stmm 8086557Stmm#define OFW_PCI_PHYS_HI_SPACE_CONFIG 0x00000000 8186557Stmm#define OFW_PCI_PHYS_HI_SPACE_IO 0x01000000 8286557Stmm#define OFW_PCI_PHYS_HI_SPACE_MEM32 0x02000000 8386557Stmm#define OFW_PCI_PHYS_HI_SPACE_MEM64 0x03000000 8486557Stmm 8586557Stmm#define OFW_PCI_PHYS_HI_BUS(hi) \ 8686557Stmm (((hi) & OFW_PCI_PHYS_HI_BUSMASK) >> OFW_PCI_PHYS_HI_BUSSHIFT) 8786557Stmm#define OFW_PCI_PHYS_HI_DEVICE(hi) \ 8886557Stmm (((hi) & OFW_PCI_PHYS_HI_DEVICEMASK) >> OFW_PCI_PHYS_HI_DEVICESHIFT) 8986557Stmm#define OFW_PCI_PHYS_HI_FUNCTION(hi) \ 9086557Stmm (((hi) & OFW_PCI_PHYS_HI_FUNCTIONMASK) >> OFW_PCI_PHYS_HI_FUNCTIONSHIFT) 9186557Stmm 9286557Stmm/* 9386557Stmm * This has the 3 32bit cell values, plus 2 more to make up a 64-bit size. 9486557Stmm */ 9586557Stmmstruct ofw_pci_register { 9686557Stmm u_int32_t phys_hi; 9786557Stmm u_int32_t phys_mid; 9886557Stmm u_int32_t phys_lo; 9986557Stmm u_int32_t size_hi; 10086557Stmm u_int32_t size_lo; 10186557Stmm}; 10286557Stmm 10386557Stmm#endif /* _DEV_OFW_OFW_PCI_H_ */ 104