xgehal-config.c revision 171095
1/*- 2 * Copyright (c) 2002-2007 Neterion, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nxge/xgehal/xgehal-config.c 171095 2007-06-29 22:47:18Z sam $ 27 */ 28 29/* 30 * FileName : xgehal-config.c 31 * 32 * Description: configuration functionality 33 * 34 * Created: 14 May 2004 35 */ 36 37#include <dev/nxge/include/xgehal-config.h> 38#include <dev/nxge/include/xge-debug.h> 39 40/* 41 * __hal_tti_config_check - Check tti configuration 42 * @new_config: tti configuration information 43 * 44 * Returns: XGE_HAL_OK - success, 45 * otherwise one of the xge_hal_status_e{} enumerated error codes. 46 */ 47static xge_hal_status_e 48__hal_tti_config_check (xge_hal_tti_config_t *new_config) 49{ 50 if ((new_config->urange_a < XGE_HAL_MIN_TX_URANGE_A) || 51 (new_config->urange_a > XGE_HAL_MAX_TX_URANGE_A)) { 52 return XGE_HAL_BADCFG_TX_URANGE_A; 53 } 54 55 if ((new_config->ufc_a < XGE_HAL_MIN_TX_UFC_A) || 56 (new_config->ufc_a > XGE_HAL_MAX_TX_UFC_A)) { 57 return XGE_HAL_BADCFG_TX_UFC_A; 58 } 59 60 if ((new_config->urange_b < XGE_HAL_MIN_TX_URANGE_B) || 61 (new_config->urange_b > XGE_HAL_MAX_TX_URANGE_B)) { 62 return XGE_HAL_BADCFG_TX_URANGE_B; 63 } 64 65 if ((new_config->ufc_b < XGE_HAL_MIN_TX_UFC_B) || 66 (new_config->ufc_b > XGE_HAL_MAX_TX_UFC_B)) { 67 return XGE_HAL_BADCFG_TX_UFC_B; 68 } 69 70 if ((new_config->urange_c < XGE_HAL_MIN_TX_URANGE_C) || 71 (new_config->urange_c > XGE_HAL_MAX_TX_URANGE_C)) { 72 return XGE_HAL_BADCFG_TX_URANGE_C; 73 } 74 75 if ((new_config->ufc_c < XGE_HAL_MIN_TX_UFC_C) || 76 (new_config->ufc_c > XGE_HAL_MAX_TX_UFC_C)) { 77 return XGE_HAL_BADCFG_TX_UFC_C; 78 } 79 80 if ((new_config->ufc_d < XGE_HAL_MIN_TX_UFC_D) || 81 (new_config->ufc_d > XGE_HAL_MAX_TX_UFC_D)) { 82 return XGE_HAL_BADCFG_TX_UFC_D; 83 } 84 85 if ((new_config->timer_val_us < XGE_HAL_MIN_TX_TIMER_VAL) || 86 (new_config->timer_val_us > XGE_HAL_MAX_TX_TIMER_VAL)) { 87 return XGE_HAL_BADCFG_TX_TIMER_VAL; 88 } 89 90 if ((new_config->timer_ci_en < XGE_HAL_MIN_TX_TIMER_CI_EN) || 91 (new_config->timer_ci_en > XGE_HAL_MAX_TX_TIMER_CI_EN)) { 92 return XGE_HAL_BADCFG_TX_TIMER_CI_EN; 93 } 94 95 if ((new_config->timer_ac_en < XGE_HAL_MIN_TX_TIMER_AC_EN) || 96 (new_config->timer_ac_en > XGE_HAL_MAX_TX_TIMER_AC_EN)) { 97 return XGE_HAL_BADCFG_TX_TIMER_AC_EN; 98 } 99 100 return XGE_HAL_OK; 101} 102 103/* 104 * __hal_rti_config_check - Check rti configuration 105 * @new_config: rti configuration information 106 * 107 * Returns: XGE_HAL_OK - success, 108 * otherwise one of the xge_hal_status_e{} enumerated error codes. 109 */ 110static xge_hal_status_e 111__hal_rti_config_check (xge_hal_rti_config_t *new_config) 112{ 113 if ((new_config->urange_a < XGE_HAL_MIN_RX_URANGE_A) || 114 (new_config->urange_a > XGE_HAL_MAX_RX_URANGE_A)) { 115 return XGE_HAL_BADCFG_RX_URANGE_A; 116 } 117 118 if ((new_config->ufc_a < XGE_HAL_MIN_RX_UFC_A) || 119 (new_config->ufc_a > XGE_HAL_MAX_RX_UFC_A)) { 120 return XGE_HAL_BADCFG_RX_UFC_A; 121 } 122 123 if ((new_config->urange_b < XGE_HAL_MIN_RX_URANGE_B) || 124 (new_config->urange_b > XGE_HAL_MAX_RX_URANGE_B)) { 125 return XGE_HAL_BADCFG_RX_URANGE_B; 126 } 127 128 if ((new_config->ufc_b < XGE_HAL_MIN_RX_UFC_B) || 129 (new_config->ufc_b > XGE_HAL_MAX_RX_UFC_B)) { 130 return XGE_HAL_BADCFG_RX_UFC_B; 131 } 132 133 if ((new_config->urange_c < XGE_HAL_MIN_RX_URANGE_C) || 134 (new_config->urange_c > XGE_HAL_MAX_RX_URANGE_C)) { 135 return XGE_HAL_BADCFG_RX_URANGE_C; 136 } 137 138 if ((new_config->ufc_c < XGE_HAL_MIN_RX_UFC_C) || 139 (new_config->ufc_c > XGE_HAL_MAX_RX_UFC_C)) { 140 return XGE_HAL_BADCFG_RX_UFC_C; 141 } 142 143 if ((new_config->ufc_d < XGE_HAL_MIN_RX_UFC_D) || 144 (new_config->ufc_d > XGE_HAL_MAX_RX_UFC_D)) { 145 return XGE_HAL_BADCFG_RX_UFC_D; 146 } 147 148 if ((new_config->timer_val_us < XGE_HAL_MIN_RX_TIMER_VAL) || 149 (new_config->timer_val_us > XGE_HAL_MAX_RX_TIMER_VAL)) { 150 return XGE_HAL_BADCFG_RX_TIMER_VAL; 151 } 152 153 if ((new_config->timer_ac_en < XGE_HAL_MIN_RX_TIMER_AC_EN) || 154 (new_config->timer_ac_en > XGE_HAL_MAX_RX_TIMER_AC_EN)) { 155 return XGE_HAL_BADCFG_RX_TIMER_AC_EN; 156 } 157 158 return XGE_HAL_OK; 159} 160 161 162/* 163 * __hal_fifo_queue_check - Check fifo queue configuration 164 * @new_config: fifo queue configuration information 165 * 166 * Returns: XGE_HAL_OK - success, 167 * otherwise one of the xge_hal_status_e{} enumerated error codes. 168 */ 169static xge_hal_status_e 170__hal_fifo_queue_check (xge_hal_fifo_config_t *new_config, 171 xge_hal_fifo_queue_t *new_queue) 172{ 173 int i; 174 175 if ((new_queue->initial < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) || 176 (new_queue->initial > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) { 177 return XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH; 178 } 179 180 /* FIXME: queue "grow" feature is not supported. 181 * Use "initial" queue size as the "maximum"; 182 * Remove the next line when fixed. */ 183 new_queue->max = new_queue->initial; 184 185 if ((new_queue->max < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) || 186 (new_queue->max > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) { 187 return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH; 188 } 189 190 if (new_queue->max < new_config->reserve_threshold) { 191 return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD; 192 } 193 194 if ((new_queue->intr < XGE_HAL_MIN_FIFO_QUEUE_INTR) || 195 (new_queue->intr > XGE_HAL_MAX_FIFO_QUEUE_INTR)) { 196 return XGE_HAL_BADCFG_FIFO_QUEUE_INTR; 197 } 198 199 if ((new_queue->intr_vector < XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR) || 200 (new_queue->intr_vector > XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR)) { 201 return XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR; 202 } 203 204 for(i = 0; i < XGE_HAL_MAX_FIFO_TTI_NUM; i++) { 205 /* 206 * Validate the tti configuration parameters only if 207 * the TTI feature is enabled. 208 */ 209 if (new_queue->tti[i].enabled) { 210 xge_hal_status_e status; 211 212 if ((status = __hal_tti_config_check( 213 &new_queue->tti[i])) != XGE_HAL_OK) { 214 return status; 215 } 216 } 217 } 218 219 return XGE_HAL_OK; 220} 221 222/* 223 * __hal_ring_queue_check - Check ring queue configuration 224 * @new_config: ring queue configuration information 225 * 226 * Returns: XGE_HAL_OK - success, 227 * otherwise one of the xge_hal_status_e{} enumerated error codes. 228 */ 229static xge_hal_status_e 230__hal_ring_queue_check (xge_hal_ring_queue_t *new_config) 231{ 232 233 if ((new_config->initial < XGE_HAL_MIN_RING_QUEUE_BLOCKS) || 234 (new_config->initial > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) { 235 return XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS; 236 } 237 238 /* FIXME: queue "grow" feature is not supported. 239 * Use "initial" queue size as the "maximum"; 240 * Remove the next line when fixed. */ 241 new_config->max = new_config->initial; 242 243 if ((new_config->max < XGE_HAL_MIN_RING_QUEUE_BLOCKS) || 244 (new_config->max > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) { 245 return XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS; 246 } 247 248 if ((new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_1) && 249 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_3) && 250 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_5)) { 251 return XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE; 252 } 253 254 /* 255 * Herc has less DRAM; the check is done later inside 256 * device_initialize() 257 */ 258 if (((new_config->dram_size_mb < XGE_HAL_MIN_RING_QUEUE_SIZE) || 259 (new_config->dram_size_mb > XGE_HAL_MAX_RING_QUEUE_SIZE_XENA)) && 260 new_config->dram_size_mb != XGE_HAL_DEFAULT_USE_HARDCODE) 261 return XGE_HAL_BADCFG_RING_QUEUE_SIZE; 262 263 if ((new_config->backoff_interval_us < 264 XGE_HAL_MIN_BACKOFF_INTERVAL_US) || 265 (new_config->backoff_interval_us > 266 XGE_HAL_MAX_BACKOFF_INTERVAL_US)) { 267 return XGE_HAL_BADCFG_BACKOFF_INTERVAL_US; 268 } 269 270 if ((new_config->max_frm_len < XGE_HAL_MIN_MAX_FRM_LEN) || 271 (new_config->max_frm_len > XGE_HAL_MAX_MAX_FRM_LEN)) { 272 return XGE_HAL_BADCFG_MAX_FRM_LEN; 273 } 274 275 if ((new_config->priority < XGE_HAL_MIN_RING_PRIORITY) || 276 (new_config->priority > XGE_HAL_MAX_RING_PRIORITY)) { 277 return XGE_HAL_BADCFG_RING_PRIORITY; 278 } 279 280 if ((new_config->rth_en < XGE_HAL_MIN_RING_RTH_EN) || 281 (new_config->rth_en > XGE_HAL_MAX_RING_RTH_EN)) { 282 return XGE_HAL_BADCFG_RING_RTH_EN; 283 } 284 285 if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_MAC_EN) || 286 (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_MAC_EN)) { 287 return XGE_HAL_BADCFG_RING_RTS_MAC_EN; 288 } 289 290 if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_PORT_EN) || 291 (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) { 292 return XGE_HAL_BADCFG_RING_RTS_PORT_EN; 293 } 294 295 if ((new_config->intr_vector < XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR) || 296 (new_config->intr_vector > XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR)) { 297 return XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR; 298 } 299 300 if (new_config->indicate_max_pkts < 301 XGE_HAL_MIN_RING_INDICATE_MAX_PKTS || 302 new_config->indicate_max_pkts > 303 XGE_HAL_MAX_RING_INDICATE_MAX_PKTS) { 304 return XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS; 305 } 306 307 return __hal_rti_config_check(&new_config->rti); 308} 309 310/* 311 * __hal_mac_config_check - Check mac configuration 312 * @new_config: mac configuration information 313 * 314 * Returns: XGE_HAL_OK - success, 315 * otherwise one of the xge_hal_status_e{} enumerated error codes. 316 */ 317static xge_hal_status_e 318__hal_mac_config_check (xge_hal_mac_config_t *new_config) 319{ 320 if ((new_config->tmac_util_period < XGE_HAL_MIN_TMAC_UTIL_PERIOD) || 321 (new_config->tmac_util_period > XGE_HAL_MAX_TMAC_UTIL_PERIOD)) { 322 return XGE_HAL_BADCFG_TMAC_UTIL_PERIOD; 323 } 324 325 if ((new_config->rmac_util_period < XGE_HAL_MIN_RMAC_UTIL_PERIOD) || 326 (new_config->rmac_util_period > XGE_HAL_MAX_RMAC_UTIL_PERIOD)) { 327 return XGE_HAL_BADCFG_RMAC_UTIL_PERIOD; 328 } 329 330 if ((new_config->rmac_bcast_en < XGE_HAL_MIN_RMAC_BCAST_EN) || 331 (new_config->rmac_bcast_en > XGE_HAL_MAX_RMAC_BCAST_EN)) { 332 return XGE_HAL_BADCFG_RMAC_BCAST_EN; 333 } 334 335 if ((new_config->rmac_pause_gen_en < XGE_HAL_MIN_RMAC_PAUSE_GEN_EN) || 336 (new_config->rmac_pause_gen_en>XGE_HAL_MAX_RMAC_PAUSE_GEN_EN)) { 337 return XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN; 338 } 339 340 if ((new_config->rmac_pause_rcv_en < XGE_HAL_MIN_RMAC_PAUSE_RCV_EN) || 341 (new_config->rmac_pause_rcv_en>XGE_HAL_MAX_RMAC_PAUSE_RCV_EN)) { 342 return XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN; 343 } 344 345 if ((new_config->rmac_pause_time < XGE_HAL_MIN_RMAC_HIGH_PTIME) || 346 (new_config->rmac_pause_time > XGE_HAL_MAX_RMAC_HIGH_PTIME)) { 347 return XGE_HAL_BADCFG_RMAC_HIGH_PTIME; 348 } 349 350 if ((new_config->media < XGE_HAL_MIN_MEDIA) || 351 (new_config->media > XGE_HAL_MAX_MEDIA)) { 352 return XGE_HAL_BADCFG_MEDIA; 353 } 354 355 if ((new_config->mc_pause_threshold_q0q3 < 356 XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3) || 357 (new_config->mc_pause_threshold_q0q3 > 358 XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3)) { 359 return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3; 360 } 361 362 if ((new_config->mc_pause_threshold_q4q7 < 363 XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7) || 364 (new_config->mc_pause_threshold_q4q7 > 365 XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7)) { 366 return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7; 367 } 368 369 return XGE_HAL_OK; 370} 371 372/* 373 * __hal_fifo_config_check - Check fifo configuration 374 * @new_config: fifo configuration information 375 * 376 * Returns: XGE_HAL_OK - success, 377 * otherwise one of the xge_hal_status_e{} enumerated error codes. 378 */ 379static xge_hal_status_e 380__hal_fifo_config_check (xge_hal_fifo_config_t *new_config) 381{ 382 int i; 383 int total_fifo_length = 0; 384 385 /* 386 * recompute max_frags to be multiple of 4, 387 * which means, multiple of 128 for TxDL 388 */ 389 new_config->max_frags = ((new_config->max_frags + 3) >> 2) << 2; 390 391 if ((new_config->max_frags < XGE_HAL_MIN_FIFO_FRAGS) || 392 (new_config->max_frags > XGE_HAL_MAX_FIFO_FRAGS)) { 393 return XGE_HAL_BADCFG_FIFO_FRAGS; 394 } 395 396 if ((new_config->reserve_threshold < 397 XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD) || 398 (new_config->reserve_threshold > 399 XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD)) { 400 return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD; 401 } 402 403 if ((new_config->memblock_size < XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE) || 404 (new_config->memblock_size > XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE)) { 405 return XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE; 406 } 407 408 for(i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { 409 xge_hal_status_e status; 410 411 if (!new_config->queue[i].configured) 412 continue; 413 414 if ((status = __hal_fifo_queue_check(new_config, 415 &new_config->queue[i])) != XGE_HAL_OK) { 416 return status; 417 } 418 419 total_fifo_length += new_config->queue[i].max; 420 } 421 422 if(total_fifo_length > XGE_HAL_MAX_FIFO_QUEUE_LENGTH){ 423 return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH; 424 } 425 426 return XGE_HAL_OK; 427} 428 429/* 430 * __hal_ring_config_check - Check ring configuration 431 * @new_config: Ring configuration information 432 * 433 * Returns: XGE_HAL_OK - success, 434 * otherwise one of the xge_hal_status_e{} enumerated error codes. 435 */ 436static xge_hal_status_e 437__hal_ring_config_check (xge_hal_ring_config_t *new_config) 438{ 439 int i; 440 441 if ((new_config->memblock_size < XGE_HAL_MIN_RING_MEMBLOCK_SIZE) || 442 (new_config->memblock_size > XGE_HAL_MAX_RING_MEMBLOCK_SIZE)) { 443 return XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE; 444 } 445 446 for(i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { 447 xge_hal_status_e status; 448 449 if (!new_config->queue[i].configured) 450 continue; 451 452 if ((status = __hal_ring_queue_check(&new_config->queue[i])) 453 != XGE_HAL_OK) { 454 return status; 455 } 456 } 457 458 return XGE_HAL_OK; 459} 460 461 462/* 463 * __hal_device_config_check_common - Check device configuration. 464 * @new_config: Device configuration information 465 * 466 * Check part of configuration that is common to 467 * Xframe-I and Xframe-II. 468 * 469 * Returns: XGE_HAL_OK - success, 470 * otherwise one of the xge_hal_status_e{} enumerated error codes. 471 * 472 * See also: __hal_device_config_check_xena(). 473 */ 474xge_hal_status_e 475__hal_device_config_check_common (xge_hal_device_config_t *new_config) 476{ 477 xge_hal_status_e status; 478 479 if ((new_config->mtu < XGE_HAL_MIN_MTU) || 480 (new_config->mtu > XGE_HAL_MAX_MTU)) { 481 return XGE_HAL_BADCFG_MAX_MTU; 482 } 483 484 if ((new_config->bimodal_interrupts < XGE_HAL_BIMODAL_INTR_MIN) || 485 (new_config->bimodal_interrupts > XGE_HAL_BIMODAL_INTR_MAX)) { 486 return XGE_HAL_BADCFG_BIMODAL_INTR; 487 } 488 489 if (new_config->bimodal_interrupts && 490 ((new_config->bimodal_timer_lo_us < XGE_HAL_BIMODAL_TIMER_LO_US_MIN) || 491 (new_config->bimodal_timer_lo_us > XGE_HAL_BIMODAL_TIMER_LO_US_MAX))) { 492 return XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US; 493 } 494 495 if (new_config->bimodal_interrupts && 496 ((new_config->bimodal_timer_hi_us < XGE_HAL_BIMODAL_TIMER_HI_US_MIN) || 497 (new_config->bimodal_timer_hi_us > XGE_HAL_BIMODAL_TIMER_HI_US_MAX))) { 498 return XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US; 499 } 500 501 if ((new_config->no_isr_events < XGE_HAL_NO_ISR_EVENTS_MIN) || 502 (new_config->no_isr_events > XGE_HAL_NO_ISR_EVENTS_MAX)) { 503 return XGE_HAL_BADCFG_NO_ISR_EVENTS; 504 } 505 506 if ((new_config->isr_polling_cnt < XGE_HAL_MIN_ISR_POLLING_CNT) || 507 (new_config->isr_polling_cnt > XGE_HAL_MAX_ISR_POLLING_CNT)) { 508 return XGE_HAL_BADCFG_ISR_POLLING_CNT; 509 } 510 511 if (new_config->latency_timer && 512 new_config->latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) { 513 if ((new_config->latency_timer < XGE_HAL_MIN_LATENCY_TIMER) || 514 (new_config->latency_timer > XGE_HAL_MAX_LATENCY_TIMER)) { 515 return XGE_HAL_BADCFG_LATENCY_TIMER; 516 } 517 } 518 519 if (new_config->max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS) { 520 if ((new_config->max_splits_trans < 521 XGE_HAL_ONE_SPLIT_TRANSACTION) || 522 (new_config->max_splits_trans > 523 XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION)) 524 return XGE_HAL_BADCFG_MAX_SPLITS_TRANS; 525 } 526 527 if (new_config->mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT) 528 { 529 if ((new_config->mmrb_count < XGE_HAL_MIN_MMRB_COUNT) || 530 (new_config->mmrb_count > XGE_HAL_MAX_MMRB_COUNT)) { 531 return XGE_HAL_BADCFG_MMRB_COUNT; 532 } 533 } 534 535 if ((new_config->shared_splits < XGE_HAL_MIN_SHARED_SPLITS) || 536 (new_config->shared_splits > XGE_HAL_MAX_SHARED_SPLITS)) { 537 return XGE_HAL_BADCFG_SHARED_SPLITS; 538 } 539 540 if (new_config->stats_refresh_time_sec != 541 XGE_HAL_STATS_REFRESH_DISABLE) { 542 if ((new_config->stats_refresh_time_sec < 543 XGE_HAL_MIN_STATS_REFRESH_TIME) || 544 (new_config->stats_refresh_time_sec > 545 XGE_HAL_MAX_STATS_REFRESH_TIME)) { 546 return XGE_HAL_BADCFG_STATS_REFRESH_TIME; 547 } 548 } 549 550 if ((new_config->intr_mode != XGE_HAL_INTR_MODE_IRQLINE) && 551 (new_config->intr_mode != XGE_HAL_INTR_MODE_MSI) && 552 (new_config->intr_mode != XGE_HAL_INTR_MODE_MSIX)) { 553 return XGE_HAL_BADCFG_INTR_MODE; 554 } 555 556 if ((new_config->sched_timer_us < XGE_HAL_SCHED_TIMER_MIN) || 557 (new_config->sched_timer_us > XGE_HAL_SCHED_TIMER_MAX)) { 558 return XGE_HAL_BADCFG_SCHED_TIMER_US; 559 } 560 561 if ((new_config->sched_timer_one_shot != 562 XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE) && 563 (new_config->sched_timer_one_shot != 564 XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE)) { 565 return XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT; 566 } 567 568 /* 569 * Check adaptive schema parameters. Note that there are two 570 * configuration variables needs to be enabled in ULD: 571 * 572 * a) sched_timer_us should not be zero; 573 * b) rxufca_hi_lim should not be equal to rxufca_lo_lim. 574 * 575 * The code bellow checking for those conditions. 576 */ 577 if (new_config->sched_timer_us && 578 new_config->rxufca_hi_lim != new_config->rxufca_lo_lim) { 579 if ((new_config->rxufca_intr_thres < 580 XGE_HAL_RXUFCA_INTR_THRES_MIN) || 581 (new_config->rxufca_intr_thres > 582 XGE_HAL_RXUFCA_INTR_THRES_MAX)) { 583 return XGE_HAL_BADCFG_RXUFCA_INTR_THRES; 584 } 585 586 if ((new_config->rxufca_hi_lim < XGE_HAL_RXUFCA_HI_LIM_MIN) || 587 (new_config->rxufca_hi_lim > XGE_HAL_RXUFCA_HI_LIM_MAX)) { 588 return XGE_HAL_BADCFG_RXUFCA_HI_LIM; 589 } 590 591 if ((new_config->rxufca_lo_lim < XGE_HAL_RXUFCA_LO_LIM_MIN) || 592 (new_config->rxufca_lo_lim > XGE_HAL_RXUFCA_LO_LIM_MAX) || 593 (new_config->rxufca_lo_lim > new_config->rxufca_hi_lim)) { 594 return XGE_HAL_BADCFG_RXUFCA_LO_LIM; 595 } 596 597 if ((new_config->rxufca_lbolt_period < 598 XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN) || 599 (new_config->rxufca_lbolt_period > 600 XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX)) { 601 return XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD; 602 } 603 } 604 605 if ((new_config->link_valid_cnt < XGE_HAL_LINK_VALID_CNT_MIN) || 606 (new_config->link_valid_cnt > XGE_HAL_LINK_VALID_CNT_MAX)) { 607 return XGE_HAL_BADCFG_LINK_VALID_CNT; 608 } 609 610 if ((new_config->link_retry_cnt < XGE_HAL_LINK_RETRY_CNT_MIN) || 611 (new_config->link_retry_cnt > XGE_HAL_LINK_RETRY_CNT_MAX)) { 612 return XGE_HAL_BADCFG_LINK_RETRY_CNT; 613 } 614 615 if (new_config->link_valid_cnt > new_config->link_retry_cnt) 616 return XGE_HAL_BADCFG_LINK_VALID_CNT; 617 618 if (new_config->link_stability_period != XGE_HAL_DEFAULT_USE_HARDCODE) { 619 if ((new_config->link_stability_period < 620 XGE_HAL_MIN_LINK_STABILITY_PERIOD) || 621 (new_config->link_stability_period > 622 XGE_HAL_MAX_LINK_STABILITY_PERIOD)) { 623 return XGE_HAL_BADCFG_LINK_STABILITY_PERIOD; 624 } 625 } 626 627 if (new_config->device_poll_millis != 628 XGE_HAL_DEFAULT_USE_HARDCODE) { 629 if ((new_config->device_poll_millis < 630 XGE_HAL_MIN_DEVICE_POLL_MILLIS) || 631 (new_config->device_poll_millis > 632 XGE_HAL_MAX_DEVICE_POLL_MILLIS)) { 633 return XGE_HAL_BADCFG_DEVICE_POLL_MILLIS; 634 } 635 } 636 637 if ((new_config->rts_port_en < XGE_HAL_MIN_RING_RTS_PORT_EN) || 638 (new_config->rts_port_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) { 639 return XGE_HAL_BADCFG_RTS_PORT_EN; 640 } 641 642 if ((new_config->rts_qos_en < XGE_HAL_RTS_QOS_DISABLE) || 643 (new_config->rts_qos_en > XGE_HAL_RTS_QOS_ENABLE)) { 644 return XGE_HAL_BADCFG_RTS_QOS_EN; 645 } 646 647#if defined(XGE_HAL_CONFIG_LRO) 648 if (new_config->lro_sg_size != 649 XGE_HAL_DEFAULT_USE_HARDCODE) { 650 if ((new_config->lro_sg_size < XGE_HAL_LRO_MIN_SG_SIZE) || 651 (new_config->lro_sg_size > XGE_HAL_LRO_MAX_SG_SIZE)) { 652 return XGE_HAL_BADCFG_LRO_SG_SIZE; 653 } 654 } 655 656 if (new_config->lro_frm_len != 657 XGE_HAL_DEFAULT_USE_HARDCODE) { 658 if ((new_config->lro_frm_len < XGE_HAL_LRO_MIN_FRM_LEN) || 659 (new_config->lro_frm_len > XGE_HAL_LRO_MAX_FRM_LEN)) { 660 return XGE_HAL_BADCFG_LRO_FRM_LEN; 661 } 662 } 663#endif 664 665 if ((status = __hal_ring_config_check(&new_config->ring)) 666 != XGE_HAL_OK) { 667 return status; 668 } 669 670 if ((status = __hal_mac_config_check(&new_config->mac)) != 671 XGE_HAL_OK) { 672 return status; 673 } 674 675 if ((status = __hal_fifo_config_check(&new_config->fifo)) != 676 XGE_HAL_OK) { 677 return status; 678 } 679 680 return XGE_HAL_OK; 681} 682 683/* 684 * __hal_device_config_check_xena - Check Xframe-I configuration 685 * @new_config: Device configuration. 686 * 687 * Check part of configuration that is relevant only to Xframe-I. 688 * 689 * Returns: XGE_HAL_OK - success, 690 * otherwise one of the xge_hal_status_e{} enumerated error codes. 691 * 692 * See also: __hal_device_config_check_common(). 693 */ 694xge_hal_status_e 695__hal_device_config_check_xena (xge_hal_device_config_t *new_config) 696{ 697 if ((new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_33) && 698 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_66) && 699 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_100) && 700 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_133) && 701 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_266) && 702 (new_config->pci_freq_mherz != XGE_HAL_DEFAULT_USE_HARDCODE)) { 703 return XGE_HAL_BADCFG_PCI_FREQ_MHERZ; 704 } 705 706 return XGE_HAL_OK; 707} 708 709/* 710 * __hal_device_config_check_herc - Check device configuration 711 * @new_config: Device configuration. 712 * 713 * Check part of configuration that is relevant only to Xframe-II. 714 * 715 * Returns: XGE_HAL_OK - success, 716 * otherwise one of the xge_hal_status_e{} enumerated error codes. 717 * 718 * See also: __hal_device_config_check_common(). 719 */ 720xge_hal_status_e 721__hal_device_config_check_herc (xge_hal_device_config_t *new_config) 722{ 723 return XGE_HAL_OK; 724} 725 726 727/* 728 * __hal_driver_config_check - Check HAL configuration 729 * @new_config: Driver configuration information 730 * 731 * Returns: XGE_HAL_OK - success, 732 * otherwise one of the xge_hal_status_e{} enumerated error codes. 733 */ 734xge_hal_status_e 735__hal_driver_config_check (xge_hal_driver_config_t *new_config) 736{ 737 if ((new_config->queue_size_initial < 738 XGE_HAL_MIN_QUEUE_SIZE_INITIAL) || 739 (new_config->queue_size_initial > 740 XGE_HAL_MAX_QUEUE_SIZE_INITIAL)) { 741 return XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL; 742 } 743 744 if ((new_config->queue_size_max < XGE_HAL_MIN_QUEUE_SIZE_MAX) || 745 (new_config->queue_size_max > XGE_HAL_MAX_QUEUE_SIZE_MAX)) { 746 return XGE_HAL_BADCFG_QUEUE_SIZE_MAX; 747 } 748 749#ifdef XGE_TRACE_INTO_CIRCULAR_ARR 750 if ((new_config->tracebuf_size < XGE_HAL_MIN_CIRCULAR_ARR) || 751 (new_config->tracebuf_size > XGE_HAL_MAX_CIRCULAR_ARR)) { 752 return XGE_HAL_BADCFG_TRACEBUF_SIZE; 753 } 754 if ((new_config->tracebuf_timestamp_en < XGE_HAL_MIN_TIMESTAMP_EN) || 755 (new_config->tracebuf_timestamp_en > XGE_HAL_MAX_TIMESTAMP_EN)) { 756 return XGE_HAL_BADCFG_TRACEBUF_SIZE; 757 } 758#endif 759 760 return XGE_HAL_OK; 761} 762